diff --git a/cmake/modules/VTA.cmake b/cmake/modules/VTA.cmake index 8aad7207ecebc..0e6afe5361670 100644 --- a/cmake/modules/VTA.cmake +++ b/cmake/modules/VTA.cmake @@ -38,16 +38,9 @@ elseif(PYTHON) set_target_properties(vta PROPERTIES LINK_FLAGS "-undefined dynamic_lookup") endif(APPLE) - # PYNQ rules for Pynq v2.3 - if(${VTA_TARGET} STREQUAL "pynq") - find_library(__cma_lib NAMES cma PATH /usr/lib) - target_link_libraries(vta ${__cma_lib}) - endif() - # Ultra96 rules - if(${VTA_TARGET} STREQUAL "ultra96") - find_library(__sds_lib NAMES sds_lib PATH /usr/lib) - target_link_libraries(vta ${__sds_lib}) - endif() + # PYNQ rules for pynq v2.3 + find_library(__cma_lib NAMES cma PATH /usr/lib) + target_link_libraries(vta ${__cma_lib}) else() message(STATUS "Cannot found python in env, VTA build is skipped..") endif() diff --git a/vta/config/pynq_sample.json b/vta/config/pynq_sample.json index 5a86e2e788139..de5bc1022b1b6 100644 --- a/vta/config/pynq_sample.json +++ b/vta/config/pynq_sample.json @@ -14,6 +14,7 @@ "LOG_BATCH" : 0, "LOG_BLOCK_IN" : 4, "LOG_BLOCK_OUT" : 4, + "LOG_BUS_WIDTH" : 6, "LOG_UOP_BUFF_SIZE" : 15, "LOG_INP_BUFF_SIZE" : 15, "LOG_WGT_BUFF_SIZE" : 18, diff --git a/vta/config/ultra96_sample.json b/vta/config/ultra96_sample.json index fca0e92e6cfcb..c9e646060b0fc 100644 --- a/vta/config/ultra96_sample.json +++ b/vta/config/ultra96_sample.json @@ -14,6 +14,7 @@ "LOG_BATCH" : 0, "LOG_BLOCK_IN" : 4, "LOG_BLOCK_OUT" : 4, + "LOG_BUS_WIDTH" : 7, "LOG_UOP_BUFF_SIZE" : 15, "LOG_INP_BUFF_SIZE" : 15, "LOG_WGT_BUFF_SIZE" : 18, diff --git a/vta/config/vta_config.py b/vta/config/vta_config.py index 3ce4af07e58e5..0e9164bc33c06 100644 --- a/vta/config/vta_config.py +++ b/vta/config/vta_config.py @@ -60,6 +60,8 @@ def main(): help="returns log of tensor block in dimension") parser.add_argument("--get-blockout", action="store_true", help="returns log of tensor block out dimension") + parser.add_argument("--get-buswidth", action="store_true", + help="returns log of bus width in b") parser.add_argument("--get-uopbuffsize", action="store_true", help="returns log of micro-op buffer size in B") parser.add_argument("--get-inpbuffsize", action="store_true", @@ -182,6 +184,9 @@ def main(): if args.get_blockout: print(cfg["LOG_BLOCK_OUT"]) + if args.get_buswidth: + print(cfg["LOG_BUS_WIDTH"]) + if args.get_uopbuffsize: print(cfg["LOG_UOP_BUFF_SIZE"]) diff --git a/vta/hardware/xilinx/Makefile b/vta/hardware/xilinx/Makefile index 22a1fcf1468cf..84f60a84a1980 100644 --- a/vta/hardware/xilinx/Makefile +++ b/vta/hardware/xilinx/Makefile @@ -14,7 +14,7 @@ VIVADO = vivado HSI = hsi # HLS mode -MODE = skip_sim +MODE = all # Debug flag DEBUG = False # SLURM @@ -35,6 +35,7 @@ VTA_OUT_WIDTH := $(shell ${VTA_CONFIG} --get-outwidth) VTA_BATCH := $(shell ${VTA_CONFIG} --get-batch) VTA_IN_BLOCK := $(shell ${VTA_CONFIG} --get-blockin) VTA_OUT_BLOCK := $(shell ${VTA_CONFIG} --get-blockout) +VTA_BUS_WIDTH := $(shell ${VTA_CONFIG} --get-buswidth) VTA_UOP_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-uopbuffsize) VTA_INP_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-inpbuffsize) VTA_WGT_BUFF_SIZE := $(shell ${VTA_CONFIG} --get-wgtbuffsize) @@ -90,7 +91,7 @@ $(IP_PATH): $(SRC_DIR)/* $(MODE) $(DEBUG) $(VTA_ALU_EN) $(VTA_MUL_EN) \ $(VTA_TARGET_PER) $(VTA_GEMM_II) $(VTA_TALU_II) \ $(VTA_INP_WIDTH) $(VTA_WGT_WIDTH) $(VTA_ACC_WIDTH) $(VTA_OUT_WIDTH) \ - $(VTA_BATCH) $(VTA_IN_BLOCK) $(VTA_OUT_BLOCK) \ + $(VTA_BATCH) $(VTA_IN_BLOCK) $(VTA_OUT_BLOCK) $(VTA_BUS_WIDTH) \ $(VTA_UOP_BUFF_SIZE) $(VTA_INP_BUFF_SIZE) $(VTA_WGT_BUFF_SIZE) \ $(VTA_ACC_BUFF_SIZE) $(VTA_OUT_BUFF_SIZE) ifeq ($(SLURM), True) @@ -101,7 +102,7 @@ endif $(BIT_PATH): $(IP_PATH) mkdir -p $(HW_BUILD_PATH) cd $(HW_BUILD_PATH) && \ - $(VIVADO) -mode tcl -source $(SCRIPT_DIR)/ultra96.tcl \ + $(VIVADO) -mode tcl -source $(SCRIPT_DIR)/vivado.tcl \ -tclargs $(VTA_TARGET) $(BUILD_DIR)/hls/$(CONF) $(VTA_HW_COMP_THREADS) \ $(VTA_CLOCK_FREQ) $(VTA_GEMM_II) \ $(VTA_INP_WIDTH) $(VTA_WGT_WIDTH) $(VTA_OUT_WIDTH) \ diff --git a/vta/hardware/xilinx/scripts/hls.tcl b/vta/hardware/xilinx/scripts/hls.tcl index a64b4bd8931db..f8edf11e62de0 100644 --- a/vta/hardware/xilinx/scripts/hls.tcl +++ b/vta/hardware/xilinx/scripts/hls.tcl @@ -24,13 +24,14 @@ # Arg 17: batch size (log) # Arg 18: in block size (log) # Arg 19: out block size (log) -# Arg 20: uop buffer size in B (log) -# Arg 21: inp buffer size in B (log) -# Arg 22: wgt buffer size in B (log) -# Arg 23: acc buffer size in B (log) -# Arg 24: out buffer size in B (log) - -if { [llength $argv] eq 26 } { +# Arg 20: bus width in b (log) +# Arg 21: uop buffer size in B (log) +# Arg 22: inp buffer size in B (log) +# Arg 23: wgt buffer size in B (log) +# Arg 24: acc buffer size in B (log) +# Arg 25: out buffer size in B (log) + +if { [llength $argv] eq 27 } { set target [lindex $argv 2] set src_dir [lindex $argv 3] set sim_dir [lindex $argv 4] @@ -50,43 +51,24 @@ if { [llength $argv] eq 26 } { set batch [lindex $argv 18] set block_in [lindex $argv 19] set block_out [lindex $argv 20] - set uop_buff_size [lindex $argv 21] - set inp_buff_size [lindex $argv 22] - set wgt_buff_size [lindex $argv 23] - set acc_buff_size [lindex $argv 24] - set out_buff_size [lindex $argv 25] + set bus_width [lindex $argv 21] + set uop_buff_size [lindex $argv 22] + set inp_buff_size [lindex $argv 23] + set wgt_buff_size [lindex $argv 24] + set acc_buff_size [lindex $argv 25] + set out_buff_size [lindex $argv 26] } else { - set target "pynq" - set src_dir "../src" - set sim_dir "../sim" - set test_dir "../../src/test" - set include_dir "../../include" - set mode "all" - set debug "False" - set alu_ena "True" - set mul_ena "True" - set target_period 8 - set target_gemm_ii 10 - set target_alu_ii 16 - set inp_width 3 - set wgt_width 3 - set acc_width 5 - set out_width 3 - set batch 1 - set block_in 4 - set block_out 4 - set uop_buff_size 15 - set inp_buff_size 15 - set wgt_buff_size 15 - set acc_buff_size 17 - set out_buff_size 15 + puts "Not enough arguments provided!" exit } +puts "about to start doing some stuff" + + # Initializes the HLS design and sets HLS pragmas for memory partitioning. # This is necessary because of a Vivado restriction that doesn't allow for # buses wider than 1024 bits. -proc init_design {target per g_ii a_ii inp_width wgt_width out_width acc_width batch block_in block_out alu_ena} { +proc init_design {target per g_ii a_ii bus_width inp_width wgt_width out_width acc_width batch block_in block_out alu_ena} { # Set device number if {$target=="pynq"} { @@ -95,28 +77,25 @@ proc init_design {target per g_ii a_ii inp_width wgt_width out_width acc_width b set_part {xczu3eg-sbva484-1-e} } elseif {$target=="zcu102"} { set_part {xczu9eg-ffvb1156-2-e} + } elseif {$target=="f1"} { + set_part {xcvu9p-flgb2104-2-i} + # config_interface -m_axi_addr64 } # Max bus width (supported by Vivado) set max_width 1024 - # Set axi width (TODO derive from top level config) - if {$target=="pynq"} { - set axi_width 64 - } elseif {$target=="ultra96"} { - set axi_width 128 - } elseif {$target=="zcu102"} { - set axi_width 128 - } + # Set axi width + set axi_width [expr {1 << $bus_width}] # Set the clock frequency create_clock -period $per -name default # Set pipeline directive - set_directive_pipeline -II $g_ii "compute/READ_GEMM_UOP" + set_directive_pipeline -II $g_ii "gemm/READ_GEMM_UOP" if {$alu_ena=="True"} { - set_directive_pipeline -II $a_ii "compute/READ_ALU_UOP" + set_directive_pipeline -II $a_ii "alu/READ_ALU_UOP" } # Set input partition factor to (INP_VECTOR_WIDTH*BATCH/(1024*g_ii) @@ -174,7 +153,8 @@ set cflags "-I $include_dir -I $src_dir -I $test_dir \ -DVTA_LOG_BATCH=$batch -DVTA_LOG_BLOCK_OUT=$block_out -DVTA_LOG_BLOCK_IN=$block_in \ -DVTA_LOG_UOP_BUFF_SIZE=$uop_buff_size -DVTA_LOG_INP_BUFF_SIZE=$inp_buff_size \ -DVTA_LOG_WGT_BUFF_SIZE=$wgt_buff_size -DVTA_LOG_ACC_BUFF_SIZE=$acc_buff_size \ - -DVTA_LOG_OUT_BUFF_SIZE=$out_buff_size" + -DVTA_LOG_OUT_BUFF_SIZE=$out_buff_size -DVTA_LOG_BUS_WIDTH=$bus_width \ + -DVTA_GEMM_II=$target_gemm_ii" if {$debug=="True"} { append cflags " -DVTA_DEBUG=1" } @@ -185,6 +165,7 @@ if {$mul_ena=="True"} { append cflags " -DMUL_EN" } + # HLS behavioral sim if {$mode=="all" || $mode=="sim"} { open_project vta_sim @@ -193,7 +174,7 @@ if {$mode=="all" || $mode=="sim"} { add_files -tb $sim_dir/vta_test.cc -cflags $cflags add_files -tb $test_dir/test_lib.cc -cflags $cflags open_solution "solution0" - init_design $target $target_period $target_gemm_ii $target_alu_ii $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena + init_design $target $target_period $target_gemm_ii $target_alu_ii $bus_width $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena csim_design -clean close_project } @@ -204,7 +185,7 @@ if {$mode=="all" || $mode=="skip_sim" || $mode=="fetch"} { set_top fetch add_files $src_dir/vta.cc -cflags $cflags open_solution "solution0" - init_design $target $target_period $target_gemm_ii $target_alu_ii $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena + init_design $target $target_period $target_gemm_ii $target_alu_ii $bus_width $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena csynth_design if {$mode=="all" || $mode=="skip_sim"} { export_design -format ip_catalog @@ -218,7 +199,7 @@ if {$mode=="all" || $mode=="skip_sim" || $mode=="load"} { set_top load add_files $src_dir/vta.cc -cflags $cflags open_solution "solution0" - init_design $target $target_period $target_gemm_ii $target_alu_ii $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena + init_design $target $target_period $target_gemm_ii $target_alu_ii $bus_width $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena csynth_design if {$mode=="all" || $mode=="skip_sim"} { export_design -format ip_catalog @@ -232,7 +213,7 @@ if {$mode=="all" || $mode=="skip_sim" || $mode=="compute"} { set_top compute add_files $src_dir/vta.cc -cflags $cflags open_solution "solution0" - init_design $target $target_period $target_gemm_ii $target_alu_ii $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena + init_design $target $target_period $target_gemm_ii $target_alu_ii $bus_width $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena csynth_design if {$mode=="all" || $mode=="skip_sim"} { export_design -format ip_catalog @@ -246,7 +227,7 @@ if {$mode=="all" || $mode=="skip_sim" || $mode=="store"} { set_top store add_files $src_dir/vta.cc -cflags $cflags open_solution "solution0" - init_design $target $target_period $target_gemm_ii $target_alu_ii $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena + init_design $target $target_period $target_gemm_ii $target_alu_ii $bus_width $inp_width $wgt_width $out_width $acc_width $batch $block_in $block_out $alu_ena csynth_design if {$mode=="all" || $mode=="skip_sim"} { export_design -format ip_catalog diff --git a/vta/hardware/xilinx/scripts/ultra96.tcl b/vta/hardware/xilinx/scripts/ultra96.tcl deleted file mode 100644 index c2d8be4935900..0000000000000 --- a/vta/hardware/xilinx/scripts/ultra96.tcl +++ /dev/null @@ -1,2200 +0,0 @@ -# -# Copyright (c) 2018 by Xilinx, Contributors -# file: vivado.tcl -# brief: Vivado compilation script. Partially automatically generated -# by Vivado. -# - -# Check if script is running in correct Vivado version. -set scripts_vivado_version 2018.2 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado \ - <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. \ - Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado \ - <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP \ - Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -# Parse argument list, derive the clock to utilize -if { [llength $argv] eq 14 } { - set target [lindex $argv 0] - set ip_path [lindex $argv 1] - set num_threads [lindex $argv 2] - set clock_freq [lindex $argv 3] - set gemm_ii [lindex $argv 4] - set inp_width [expr 1 << [lindex $argv 5]] - set wgt_width [expr 1 << [lindex $argv 6]] - set out_width [expr 1 << [lindex $argv 7]] - set batch [expr 1 << [lindex $argv 8]] - set out_block [expr 1 << [lindex $argv 9]] - set in_block [expr 1 << [lindex $argv 10]] - set inp_mem_size [expr 1 << [lindex $argv 11]] - set wgt_mem_size [expr 1 << [lindex $argv 12]] - set out_mem_size [expr 1 << [lindex $argv 13]] -} else { - puts "Arg list incomplete: \ - \ - " - return 1 -} - -# Derive input mem parameters -set inp_mem_width [expr $inp_width * $batch * $in_block / $gemm_ii] -set inp_bus_width 1024 -set inp_part [expr $inp_mem_width / $inp_bus_width] -if {[expr $inp_part == 0]} { - set inp_part 1 - set inp_bus_width $inp_mem_width -} -set inp_mem_depth [expr $inp_mem_size * 8 / ($inp_mem_width * $inp_part)] - -# Derive weight mem parameters -set wgt_mem_width [expr $wgt_width * $out_block * $in_block / $gemm_ii] -set wgt_bus_width 1024 -set wgt_part [expr $wgt_mem_width / $wgt_bus_width] -if {[expr $wgt_part == 0]} { - set wgt_part 1 - set wgt_bus_width $wgt_mem_width -} -set wgt_mem_depth [expr $wgt_mem_size * 8 / ($wgt_mem_width * $wgt_part)] - -# Derive output mem parameters -set out_mem_width [expr $out_width * $batch * $out_block / $gemm_ii] -set out_bus_width 1024 -set out_part [expr $out_mem_width / $out_bus_width] -if {[expr $out_part == 0]} { - set out_part 1 - set out_bus_width $out_mem_width -} -set out_mem_depth [expr $out_mem_size * 8 / ($out_mem_width * $out_part)] - -# User defined paths -set proj_name vta -set proj_path "." -set ip_lib "ip_lib" -set fetch_ip "${ip_path}/vta_fetch/solution0/impl/ip/xilinx_com_hls_fetch_1_0.zip" -set load_ip "${ip_path}/vta_load/solution0/impl/ip/xilinx_com_hls_load_1_0.zip" -set compute_ip "${ip_path}/vta_compute/solution0/impl/ip/xilinx_com_hls_compute_1_0.zip" -set store_ip "${ip_path}/vta_store/solution0/impl/ip/xilinx_com_hls_store_1_0.zip" - -# Create custom project -if { ${target} eq "ultra96" } { - create_project -force $proj_name $proj_path -part xczu3eg-sbva484-1-e - set_property BOARD_PART em.avnet.com:ultra96:part0:1.0 [current_project] -} elseif { ${target} eq "zcu102" } { - create_project -force $proj_name $proj_path -part xczu9eg-ffvb1156-2-e - set_property BOARD_PART xilinx.com:zcu102:part0:3.2 [current_project] -} - -# Update IP repository with generated IP -file mkdir $ip_lib -set_property ip_repo_paths $ip_lib [current_project] -update_ip_catalog -update_ip_catalog -add_ip $fetch_ip -repo_path $ip_lib -update_ip_catalog -add_ip $load_ip -repo_path $ip_lib -update_ip_catalog -add_ip $compute_ip -repo_path $ip_lib -update_ip_catalog -add_ip $store_ip -repo_path $ip_lib - -# CHANGE DESIGN NAME HERE -set design_name $proj_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -xilinx.com:ip:smartconnect:1.0\ -xilinx.com:hls:compute:1.0\ -xilinx.com:hls:fetch:1.0\ -xilinx.com:ip:fifo_generator:13.2\ -xilinx.com:ip:blk_mem_gen:8.4\ -xilinx.com:hls:load:1.0\ -xilinx.com:ip:clk_wiz:6.0\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:zynq_ultra_ps_e:3.2\ -xilinx.com:hls:store:1.0\ -" - - set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - -################################################################## -# DESIGN PROCs -################################################################## - - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell inp_part wgt_part out_part inp_bus_width inp_mem_depth wgt_bus_width wgt_mem_depth out_bus_width out_mem_depth } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - - # Create ports - - # Create instance: proc_sys_reset, and set properties - set proc_sys_reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset ] - - # Create instance: pll_clk, and set properties - set pll_clk [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 pll_clk ] - set_property -dict [ list \ - CONFIG.CLKOUT1_JITTER {98.427} \ - CONFIG.CLKOUT1_PHASE_ERROR {87.466} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {250} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {11.875} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {4.750} \ - CONFIG.MMCM_DIVCLK_DIVIDE {1} \ - CONFIG.RESET_PORT {resetn} \ - CONFIG.RESET_TYPE {ACTIVE_LOW} \ - CONFIG.USE_LOCKED {false} \ - ] $pll_clk - - # Create instance: fetch_0, and set properties - set fetch_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:fetch:1.0 fetch_0 ] - set_property -dict [ list \ - CONFIG.C_M_AXI_INS_PORT_CACHE_VALUE {"0011"} \ - ] $fetch_0 - - # Create instance: load_0, and set properties - set load_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:load:1.0 load_0 ] - set_property -dict [ list \ - CONFIG.C_M_AXI_DATA_PORT_CACHE_VALUE {"0011"} \ - ] $load_0 - - # Create instance: compute_0, and set properties - set compute_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:compute:1.0 compute_0 ] - set_property -dict [ list \ - CONFIG.C_M_AXI_DATA_PORT_CACHE_VALUE {"0011"} \ - CONFIG.C_M_AXI_UOP_PORT_CACHE_VALUE {"0011"} \ - ] $compute_0 - - # Create instance: store_0, and set properties - set store_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:store:1.0 store_0 ] - set_property -dict [ list \ - CONFIG.C_M_AXI_DATA_PORT_CACHE_VALUE {"0011"} \ - ] $store_0 - - # Create instance: axi_smc_0, and set properties - set axi_smc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_0 ] - set_property -dict [ list \ - CONFIG.NUM_SI {2} \ - ] $axi_smc_0 - - # Create instance: axi_smc_1, and set properties - set axi_smc_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_1 ] - set_property -dict [ list \ - CONFIG.NUM_SI {1} \ - ] $axi_smc_1 - - # Create instance: axi_smc_2, and set properties - set axi_smc_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_2 ] - set_property -dict [ list \ - CONFIG.NUM_SI {1} \ - ] $axi_smc_2 - - # Create instance: axi_smc_3, and set properties - set axi_smc_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc_3 ] - set_property -dict [ list \ - CONFIG.NUM_SI {1} \ - ] $axi_smc_3 - - # Create instance: axi_xbar, and set properties - set axi_xbar [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_xbar ] - set_property -dict [ list \ - CONFIG.NUM_MI {4} \ - CONFIG.NUM_SI {1} \ - ] $axi_xbar - - # Create instance: load_queue, and set properties - set load_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 load_queue ] - set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {510} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_axis {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_rdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {0} \ - CONFIG.Full_Threshold_Assert_Value_axis {511} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {512} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TDATA_NUM_BYTES {16} \ - CONFIG.TKEEP_WIDTH {16} \ - CONFIG.TSTRB_WIDTH {16} \ - CONFIG.TUSER_WIDTH {0} \ - ] $load_queue - - # Create instance: gemm_queue, and set properties - set gemm_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 gemm_queue ] - set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {510} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_axis {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_rdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {0} \ - CONFIG.Full_Threshold_Assert_Value_axis {511} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {512} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TDATA_NUM_BYTES {16} \ - CONFIG.TKEEP_WIDTH {16} \ - CONFIG.TSTRB_WIDTH {16} \ - CONFIG.TUSER_WIDTH {0} \ - ] $gemm_queue - - # Create instance: store_queue, and set properties - set store_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 store_queue ] - set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {510} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_axis {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_rdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {0} \ - CONFIG.Full_Threshold_Assert_Value_axis {511} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {512} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TDATA_NUM_BYTES {16} \ - CONFIG.TKEEP_WIDTH {16} \ - CONFIG.TSTRB_WIDTH {16} \ - CONFIG.TUSER_WIDTH {0} \ - ] $store_queue - - # Create instance: l2g_queue, and set properties - set l2g_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 l2g_queue ] - set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {1022} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_axis {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_rdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {0} \ - CONFIG.Full_Threshold_Assert_Value_axis {1023} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {1024} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TUSER_WIDTH {0} \ - ] $l2g_queue - - # Create instance: g2l_queue, and set properties - set g2l_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 g2l_queue ] - set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {1022} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_axis {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_rdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {0} \ - CONFIG.Full_Threshold_Assert_Value_axis {1023} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {1024} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TUSER_WIDTH {0} \ - ] $g2l_queue - - # Create instance: g2s_queue, and set properties - set g2s_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 g2s_queue ] - set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {1022} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_axis {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_rdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {0} \ - CONFIG.Full_Threshold_Assert_Value_axis {1023} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {1024} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TUSER_WIDTH {0} \ - ] $g2s_queue - - # Create instance: s2g_queue, and set properties - set s2g_queue [ create_bd_cell -type ip -vlnv xilinx.com:ip:fifo_generator:13.2 s2g_queue ] - set_property -dict [ list \ - CONFIG.Empty_Threshold_Assert_Value_axis {1022} \ - CONFIG.Empty_Threshold_Assert_Value_rach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wach {14} \ - CONFIG.Empty_Threshold_Assert_Value_wrch {14} \ - CONFIG.FIFO_Implementation_axis {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_rdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} \ - CONFIG.FIFO_Implementation_wdch {Common_Clock_Builtin_FIFO} \ - CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} \ - CONFIG.Full_Flags_Reset_Value {0} \ - CONFIG.Full_Threshold_Assert_Value_axis {1023} \ - CONFIG.Full_Threshold_Assert_Value_rach {15} \ - CONFIG.Full_Threshold_Assert_Value_wach {15} \ - CONFIG.Full_Threshold_Assert_Value_wrch {15} \ - CONFIG.INTERFACE_TYPE {AXI_STREAM} \ - CONFIG.Input_Depth_axis {1024} \ - CONFIG.Reset_Type {Asynchronous_Reset} \ - CONFIG.TUSER_WIDTH {0} \ - ] $s2g_queue - # Create instance: ps_e_0, and set properties - set ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.2 ps_e_0 ] - set_property -dict [ list \ - CONFIG.CAN0_BOARD_INTERFACE {custom} \ - CONFIG.CAN1_BOARD_INTERFACE {custom} \ - CONFIG.CSU_BOARD_INTERFACE {custom} \ - CONFIG.DP_BOARD_INTERFACE {custom} \ - CONFIG.GEM0_BOARD_INTERFACE {custom} \ - CONFIG.GEM1_BOARD_INTERFACE {custom} \ - CONFIG.GEM2_BOARD_INTERFACE {custom} \ - CONFIG.GEM3_BOARD_INTERFACE {custom} \ - CONFIG.GPIO_BOARD_INTERFACE {custom} \ - CONFIG.IIC0_BOARD_INTERFACE {custom} \ - CONFIG.IIC1_BOARD_INTERFACE {custom} \ - CONFIG.NAND_BOARD_INTERFACE {custom} \ - CONFIG.PCIE_BOARD_INTERFACE {custom} \ - CONFIG.PJTAG_BOARD_INTERFACE {custom} \ - CONFIG.PMU_BOARD_INTERFACE {custom} \ - CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \ - CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \ - CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ - CONFIG.PSU_IMPORT_BOARD_PRESET {} \ - CONFIG.PSU_MIO_0_DIRECTION {out} \ - CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_0_SLEW {slow} \ - CONFIG.PSU_MIO_10_DIRECTION {inout} \ - CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_10_SLEW {slow} \ - CONFIG.PSU_MIO_11_DIRECTION {inout} \ - CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_11_SLEW {slow} \ - CONFIG.PSU_MIO_12_DIRECTION {inout} \ - CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_12_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_12_SLEW {slow} \ - CONFIG.PSU_MIO_13_DIRECTION {inout} \ - CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_13_SLEW {slow} \ - CONFIG.PSU_MIO_14_DIRECTION {inout} \ - CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_14_SLEW {slow} \ - CONFIG.PSU_MIO_15_DIRECTION {inout} \ - CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_15_SLEW {slow} \ - CONFIG.PSU_MIO_16_DIRECTION {inout} \ - CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_16_SLEW {slow} \ - CONFIG.PSU_MIO_17_DIRECTION {inout} \ - CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_17_SLEW {slow} \ - CONFIG.PSU_MIO_18_DIRECTION {inout} \ - CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_18_SLEW {slow} \ - CONFIG.PSU_MIO_19_DIRECTION {inout} \ - CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_19_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_19_SLEW {slow} \ - CONFIG.PSU_MIO_1_DIRECTION {in} \ - CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_1_SLEW {slow} \ - CONFIG.PSU_MIO_20_DIRECTION {inout} \ - CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_20_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_20_SLEW {slow} \ - CONFIG.PSU_MIO_21_DIRECTION {inout} \ - CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_21_SLEW {slow} \ - CONFIG.PSU_MIO_22_DIRECTION {out} \ - CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_22_SLEW {slow} \ - CONFIG.PSU_MIO_23_DIRECTION {inout} \ - CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_23_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_23_SLEW {slow} \ - CONFIG.PSU_MIO_24_DIRECTION {in} \ - CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_24_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_24_SLEW {slow} \ - CONFIG.PSU_MIO_25_DIRECTION {inout} \ - CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_25_SLEW {slow} \ - CONFIG.PSU_MIO_26_DIRECTION {in} \ - CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_26_SLEW {slow} \ - CONFIG.PSU_MIO_27_DIRECTION {out} \ - CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_27_SLEW {slow} \ - CONFIG.PSU_MIO_28_DIRECTION {in} \ - CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_28_SLEW {slow} \ - CONFIG.PSU_MIO_29_DIRECTION {out} \ - CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_29_SLEW {slow} \ - CONFIG.PSU_MIO_2_DIRECTION {in} \ - CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_2_SLEW {slow} \ - CONFIG.PSU_MIO_30_DIRECTION {in} \ - CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_30_SLEW {slow} \ - CONFIG.PSU_MIO_31_DIRECTION {inout} \ - CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_31_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_31_SLEW {slow} \ - CONFIG.PSU_MIO_32_DIRECTION {out} \ - CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_32_SLEW {slow} \ - CONFIG.PSU_MIO_33_DIRECTION {out} \ - CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_33_SLEW {slow} \ - CONFIG.PSU_MIO_34_DIRECTION {out} \ - CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_34_SLEW {slow} \ - CONFIG.PSU_MIO_35_DIRECTION {inout} \ - CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_35_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_35_SLEW {slow} \ - CONFIG.PSU_MIO_36_DIRECTION {inout} \ - CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_36_SLEW {slow} \ - CONFIG.PSU_MIO_37_DIRECTION {inout} \ - CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_37_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_37_SLEW {slow} \ - CONFIG.PSU_MIO_38_DIRECTION {inout} \ - CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_38_SLEW {slow} \ - CONFIG.PSU_MIO_39_DIRECTION {inout} \ - CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_39_SLEW {slow} \ - CONFIG.PSU_MIO_3_DIRECTION {out} \ - CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_3_SLEW {slow} \ - CONFIG.PSU_MIO_40_DIRECTION {inout} \ - CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_40_SLEW {slow} \ - CONFIG.PSU_MIO_41_DIRECTION {inout} \ - CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_41_SLEW {slow} \ - CONFIG.PSU_MIO_42_DIRECTION {inout} \ - CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_42_SLEW {slow} \ - CONFIG.PSU_MIO_43_DIRECTION {inout} \ - CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_43_SLEW {slow} \ - CONFIG.PSU_MIO_44_DIRECTION {inout} \ - CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_44_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_44_SLEW {slow} \ - CONFIG.PSU_MIO_45_DIRECTION {inout} \ - CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_45_SLEW {slow} \ - CONFIG.PSU_MIO_46_DIRECTION {inout} \ - CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_46_SLEW {slow} \ - CONFIG.PSU_MIO_47_DIRECTION {inout} \ - CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_47_SLEW {slow} \ - CONFIG.PSU_MIO_48_DIRECTION {inout} \ - CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_48_SLEW {slow} \ - CONFIG.PSU_MIO_49_DIRECTION {inout} \ - CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_49_SLEW {slow} \ - CONFIG.PSU_MIO_4_DIRECTION {inout} \ - CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_4_SLEW {slow} \ - CONFIG.PSU_MIO_50_DIRECTION {inout} \ - CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_50_SLEW {slow} \ - CONFIG.PSU_MIO_51_DIRECTION {out} \ - CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_51_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_51_SLEW {slow} \ - CONFIG.PSU_MIO_52_DIRECTION {in} \ - CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_52_SLEW {slow} \ - CONFIG.PSU_MIO_53_DIRECTION {in} \ - CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_53_SLEW {slow} \ - CONFIG.PSU_MIO_54_DIRECTION {inout} \ - CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_54_SLEW {slow} \ - CONFIG.PSU_MIO_55_DIRECTION {in} \ - CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_55_SLEW {slow} \ - CONFIG.PSU_MIO_56_DIRECTION {inout} \ - CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_56_SLEW {slow} \ - CONFIG.PSU_MIO_57_DIRECTION {inout} \ - CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_57_SLEW {slow} \ - CONFIG.PSU_MIO_58_DIRECTION {out} \ - CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_58_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_58_SLEW {slow} \ - CONFIG.PSU_MIO_59_DIRECTION {inout} \ - CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_59_SLEW {slow} \ - CONFIG.PSU_MIO_5_DIRECTION {inout} \ - CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_5_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_5_SLEW {slow} \ - CONFIG.PSU_MIO_60_DIRECTION {inout} \ - CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_60_SLEW {slow} \ - CONFIG.PSU_MIO_61_DIRECTION {inout} \ - CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_61_SLEW {slow} \ - CONFIG.PSU_MIO_62_DIRECTION {inout} \ - CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_62_SLEW {slow} \ - CONFIG.PSU_MIO_63_DIRECTION {inout} \ - CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_63_SLEW {slow} \ - CONFIG.PSU_MIO_64_DIRECTION {in} \ - CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_64_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_64_SLEW {slow} \ - CONFIG.PSU_MIO_65_DIRECTION {in} \ - CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_65_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_65_SLEW {slow} \ - CONFIG.PSU_MIO_66_DIRECTION {inout} \ - CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_66_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_66_SLEW {slow} \ - CONFIG.PSU_MIO_67_DIRECTION {in} \ - CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_67_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_67_SLEW {slow} \ - CONFIG.PSU_MIO_68_DIRECTION {inout} \ - CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_68_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_68_SLEW {slow} \ - CONFIG.PSU_MIO_69_DIRECTION {inout} \ - CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_69_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_69_SLEW {slow} \ - CONFIG.PSU_MIO_6_DIRECTION {inout} \ - CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_6_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_6_SLEW {slow} \ - CONFIG.PSU_MIO_70_DIRECTION {out} \ - CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_70_SLEW {slow} \ - CONFIG.PSU_MIO_71_DIRECTION {inout} \ - CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_71_SLEW {slow} \ - CONFIG.PSU_MIO_72_DIRECTION {inout} \ - CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_72_SLEW {slow} \ - CONFIG.PSU_MIO_73_DIRECTION {inout} \ - CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_73_SLEW {slow} \ - CONFIG.PSU_MIO_74_DIRECTION {inout} \ - CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_74_SLEW {slow} \ - CONFIG.PSU_MIO_75_DIRECTION {inout} \ - CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_75_SLEW {slow} \ - CONFIG.PSU_MIO_76_DIRECTION {inout} \ - CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_76_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_76_SLEW {slow} \ - CONFIG.PSU_MIO_77_DIRECTION {inout} \ - CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_77_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_77_SLEW {slow} \ - CONFIG.PSU_MIO_7_DIRECTION {inout} \ - CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_7_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_7_SLEW {slow} \ - CONFIG.PSU_MIO_8_DIRECTION {inout} \ - CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_8_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_8_SLEW {slow} \ - CONFIG.PSU_MIO_9_DIRECTION {inout} \ - CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_9_SLEW {slow} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \ - CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \ - CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ - CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \ - CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \ - CONFIG.PSU_SMC_CYCLE_T0 {NA} \ - CONFIG.PSU_SMC_CYCLE_T1 {NA} \ - CONFIG.PSU_SMC_CYCLE_T2 {NA} \ - CONFIG.PSU_SMC_CYCLE_T3 {NA} \ - CONFIG.PSU_SMC_CYCLE_T4 {NA} \ - CONFIG.PSU_SMC_CYCLE_T5 {NA} \ - CONFIG.PSU_SMC_CYCLE_T6 {NA} \ - CONFIG.PSU_VALUE_SILVERSION {3} \ - CONFIG.PSU__ACPU0__POWER__ON {1} \ - CONFIG.PSU__ACPU1__POWER__ON {1} \ - CONFIG.PSU__ACPU2__POWER__ON {1} \ - CONFIG.PSU__ACPU3__POWER__ON {1} \ - CONFIG.PSU__ACTUAL__IP {1} \ - CONFIG.PSU__ACT_DDR_FREQ_MHZ {525.000000} \ - CONFIG.PSU__AFI0_COHERENCY {0} \ - CONFIG.PSU__AFI1_COHERENCY {0} \ - CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ - CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ - CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000024} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ - CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000005} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000005} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {262.500005} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000012} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000006} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000012} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000010} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ - CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000002} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000011} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000010} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000001} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000010} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000005} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.999985} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000002} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000005} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000002} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000010} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500004} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000002} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100.000002} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100.000002} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100.000002} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {300} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500004} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500004} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500004} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500004} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000002} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000002} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000002} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000005} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000005} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ - CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ - CONFIG.PSU__CSU_COHERENCY {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__DDRC__ADDR_MIRROR {1} \ - CONFIG.PSU__DDRC__AL {0} \ - CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \ - CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \ - CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ - CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \ - CONFIG.PSU__DDRC__CL {NA} \ - CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ - CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ - CONFIG.PSU__DDRC__COMPONENTS {Components} \ - CONFIG.PSU__DDRC__CWL {NA} \ - CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \ - CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \ - CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \ - CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \ - CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \ - CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \ - CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \ - CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ - CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ - CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ - CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ - CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ - CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ - CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ - CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ - CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ - CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ - CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ - CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ - CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ - CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ - CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ - CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ - CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ - CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ - CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ - CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \ - CONFIG.PSU__DDRC__ECC {Disabled} \ - CONFIG.PSU__DDRC__ECC_SCRUB {0} \ - CONFIG.PSU__DDRC__ENABLE {1} \ - CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ - CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \ - CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ - CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ - CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ - CONFIG.PSU__DDRC__FGRM {NA} \ - CONFIG.PSU__DDRC__FREQ_MHZ {1} \ - CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \ - CONFIG.PSU__DDRC__LP_ASR {NA} \ - CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \ - CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \ - CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ - CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ - CONFIG.PSU__DDRC__PLL_BYPASS {0} \ - CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \ - CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ - CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \ - CONFIG.PSU__DDRC__SB_TARGET {NA} \ - CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \ - CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \ - CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ - CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ - CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ - CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ - CONFIG.PSU__DDRC__T_FAW {40.0} \ - CONFIG.PSU__DDRC__T_RAS_MIN {42} \ - CONFIG.PSU__DDRC__T_RC {63} \ - CONFIG.PSU__DDRC__T_RCD {15} \ - CONFIG.PSU__DDRC__T_RP {15} \ - CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ - CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ - CONFIG.PSU__DDRC__VREF {0} \ - CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \ - CONFIG.PSU__DDR_QOS_ENABLE {1} \ - CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \ - CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \ - CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \ - CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \ - CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \ - CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \ - CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \ - CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \ - CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \ - CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \ - CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \ - CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \ - CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \ - CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \ - CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \ - CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \ - CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \ - CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \ - CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \ - CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \ - CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \ - CONFIG.PSU__DEVICE_TYPE {EG} \ - CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ - CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DLL__ISUSED {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ - CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ - CONFIG.PSU__DP__REF_CLK_FREQ {27} \ - CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \ - CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ - CONFIG.PSU__ENET0__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET0__PTP__ENABLE {0} \ - CONFIG.PSU__ENET0__TSU__ENABLE {0} \ - CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET1__PTP__ENABLE {0} \ - CONFIG.PSU__ENET1__TSU__ENABLE {0} \ - CONFIG.PSU__ENET2__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET2__PTP__ENABLE {0} \ - CONFIG.PSU__ENET2__TSU__ENABLE {0} \ - CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET3__PTP__ENABLE {0} \ - CONFIG.PSU__ENET3__TSU__ENABLE {0} \ - CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ - CONFIG.PSU__EN_EMIO_TRACE {0} \ - CONFIG.PSU__EP__IP {0} \ - CONFIG.PSU__EXPAND__CORESIGHT {0} \ - CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ - CONFIG.PSU__EXPAND__GIC {0} \ - CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ - CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ - CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ - CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \ - CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__FPGA_PL0_ENABLE {1} \ - CONFIG.PSU__FPGA_PL1_ENABLE {1} \ - CONFIG.PSU__FPGA_PL2_ENABLE {1} \ - CONFIG.PSU__FPGA_PL3_ENABLE {1} \ - CONFIG.PSU__FP__POWER__ON {1} \ - CONFIG.PSU__FTM__CTI_IN_0 {0} \ - CONFIG.PSU__FTM__CTI_IN_1 {0} \ - CONFIG.PSU__FTM__CTI_IN_2 {0} \ - CONFIG.PSU__FTM__CTI_IN_3 {0} \ - CONFIG.PSU__FTM__CTI_OUT_0 {0} \ - CONFIG.PSU__FTM__CTI_OUT_1 {0} \ - CONFIG.PSU__FTM__CTI_OUT_2 {0} \ - CONFIG.PSU__FTM__CTI_OUT_3 {0} \ - CONFIG.PSU__FTM__GPI {0} \ - CONFIG.PSU__FTM__GPO {0} \ - CONFIG.PSU__GEM0_COHERENCY {0} \ - CONFIG.PSU__GEM1_COHERENCY {0} \ - CONFIG.PSU__GEM2_COHERENCY {0} \ - CONFIG.PSU__GEM3_COHERENCY {0} \ - CONFIG.PSU__GEM__TSU__ENABLE {0} \ - CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ - CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ - CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ - CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ - CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ - CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ - CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ - CONFIG.PSU__GEN_IPI__TRUSTZONE {} \ + CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ + CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ + CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \ + CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO_WIDTH {95} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {95} \ + CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \ + CONFIG.PSU__GPU_PP0__POWER__ON {1} \ + CONFIG.PSU__GPU_PP1__POWER__ON {1} \ + CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__GT__LINK_SPEED {HBR} \ + CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \ + CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \ + CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \ + CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \ + CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \ + CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \ + CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \ + CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \ + CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \ + CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \ + CONFIG.PSU__IRQ_P2F_AMS__INT {0} \ + CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \ + CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \ + CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \ + CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \ + CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_CSU__INT {0} \ + CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \ + CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \ + CONFIG.PSU__IRQ_P2F_GPU__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \ + CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \ + CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \ + CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \ + CONFIG.PSU__IRQ_P2F_NAND__INT {0} \ + CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \ + CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \ + CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \ + CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \ + CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \ + CONFIG.PSU__IRQ_P2F_SATA__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \ + CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \ + CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \ + CONFIG.PSU__IRQ_P2F_UART0__INT {0} \ + CONFIG.PSU__IRQ_P2F_UART1__INT {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \ + CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \ + CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \ + CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \ + CONFIG.PSU__L2_BANK0__POWER__ON {1} \ + CONFIG.PSU__LPDMA0_COHERENCY {0} \ + CONFIG.PSU__LPDMA1_COHERENCY {0} \ + CONFIG.PSU__LPDMA2_COHERENCY {0} \ + CONFIG.PSU__LPDMA3_COHERENCY {0} \ + CONFIG.PSU__LPDMA4_COHERENCY {0} \ + CONFIG.PSU__LPDMA5_COHERENCY {0} \ + CONFIG.PSU__LPDMA6_COHERENCY {0} \ + CONFIG.PSU__LPDMA7_COHERENCY {0} \ + CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \ + CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \ + CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \ + CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \ + CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \ + CONFIG.PSU__NAND_COHERENCY {0} \ + CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \ + CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \ + CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \ + CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \ + CONFIG.PSU__NUM_FABRIC_RESETS {1} \ + CONFIG.PSU__OCM_BANK0__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK1__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK2__POWER__ON {1} \ + CONFIG.PSU__OCM_BANK3__POWER__ON {1} \ + CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \ + CONFIG.PSU__PCIE__ACS_VIOLAION {0} \ + CONFIG.PSU__PCIE__ACS_VIOLATION {0} \ + CONFIG.PSU__PCIE__AER_CAPABILITY {0} \ + CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \ + CONFIG.PSU__PCIE__BAR0_64BIT {0} \ + CONFIG.PSU__PCIE__BAR0_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR0_VAL {} \ + CONFIG.PSU__PCIE__BAR1_64BIT {0} \ + CONFIG.PSU__PCIE__BAR1_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR1_VAL {} \ + CONFIG.PSU__PCIE__BAR2_64BIT {0} \ + CONFIG.PSU__PCIE__BAR2_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR2_VAL {} \ + CONFIG.PSU__PCIE__BAR3_64BIT {0} \ + CONFIG.PSU__PCIE__BAR3_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR3_VAL {} \ + CONFIG.PSU__PCIE__BAR4_64BIT {0} \ + CONFIG.PSU__PCIE__BAR4_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR4_VAL {} \ + CONFIG.PSU__PCIE__BAR5_64BIT {0} \ + CONFIG.PSU__PCIE__BAR5_ENABLE {0} \ + CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \ + CONFIG.PSU__PCIE__BAR5_VAL {} \ + CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \ + CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \ + CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \ + CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \ + CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \ + CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \ + CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \ + CONFIG.PSU__PCIE__DEVICE_ID {} \ + CONFIG.PSU__PCIE__ECRC_CHECK {0} \ + CONFIG.PSU__PCIE__ECRC_ERR {0} \ + CONFIG.PSU__PCIE__ECRC_GEN {0} \ + CONFIG.PSU__PCIE__EROM_ENABLE {0} \ + CONFIG.PSU__PCIE__EROM_VAL {} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \ + CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \ + CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \ + CONFIG.PSU__PCIE__INTX_GENERATION {0} \ + CONFIG.PSU__PCIE__LANE0__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE1__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE2__ENABLE {0} \ + CONFIG.PSU__PCIE__LANE3__ENABLE {0} \ + CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \ + CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \ + CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \ + CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \ + CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \ + CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \ + CONFIG.PSU__PCIE__MULTIHEADER {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \ + CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \ + CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \ + CONFIG.PSU__PCIE__RECEIVER_ERR {0} \ + CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \ + CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \ + CONFIG.PSU__PCIE__REVISION_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \ + CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \ + CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \ + CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \ + CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \ + CONFIG.PSU__PCIE__VENDOR_ID {} \ + CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__PL_CLK0_BUF {TRUE} \ + CONFIG.PSU__PL_CLK1_BUF {TRUE} \ + CONFIG.PSU__PL_CLK2_BUF {TRUE} \ + CONFIG.PSU__PL_CLK3_BUF {TRUE} \ + CONFIG.PSU__PL__POWER__ON {1} \ + CONFIG.PSU__PMU_COHERENCY {0} \ + CONFIG.PSU__PMU__AIBACK__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \ + CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \ + CONFIG.PSU__PMU__GPI0__ENABLE {1} \ + CONFIG.PSU__PMU__GPI0__IO {MIO 26} \ + CONFIG.PSU__PMU__GPI1__ENABLE {0} \ + CONFIG.PSU__PMU__GPI2__ENABLE {0} \ + CONFIG.PSU__PMU__GPI3__ENABLE {0} \ + CONFIG.PSU__PMU__GPI4__ENABLE {0} \ + CONFIG.PSU__PMU__GPI5__ENABLE {0} \ + CONFIG.PSU__PMU__GPO0__ENABLE {1} \ + CONFIG.PSU__PMU__GPO0__IO {MIO 32} \ + CONFIG.PSU__PMU__GPO1__ENABLE {1} \ + CONFIG.PSU__PMU__GPO1__IO {MIO 33} \ + CONFIG.PSU__PMU__GPO2__ENABLE {1} \ + CONFIG.PSU__PMU__GPO2__IO {MIO 34} \ + CONFIG.PSU__PMU__GPO2__POLARITY {high} \ + CONFIG.PSU__PMU__GPO3__ENABLE {0} \ + CONFIG.PSU__PMU__GPO4__ENABLE {0} \ + CONFIG.PSU__PMU__GPO5__ENABLE {0} \ + CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__PMU__PLERROR__ENABLE {0} \ + CONFIG.PSU__PRESET_APPLIED {1} \ + CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__DEBUG {0} \ + CONFIG.PSU__PROTECTION__ENABLE {0} \ + CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000 ;SIZE:1280;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD000000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD010000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD020000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD030000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD040000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD050000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD610000 ;SIZE:512;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFD5D0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \ + CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \ + CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF5E0000 ;SIZE:2560;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFCC0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF180000 ;SIZE:768;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF410000 ;SIZE:640;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFFA70000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware|SA:0xFF9A0000 ;SIZE:64;UNIT:KB ;RegionTZ:Secure ;WrAllowed:Read/Write;subsystemId:PMU Firmware} \ + CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;1|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \ + CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure} \ + CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \ + CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \ + CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|FPD;RCPU_GIC;F9000000;F900FFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;0|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9000000;F907FFFF;1} \ + CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU} \ + CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \ + CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \ + CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \ + CONFIG.PSU__QSPI_COHERENCY {0} \ + CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \ + CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__REPORT__DBGLOG {0} \ + CONFIG.PSU__RPU_COHERENCY {0} \ + CONFIG.PSU__RPU__POWER__ON {1} \ + CONFIG.PSU__SATA__LANE0__ENABLE {0} \ + CONFIG.PSU__SATA__LANE1__ENABLE {0} \ + CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \ + CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \ + CONFIG.PSU__SD0_COHERENCY {0} \ + CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \ + CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \ + CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \ + CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \ + CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \ + CONFIG.PSU__SD0__RESET__ENABLE {0} \ + CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \ + CONFIG.PSU__SD1_COHERENCY {0} \ + CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \ + CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \ + CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \ + CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \ + CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \ + CONFIG.PSU__SD1__RESET__ENABLE {0} \ + CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \ + CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \ + CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \ + CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \ + CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \ + CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \ + CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \ + CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \ + CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \ + CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \ + CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT0__RESET__ENABLE {0} \ + CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \ + CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__SWDT1__RESET__ENABLE {0} \ + CONFIG.PSU__TCM0A__POWER__ON {1} \ + CONFIG.PSU__TCM0B__POWER__ON {1} \ + CONFIG.PSU__TCM1A__POWER__ON {1} \ + CONFIG.PSU__TCM1B__POWER__ON {1} \ + CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \ + CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \ + CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \ + CONFIG.PSU__TRISTATE__INVERTED {1} \ + CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \ + CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \ + CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \ + CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \ + CONFIG.PSU__UART0__BAUD_RATE {115200} \ + CONFIG.PSU__UART0__MODEM__ENABLE {1} \ + CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \ + CONFIG.PSU__UART1__BAUD_RATE {115200} \ + CONFIG.PSU__UART1__MODEM__ENABLE {0} \ + CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \ + CONFIG.PSU__USB0_COHERENCY {0} \ + CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \ + CONFIG.PSU__USB0__REF_CLK_FREQ {26} \ + CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \ + CONFIG.PSU__USB1_COHERENCY {0} \ + CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \ + CONFIG.PSU__USB1__REF_CLK_FREQ {26} \ + CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \ + CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \ + CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \ + CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \ + CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \ + CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \ + CONFIG.PSU__USE__ADMA {0} \ + CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__AUDIO {0} \ + CONFIG.PSU__USE__CLK {0} \ + CONFIG.PSU__USE__CLK0 {0} \ + CONFIG.PSU__USE__CLK1 {0} \ + CONFIG.PSU__USE__CLK2 {0} \ + CONFIG.PSU__USE__CLK3 {0} \ + CONFIG.PSU__USE__CROSS_TRIGGER {0} \ + CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \ + CONFIG.PSU__USE__DEBUG__TEST {0} \ + CONFIG.PSU__USE__EVENT_RPU {0} \ + CONFIG.PSU__USE__FABRIC__RST {1} \ + CONFIG.PSU__USE__FTM {0} \ + CONFIG.PSU__USE__GDMA {0} \ + CONFIG.PSU__USE__IRQ {0} \ + CONFIG.PSU__USE__IRQ0 {0} \ + CONFIG.PSU__USE__IRQ1 {0} \ + CONFIG.PSU__USE__M_AXI_GP0 {1} \ + CONFIG.PSU__USE__M_AXI_GP1 {0} \ + CONFIG.PSU__USE__M_AXI_GP2 {0} \ + CONFIG.PSU__USE__PROC_EVENT_BUS {0} \ + CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \ + CONFIG.PSU__USE__RST0 {0} \ + CONFIG.PSU__USE__RST1 {0} \ + CONFIG.PSU__USE__RST2 {0} \ + CONFIG.PSU__USE__RST3 {0} \ + CONFIG.PSU__USE__RTC {0} \ + CONFIG.PSU__USE__STM {0} \ + CONFIG.PSU__USE__S_AXI_ACE {0} \ + CONFIG.PSU__USE__S_AXI_ACP {0} \ + CONFIG.PSU__USE__S_AXI_GP0 {1} \ + CONFIG.PSU__USE__S_AXI_GP1 {1} \ + CONFIG.PSU__USE__S_AXI_GP2 {0} \ + CONFIG.PSU__USE__S_AXI_GP3 {0} \ + CONFIG.PSU__USE__S_AXI_GP4 {0} \ + CONFIG.PSU__USE__S_AXI_GP5 {0} \ + CONFIG.PSU__USE__S_AXI_GP6 {0} \ + CONFIG.PSU__USE__USB3_0_HUB {0} \ + CONFIG.PSU__USE__USB3_1_HUB {0} \ + CONFIG.PSU__USE__VIDEO {0} \ + CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \ + CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \ + CONFIG.QSPI_BOARD_INTERFACE {custom} \ + CONFIG.SATA_BOARD_INTERFACE {custom} \ + CONFIG.SD0_BOARD_INTERFACE {custom} \ + CONFIG.SD1_BOARD_INTERFACE {custom} \ + CONFIG.SPI0_BOARD_INTERFACE {custom} \ + CONFIG.SPI1_BOARD_INTERFACE {custom} \ + CONFIG.SUBPRESET1 {Custom} \ + CONFIG.SUBPRESET2 {Custom} \ + CONFIG.SWDT0_BOARD_INTERFACE {custom} \ + CONFIG.SWDT1_BOARD_INTERFACE {custom} \ + CONFIG.TRACE_BOARD_INTERFACE {custom} \ + CONFIG.TTC0_BOARD_INTERFACE {custom} \ + CONFIG.TTC1_BOARD_INTERFACE {custom} \ + CONFIG.TTC2_BOARD_INTERFACE {custom} \ + CONFIG.TTC3_BOARD_INTERFACE {custom} \ + CONFIG.UART0_BOARD_INTERFACE {custom} \ + CONFIG.UART1_BOARD_INTERFACE {custom} \ + CONFIG.USB0_BOARD_INTERFACE {custom} \ + CONFIG.USB1_BOARD_INTERFACE {custom} \ + ] $ps_e_0 + } + # Create interface connections - connect_bd_intf_net -intf_net axi_interconnect_1_M01_AXI \ - [get_bd_intf_pins axi_interconnect_1/M01_AXI] \ - [get_bd_intf_pins fetch_0/s_axi_CONTROL_BUS] - connect_bd_intf_net -intf_net axi_interconnect_1_M02_AXI \ - [get_bd_intf_pins axi_interconnect_1/M02_AXI] \ - [get_bd_intf_pins load_0/s_axi_CONTROL_BUS] - connect_bd_intf_net -intf_net axi_interconnect_1_M03_AXI \ - [get_bd_intf_pins axi_interconnect_1/M03_AXI] \ - [get_bd_intf_pins compute_0/s_axi_CONTROL_BUS] - connect_bd_intf_net -intf_net axi_interconnect_1_M04_AXI \ - [get_bd_intf_pins axi_interconnect_1/M04_AXI] \ - [get_bd_intf_pins store_0/s_axi_CONTROL_BUS] - connect_bd_intf_net -intf_net axi_smc_M00_AXI \ - [get_bd_intf_pins axi_smc/M00_AXI] \ - [get_bd_intf_pins processing_system7_1/S_AXI_ACP] - connect_bd_intf_net -intf_net compute_0_g2l_dep_queue_V \ - [get_bd_intf_pins compute_0/g2l_dep_queue_V] \ - [get_bd_intf_pins g2l_queue/S_AXIS] - connect_bd_intf_net -intf_net compute_0_g2s_dep_queue_V \ - [get_bd_intf_pins compute_0/g2s_dep_queue_V] \ - [get_bd_intf_pins g2s_queue/S_AXIS] - connect_bd_intf_net -intf_net compute_0_m_axi_data_port \ - [get_bd_intf_pins axi_smc/S02_AXI] \ - [get_bd_intf_pins compute_0/m_axi_data_port] - connect_bd_intf_net -intf_net compute_0_m_axi_uop_port \ - [get_bd_intf_pins axi_smc/S01_AXI] \ - [get_bd_intf_pins compute_0/m_axi_uop_port] - connect_bd_intf_net -intf_net fetch_0_gemm_queue_V_V \ - [get_bd_intf_pins fetch_0/gemm_queue_V_V] \ - [get_bd_intf_pins gemm_queue/S_AXIS] - connect_bd_intf_net -intf_net fetch_0_l2g_dep_queue_V \ - [get_bd_intf_pins l2g_queue/S_AXIS] \ - [get_bd_intf_pins load_0/l2g_dep_queue_V] - connect_bd_intf_net -intf_net fetch_0_load_queue_V_V \ - [get_bd_intf_pins fetch_0/load_queue_V_V] \ - [get_bd_intf_pins load_queue/S_AXIS] - connect_bd_intf_net -intf_net fetch_0_m_axi_ins_port \ - [get_bd_intf_pins axi_smc/S00_AXI] \ - [get_bd_intf_pins fetch_0/m_axi_ins_port] - connect_bd_intf_net -intf_net fetch_0_store_queue_V_V \ - [get_bd_intf_pins fetch_0/store_queue_V_V] \ - [get_bd_intf_pins store_queue/S_AXIS] - connect_bd_intf_net -intf_net g2l_queue_M_AXIS \ - [get_bd_intf_pins g2l_queue/M_AXIS] \ - [get_bd_intf_pins load_0/g2l_dep_queue_V] - connect_bd_intf_net -intf_net g2s_queue_M_AXIS \ - [get_bd_intf_pins g2s_queue/M_AXIS] \ - [get_bd_intf_pins store_0/g2s_dep_queue_V] - connect_bd_intf_net -intf_net gemm_queue_M_AXIS \ - [get_bd_intf_pins compute_0/gemm_queue_V_V] \ - [get_bd_intf_pins gemm_queue/M_AXIS] - connect_bd_intf_net -intf_net l2g_queue_M_AXIS \ - [get_bd_intf_pins compute_0/l2g_dep_queue_V] \ - [get_bd_intf_pins l2g_queue/M_AXIS] - connect_bd_intf_net -intf_net load_0_m_axi_data_port \ - [get_bd_intf_pins axi_smc/S03_AXI] \ - [get_bd_intf_pins load_0/m_axi_data_port] - connect_bd_intf_net -intf_net load_queue_M_AXIS \ - [get_bd_intf_pins load_0/load_queue_V_V] \ - [get_bd_intf_pins load_queue/M_AXIS] - connect_bd_intf_net -intf_net processing_system7_1_axi_periph_m00_axi \ - [get_bd_intf_pins axi_interconnect_1/M00_AXI] \ - [get_bd_intf_pins axi_timer_1/S_AXI] - connect_bd_intf_net -intf_net processing_system7_1_ddr \ - [get_bd_intf_ports DDR] \ - [get_bd_intf_pins processing_system7_1/DDR] - connect_bd_intf_net -intf_net processing_system7_1_fixed_io \ - [get_bd_intf_ports FIXED_IO] \ - [get_bd_intf_pins processing_system7_1/FIXED_IO] - connect_bd_intf_net -intf_net processing_system7_1_m_axi_gp0 \ - [get_bd_intf_pins axi_interconnect_1/S00_AXI] \ - [get_bd_intf_pins processing_system7_1/M_AXI_GP0] - connect_bd_intf_net -intf_net s2g_queue_M_AXIS \ - [get_bd_intf_pins compute_0/s2g_dep_queue_V] \ - [get_bd_intf_pins s2g_queue/M_AXIS] - connect_bd_intf_net -intf_net store_0_m_axi_data_port \ - [get_bd_intf_pins axi_smc/S04_AXI] \ - [get_bd_intf_pins store_0/m_axi_data_port] - connect_bd_intf_net -intf_net store_0_s2g_dep_queue_V \ - [get_bd_intf_pins s2g_queue/S_AXIS] \ - [get_bd_intf_pins store_0/s2g_dep_queue_V] - connect_bd_intf_net -intf_net store_queue_M_AXIS \ - [get_bd_intf_pins store_0/store_queue_V_V] \ - [get_bd_intf_pins store_queue/M_AXIS] + connect_bd_intf_net -intf_net axi_xbar_M00_AXI [get_bd_intf_pins axi_xbar/M00_AXI] [get_bd_intf_pins fetch_0/s_axi_CONTROL_BUS] + connect_bd_intf_net -intf_net axi_xbar_M01_AXI [get_bd_intf_pins axi_xbar/M01_AXI] [get_bd_intf_pins load_0/s_axi_CONTROL_BUS] + connect_bd_intf_net -intf_net axi_xbar_M02_AXI [get_bd_intf_pins axi_xbar/M02_AXI] [get_bd_intf_pins compute_0/s_axi_CONTROL_BUS] + connect_bd_intf_net -intf_net axi_xbar_M03_AXI [get_bd_intf_pins axi_xbar/M03_AXI] [get_bd_intf_pins store_0/s_axi_CONTROL_BUS] + connect_bd_intf_net -intf_net fetch_0_l2g_dep_queue_V [get_bd_intf_pins l2g_queue/S_AXIS] [get_bd_intf_pins load_0/l2g_dep_queue_V] + connect_bd_intf_net -intf_net fetch_0_load_queue_V_V [get_bd_intf_pins fetch_0/load_queue_V_V] [get_bd_intf_pins load_queue/S_AXIS] + connect_bd_intf_net -intf_net fetch_0_gemm_queue_V_V [get_bd_intf_pins fetch_0/gemm_queue_V_V] [get_bd_intf_pins gemm_queue/S_AXIS] + connect_bd_intf_net -intf_net fetch_0_store_queue_V_V [get_bd_intf_pins fetch_0/store_queue_V_V] [get_bd_intf_pins store_queue/S_AXIS] + connect_bd_intf_net -intf_net compute_0_g2l_dep_queue_V [get_bd_intf_pins compute_0/g2l_dep_queue_V] [get_bd_intf_pins g2l_queue/S_AXIS] + connect_bd_intf_net -intf_net compute_0_g2s_dep_queue_V [get_bd_intf_pins compute_0/g2s_dep_queue_V] [get_bd_intf_pins g2s_queue/S_AXIS] + connect_bd_intf_net -intf_net store_0_s2g_dep_queue_V [get_bd_intf_pins s2g_queue/S_AXIS] [get_bd_intf_pins store_0/s2g_dep_queue_V] + connect_bd_intf_net -intf_net load_queue_M_AXIS [get_bd_intf_pins load_0/load_queue_V_V] [get_bd_intf_pins load_queue/M_AXIS] + connect_bd_intf_net -intf_net gemm_queue_M_AXIS [get_bd_intf_pins compute_0/gemm_queue_V_V] [get_bd_intf_pins gemm_queue/M_AXIS] + connect_bd_intf_net -intf_net store_queue_M_AXIS [get_bd_intf_pins store_0/store_queue_V_V] [get_bd_intf_pins store_queue/M_AXIS] + connect_bd_intf_net -intf_net l2g_queue_M_AXIS [get_bd_intf_pins compute_0/l2g_dep_queue_V] [get_bd_intf_pins l2g_queue/M_AXIS] + connect_bd_intf_net -intf_net g2l_queue_M_AXIS [get_bd_intf_pins g2l_queue/M_AXIS] [get_bd_intf_pins load_0/g2l_dep_queue_V] + connect_bd_intf_net -intf_net g2s_queue_M_AXIS [get_bd_intf_pins g2s_queue/M_AXIS] [get_bd_intf_pins store_0/g2s_dep_queue_V] + connect_bd_intf_net -intf_net s2g_queue_M_AXIS [get_bd_intf_pins compute_0/s2g_dep_queue_V] [get_bd_intf_pins s2g_queue/M_AXIS] + + if { ${target} eq "pynq" } { + connect_bd_intf_net -intf_net fetch_0_m_axi_ins_port [get_bd_intf_pins axi_smc0/S00_AXI] [get_bd_intf_pins fetch_0/m_axi_ins_port] + connect_bd_intf_net -intf_net load_0_m_axi_data_port [get_bd_intf_pins axi_smc0/S01_AXI] [get_bd_intf_pins load_0/m_axi_data_port] + connect_bd_intf_net -intf_net compute_0_m_axi_uop_port [get_bd_intf_pins axi_smc0/S02_AXI] [get_bd_intf_pins compute_0/m_axi_uop_port] + connect_bd_intf_net -intf_net compute_0_m_axi_data_port [get_bd_intf_pins axi_smc0/S03_AXI] [get_bd_intf_pins compute_0/m_axi_data_port] + connect_bd_intf_net -intf_net store_0_m_axi_data_port [get_bd_intf_pins axi_smc0/S04_AXI] [get_bd_intf_pins store_0/m_axi_data_port] + connect_bd_intf_net -intf_net axi_smc0_M00_AXI [get_bd_intf_pins axi_smc0/M00_AXI] [get_bd_intf_pins processing_system7_1/S_AXI_ACP] + connect_bd_intf_net -intf_net processing_system7_1_m_axi_gp0 [get_bd_intf_pins axi_xbar/S00_AXI] [get_bd_intf_pins processing_system7_1/M_AXI_GP0] + # External interface connections only apply to Pynq + connect_bd_intf_net -intf_net processing_system7_1_ddr [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_1/DDR] + connect_bd_intf_net -intf_net processing_system7_1_fixed_io [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_1/FIXED_IO] + } elseif { ${target} eq "ultra96" || ${target} eq "zcu102"} { + connect_bd_intf_net -intf_net fetch_0_m_axi_ins_port [get_bd_intf_pins axi_smc0/S00_AXI] [get_bd_intf_pins fetch_0/m_axi_ins_port] + connect_bd_intf_net -intf_net load_0_m_axi_data_port [get_bd_intf_pins axi_smc1/S00_AXI] [get_bd_intf_pins load_0/m_axi_data_port] + connect_bd_intf_net -intf_net compute_0_m_axi_uop_port [get_bd_intf_pins axi_smc0/S01_AXI] [get_bd_intf_pins compute_0/m_axi_uop_port] + connect_bd_intf_net -intf_net compute_0_m_axi_data_port [get_bd_intf_pins axi_smc0/S02_AXI] [get_bd_intf_pins compute_0/m_axi_data_port] + connect_bd_intf_net -intf_net store_0_m_axi_data_port [get_bd_intf_pins axi_smc0/S03_AXI] [get_bd_intf_pins store_0/m_axi_data_port] + connect_bd_intf_net -intf_net axi_smc0_M00_AXI [get_bd_intf_pins axi_smc0/M00_AXI] [get_bd_intf_pins ps_e_0/S_AXI_HPC0_FPD] + connect_bd_intf_net -intf_net axi_smc1_M00_AXI [get_bd_intf_pins axi_smc1/M00_AXI] [get_bd_intf_pins ps_e_0/S_AXI_HPC1_FPD] + connect_bd_intf_net -intf_net ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins axi_xbar/S00_AXI] [get_bd_intf_pins ps_e_0/M_AXI_HPM0_FPD] + } # Create port connections - connect_bd_net -net axi_timer_1_interrupt \ - [get_bd_pins axi_timer_1/interrupt] \ - [get_bd_pins xlconcat_1/In0] - connect_bd_net -net compute_0_interrupt \ - [get_bd_pins compute_0/interrupt] \ - [get_bd_pins xlconcat_1/In3] - connect_bd_net -net fetch_0_interrupt \ - [get_bd_pins fetch_0/interrupt] \ - [get_bd_pins xlconcat_1/In1] - connect_bd_net -net load_0_interrupt \ - [get_bd_pins load_0/interrupt] \ - [get_bd_pins xlconcat_1/In2] connect_bd_net -net proc_sys_reset_interconnect_aresetn \ - [get_bd_pins axi_interconnect_1/ARESETN] \ + [get_bd_pins axi_xbar/ARESETN] \ [get_bd_pins proc_sys_reset/interconnect_aresetn] - connect_bd_net -net proc_sys_reset_peripheral_aresetn \ - [get_bd_pins axi_interconnect_1/M00_ARESETN] \ - [get_bd_pins axi_interconnect_1/M01_ARESETN] \ - [get_bd_pins axi_interconnect_1/M02_ARESETN] \ - [get_bd_pins axi_interconnect_1/M03_ARESETN] \ - [get_bd_pins axi_interconnect_1/M04_ARESETN] \ - [get_bd_pins axi_interconnect_1/S00_ARESETN] \ - [get_bd_pins axi_smc/aresetn] \ - [get_bd_pins axi_timer_1/s_axi_aresetn] \ - [get_bd_pins compute_0/ap_rst_n] \ - [get_bd_pins fetch_0/ap_rst_n] \ - [get_bd_pins g2l_queue/s_aresetn] \ - [get_bd_pins g2s_queue/s_aresetn] \ - [get_bd_pins gemm_queue/s_aresetn] \ - [get_bd_pins l2g_queue/s_aresetn] \ - [get_bd_pins load_0/ap_rst_n] \ - [get_bd_pins load_queue/s_aresetn] \ - [get_bd_pins proc_sys_reset/peripheral_aresetn] \ - [get_bd_pins s2g_queue/s_aresetn] \ - [get_bd_pins store_0/ap_rst_n] \ - [get_bd_pins store_queue/s_aresetn] - connect_bd_net -net processing_system7_1_FCLK_CLK \ - [get_bd_pins axi_interconnect_1/ACLK] \ - [get_bd_pins axi_interconnect_1/M00_ACLK] \ - [get_bd_pins axi_interconnect_1/M01_ACLK] \ - [get_bd_pins axi_interconnect_1/M02_ACLK] \ - [get_bd_pins axi_interconnect_1/M03_ACLK] \ - [get_bd_pins axi_interconnect_1/M04_ACLK] \ - [get_bd_pins axi_interconnect_1/S00_ACLK] \ - [get_bd_pins axi_smc/aclk] \ - [get_bd_pins axi_timer_1/s_axi_aclk] \ - [get_bd_pins compute_0/ap_clk] \ - [get_bd_pins fetch_0/ap_clk] \ - [get_bd_pins g2l_queue/s_aclk] \ - [get_bd_pins g2s_queue/s_aclk] \ - [get_bd_pins gemm_queue/s_aclk] \ - [get_bd_pins l2g_queue/s_aclk] \ - [get_bd_pins load_0/ap_clk] \ - [get_bd_pins load_queue/s_aclk] \ - [get_bd_pins proc_sys_reset/slowest_sync_clk] \ - [get_bd_pins processing_system7_1/FCLK_CLK${clk}] \ - [get_bd_pins processing_system7_1/M_AXI_GP0_ACLK] \ - [get_bd_pins processing_system7_1/S_AXI_ACP_ACLK] \ - [get_bd_pins s2g_queue/s_aclk] \ - [get_bd_pins store_0/ap_clk] \ - [get_bd_pins store_queue/s_aclk] - connect_bd_net -net processing_system7_1_fclk_reset0_n \ - [get_bd_pins proc_sys_reset/ext_reset_in] \ - [get_bd_pins processing_system7_1/FCLK_RESET0_N] - connect_bd_net -net store_0_interrupt \ - [get_bd_pins store_0/interrupt] \ - [get_bd_pins xlconcat_1/In4] - connect_bd_net -net xlconcat_1_dout \ - [get_bd_pins processing_system7_1/IRQ_F2P] \ - [get_bd_pins xlconcat_1/dout] + if { ${target} eq "pynq" } { + connect_bd_net -net proc_sys_reset_peripheral_aresetn \ + [get_bd_pins proc_sys_reset/peripheral_aresetn] \ + [get_bd_pins axi_smc0/aresetn] \ + [get_bd_pins axi_xbar/M00_ARESETN] \ + [get_bd_pins axi_xbar/M01_ARESETN] \ + [get_bd_pins axi_xbar/M02_ARESETN] \ + [get_bd_pins axi_xbar/M03_ARESETN] \ + [get_bd_pins axi_xbar/S00_ARESETN] \ + [get_bd_pins fetch_0/ap_rst_n] \ + [get_bd_pins load_0/ap_rst_n] \ + [get_bd_pins store_0/ap_rst_n] \ + [get_bd_pins compute_0/ap_rst_n] \ + [get_bd_pins load_queue/s_aresetn] \ + [get_bd_pins gemm_queue/s_aresetn] \ + [get_bd_pins store_queue/s_aresetn] \ + [get_bd_pins l2g_queue/s_aresetn] \ + [get_bd_pins g2l_queue/s_aresetn] \ + [get_bd_pins g2s_queue/s_aresetn] \ + [get_bd_pins s2g_queue/s_aresetn] + connect_bd_net -net ps_clk_net \ + [get_bd_pins pll_clk/clk_in1] \ + [get_bd_pins processing_system7_1/FCLK_CLK0] + connect_bd_net -net processing_system7_1_FCLK_CLK \ + [get_bd_pins pll_clk/clk_out1] \ + [get_bd_pins proc_sys_reset/slowest_sync_clk] \ + [get_bd_pins axi_smc0/aclk] \ + [get_bd_pins axi_xbar/ACLK] \ + [get_bd_pins axi_xbar/M00_ACLK] \ + [get_bd_pins axi_xbar/M01_ACLK] \ + [get_bd_pins axi_xbar/M02_ACLK] \ + [get_bd_pins axi_xbar/M03_ACLK] \ + [get_bd_pins axi_xbar/S00_ACLK] \ + [get_bd_pins fetch_0/ap_clk] \ + [get_bd_pins load_0/ap_clk] \ + [get_bd_pins compute_0/ap_clk] \ + [get_bd_pins store_0/ap_clk] \ + [get_bd_pins load_queue/s_aclk] \ + [get_bd_pins gemm_queue/s_aclk] \ + [get_bd_pins store_queue/s_aclk] \ + [get_bd_pins l2g_queue/s_aclk] \ + [get_bd_pins g2l_queue/s_aclk] \ + [get_bd_pins g2s_queue/s_aclk] \ + [get_bd_pins s2g_queue/s_aclk] \ + [get_bd_pins processing_system7_1/M_AXI_GP0_ACLK] \ + [get_bd_pins processing_system7_1/S_AXI_ACP_ACLK] + connect_bd_net -net processing_system7_1_fclk_reset0_n \ + [get_bd_pins pll_clk/resetn] \ + [get_bd_pins proc_sys_reset/ext_reset_in] \ + [get_bd_pins processing_system7_1/FCLK_RESET0_N] + } elseif { ${target} eq "ultra96" || ${target} eq "zcu102"} { + connect_bd_net -net proc_sys_reset_peripheral_aresetn \ + [get_bd_pins proc_sys_reset/peripheral_aresetn] \ + [get_bd_pins axi_smc0/aresetn] \ + [get_bd_pins axi_smc1/aresetn] \ + [get_bd_pins axi_xbar/M00_ARESETN] \ + [get_bd_pins axi_xbar/M01_ARESETN] \ + [get_bd_pins axi_xbar/M02_ARESETN] \ + [get_bd_pins axi_xbar/M03_ARESETN] \ + [get_bd_pins axi_xbar/S00_ARESETN] \ + [get_bd_pins fetch_0/ap_rst_n] \ + [get_bd_pins load_0/ap_rst_n] \ + [get_bd_pins store_0/ap_rst_n] \ + [get_bd_pins compute_0/ap_rst_n] \ + [get_bd_pins load_queue/s_aresetn] \ + [get_bd_pins gemm_queue/s_aresetn] \ + [get_bd_pins store_queue/s_aresetn] \ + [get_bd_pins l2g_queue/s_aresetn] \ + [get_bd_pins g2l_queue/s_aresetn] \ + [get_bd_pins g2s_queue/s_aresetn] \ + [get_bd_pins s2g_queue/s_aresetn] + connect_bd_net -net ps_clk_net \ + [get_bd_pins pll_clk/clk_in1] \ + [get_bd_pins ps_e_0/pl_clk0] + connect_bd_net -net ps_e_0_clk \ + [get_bd_pins axi_smc0/aclk] \ + [get_bd_pins axi_smc1/aclk] \ + [get_bd_pins pll_clk/clk_out1] \ + [get_bd_pins proc_sys_reset/slowest_sync_clk] \ + [get_bd_pins axi_xbar/ACLK] \ + [get_bd_pins axi_xbar/M00_ACLK] \ + [get_bd_pins axi_xbar/M01_ACLK] \ + [get_bd_pins axi_xbar/M02_ACLK] \ + [get_bd_pins axi_xbar/M03_ACLK] \ + [get_bd_pins axi_xbar/S00_ACLK] \ + [get_bd_pins fetch_0/ap_clk] \ + [get_bd_pins load_0/ap_clk] \ + [get_bd_pins compute_0/ap_clk] \ + [get_bd_pins store_0/ap_clk] \ + [get_bd_pins load_queue/s_aclk] \ + [get_bd_pins gemm_queue/s_aclk] \ + [get_bd_pins store_queue/s_aclk] \ + [get_bd_pins l2g_queue/s_aclk] \ + [get_bd_pins g2l_queue/s_aclk] \ + [get_bd_pins g2s_queue/s_aclk] \ + [get_bd_pins s2g_queue/s_aclk] \ + [get_bd_pins ps_e_0/maxihpm0_fpd_aclk] \ + [get_bd_pins ps_e_0/saxihpc1_fpd_aclk] \ + [get_bd_pins ps_e_0/saxihpc0_fpd_aclk] + connect_bd_net -net ps_e_0_reset \ + [get_bd_pins pll_clk/resetn] \ + [get_bd_pins proc_sys_reset/ext_reset_in] \ + [get_bd_pins ps_e_0/pl_resetn0] + } # Create address segments - create_bd_addr_seg -range 0x40000000 -offset 0x00000000 \ - [get_bd_addr_spaces compute_0/Data_m_axi_uop_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_DDR_LOWOCM] \ - SEG_processing_system7_1_ACP_DDR_LOWOCM - create_bd_addr_seg -range 0x40000000 -offset 0x00000000 \ - [get_bd_addr_spaces compute_0/Data_m_axi_data_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_DDR_LOWOCM] \ - SEG_processing_system7_1_ACP_DDR_LOWOCM - create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 \ - [get_bd_addr_spaces compute_0/Data_m_axi_uop_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_HIGH_OCM] \ - SEG_processing_system7_1_ACP_HIGH_OCM - create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 \ - [get_bd_addr_spaces compute_0/Data_m_axi_data_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_HIGH_OCM] \ - SEG_processing_system7_1_ACP_HIGH_OCM - create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 \ - [get_bd_addr_spaces compute_0/Data_m_axi_uop_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_IOP] \ - SEG_processing_system7_1_ACP_IOP - create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 \ - [get_bd_addr_spaces compute_0/Data_m_axi_data_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_IOP] \ - SEG_processing_system7_1_ACP_IOP - create_bd_addr_seg -range 0x40000000 -offset 0x40000000 \ - [get_bd_addr_spaces compute_0/Data_m_axi_uop_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_M_AXI_GP0] \ - SEG_processing_system7_1_ACP_M_AXI_GP0 - create_bd_addr_seg -range 0x40000000 -offset 0x40000000 \ - [get_bd_addr_spaces compute_0/Data_m_axi_data_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_M_AXI_GP0] \ - SEG_processing_system7_1_ACP_M_AXI_GP0 - create_bd_addr_seg -range 0x40000000 -offset 0x00000000 \ - [get_bd_addr_spaces fetch_0/Data_m_axi_ins_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_DDR_LOWOCM] \ - SEG_processing_system7_1_ACP_DDR_LOWOCM - create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 \ - [get_bd_addr_spaces fetch_0/Data_m_axi_ins_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_HIGH_OCM] \ - SEG_processing_system7_1_ACP_HIGH_OCM - create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 \ - [get_bd_addr_spaces fetch_0/Data_m_axi_ins_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_IOP] \ - SEG_processing_system7_1_ACP_IOP - create_bd_addr_seg -range 0x40000000 -offset 0x40000000 \ - [get_bd_addr_spaces fetch_0/Data_m_axi_ins_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_M_AXI_GP0] \ - SEG_processing_system7_1_ACP_M_AXI_GP0 - create_bd_addr_seg -range 0x40000000 -offset 0x00000000 \ - [get_bd_addr_spaces load_0/Data_m_axi_data_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_DDR_LOWOCM] \ - SEG_processing_system7_1_ACP_DDR_LOWOCM - create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 \ - [get_bd_addr_spaces load_0/Data_m_axi_data_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_HIGH_OCM] \ - SEG_processing_system7_1_ACP_HIGH_OCM - create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 \ - [get_bd_addr_spaces load_0/Data_m_axi_data_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_IOP] \ - SEG_processing_system7_1_ACP_IOP - create_bd_addr_seg -range 0x40000000 -offset 0x40000000 \ - [get_bd_addr_spaces load_0/Data_m_axi_data_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_M_AXI_GP0] \ - SEG_processing_system7_1_ACP_M_AXI_GP0 - create_bd_addr_seg -range 0x00010000 -offset 0x42800000 \ - [get_bd_addr_spaces processing_system7_1/Data] \ - [get_bd_addr_segs axi_timer_1/S_AXI/Reg] SEG_axi_timer_1_Reg - create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 \ - [get_bd_addr_spaces processing_system7_1/Data] \ - [get_bd_addr_segs compute_0/s_axi_CONTROL_BUS/Reg] SEG_compute_0_Reg - create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 \ - [get_bd_addr_spaces processing_system7_1/Data] \ - [get_bd_addr_segs fetch_0/s_axi_CONTROL_BUS/Reg] SEG_fetch_0_Reg - create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 \ - [get_bd_addr_spaces processing_system7_1/Data] \ - [get_bd_addr_segs load_0/s_axi_CONTROL_BUS/Reg] SEG_load_0_Reg - create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 \ - [get_bd_addr_spaces processing_system7_1/Data] \ - [get_bd_addr_segs store_0/s_axi_CONTROL_BUS/Reg] SEG_store_0_Reg - create_bd_addr_seg -range 0x40000000 -offset 0x00000000 \ - [get_bd_addr_spaces store_0/Data_m_axi_data_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_DDR_LOWOCM] \ - SEG_processing_system7_1_ACP_DDR_LOWOCM - create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 \ - [get_bd_addr_spaces store_0/Data_m_axi_data_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_HIGH_OCM] \ - SEG_processing_system7_1_ACP_HIGH_OCM - create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 \ - [get_bd_addr_spaces store_0/Data_m_axi_data_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_IOP] \ - SEG_processing_system7_1_ACP_IOP - create_bd_addr_seg -range 0x40000000 -offset 0x40000000 \ - [get_bd_addr_spaces store_0/Data_m_axi_data_port] \ - [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_M_AXI_GP0] \ - SEG_processing_system7_1_ACP_M_AXI_GP0 - + if { ${target} eq "pynq" } { + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces compute_0/Data_m_axi_uop_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system7_1_ACP_DDR_LOWOCM + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces compute_0/Data_m_axi_data_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system7_1_ACP_DDR_LOWOCM + create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces compute_0/Data_m_axi_uop_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_HIGH_OCM] SEG_processing_system7_1_ACP_HIGH_OCM + create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces compute_0/Data_m_axi_data_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_HIGH_OCM] SEG_processing_system7_1_ACP_HIGH_OCM + create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 [get_bd_addr_spaces compute_0/Data_m_axi_uop_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_IOP] SEG_processing_system7_1_ACP_IOP + create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 [get_bd_addr_spaces compute_0/Data_m_axi_data_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_IOP] SEG_processing_system7_1_ACP_IOP + create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces compute_0/Data_m_axi_uop_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_M_AXI_GP0] SEG_processing_system7_1_ACP_M_AXI_GP0 + create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces compute_0/Data_m_axi_data_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_M_AXI_GP0] SEG_processing_system7_1_ACP_M_AXI_GP0 + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces fetch_0/Data_m_axi_ins_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system7_1_ACP_DDR_LOWOCM + create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces fetch_0/Data_m_axi_ins_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_HIGH_OCM] SEG_processing_system7_1_ACP_HIGH_OCM + create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 [get_bd_addr_spaces fetch_0/Data_m_axi_ins_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_IOP] SEG_processing_system7_1_ACP_IOP + create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces fetch_0/Data_m_axi_ins_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_M_AXI_GP0] SEG_processing_system7_1_ACP_M_AXI_GP0 + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces load_0/Data_m_axi_data_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system7_1_ACP_DDR_LOWOCM + create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces load_0/Data_m_axi_data_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_HIGH_OCM] SEG_processing_system7_1_ACP_HIGH_OCM + create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 [get_bd_addr_spaces load_0/Data_m_axi_data_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_IOP] SEG_processing_system7_1_ACP_IOP + create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces load_0/Data_m_axi_data_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_M_AXI_GP0] SEG_processing_system7_1_ACP_M_AXI_GP0 + create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs fetch_0/s_axi_CONTROL_BUS/Reg] SEG_fetch_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs compute_0/s_axi_CONTROL_BUS/Reg] SEG_compute_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs load_0/s_axi_CONTROL_BUS/Reg] SEG_load_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs store_0/s_axi_CONTROL_BUS/Reg] SEG_store_0_Reg + create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces store_0/Data_m_axi_data_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_DDR_LOWOCM] SEG_processing_system7_1_ACP_DDR_LOWOCM + create_bd_addr_seg -range 0x00040000 -offset 0xFFFC0000 [get_bd_addr_spaces store_0/Data_m_axi_data_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_HIGH_OCM] SEG_processing_system7_1_ACP_HIGH_OCM + create_bd_addr_seg -range 0x00400000 -offset 0xE0000000 [get_bd_addr_spaces store_0/Data_m_axi_data_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_IOP] SEG_processing_system7_1_ACP_IOP + create_bd_addr_seg -range 0x40000000 -offset 0x40000000 [get_bd_addr_spaces store_0/Data_m_axi_data_port] [get_bd_addr_segs processing_system7_1/S_AXI_ACP/ACP_M_AXI_GP0] SEG_processing_system7_1_ACP_M_AXI_GP0 + } elseif { ${target} eq "ultra96" || ${target} eq "zcu102"} { + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces fetch_0/Data_m_axi_ins_port] [get_bd_addr_segs ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_ps_e_0_HPC0_DDR_LOW + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces load_0/Data_m_axi_data_port] [get_bd_addr_segs ps_e_0/SAXIGP1/HPC1_DDR_LOW] SEG_ps_e_0_HPC1_DDR_LOW + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces compute_0/Data_m_axi_uop_port] [get_bd_addr_segs ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_ps_e_0_HPC0_DDR_LOW + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces compute_0/Data_m_axi_data_port] [get_bd_addr_segs ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_ps_e_0_HPC0_DDR_LOW + create_bd_addr_seg -range 0x80000000 -offset 0x00000000 [get_bd_addr_spaces store_0/Data_m_axi_data_port] [get_bd_addr_segs ps_e_0/SAXIGP0/HPC0_DDR_LOW] SEG_ps_e_0_HPC0_DDR_LOW + create_bd_addr_seg -range 0x00001000 -offset 0xA0001000 [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs fetch_0/s_axi_CONTROL_BUS/Reg] SEG_fetch_0_Reg + create_bd_addr_seg -range 0x00001000 -offset 0xA0002000 [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs load_0/s_axi_CONTROL_BUS/Reg] SEG_load_0_Reg + create_bd_addr_seg -range 0x00001000 -offset 0xA0003000 [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs compute_0/s_axi_CONTROL_BUS/Reg] SEG_compute_0_Reg + create_bd_addr_seg -range 0x00001000 -offset 0xA0004000 [get_bd_addr_spaces ps_e_0/Data] [get_bd_addr_segs store_0/s_axi_CONTROL_BUS/Reg] SEG_store_0_Reg + } # Restore current instance current_bd_instance $oldCurInst @@ -911,7 +2110,7 @@ CONFIG.NUM_PORTS {5} \ # MAIN FLOW ################################################################## -create_root_design "" $clock_id $inp_part $wgt_part $out_part $inp_bus_width \ +create_root_design "" $target $clock_freq $inp_part $wgt_part $out_part $inp_bus_width \ $inp_mem_depth $wgt_bus_width $wgt_mem_depth $out_bus_width $out_mem_depth # Create top-level wrapper file diff --git a/vta/hardware/xilinx/sim/vta_test.cc b/vta/hardware/xilinx/sim/vta_test.cc index 514c15e94fab8..871ed052bcd3e 100644 --- a/vta/hardware/xilinx/sim/vta_test.cc +++ b/vta/hardware/xilinx/sim/vta_test.cc @@ -16,17 +16,6 @@ int main(void) { printParameters(); #endif - // Micro op bound - assert(VTA_UOP_GEM_2_1 < VTA_UOP_WIDTH); - assert(VTA_UOP_ALU_1_1 < VTA_UOP_WIDTH); - // Make sure there is no misaligment - assert(VTA_INSN_GEM_9_1 < VTA_INSN_GEM_A_0); - assert(VTA_INSN_MEM_7_1 < VTA_INSN_MEM_8_0); - // Instruction bounds - assert(VTA_INSN_MEM_E_1 < VTA_INS_WIDTH); - assert(VTA_INSN_GEM_F_1 < VTA_INS_WIDTH); - assert(VTA_INSN_ALU_G_1 < VTA_INS_WIDTH); - int status = 0; #ifdef ALU_EN diff --git a/vta/hardware/xilinx/src/vta.cc b/vta/hardware/xilinx/src/vta.cc index de2ac8291502f..4e5973282040f 100644 --- a/vta/hardware/xilinx/src/vta.cc +++ b/vta/hardware/xilinx/src/vta.cc @@ -10,6 +10,107 @@ #include "vta.h" +template +void reset_mem( + memop_sram_T &sram_idx, + memop_sram_T range, + DATA_T mem[][MAT_AXI_RATIO]) { + + for (int i = 0; i < range; i ++) { + for (int j = 0; j < MAT_AXI_RATIO; j ++) { +#pragma HLS UNROLL + mem[sram_idx][j] = 0; + } + sram_idx ++; + } +} + +template +void load_pad_2d( + volatile DATA_T *src, + DATA_T dst[][MAT_AXI_RATIO], + memop_sram_T sram_idx, + memop_dram_T dram_idx, + memop_size_T y_size, + memop_size_T x_size, + memop_stride_T x_stride, + memop_pad_T x_pad_0, + memop_pad_T x_pad_1, + memop_sram_T y_offset_0, + memop_sram_T y_offset_1) { +#pragma HLS INLINE + + reset_mem(sram_idx, y_offset_0, dst); + for (int y = 0; y < y_size; y++) { +#pragma HLS PIPELINE + reset_mem(sram_idx, x_pad_0, dst); + memcpy(&dst[sram_idx][0], + (const DATA_T*) &src[dram_idx * MAT_AXI_RATIO], + x_size * ELEM_BYTES); + sram_idx += x_size; + dram_idx += x_stride; + reset_mem(sram_idx, x_pad_1, dst); + } + reset_mem(sram_idx, y_offset_1, dst); +} + +template +void load_2d( + volatile DATA_T *src, + DATA_T dst[][MAT_AXI_RATIO], + memop_sram_T sram_idx, + memop_dram_T dram_idx, + memop_size_T y_size, + memop_size_T x_size, + memop_stride_T x_stride) { +#pragma HLS INLINE + + for (int y = 0; y < y_size; y++) { + memcpy(&dst[sram_idx][0], + (const DATA_T*) &src[dram_idx * MAT_AXI_RATIO], + x_size * ELEM_BYTES); +#pragma HLS RESOURCE variable = sram_idx core = Mul_LUT + sram_idx += x_size; + dram_idx += x_stride; + } +} + +template +void read_tensor( + IDX_T idx, + WIDE_T src[][NARROW_W * Y_DIM * X_DIM / WIDE_W], + NARROW_T dst[Y_DIM][X_DIM]) { +#pragma HLS INLINE + + // Read in weight tensor + for (int p = 0; p < NARROW_W * Y_DIM * X_DIM / WIDE_W; p++) { + WIDE_T packet = src[idx][p]; + for (int w = 0; w < (WIDE_W / NARROW_W); w++) { + int x = (p * (WIDE_W / NARROW_W) + w) / X_DIM; + int y = (p * (WIDE_W / NARROW_W) + w) % X_DIM; + dst[x][y] = (NARROW_T) packet.range((w + 1) * NARROW_W - 1, w * NARROW_W); + } + } +} + +template +void write_tensor( + IDX_T idx, + NARROW_T src[Y_DIM][X_DIM], + WIDE_T dst[][NARROW_W * Y_DIM * X_DIM / WIDE_W]) { +#pragma HLS INLINE + + for (int p = 0; p < NARROW_W * Y_DIM * X_DIM / WIDE_W; p++) { + WIDE_T packet = 0; + for (int w = 0; w < (WIDE_W / NARROW_W); w++) { + int x = (p * (WIDE_W / NARROW_W) + w) / X_DIM; + int y = (p * (WIDE_W / NARROW_W) + w) % X_DIM; + packet.range((w + 1) * NARROW_W - 1, w * NARROW_W) = src[x][y]; + } + dst[idx][p] = packet; + } +} + void fetch( uint32_t insn_count, volatile insn_T *insns, @@ -26,61 +127,37 @@ void fetch( INSN_DECODE: for (int pc = 0; pc < insn_count; pc++) { #pragma HLS PIPELINE // Read instruction fields - insn_T insn = insns[pc]; + insn_T raw_insn = insns[pc]; + VTAInsn insn; + insn.generic = *((VTAGenericInsn *) &raw_insn); // Do some partial decoding - opcode_T opcode = insn.range(VTA_INSN_MEM_0_1, VTA_INSN_MEM_0_0); - memop_id_T memory_type = insn.range(VTA_INSN_MEM_5_1, VTA_INSN_MEM_5_0); + opcode_T opcode = insn.generic.opcode; + memop_id_T memory_type = insn.mem.memory_type; // Push to appropriate instruction queue if (opcode == VTA_OPCODE_STORE) { - store_queue.write(insn); - } else if (opcode == VTA_OPCODE_LOAD && - (memory_type == VTA_MEM_ID_INP || memory_type == VTA_MEM_ID_WGT)) { - load_queue.write(insn); - } else { - gemm_queue.write(insn); - } - } -} - -void reset_mem( - memop_sram_T &sram_idx, - memop_sram_T range, - memop_id_T memory_type, - axi_T inp_mem[VTA_INP_BUFF_DEPTH][INP_MAT_AXI_RATIO], - axi_T wgt_mem[VTA_WGT_BUFF_DEPTH][WGT_MAT_AXI_RATIO] - ) { - - if (memory_type == VTA_MEM_ID_INP) { - for (int i = 0; i < range; i++) { -#pragma HLS PIPELINE - for (int j = 0; j < INP_MAT_AXI_RATIO; j++) { - inp_mem[sram_idx][j] = 0; - } - sram_idx++; - } - } else { - for (int i = 0; i < range; i++) { -#pragma HLS PIPELINE - for (int j = 0; j < WGT_MAT_AXI_RATIO; j++) { - wgt_mem[sram_idx][j] = 0; + store_queue.write(raw_insn); + } else if (opcode == VTA_OPCODE_LOAD) { + if (memory_type == VTA_MEM_ID_INP || memory_type == VTA_MEM_ID_WGT) { + load_queue.write(raw_insn); + } else { + gemm_queue.write(raw_insn); } - sram_idx++; + } else { + gemm_queue.write(raw_insn); } } - } void load( - volatile axi_T *inputs, - volatile axi_T *weights, + volatile bus_T *inputs, + volatile bus_T *weights, hls::stream &load_queue, hls::stream &g2l_dep_queue, hls::stream &l2g_dep_queue, - axi_T inp_mem[VTA_INP_BUFF_DEPTH][INP_MAT_AXI_RATIO], - axi_T wgt_mem[VTA_WGT_BUFF_DEPTH][WGT_MAT_AXI_RATIO] - ) { -#pragma HLS INTERFACE m_axi port = weights offset = slave bundle = data_port + bus_T inp_mem[VTA_INP_BUFF_DEPTH][INP_MAT_AXI_RATIO], + bus_T wgt_mem[VTA_WGT_BUFF_DEPTH][WGT_MAT_AXI_RATIO]) { #pragma HLS INTERFACE m_axi port = inputs offset = slave bundle = data_port +#pragma HLS INTERFACE m_axi port = weights offset = slave bundle = data_port #pragma HLS INTERFACE axis port = load_queue #pragma HLS INTERFACE axis port = g2l_dep_queue #pragma HLS INTERFACE axis port = l2g_dep_queue @@ -91,106 +168,248 @@ void load( #pragma HLS RESOURCE variable = wgt_mem core = RAM_1P // Pop load instruction - insn_T insn = load_queue.read(); - - // Decode instruction - bool pop_prev_dependence = insn[VTA_INSN_MEM_1]; - bool pop_next_dependence = insn[VTA_INSN_MEM_2]; - bool push_prev_dependence = insn[VTA_INSN_MEM_3]; - bool push_next_dependence = insn[VTA_INSN_MEM_4]; - memop_id_T memory_type = insn.range(VTA_INSN_MEM_5_1, VTA_INSN_MEM_5_0); - memop_sram_T sram_base = insn.range(VTA_INSN_MEM_6_1, VTA_INSN_MEM_6_0); - memop_dram_T dram_base = insn.range(VTA_INSN_MEM_7_1, VTA_INSN_MEM_7_0); - memop_size_T y_size = insn.range(VTA_INSN_MEM_8_1, VTA_INSN_MEM_8_0); - memop_size_T x_size = insn.range(VTA_INSN_MEM_9_1, VTA_INSN_MEM_9_0); - memop_stride_T x_stride = insn.range(VTA_INSN_MEM_A_1, VTA_INSN_MEM_A_0); - memop_pad_T y_pad_0 = insn.range(VTA_INSN_MEM_B_1, VTA_INSN_MEM_B_0); - memop_pad_T y_pad_1 = insn.range(VTA_INSN_MEM_C_1, VTA_INSN_MEM_C_0); - memop_pad_T x_pad_0 = insn.range(VTA_INSN_MEM_D_1, VTA_INSN_MEM_D_0); - memop_pad_T x_pad_1 = insn.range(VTA_INSN_MEM_E_1, VTA_INSN_MEM_E_0); + insn_T raw_insn = load_queue.read(); + // Cast to MemInsn + insn_T raw_copy = raw_insn; + VTAMemInsn insn = *((VTAMemInsn *) &raw_copy); // Pop dependence token if instructed - if (pop_next_dependence) { + if (insn.pop_next_dep) { g2l_dep_queue.read(); } - // Initialize indices - memop_sram_T sram_idx = sram_base; - memop_dram_T dram_idx = dram_base; - - // Pre-compute data and force to use no DSPs - memop_sram_T x_line = x_pad_0 + x_size + x_pad_1; - memop_sram_T y_offset_0 = x_line * y_pad_0; -#pragma HLS RESOURCE variable = y_offset_0 core = Mul_LUT - memop_sram_T y_offset_1 = x_line * y_pad_1; -#pragma HLS RESOURCE variable = y_offset_1 core = Mul_LUT - - // Skip top padding - sram_idx += y_offset_0; - if (memory_type == VTA_MEM_ID_INP) { - for (int y = 0; y < y_size; y++) { -#pragma HLS PIPELINE - // Skip left padding - sram_idx += x_pad_0; - // Data transfer - memcpy(&inp_mem[sram_idx][0], - (const axi_T*) &inputs[dram_idx * INP_MAT_AXI_RATIO], - x_size * VTA_INP_ELEM_BYTES); - sram_idx += x_size; - dram_idx += x_stride; - // Skip right Padding - sram_idx += x_pad_1; - } - } else { - for (int y = 0; y < y_size; y++) { -#pragma HLS PIPELINE - // Skip left padding - sram_idx += x_pad_0; - // Data transfer - memcpy(&wgt_mem[sram_idx][0], - (const axi_T*) &weights[dram_idx * WGT_MAT_AXI_RATIO], - x_size * VTA_WGT_ELEM_BYTES); - sram_idx += x_size; - dram_idx += x_stride; - // Skip right Padding - sram_idx += x_pad_1; - } - } - // Reset Index - sram_idx = sram_base; - - // Top padding - reset_mem(sram_idx, y_offset_0, memory_type, inp_mem, wgt_mem); - for (int y = 0; y < y_size; y++) { - // Left padding - reset_mem(sram_idx, x_pad_0, memory_type, inp_mem, wgt_mem); - // Skip line - sram_idx += x_size; - // Right Padding - reset_mem(sram_idx, x_pad_1, memory_type, inp_mem, wgt_mem); + // Pre-processing + memop_sram_T x_width = (insn.x_pad_0 + insn.x_size + insn.x_pad_1); + memop_sram_T y_offset_0 = x_width * insn.y_pad_0; +#pragma HLS RESOURCE variable = y_offset_0 core = Mul_LUT latency = 4 + memop_sram_T y_offset_1 = x_width * insn.y_pad_1; +#pragma HLS RESOURCE variable = y_offset_1 core = Mul_LUT latency = 4 + + if (insn.memory_type == VTA_MEM_ID_INP) { + load_pad_2d( + inputs, + inp_mem, + insn.sram_base, + insn.dram_base, + insn.y_size, + insn.x_size, + insn.x_stride, + insn.x_pad_0, + insn.x_pad_1, + y_offset_0, + y_offset_1); + } else if (insn.memory_type == VTA_MEM_ID_WGT) { + load_2d( + weights, + wgt_mem, + insn.sram_base, + insn.dram_base, + insn.y_size, + insn.x_size, + insn.x_stride); } - // Bottom padding - reset_mem(sram_idx, y_offset_1, memory_type, inp_mem, wgt_mem); // Push dependence token if instructed - if (push_next_dependence) { + if (insn.push_next_dep) { l2g_dep_queue.write(1); } } +void gemm( + insn_T insn_raw, + uop_T uop_mem[VTA_UOP_BUFF_DEPTH], + bus_T acc_mem[VTA_ACC_BUFF_DEPTH][ACC_MAT_AXI_RATIO], + bus_T inp_mem[VTA_INP_BUFF_DEPTH][INP_MAT_AXI_RATIO], + bus_T wgt_mem[VTA_WGT_BUFF_DEPTH][WGT_MAT_AXI_RATIO], + bus_T out_mem[VTA_ACC_BUFF_DEPTH][OUT_MAT_AXI_RATIO]) { +#pragma HLS INLINE + + VTAGemInsn insn = *((VTAGemInsn *) &insn_raw); + + // Loop offset + acc_idx_T dst_offset_out = 0; + inp_idx_T src_offset_out = 0; + wgt_idx_T wgt_offset_out = 0; + + // Outer Loop + EXE_OUT_LOOP: for (int it_out = 0; it_out < insn.iter_out; it_out++) { + acc_idx_T dst_offset_in = dst_offset_out; + inp_idx_T src_offset_in = src_offset_out; + wgt_idx_T wgt_offset_in = wgt_offset_out; + + // Inner Loop + EXE_IN_LOOP: for (int it_in = 0; it_in < insn.iter_in; it_in++) { + + // Iterate over micro op + READ_GEMM_UOP: for (int upc = insn.uop_bgn; upc < insn.uop_end; upc++) { + + // Read micro-op fields + uop_T uop = uop_mem[upc]; + + // Decode indices + acc_idx_T dst_idx = + uop.range(VTA_UOP_GEM_0_1, VTA_UOP_GEM_0_0) + dst_offset_in; + inp_idx_T src_idx = + uop.range(VTA_UOP_GEM_1_1, VTA_UOP_GEM_1_0) + src_offset_in; + wgt_idx_T wgt_idx = + uop.range(VTA_UOP_GEM_2_1, VTA_UOP_GEM_2_0) + wgt_offset_in; + + // Read in weight tensor + wgt_T w_tensor[VTA_BLOCK_OUT][VTA_BLOCK_IN]; + read_tensor(wgt_idx, wgt_mem, w_tensor); + // Read in input tensor + inp_T i_tensor[VTA_BATCH][VTA_BLOCK_IN]; + read_tensor(src_idx, inp_mem, i_tensor); + // Read in accum tensor + reg_T a_tensor[VTA_BATCH][VTA_BLOCK_OUT]; + read_tensor(dst_idx, acc_mem, a_tensor); + // Output tensor + out_T o_tensor[VTA_BATCH][VTA_BLOCK_OUT]; + + // Inner GEMM loop + for (int b = 0; b < VTA_BATCH; b++) { + for (int oc = 0; oc < VTA_BLOCK_OUT; oc++) { + // Initialize the accumulator values + reg_T accum = a_tensor[b][oc]; + // Dot product sum + sum_T tmp = 0; + // Inner matrix multiplication loop (input channel/feature) + for (int ic = 0; ic < VTA_BLOCK_IN; ic++) { + wgt_T w_elem = w_tensor[oc][ic]; + inp_T i_elem = i_tensor[b][ic]; + mul_T prod_dsp = i_elem * w_elem; + tmp += (sum_T) prod_dsp; + } + // Update summation + accum += (reg_T) tmp; + // Write back result acc_mem + a_tensor[b][oc] = insn.reset_reg ? (reg_T) 0 : accum; + // And output vector + o_tensor[b][oc] = (out_T) accum.range(VTA_OUT_WIDTH - 1, 0); + } + } + + // Write the results back into accumulator + write_tensor(dst_idx, a_tensor, acc_mem); + // Write the results back in the output buffer + write_tensor(dst_idx, o_tensor, out_mem); + } + // Update offsets + dst_offset_in += insn.dst_factor_in; + src_offset_in += insn.src_factor_in; + wgt_offset_in += insn.wgt_factor_in; + } + // Update offsets + dst_offset_out += insn.dst_factor_out; + src_offset_out += insn.src_factor_out; + wgt_offset_out += insn.wgt_factor_out; + } +} + +void alu( + insn_T insn_raw, + uop_T uop_mem[VTA_UOP_BUFF_DEPTH], + bus_T acc_mem[VTA_ACC_BUFF_DEPTH][ACC_MAT_AXI_RATIO], + bus_T inp_mem[VTA_INP_BUFF_DEPTH][INP_MAT_AXI_RATIO], + bus_T wgt_mem[VTA_WGT_BUFF_DEPTH][WGT_MAT_AXI_RATIO], + bus_T out_mem[VTA_ACC_BUFF_DEPTH][OUT_MAT_AXI_RATIO]) { +#pragma HLS INLINE + + VTAAluInsn insn = *((VTAAluInsn *) &insn_raw); + + // Loop offset + acc_idx_T dst_offset_out = 0; + inp_idx_T src_offset_out = 0; + + // Outer Loop + EXE_OUT_LOOP: for (int it_out = 0; it_out < insn.iter_out; it_out++) { + acc_idx_T dst_offset_in = dst_offset_out; + inp_idx_T src_offset_in = src_offset_out; + + // Inner Loop + EXE_IN_LOOP: for (int it_in = 0; it_in < insn.iter_in; it_in++) { + // Iterate over micro op + READ_ALU_UOP: for (int upc = insn.uop_bgn; upc < insn.uop_end; upc++) { + // Read micro-op fields + uop_T uop = uop_mem[upc]; + + // Decode + acc_idx_T dst_idx = + uop.range(VTA_UOP_ALU_0_1, VTA_UOP_ALU_0_0) + dst_offset_in; + acc_idx_T src_idx = + uop.range(VTA_UOP_ALU_1_1, VTA_UOP_ALU_1_0) + src_offset_in; + + // Read in src tensor + reg_T src_tensor[VTA_BATCH][VTA_BLOCK_OUT]; + read_tensor(src_idx, acc_mem, src_tensor); + // Read in dst tensor + reg_T dst_tensor[VTA_BATCH][VTA_BLOCK_OUT]; + read_tensor(dst_idx, acc_mem, dst_tensor); + // Output tensor + out_T o_tensor[VTA_BATCH][VTA_BLOCK_OUT]; + + // Perform ALU op over matrix elements + for (int i = 0; i < VTA_BATCH; i++) { + for (int b = 0; b < VTA_BLOCK_OUT; b++) { + // Read in operands + reg_T src_0 = dst_tensor[i][b]; + reg_T src_1 = insn.use_imm ? (reg_T) insn.imm : src_tensor[i][b]; + aluop_shr_arg_T shft_by = src_1.range(VTA_SHR_ARG_BIT_WIDTH - 1, 0); + aluop_mul_arg_T mul_by = src_1.range(VTA_MUL_ARG_BIT_WIDTH - 1, 0); + if (insn.alu_opcode == VTA_ALU_OPCODE_MIN || insn.alu_opcode == VTA_ALU_OPCODE_MAX) { + // Compute Min/Max + reg_T mix_val = src_0 < src_1 ? + (insn.alu_opcode == VTA_ALU_OPCODE_MIN ? src_0 : src_1) : + (insn.alu_opcode == VTA_ALU_OPCODE_MIN ? src_1 : src_0); + dst_tensor[i][b] = mix_val; + o_tensor[i][b] = (out_T) mix_val.range(VTA_OUT_WIDTH - 1, 0); + } else if (insn.alu_opcode == VTA_ALU_OPCODE_ADD) { + // Compute Sum + reg_T add_val = + src_0.range(VTA_REG_WIDTH - 1, 0) + src_1.range(VTA_REG_WIDTH - 1, 0); + dst_tensor[i][b] = add_val; + o_tensor[i][b] = (out_T) add_val.range(VTA_OUT_WIDTH - 1, 0); + } else if (insn.alu_opcode == VTA_ALU_OPCODE_SHR) { + // Compute Shift Right + reg_T shr_val = src_0 >> shft_by; + dst_tensor[i][b] = shr_val; + o_tensor[i][b] = (out_T) shr_val.range(VTA_OUT_WIDTH - 1, 0); + } else if (insn.alu_opcode == VTA_ALU_OPCODE_MUL) { + // Compute Product + reg_T prod_val = src_0 * mul_by; + dst_tensor[i][b] = prod_val; + o_tensor[i][b] = (out_T) prod_val.range(VTA_OUT_WIDTH - 1, 0); + } + } + } + + // Write the results back into accumulator + write_tensor(dst_idx, dst_tensor, acc_mem); + // Write the results back in the output buffer + write_tensor(dst_idx, o_tensor, out_mem); + } + // Update offsets + dst_offset_in += insn.dst_factor_in; + src_offset_in += insn.src_factor_in; + } + // Update offsets + dst_offset_out += insn.dst_factor_out; + src_offset_out += insn.src_factor_out; + } +} + void compute( volatile uint32_t &done, volatile uop_T *uops, - volatile axi_T *biases, + volatile bus_T *biases, hls::stream &gemm_queue, hls::stream &l2g_dep_queue, hls::stream &s2g_dep_queue, hls::stream &g2l_dep_queue, hls::stream &g2s_dep_queue, - axi_T inp_mem[VTA_INP_BUFF_DEPTH][INP_MAT_AXI_RATIO], - axi_T wgt_mem[VTA_WGT_BUFF_DEPTH][WGT_MAT_AXI_RATIO], - axi_T out_mem[VTA_ACC_BUFF_DEPTH][OUT_MAT_AXI_RATIO] - ) { + bus_T inp_mem[VTA_INP_BUFF_DEPTH][INP_MAT_AXI_RATIO], + bus_T wgt_mem[VTA_WGT_BUFF_DEPTH][WGT_MAT_AXI_RATIO], + bus_T out_mem[VTA_ACC_BUFF_DEPTH][OUT_MAT_AXI_RATIO]) { #pragma HLS INTERFACE s_axilite port = done bundle = CONTROL_BUS #pragma HLS INTERFACE m_axi port = uops offset = slave bundle = uop_port #pragma HLS INTERFACE m_axi port = biases offset = slave bundle = data_port @@ -211,330 +430,76 @@ void compute( static uop_T uop_mem[VTA_UOP_BUFF_DEPTH]; // Accumulator storage - static axi_T acc_mem[VTA_ACC_BUFF_DEPTH][ACC_MAT_AXI_RATIO]; + static bus_T acc_mem[VTA_ACC_BUFF_DEPTH][ACC_MAT_AXI_RATIO]; #pragma HLS ARRAY_RESHAPE variable = acc_mem complete dim=2 // This is necessary to obtain II=1 #pragma HLS DEPENDENCE variable = acc_mem inter false // Pop GEMM instruction - insn_T insn = gemm_queue.read(); - - // Decode - opcode_T opcode = insn.range(VTA_INSN_MEM_0_1, VTA_INSN_MEM_0_0); - bool pop_prev_dependence = insn[VTA_INSN_MEM_1]; - bool pop_next_dependence = insn[VTA_INSN_MEM_2]; - bool push_prev_dependence = insn[VTA_INSN_MEM_3]; - bool push_next_dependence = insn[VTA_INSN_MEM_4]; + insn_T raw_insn = gemm_queue.read(); + // Cast to GenericInsn + VTAInsn insn; + insn_T raw_copy = raw_insn; + insn.generic = *((VTAGenericInsn *) &raw_copy); // Pop dependence token if instructed - if (pop_prev_dependence) { + if (insn.generic.pop_prev_dep) { l2g_dep_queue.read(); } - if (pop_next_dependence) { + if (insn.generic.pop_next_dep) { s2g_dep_queue.read(); } + // Set done value + done = 0; // Perform action based on opcode - if (opcode == VTA_OPCODE_FINISH) { + if (insn.generic.opcode == VTA_OPCODE_FINISH) { // Set done flag if we reach a FINISH instruction done = 1; - } else if (opcode == VTA_OPCODE_LOAD || opcode == VTA_OPCODE_STORE) { - // Set done value - done = 0; - - // Decode instruction - memop_id_T memory_type = insn.range(VTA_INSN_MEM_5_1, VTA_INSN_MEM_5_0); - memop_sram_T sram_base = insn.range(VTA_INSN_MEM_6_1, VTA_INSN_MEM_6_0); - memop_dram_T dram_base = insn.range(VTA_INSN_MEM_7_1, VTA_INSN_MEM_7_0); - memop_size_T y_size = insn.range(VTA_INSN_MEM_8_1, VTA_INSN_MEM_8_0); - memop_size_T x_size = insn.range(VTA_INSN_MEM_9_1, VTA_INSN_MEM_9_0); - memop_stride_T x_stride = insn.range(VTA_INSN_MEM_A_1, VTA_INSN_MEM_A_0); - memop_pad_T y_pad_0 = insn.range(VTA_INSN_MEM_B_1, VTA_INSN_MEM_B_0); - memop_pad_T y_pad_1 = insn.range(VTA_INSN_MEM_C_1, VTA_INSN_MEM_C_0); - memop_pad_T x_pad_0 = insn.range(VTA_INSN_MEM_D_1, VTA_INSN_MEM_D_0); - memop_pad_T x_pad_1 = insn.range(VTA_INSN_MEM_E_1, VTA_INSN_MEM_E_0); - + } else if (insn.generic.opcode == VTA_OPCODE_LOAD) { // Initialize indices - memop_sram_T sram_idx = sram_base; - memop_dram_T dram_idx = dram_base; - - if (memory_type == VTA_MEM_ID_UOP) { + memop_sram_T sram_idx = insn.mem.sram_base; + memop_dram_T dram_idx = insn.mem.dram_base; + if (insn.mem.memory_type == VTA_MEM_ID_UOP) { // Perform data transfer - memcpy(&uop_mem[sram_base], - (const uop_T*) &uops[dram_base], - x_size * sizeof(uop_T)); - } else { + memcpy(&uop_mem[sram_idx], + (const uop_T*) &uops[dram_idx], + insn.mem.x_size * sizeof(uop_T)); + } else if (insn.mem.memory_type == VTA_MEM_ID_ACC) { // Perform data transfer from DRAM - for (int y = 0; y < y_size; y++) { - // Perform data transfer - memcpy(&acc_mem[sram_idx][0], - (const axi_T*) &biases[dram_idx * ACC_MAT_AXI_RATIO], - x_size * VTA_ACC_ELEM_BYTES); - sram_idx += x_size; - dram_idx += x_stride; - } - } - } else if (opcode == VTA_OPCODE_GEMM || opcode == VTA_OPCODE_ALU) { - // Set done value - done = 0; - - // Decode - bool reset_out = insn[VTA_INSN_GEM_5]; - uop_idx_T uop_bgn = insn.range(VTA_INSN_GEM_6_1, VTA_INSN_GEM_6_0); - uop_idx_T uop_end = insn.range(VTA_INSN_GEM_7_1, VTA_INSN_GEM_7_0); - loop_T iter_out = insn.range(VTA_INSN_GEM_8_1, VTA_INSN_GEM_8_0); - loop_T iter_in = insn.range(VTA_INSN_GEM_9_1, VTA_INSN_GEM_9_0); - acc_idx_T dst_factor_out = insn.range(VTA_INSN_GEM_A_1, VTA_INSN_GEM_A_0); - acc_idx_T dst_factor_in = insn.range(VTA_INSN_GEM_B_1, VTA_INSN_GEM_B_0); - inp_idx_T src_factor_out = insn.range(VTA_INSN_GEM_C_1, VTA_INSN_GEM_C_0); - inp_idx_T src_factor_in = insn.range(VTA_INSN_GEM_D_1, VTA_INSN_GEM_D_0); - - // GEMM-specific fields - wgt_idx_T wgt_factor_out = insn.range(VTA_INSN_GEM_E_1, VTA_INSN_GEM_E_0); - wgt_idx_T wgt_factor_in = insn.range(VTA_INSN_GEM_F_1, VTA_INSN_GEM_F_0); - - // ALU-specific field - aluop_opcode_T alu_opcode = insn.range(VTA_INSN_ALU_E_1, VTA_INSN_ALU_E_0); - bool use_imm = insn[VTA_INSN_ALU_F]; - aluop_imm_T imm = insn.range(VTA_INSN_ALU_G_1, VTA_INSN_ALU_G_0); - acc_idx_T dst_offset_out = 0; - inp_idx_T src_offset_out = 0; - wgt_idx_T wgt_offset_out = 0; - - // Outer Loop - EXE_OUT_LOOP: for (int it_out = 0; it_out < iter_out; it_out++) { - acc_idx_T dst_offset_in = dst_offset_out; - inp_idx_T src_offset_in = src_offset_out; - wgt_idx_T wgt_offset_in = wgt_offset_out; - - // Inner Loop - EXE_IN_LOOP: for (int it_in = 0; it_in < iter_in; it_in++) { - // Perform appropriate computation based on opcode - if (opcode == VTA_OPCODE_GEMM) { - // Iterate over micro op - READ_GEMM_UOP: for (int upc = uop_bgn; upc < uop_end; upc++) { - - // Read micro-op fields - uop_T uop = uop_mem[upc]; - - // Decode indices - acc_idx_T dst_idx = - uop.range(VTA_UOP_GEM_0_1, VTA_UOP_GEM_0_0) + dst_offset_in; - inp_idx_T src_idx = - uop.range(VTA_UOP_GEM_1_1, VTA_UOP_GEM_1_0) + src_offset_in; - wgt_idx_T wgt_idx = - uop.range(VTA_UOP_GEM_2_1, VTA_UOP_GEM_2_0) + wgt_offset_in; - - // Read in weight tensor - wgt_T w_tensor[VTA_BLOCK_OUT][VTA_BLOCK_IN]; - for (int p = 0; p < WGT_MAT_AXI_RATIO; p++) { - axi_T packet = wgt_mem[wgt_idx][p]; - for (int w = 0; w < AXI_WGT_RATIO; w++) { - int oc_idx = (p * AXI_WGT_RATIO + w) / VTA_BLOCK_IN; - int ic_idx = (p * AXI_WGT_RATIO + w) % VTA_BLOCK_IN; - w_tensor[oc_idx][ic_idx] = - packet.range((w + 1) * VTA_WGT_WIDTH - 1, w * VTA_WGT_WIDTH); - } - } - - // Read in input tensor - inp_T i_tensor[VTA_BATCH][VTA_BLOCK_IN]; - for (int p = 0; p < INP_MAT_AXI_RATIO; p++) { - axi_T packet = inp_mem[src_idx][p]; - for (int w = 0; w < AXI_INP_RATIO; w++) { - int b_idx = (p * AXI_INP_RATIO + w) / VTA_BLOCK_IN; - int ic_idx = (p * AXI_INP_RATIO + w) % VTA_BLOCK_IN; - i_tensor[b_idx][ic_idx] = - packet.range((w + 1) * VTA_INP_WIDTH - 1, w * VTA_INP_WIDTH); - } - } - - // Read in accum tensor - reg_T a_tensor[VTA_BATCH][VTA_BLOCK_OUT]; - for (int p = 0; p < ACC_MAT_AXI_RATIO; p++) { - axi_T packet = acc_mem[dst_idx][p]; - for (int w = 0; w < AXI_ACC_RATIO; w++) { - int b_idx = (p * AXI_ACC_RATIO + w) / VTA_BLOCK_OUT; - int oc_idx = (p * AXI_ACC_RATIO + w) % VTA_BLOCK_OUT; - a_tensor[b_idx][oc_idx] = - packet.range(w * VTA_ACC_WIDTH + VTA_REG_WIDTH - 1, w * VTA_ACC_WIDTH); - } - } - - // Output tensor - out_T o_tensor[VTA_BATCH][VTA_BLOCK_OUT]; - - // Inner GEMM loop - for (int b = 0; b < VTA_BATCH; b++) { - for (int oc = 0; oc < VTA_BLOCK_OUT; oc++) { - // Initialize the accumulator values - reg_T accum = a_tensor[b][oc]; - // Dot product sum - sum_T tmp = 0; - // Inner matrix multiplication loop (input channel/feature) - for (int ic = 0; ic < VTA_BLOCK_IN; ic++) { - wgt_T w_elem = w_tensor[oc][ic]; - inp_T i_elem = i_tensor[b][ic]; - mul_T prod = i_elem * w_elem; - tmp += (sum_T) prod; - } - // Update summation - accum += (reg_T) tmp; - // Write back result acc_mem - a_tensor[b][oc] = reset_out ? (reg_T) 0 : accum; - // And output vector - o_tensor[b][oc] = (out_T) accum.range(VTA_OUT_WIDTH - 1, 0); - } - } - - // Write the results back into accumulator - for (int p = 0; p < ACC_MAT_AXI_RATIO; p++) { - axi_T packet = 0; - for (int w = 0; w < AXI_ACC_RATIO; w++) { - int b_idx = (p * AXI_ACC_RATIO + w) / VTA_BLOCK_OUT; - int oc_idx = (p * AXI_ACC_RATIO + w) % VTA_BLOCK_OUT; - packet.range((w + 1) * VTA_ACC_WIDTH - 1, w * VTA_ACC_WIDTH) = - (acc_T) a_tensor[b_idx][oc_idx]; - } - acc_mem[dst_idx][p] = packet; - } - - // Write the results back in the output buffer - for (int p = 0; p < OUT_MAT_AXI_RATIO; p++) { - axi_T packet = 0; - for (int w = 0; w < AXI_OUT_RATIO; w++) { - int b_idx = (p * AXI_OUT_RATIO + w) / VTA_BLOCK_OUT; - int oc_idx = (p * AXI_OUT_RATIO + w) % VTA_BLOCK_OUT; - packet.range((w + 1) * VTA_OUT_WIDTH - 1, w * VTA_OUT_WIDTH) = - o_tensor[b_idx][oc_idx]; - } - out_mem[dst_idx][p] = packet; - } - } - } else if (opcode == VTA_OPCODE_ALU) { - // Iterate over micro op - READ_ALU_UOP: for (int upc = uop_bgn; upc < uop_end; upc++) { - // Read micro-op fields - uop_T uop = uop_mem[upc]; - - // Decode - acc_idx_T dst_idx = - uop.range(VTA_UOP_ALU_0_1, VTA_UOP_ALU_0_0) + dst_offset_in; - acc_idx_T src_idx = - uop.range(VTA_UOP_ALU_1_1, VTA_UOP_ALU_1_0) + src_offset_in; - - // Read in src tensor - reg_T src_tensor[VTA_BATCH][VTA_BLOCK_OUT]; - for (int p = 0; p < ACC_MAT_AXI_RATIO; p++) { - axi_T packet = acc_mem[src_idx][p]; - for (int w = 0; w < AXI_ACC_RATIO; w++) { - int b_idx = (p * AXI_ACC_RATIO + w) / VTA_BLOCK_OUT; - int oc_idx = (p * AXI_ACC_RATIO + w) % VTA_BLOCK_OUT; - src_tensor[b_idx][oc_idx] = - packet.range(w * VTA_ACC_WIDTH + VTA_REG_WIDTH - 1, w * VTA_ACC_WIDTH); - } - } - - // Read in dst tensor - reg_T dst_tensor[VTA_BATCH][VTA_BLOCK_OUT]; - for (int p = 0; p < ACC_MAT_AXI_RATIO; p++) { - axi_T packet = acc_mem[dst_idx][p]; - for (int w = 0; w < AXI_ACC_RATIO; w++) { - int b_idx = (p * AXI_ACC_RATIO + w) / VTA_BLOCK_OUT; - int oc_idx = (p * AXI_ACC_RATIO + w) % VTA_BLOCK_OUT; - dst_tensor[b_idx][oc_idx] = - packet.range(w * VTA_ACC_WIDTH + VTA_REG_WIDTH - 1, w * VTA_ACC_WIDTH); - } - } - - // Output tensor - out_T o_tensor[VTA_BATCH][VTA_BLOCK_OUT]; - - // Perform ALU op over matrix elements - for (int i = 0; i < VTA_BATCH; i++) { - for (int b = 0; b < VTA_BLOCK_OUT; b++) { - // Read in operands - reg_T src_0 = dst_tensor[i][b]; - reg_T src_1 = use_imm ? (reg_T) imm : src_tensor[i][b]; - aluop_shr_arg_T shft_by = src_1.range(VTA_SHR_ARG_BIT_WIDTH - 1, 0); - aluop_mul_arg_T mul_by = src_1.range(VTA_MUL_ARG_BIT_WIDTH - 1, 0); - if (alu_opcode == VTA_ALU_OPCODE_MIN || alu_opcode == VTA_ALU_OPCODE_MAX) { - // Compute Min/Max - reg_T mix_val = src_0 < src_1 ? - (alu_opcode == VTA_ALU_OPCODE_MIN ? src_0 : src_1) : - (alu_opcode == VTA_ALU_OPCODE_MIN ? src_1 : src_0); - dst_tensor[i][b] = mix_val; - o_tensor[i][b] = (out_T) mix_val.range(VTA_OUT_WIDTH - 1, 0); - } else if (alu_opcode == VTA_ALU_OPCODE_ADD) { - // Compute Sum - reg_T add_val = - src_0.range(VTA_REG_WIDTH - 1, 0) + src_1.range(VTA_REG_WIDTH - 1, 0); - dst_tensor[i][b] = add_val; - o_tensor[i][b] = (out_T) add_val.range(VTA_OUT_WIDTH - 1, 0); - } else if (alu_opcode == VTA_ALU_OPCODE_SHR) { - // Compute Shift Right - reg_T shr_val = src_0 >> shft_by; - dst_tensor[i][b] = shr_val; - o_tensor[i][b] = (out_T) shr_val.range(VTA_OUT_WIDTH-1, 0); - } - } - } - - // Write the results back into accumulator - for (int p = 0; p < ACC_MAT_AXI_RATIO; p++) { - axi_T packet = 0; - for (int w = 0; w < AXI_ACC_RATIO; w++) { - int b_idx = (p * AXI_ACC_RATIO + w) / VTA_BLOCK_OUT; - int oc_idx = (p * AXI_ACC_RATIO + w) % VTA_BLOCK_OUT; - packet.range((w + 1) * VTA_ACC_WIDTH - 1, w * VTA_ACC_WIDTH) = - (acc_T) dst_tensor[b_idx][oc_idx]; - } - acc_mem[dst_idx][p] = packet; - } - - // Write the results back in the output buffer - for (int p = 0; p < OUT_MAT_AXI_RATIO; p++) { - axi_T packet = 0; - for (int w = 0; w < AXI_OUT_RATIO; w++) { - int b_idx = (p * AXI_OUT_RATIO + w) / VTA_BLOCK_OUT; - int oc_idx = (p * AXI_OUT_RATIO + w) % VTA_BLOCK_OUT; - packet.range((w + 1) * VTA_OUT_WIDTH - 1, w * VTA_OUT_WIDTH) = - o_tensor[b_idx][oc_idx]; - } - out_mem[dst_idx][p] = packet; - } - } - } - - // Update offsets - dst_offset_in += dst_factor_in; - src_offset_in += src_factor_in; - wgt_offset_in += wgt_factor_in; - } - - // Update offsets - dst_offset_out += dst_factor_out; - src_offset_out += src_factor_out; - wgt_offset_out += wgt_factor_out; + load_2d( + biases, + acc_mem, + sram_idx, + dram_idx, + insn.mem.y_size, + insn.mem.x_size, + insn.mem.x_stride); } + } else if (insn.generic.opcode == VTA_OPCODE_GEMM) { + gemm(raw_copy, uop_mem, acc_mem, inp_mem, wgt_mem, out_mem); } +#ifdef ALU_EN + else if (insn.generic.opcode == VTA_OPCODE_ALU) { + alu(raw_copy, uop_mem, acc_mem, inp_mem, wgt_mem, out_mem); + } +#endif // VTA_ALU_EN // Push dependence token if instructed - if (push_prev_dependence) { + if (insn.generic.push_prev_dep) { g2l_dep_queue.write(1); } - if (push_next_dependence) { + if (insn.generic.push_next_dep) { g2s_dep_queue.write(1); } } void store( - volatile axi_T *outputs, + volatile bus_T *outputs, hls::stream &store_queue, hls::stream &g2s_dep_queue, hls::stream &s2g_dep_queue, - axi_T out_mem[VTA_ACC_BUFF_DEPTH][OUT_MAT_AXI_RATIO] - ) { + bus_T out_mem[VTA_ACC_BUFF_DEPTH][OUT_MAT_AXI_RATIO]) { #pragma HLS INTERFACE m_axi port = outputs offset = slave bundle = data_port #pragma HLS INTERFACE axis port = store_queue #pragma HLS INTERFACE axis port = g2s_dep_queue @@ -543,49 +508,36 @@ void store( #pragma HLS INTERFACE s_axilite port = return bundle = CONTROL_BUS #pragma HLS RESOURCE variable = out_mem core = RAM_1P - // Load buffer - insn_T insn = store_queue.read(); - - // Decode - bool pop_prev_dependence = insn[VTA_INSN_MEM_1]; - bool pop_next_dependence = insn[VTA_INSN_MEM_2]; - bool push_prev_dependence = insn[VTA_INSN_MEM_3]; - bool push_next_dependence = insn[VTA_INSN_MEM_4]; - memop_id_T memory_type = insn.range(VTA_INSN_MEM_5_1, VTA_INSN_MEM_5_0); - memop_sram_T sram_base = insn.range(VTA_INSN_MEM_6_1, VTA_INSN_MEM_6_0); - memop_dram_T dram_base = insn.range(VTA_INSN_MEM_7_1, VTA_INSN_MEM_7_0); - memop_size_T y_size = insn.range(VTA_INSN_MEM_8_1, VTA_INSN_MEM_8_0); - memop_size_T x_size = insn.range(VTA_INSN_MEM_9_1, VTA_INSN_MEM_9_0); - memop_stride_T x_stride = insn.range(VTA_INSN_MEM_A_1, VTA_INSN_MEM_A_0); - memop_pad_T y_pad_0 = insn.range(VTA_INSN_MEM_B_1, VTA_INSN_MEM_B_0); - memop_pad_T y_pad_1 = insn.range(VTA_INSN_MEM_C_1, VTA_INSN_MEM_C_0); - memop_pad_T x_pad_0 = insn.range(VTA_INSN_MEM_D_1, VTA_INSN_MEM_D_0); - memop_pad_T x_pad_1 = insn.range(VTA_INSN_MEM_E_1, VTA_INSN_MEM_E_0); + // Pop store instruction + insn_T raw_insn = store_queue.read(); + // Cast to MemInsn + insn_T raw_copy = raw_insn; + VTAMemInsn insn = *((VTAMemInsn *) &raw_copy); // Pop dependence token if instructed - if (pop_prev_dependence) { + if (insn.pop_prev_dep) { g2s_dep_queue.read(); } // Initialize indices - memop_sram_T sram_idx = sram_base; - memop_dram_T dram_idx = dram_base; + memop_sram_T sram_idx = insn.sram_base; + memop_dram_T dram_idx = insn.dram_base; // Copy along y dimension - for (int y = 0; y < y_size; y++) { + for (int y = 0; y < insn.y_size; y++) { #pragma HLS PIPELINE // Perform data transfer memcpy( - const_cast(&outputs[dram_idx * OUT_MAT_AXI_RATIO]), - (const axi_T*) &out_mem[sram_idx][0], - x_size * VTA_OUT_ELEM_BYTES); + const_cast(&outputs[dram_idx * OUT_MAT_AXI_RATIO]), + (const bus_T*) &out_mem[sram_idx][0], + insn.x_size * VTA_OUT_ELEM_BYTES); #pragma HLS RESOURCE variable = sram_idx core = Mul_LUT - sram_idx += x_size; - dram_idx += x_stride; + sram_idx += insn.x_size; + dram_idx += insn.x_stride; } // Push dependence token if instructed - if (push_prev_dependence) { + if (insn.push_prev_dep) { s2g_dep_queue.write(1); } } @@ -594,10 +546,10 @@ void vta( uint32_t insn_count, volatile insn_T *insns, volatile uop_T *uops, - volatile axi_T *inputs, - volatile axi_T *weights, - volatile axi_T *biases, - volatile axi_T *outputs) { + volatile bus_T *inputs, + volatile bus_T *weights, + volatile bus_T *biases, + volatile bus_T *outputs) { #pragma HLS INTERFACE s_axilite port = insn_count bundle = CONTROL_BUS #pragma HLS INTERFACE m_axi port = insns offset = slave bundle = ins_port #pragma HLS INTERFACE m_axi port = uops offset = slave bundle = uop_port @@ -624,9 +576,9 @@ void vta( hls::stream g2s_dep_queue; // Instantiate memories - axi_T inp_mem[VTA_INP_BUFF_DEPTH][INP_MAT_AXI_RATIO]; - axi_T wgt_mem[VTA_WGT_BUFF_DEPTH][WGT_MAT_AXI_RATIO]; - axi_T out_mem[VTA_ACC_BUFF_DEPTH][OUT_MAT_AXI_RATIO]; + bus_T inp_mem[VTA_INP_BUFF_DEPTH][INP_MAT_AXI_RATIO]; + bus_T wgt_mem[VTA_WGT_BUFF_DEPTH][WGT_MAT_AXI_RATIO]; + bus_T out_mem[VTA_ACC_BUFF_DEPTH][OUT_MAT_AXI_RATIO]; // Push all instructions into the queues fetch(insn_count, insns, tmp_load_queue, tmp_gemm_queue, tmp_store_queue); @@ -655,9 +607,9 @@ void vta( tmp_load_popped = true; } // Check dependences and invoke the load stage - bool pop_next_dependence = tmp_load[VTA_INSN_MEM_2]; - if ((pop_next_dependence && !g2l_dep_queue.empty()) || - !pop_next_dependence) { + VTAGenericInsn insn = *((VTAGenericInsn *) &tmp_load); + if ((insn.pop_next_dep && !g2l_dep_queue.empty()) || + !insn.pop_next_dep) { // Push the instruction in the load queue load_queue.write(tmp_load); tmp_load_popped = false; @@ -675,16 +627,15 @@ void vta( tmp_gemm_popped = true; } // Check dependences and invoke the load stage - bool pop_prev_dependence = tmp_gemv[VTA_INSN_MEM_1]; - bool pop_next_dependence = tmp_gemv[VTA_INSN_MEM_2]; + VTAGenericInsn insn = *((VTAGenericInsn *) &tmp_gemv); if ( - (pop_prev_dependence && !l2g_dep_queue.empty() && - pop_next_dependence && !s2g_dep_queue.empty()) || - (!pop_prev_dependence && pop_next_dependence && + (insn.pop_prev_dep && !l2g_dep_queue.empty() && + insn.pop_next_dep && !s2g_dep_queue.empty()) || + (!insn.pop_prev_dep && insn.pop_next_dep && !s2g_dep_queue.empty()) || - (pop_prev_dependence && !l2g_dep_queue.empty() && - !pop_next_dependence) || - (!pop_prev_dependence && !pop_next_dependence) + (insn.pop_prev_dep && !l2g_dep_queue.empty() && + !insn.pop_next_dep) || + (!insn.pop_prev_dep && !insn.pop_next_dep) ) { // Push the instruction in the load queue gemm_queue.write(tmp_gemv); @@ -705,9 +656,10 @@ void vta( tmp_store_popped = true; } // Check dependences and invoke the load stage - bool pop_prev_dependence = tmp_store[VTA_INSN_MEM_1]; - if ((pop_prev_dependence && !g2s_dep_queue.empty()) || - !pop_prev_dependence) { + VTAGenericInsn insn = *((VTAGenericInsn *) &tmp_store); + + if ((insn.pop_prev_dep && !g2s_dep_queue.empty()) || + !insn.pop_prev_dep) { // Push the instruction in the load queue store_queue.write(tmp_store); tmp_store_popped = false; @@ -729,10 +681,11 @@ void vta( } } if (tmp_gemm_popped) { - if (l2g_dep_queue.empty() && tmp_gemv[VTA_INSN_MEM_1]) { + VTAGenericInsn insn = *((VTAGenericInsn *) &tmp_gemv); + if (l2g_dep_queue.empty() && insn.pop_prev_dep) { printf("waiting on l2g\n"); } - if (s2g_dep_queue.empty() && tmp_gemv[VTA_INSN_MEM_2]) { + if (s2g_dep_queue.empty() && insn.pop_next_dep) { printf("waiting on s2g\n"); } } diff --git a/vta/hardware/xilinx/src/vta.h b/vta/hardware/xilinx/src/vta.h index c991bbee87069..21a50ab7e99ad 100644 --- a/vta/hardware/xilinx/src/vta.h +++ b/vta/hardware/xilinx/src/vta.h @@ -13,8 +13,9 @@ #include -/* \typedef axi_T AXI datatype*/ -typedef ap_uint axi_T; + +/* \typedef bus_T memory bus datatype*/ +typedef ap_uint bus_T; /* \typedef uop_T Micro-op datatype*/ typedef ap_uint uop_T; @@ -124,13 +125,13 @@ void fetch( * \param wgt_mem Local weight SRAM buffer. Write only single port BRAM. */ void load( - volatile axi_T *inputs, - volatile axi_T *weights, + volatile bus_T *inputs, + volatile bus_T *weights, hls::stream &load_queue, hls::stream &g2l_dep_queue, hls::stream &l2g_dep_queue, - axi_T inp_mem[VTA_INP_BUFF_DEPTH][INP_MAT_AXI_RATIO], - axi_T wgt_mem[VTA_WGT_BUFF_DEPTH][WGT_MAT_AXI_RATIO]); + bus_T inp_mem[VTA_INP_BUFF_DEPTH][INP_MAT_AXI_RATIO], + bus_T wgt_mem[VTA_WGT_BUFF_DEPTH][WGT_MAT_AXI_RATIO]); /*! * \brief Compute module. @@ -158,15 +159,15 @@ void load( void compute( volatile uint32_t &done, volatile uop_T *uops, - volatile axi_T *biases, + volatile bus_T *biases, hls::stream &gemm_queue, hls::stream &l2g_dep_queue, hls::stream &s2g_dep_queue, hls::stream &g2l_dep_queue, hls::stream &g2s_dep_queue, - axi_T inp_mem[VTA_INP_BUFF_DEPTH][INP_MAT_AXI_RATIO], - axi_T wgt_mem[VTA_WGT_BUFF_DEPTH][WGT_MAT_AXI_RATIO], - axi_T out_mem[VTA_ACC_BUFF_DEPTH][OUT_MAT_AXI_RATIO]); + bus_T inp_mem[VTA_INP_BUFF_DEPTH][INP_MAT_AXI_RATIO], + bus_T wgt_mem[VTA_WGT_BUFF_DEPTH][WGT_MAT_AXI_RATIO], + bus_T out_mem[VTA_ACC_BUFF_DEPTH][OUT_MAT_AXI_RATIO]); /*! * \brief Store module. @@ -182,11 +183,11 @@ void compute( * \param out_mem Local output SRAM buffer. Read only single port BRAM. */ void store( - volatile axi_T *outputs, + volatile bus_T *outputs, hls::stream &store_queue, hls::stream &g2s_dep_queue, hls::stream &s2g_dep_queue, - axi_T out_mem[VTA_ACC_BUFF_DEPTH][OUT_MAT_AXI_RATIO]); + bus_T out_mem[VTA_ACC_BUFF_DEPTH][OUT_MAT_AXI_RATIO]); /*! * \brief VTA wrapper for simulation purpose only. @@ -203,9 +204,9 @@ void vta( uint32_t insn_count, volatile insn_T *insns, volatile uop_T *uops, - volatile axi_T *inputs, - volatile axi_T *weights, - volatile axi_T *biases, - volatile axi_T *outputs); + volatile bus_T *inputs, + volatile bus_T *weights, + volatile bus_T *biases, + volatile bus_T *outputs); #endif // VTA_VTA_H_ diff --git a/vta/include/vta/driver.h b/vta/include/vta/driver.h index 26d8bb0fab9e8..8fd17f64d6775 100644 --- a/vta/include/vta/driver.h +++ b/vta/include/vta/driver.h @@ -23,7 +23,7 @@ extern "C" { /*! \brief Physically contiguous buffer size limit in B */ #ifndef VTA_MAX_XFER -#define VTA_MAX_XFER (1<<22) +#define VTA_MAX_XFER (1 << 25) #endif /*! \brief Device resource context */ diff --git a/vta/include/vta/hw_spec.h b/vta/include/vta/hw_spec.h index b50c1ae5907b0..544a06c75bbb2 100644 --- a/vta/include/vta/hw_spec.h +++ b/vta/include/vta/hw_spec.h @@ -13,8 +13,8 @@ extern "C" { #include -/*! AXI bus width */ -#define VTA_AXI_WIDTH 128 +/*! Memory bus width */ +#define VTA_BUS_WIDTH (1 << VTA_LOG_BUS_WIDTH) /*! Register file width */ #define VTA_REG_WIDTH 24 @@ -35,12 +35,6 @@ extern "C" { #define VTA_OUT_WIDTH (1 << VTA_LOG_OUT_WIDTH) /*! Accumulator data type width */ #define VTA_ACC_WIDTH (1 << VTA_LOG_ACC_WIDTH) -/*! Accumulator truncation bits */ -#define VTA_ACC_TRUC_BITS 24 -/*! log2 of ALU data type width */ -#define VTA_LOG_ALU_WIDTH (VTA_LOG_ACC_WIDTH - 1) -/*! ALU data type width */ -#define VTA_ALU_WIDTH (1 << VTA_LOG_ALU_WIDTH) /*! Batch size (corresponds to A in (A,B)x(B,C) mat mult)*/ #define VTA_BATCH (1 << VTA_LOG_BATCH) @@ -49,56 +43,45 @@ extern "C" { /*! Blocking factor of the outer loop (corresponds to C in (A,B)x(B,C) mat mult) */ #define VTA_BLOCK_OUT (1 << VTA_LOG_BLOCK_OUT) +/*! On-chip micro-op buffer size in B */ +#define VTA_UOP_BUFF_SIZE (1 << VTA_LOG_UOP_BUFF_SIZE) +/*! On-chip weight buffer size in B */ +#define VTA_WGT_BUFF_SIZE (1 << VTA_LOG_WGT_BUFF_SIZE) +/*! On-chip activation buffer size in B */ +#define VTA_INP_BUFF_SIZE (1 << VTA_LOG_INP_BUFF_SIZE) +/*! On-chip accumulator buffer size in B */ +#define VTA_ACC_BUFF_SIZE (1 << VTA_LOG_ACC_BUFF_SIZE) + /*! Input vector size in bits */ #define VTA_INP_MATRIX_WIDTH (VTA_INP_WIDTH * VTA_BATCH * VTA_BLOCK_IN) /*! Weight vector size in bits */ #define VTA_WGT_MATRIX_WIDTH (VTA_WGT_WIDTH * VTA_BLOCK_OUT * VTA_BLOCK_IN) /*! Accumulator vector size in bits */ #define VTA_ACC_MATRIX_WIDTH (VTA_ACC_WIDTH * VTA_BATCH * VTA_BLOCK_OUT) -/*! Register file vector size in bits */ -#define VTA_REG_MATRIX_WIDTH (VTA_REG_WIDTH * VTA_BATCH * VTA_BLOCK_OUT) /*! Output vector size in bits */ #define VTA_OUT_MATRIX_WIDTH (VTA_OUT_WIDTH * VTA_BATCH * VTA_BLOCK_OUT) /*! Ratio between input matrix size and axi width */ -#define INP_MAT_AXI_RATIO (VTA_INP_MATRIX_WIDTH / VTA_AXI_WIDTH) +#define INP_MAT_AXI_RATIO (VTA_INP_MATRIX_WIDTH / VTA_BUS_WIDTH) /*! Ratio between weight matrix size and axi width */ -#define WGT_MAT_AXI_RATIO (VTA_WGT_MATRIX_WIDTH / VTA_AXI_WIDTH) +#define WGT_MAT_AXI_RATIO (VTA_WGT_MATRIX_WIDTH / VTA_BUS_WIDTH) /*! Ratio between accumulator matrix size and axi width */ -#define ACC_MAT_AXI_RATIO (VTA_ACC_MATRIX_WIDTH / VTA_AXI_WIDTH) +#define ACC_MAT_AXI_RATIO (VTA_ACC_MATRIX_WIDTH / VTA_BUS_WIDTH) /*! Ratio between output matrix size and axi width */ -#define OUT_MAT_AXI_RATIO (VTA_OUT_MATRIX_WIDTH / VTA_AXI_WIDTH) - -/*! Ratio between input matrix size and axi width */ -#define AXI_INP_RATIO (VTA_AXI_WIDTH / VTA_INP_WIDTH) -/*! Ratio between weight matrix size and axi width */ -#define AXI_WGT_RATIO (VTA_AXI_WIDTH / VTA_WGT_WIDTH) -/*! Ratio between accumulator matrix size and axi width */ -#define AXI_ACC_RATIO (VTA_AXI_WIDTH / VTA_ACC_WIDTH) -/*! Ratio between output matrix size and axi width */ -#define AXI_OUT_RATIO (VTA_AXI_WIDTH / VTA_OUT_WIDTH) - -/*! On-chip micro-op buffer size in B */ -#define VTA_UOP_BUFF_SIZE (1 << VTA_LOG_UOP_BUFF_SIZE) -/*! On-chip weight buffer size in B */ -#define VTA_WGT_BUFF_SIZE (1 << VTA_LOG_WGT_BUFF_SIZE) -/*! On-chip activation buffer size in B */ -#define VTA_INP_BUFF_SIZE (1 << VTA_LOG_INP_BUFF_SIZE) -/*! On-chip accumulator buffer size in B */ -#define VTA_ACC_BUFF_SIZE (1 << VTA_LOG_ACC_BUFF_SIZE) +#define OUT_MAT_AXI_RATIO (VTA_OUT_MATRIX_WIDTH / VTA_BUS_WIDTH) /*! Size of instruction buffer element in B */ #define VTA_INS_ELEM_BYTES (VTA_INS_WIDTH / 8) /*! Size of uop buffer element in B*/ #define VTA_UOP_ELEM_BYTES (VTA_UOP_WIDTH / 8) /*! Size of activation buffer element in B*/ -#define VTA_INP_ELEM_BYTES (VTA_BATCH * VTA_BLOCK_IN * VTA_INP_WIDTH / 8) +#define VTA_INP_ELEM_BYTES (VTA_INP_MATRIX_WIDTH / 8) /*! Size of weight buffer element in B*/ -#define VTA_WGT_ELEM_BYTES (VTA_BLOCK_OUT * VTA_BLOCK_IN * VTA_WGT_WIDTH / 8) +#define VTA_WGT_ELEM_BYTES (VTA_WGT_MATRIX_WIDTH / 8) /*! Size of accumulator buffer element in B*/ -#define VTA_ACC_ELEM_BYTES (VTA_BATCH * VTA_BLOCK_OUT * VTA_ACC_WIDTH / 8) +#define VTA_ACC_ELEM_BYTES (VTA_ACC_MATRIX_WIDTH / 8) /*! Size of output buffer element in B*/ -#define VTA_OUT_ELEM_BYTES (VTA_BATCH * VTA_BLOCK_OUT * VTA_OUT_WIDTH / 8) +#define VTA_OUT_ELEM_BYTES (VTA_OUT_MATRIX_WIDTH / 8) /*! On-chip micro-op buffer depth */ #define VTA_UOP_BUFF_DEPTH (VTA_UOP_BUFF_SIZE / VTA_UOP_ELEM_BYTES) @@ -181,186 +164,6 @@ extern "C" { /*! Mem ID constant: output store buffer */ #define VTA_MEM_ID_OUT 4 -// Instruction organization layout: -// -// LOAD/STORE -// _____________________________|_type______________| -// arg 0: opcode | opcode_T | -// arg 1: pop_prev_dependence | bool | -// arg 2: pop_next_dependence | bool | -// arg 3: push_prev_dependence | bool | -// arg 4: push_next_dependence | bool | -// arg 5: memory_type | memop_id_T | -// arg 6: pad_value | memop_pad_val_T | -// arg 7: sram_base | memop_sram_T | -// arg 8: dram_base | memop_dram_T | -// arg 9: y_size | memop_size_T | -// arg a: x_size | memop_size_T | -// arg b: x_stride | memop_stride_T | -// arg c: y_pad_0 | memop_pad_T | -// arg d: y_pad_1 | memop_pad_T | -// arg e: x_pad_0 | memop_pad_T | -// arg f: x_pad_1 | memop_pad_T | -// -// GEMM -// _____________________________|_type______________| -// arg 0: opcode | opcode_T | -// arg 1: pop_prev_dependence | bool | -// arg 2: pop_next_dependence | bool | -// arg 3: push_prev_dependence | bool | -// arg 4: push_next_dependence | bool | -// arg 5: reset_reg | bool | -// arg 6: uop_bgn | uop_idx_T | -// arg 7: uop_end | uop_idx_T | -// arg 8: iteration count ax0 | loop_T | -// arg 9: iteration count ax1 | loop_T | -// arg a: accum idx factor ax0 | acc_idx_T | -// arg b: accum idx factor ax1 | acc_idx_T | -// arg c: input idx factor ax0 | inp_idx_T | -// arg d: input idx factor ax1 | inp_idx_T | -// arg e: weight idx factor ax0 | wgt_idx_T | -// arg f: weight idx factor ax1 | wgt_idx_T | -// -// ALU -// _____________________________|_type______________| -// arg 0: opcode | opcode_T | -// arg 1: pop_prev_dependence | bool | -// arg 2: pop_next_dependence | bool | -// arg 3: push_prev_dependence | bool | -// arg 4: push_next_dependence | bool | -// arg 5: reset_reg | bool | -// arg 6: uop_bgn | uop_idx_T | -// arg 7: uop_end | uop_idx_T | -// arg 8: iteration count ax0 | loop_T | -// arg 9: iteration count ax1 | loop_T | -// arg a: dst idx factor ax0 | acc_idx_T | -// arg b: dst idx factor ax1 | acc_idx_T | -// arg c: src idx factor ax0 | inp_idx_T | -// arg d: src idx factor ax1 | inp_idx_T | -// arg e: alu_opcode | aluop_opcode_T | -// arg f: use_imm | bool | -// arg g: imm | alu_imm_T | - -/*! Load/Store instruction start position of the opcode field */ -#define VTA_INSN_MEM_0_0 0 -/*! Load/Store instruction end position of the opcode field */ -#define VTA_INSN_MEM_0_1 (VTA_INSN_MEM_0_0 + VTA_OPCODE_BIT_WIDTH - 1) -/*! Load/Store instruction position of the pop_prev_dep field */ -#define VTA_INSN_MEM_1 (VTA_INSN_MEM_0_1 + 1) -/*! Load/Store instruction position of the pop_next_dep field */ -#define VTA_INSN_MEM_2 (VTA_INSN_MEM_1 + 1) -/*! Load/Store instruction position of the push_prev_dependence field */ -#define VTA_INSN_MEM_3 (VTA_INSN_MEM_2 + 1) -/*! Load/Store instruction position of the push_next_dependence field */ -#define VTA_INSN_MEM_4 (VTA_INSN_MEM_3 + 1) -/*! Load/Store instruction start position of the memory_type field */ -#define VTA_INSN_MEM_5_0 (VTA_INSN_MEM_4 + 1) -/*! Load/Store instruction end position of the memory_type field */ -#define VTA_INSN_MEM_5_1 (VTA_INSN_MEM_5_0 + VTA_MEMOP_ID_BIT_WIDTH - 1) -/*! Load/Store instruction start position of the sram_base field */ -#define VTA_INSN_MEM_6_0 (VTA_INSN_MEM_5_1 + 1) -/*! Load/Store instruction end position of the sram_base field */ -#define VTA_INSN_MEM_6_1 (VTA_INSN_MEM_6_0 + VTA_MEMOP_SRAM_ADDR_BIT_WIDTH - 1) -/*! Load/Store instruction start position of the dram_base field */ -#define VTA_INSN_MEM_7_0 (VTA_INSN_MEM_6_1 + 1) -/*! Load/Store instruction end position of the dram_base field */ -#define VTA_INSN_MEM_7_1 (VTA_INSN_MEM_7_0 + VTA_MEMOP_DRAM_ADDR_BIT_WIDTH - 1) -/*! Load/Store instruction start position of the y_size field */ -#define VTA_INSN_MEM_8_0 64 -/*! Load/Store instruction end position of the y_size field */ -#define VTA_INSN_MEM_8_1 (VTA_INSN_MEM_8_0 + VTA_MEMOP_SIZE_BIT_WIDTH - 1) -/*! Load/Store instruction start position of the x_size field */ -#define VTA_INSN_MEM_9_0 (VTA_INSN_MEM_8_1 + 1) -/*! Load/Store instruction start position of the x_size field */ -#define VTA_INSN_MEM_9_1 (VTA_INSN_MEM_9_0 + VTA_MEMOP_SIZE_BIT_WIDTH - 1) -/*! Load/Store instruction start position of the x_stride field */ -#define VTA_INSN_MEM_A_0 (VTA_INSN_MEM_9_1 + 1) -/*! Load/Store instruction end position of the x_stride field */ -#define VTA_INSN_MEM_A_1 (VTA_INSN_MEM_A_0 + VTA_MEMOP_STRIDE_BIT_WIDTH - 1) -/*! Load/Store instruction start position of the y_pad_0 field */ -#define VTA_INSN_MEM_B_0 (VTA_INSN_MEM_A_1 + 1) -/*! Load/Store instruction start position of the y_pad_0 field */ -#define VTA_INSN_MEM_B_1 (VTA_INSN_MEM_B_0 + VTA_MEMOP_PAD_BIT_WIDTH - 1) -/*! Load/Store instruction start position of the y_pad_1 field */ -#define VTA_INSN_MEM_C_0 (VTA_INSN_MEM_B_1 + 1) -/*! Load/Store instruction start position of the y_pad_1 field */ -#define VTA_INSN_MEM_C_1 (VTA_INSN_MEM_C_0 + VTA_MEMOP_PAD_BIT_WIDTH - 1) -/*! Load/Store instruction start position of the x_pad_0 field */ -#define VTA_INSN_MEM_D_0 (VTA_INSN_MEM_C_1 + 1) -/*! Load/Store instruction start position of the x_pad_0 field */ -#define VTA_INSN_MEM_D_1 (VTA_INSN_MEM_D_0 + VTA_MEMOP_PAD_BIT_WIDTH - 1) -/*! Load/Store instruction start position of the x_pad_1 field */ -#define VTA_INSN_MEM_E_0 (VTA_INSN_MEM_D_1 + 1) -/*! Load/Store instruction start position of the x_pad_1 field */ -#define VTA_INSN_MEM_E_1 (VTA_INSN_MEM_E_0 + VTA_MEMOP_PAD_BIT_WIDTH - 1) - -/*! GEMM instruction start position of the opcode field */ -#define VTA_INSN_GEM_0_0 0 -/*! GEMM instruction end position of the opcode field */ -#define VTA_INSN_GEM_0_1 (VTA_INSN_GEM_0_0 + VTA_OPCODE_BIT_WIDTH - 1) -/*! GEMM instruction position of the pop_prev_dep field */ -#define VTA_INSN_GEM_1 (VTA_INSN_GEM_0_1 + 1) -/*! GEMM instruction position of the pop_next_dep field */ -#define VTA_INSN_GEM_2 (VTA_INSN_GEM_1 + 1) -/*! GEMM instruction position of the push_prev_dependence field */ -#define VTA_INSN_GEM_3 (VTA_INSN_GEM_2 + 1) -/*! GEMM instruction position of the push_next_dependence field */ -#define VTA_INSN_GEM_4 (VTA_INSN_GEM_3 + 1) -/*! GEMM instruction position of the reset register bit */ -#define VTA_INSN_GEM_5 (VTA_INSN_GEM_4 + 1) -/*! GEMM instruction start position of the uop_bgn field */ -#define VTA_INSN_GEM_6_0 (VTA_INSN_GEM_5 + 1) -/*! GEMM instruction end position of the uop_bgn field */ -#define VTA_INSN_GEM_6_1 (VTA_INSN_GEM_6_0 + VTA_LOG_UOP_BUFF_DEPTH - 1) -/*! GEMM instruction start position of the uop_end field */ -#define VTA_INSN_GEM_7_0 (VTA_INSN_GEM_6_1 + 1) -/*! GEMM instruction end position of the uop_end field */ -#define VTA_INSN_GEM_7_1 (VTA_INSN_GEM_7_0 + VTA_LOG_UOP_BUFF_DEPTH + 1 - 1) -/*! GEMM instruction start position of the iter_out field */ -#define VTA_INSN_GEM_8_0 (VTA_INSN_GEM_7_1 + 1) -/*! GEMM instruction end position of the iter_out field */ -#define VTA_INSN_GEM_8_1 (VTA_INSN_GEM_8_0 + VTA_LOOP_ITER_WIDTH - 1) -/*! GEMM instruction start position of the iter_in field */ -#define VTA_INSN_GEM_9_0 (VTA_INSN_GEM_8_1 + 1) -/*! GEMM instruction end position of the iter_in field */ -#define VTA_INSN_GEM_9_1 (VTA_INSN_GEM_9_0 + VTA_LOOP_ITER_WIDTH - 1) -/*! GEMM instruction start position of the dst_factor_out field */ -#define VTA_INSN_GEM_A_0 64 -/*! GEMM instruction end position of the dst_factor_out field */ -#define VTA_INSN_GEM_A_1 (VTA_INSN_GEM_A_0 + VTA_LOG_ACC_BUFF_DEPTH - 1) -/*! GEMM instruction start position of the dst_factor_in field */ -#define VTA_INSN_GEM_B_0 (VTA_INSN_GEM_A_1 + 1) -/*! GEMM instruction end position of the dst_factor_in field */ -#define VTA_INSN_GEM_B_1 (VTA_INSN_GEM_B_0 + VTA_LOG_ACC_BUFF_DEPTH - 1) -/*! GEMM instruction start position of the src_factor_out field */ -#define VTA_INSN_GEM_C_0 (VTA_INSN_GEM_B_1 + 1) -/*! GEMM instruction end position of the src_factor_out field */ -#define VTA_INSN_GEM_C_1 (VTA_INSN_GEM_C_0 + VTA_LOG_INP_BUFF_DEPTH - 1) -/*! GEMM instruction start position of the src_factor_in field */ -#define VTA_INSN_GEM_D_0 (VTA_INSN_GEM_C_1 + 1) -/*! GEMM instruction end position of the src_factor_in field */ -#define VTA_INSN_GEM_D_1 (VTA_INSN_GEM_D_0 + VTA_LOG_INP_BUFF_DEPTH - 1) - -/*! GEMM instruction start position of the wgt_factor_out field */ -#define VTA_INSN_GEM_E_0 (VTA_INSN_GEM_D_1 + 1) -/*! GEMM instruction end position of the wgt_factor_out field */ -#define VTA_INSN_GEM_E_1 (VTA_INSN_GEM_E_0 + VTA_LOG_WGT_BUFF_DEPTH - 1) -/*! GEMM instruction start position of the wgt_factor_in field */ -#define VTA_INSN_GEM_F_0 (VTA_INSN_GEM_E_1 + 1) -/*! GEMM instruction end position of the wgt_factor_in field */ -#define VTA_INSN_GEM_F_1 (VTA_INSN_GEM_F_0 + VTA_LOG_WGT_BUFF_DEPTH - 1) - -/*! ALU instruction start position of the alu_opcode field */ -#define VTA_INSN_ALU_E_0 (VTA_INSN_GEM_D_1 + 1) -/*! ALU instruction end position of the alu_opcode field */ -#define VTA_INSN_ALU_E_1 (VTA_INSN_ALU_E_0 + VTA_ALU_OPCODE_BIT_WIDTH - 1) -/*! ALU instruction position of the use_imm field */ -#define VTA_INSN_ALU_F (VTA_INSN_ALU_E_1 + 1) -/*! ALU instruction start position of the immediate field */ -#define VTA_INSN_ALU_G_0 (VTA_INSN_ALU_F + 1) -/*! ALU instruction end position of the immediate field */ -#define VTA_INSN_ALU_G_1 (VTA_INSN_ALU_G_0 + VTA_ALUOP_IMM_BIT_WIDTH - 1) - /*! GEMM Micro-op start position of the acc_idx field */ #define VTA_UOP_GEM_0_0 0 /*! GEMM Micro-op end position of the acc_idx field */ @@ -385,8 +188,20 @@ extern "C" { /*! \brief VTA generic instruction */ typedef struct { - uint64_t word_0 : 64; - uint64_t word_1 : 64; + /*! \brief The instruction opcode */ + uint64_t opcode : VTA_OPCODE_BIT_WIDTH; + /*! \brief Unused in this instruction */ + uint64_t pop_prev_dep : 1; + /*! \brief Pop dependence token from GEMM stage */ + uint64_t pop_next_dep : 1; + /*! \brief Unused in this instruction */ + uint64_t push_prev_dep : 1; + /*! \brief Push dependence token to GEMM stage */ + uint64_t push_next_dep : 1; + /*! \brief Padding */ + uint64_t pad_0 : 64 - VTA_OPCODE_BIT_WIDTH - 4; + /*! \brief Padding */ + uint64_t pad_1 : 64; } VTAGenericInsn; /*! \brief VTA load/store instruction diff --git a/vta/python/vta/environment.py b/vta/python/vta/environment.py index 86246cfad2d9d..d9edef5577a12 100644 --- a/vta/python/vta/environment.py +++ b/vta/python/vta/environment.py @@ -116,6 +116,8 @@ def __init__(self, cfg): self.BATCH = 1 << self.LOG_BATCH self.BLOCK_IN = 1 << self.LOG_BLOCK_IN self.BLOCK_OUT = 1 << self.LOG_BLOCK_OUT + # bus width + self.BUS_WIDTH = 1 << self.LOG_BUS_WIDTH # buffer size self.UOP_BUFF_SIZE = 1 << self.LOG_UOP_BUFF_SIZE self.INP_BUFF_SIZE = 1 << self.LOG_INP_BUFF_SIZE @@ -150,7 +152,7 @@ def __init__(self, cfg): self._dev_ctx = None self._last_env = None # derive bitstream name - self.BITSTREAM = "{}/{}/{}x{}x{}_a{}w{}o{}_{}_{}_{}_{}_{}MHz_{}ns_gii{}".format( + self.BITSTREAM = "{}/{}/{}x{}x{}_a{}w{}o{}_{}_{}_{}_{}_{}_{}MHz_{}ns_gii{}".format( self.HW_VER.replace('.', '_'), self.TARGET, self.BATCH, @@ -159,6 +161,7 @@ def __init__(self, cfg): self.INP_WIDTH, self.WGT_WIDTH, self.OUT_WIDTH, + self.LOG_BUS_WIDTH, self.LOG_UOP_BUFF_SIZE, self.LOG_INP_BUFF_SIZE, self.LOG_WGT_BUFF_SIZE, @@ -174,7 +177,7 @@ def __init__(self, cfg): # model - autoTVM signature that identifies VTA configuration. # This is WIP: knobs that could influence the efficacy of the # schedule have been left out for now. - self.MODEL = "{}-{}x{}x{}_a{}w{}o{}_{}_{}_{}_{}".format( + self.MODEL = "{}-{}x{}x{}_a{}w{}o{}_{}_{}_{}_{}_{}".format( self.TARGET, self.BATCH, self.BLOCK_IN, @@ -182,6 +185,7 @@ def __init__(self, cfg): self.INP_WIDTH, self.WGT_WIDTH, self.OUT_WIDTH, + self.LOG_BUS_WIDTH, self.LOG_UOP_BUFF_SIZE, self.LOG_INP_BUFF_SIZE, self.LOG_WGT_BUFF_SIZE, diff --git a/vta/python/vta/exec/pynq_utils.py b/vta/python/vta/exec/pynq_utils.py deleted file mode 100644 index 8712dc1dec520..0000000000000 --- a/vta/python/vta/exec/pynq_utils.py +++ /dev/null @@ -1,33 +0,0 @@ -"""Programming utilities for Pynq. - -Provides functions to program the Pynq FPGA. -""" -import os - -def program_pynq(bitfile_name): - """The method to download the bitstream onto PL. - Note - ---- - The class variables held by the singleton PL will also be updated. - Returns - ------- - None - """ - BS_IS_PARTIAL = "/sys/devices/soc0/amba/f8007000.devcfg/" \ - "is_partial_bitstream" - BS_XDEVCFG = "/dev/xdevcfg" - - if not os.path.exists(BS_XDEVCFG): - raise RuntimeError("Could not find programmable device") - - # Compose bitfile name, open bitfile - with open(bitfile_name, 'rb') as f: - buf = f.read() - - # Set is_partial_bitfile device attribute to the appropriate value - with open(BS_IS_PARTIAL, 'w') as fd: - fd.write('0') - - # Write bitfile to xdevcfg device - with open(BS_XDEVCFG, 'wb') as f: - f.write(buf) diff --git a/vta/python/vta/exec/rpc_server.py b/vta/python/vta/exec/rpc_server.py index 3edc940e3ab2e..f5773f15959ba 100644 --- a/vta/python/vta/exec/rpc_server.py +++ b/vta/python/vta/exec/rpc_server.py @@ -14,12 +14,11 @@ from tvm._ffi.base import c_str from tvm import rpc from tvm.contrib import cc +from pynq import Bitstream from ..environment import get_env from ..pkg_config import PkgConfig from ..libinfo import find_libvta -from .pynq_utils import program_pynq -from .ultra96_utils import program_ultra96 @tvm.register_func("tvm.rpc.server.start", override=True) @@ -54,11 +53,8 @@ def ext_dev_callback(): @tvm.register_func("tvm.contrib.vta.init", override=True) def program_fpga(file_name): path = tvm.get_global_func("tvm.rpc.server.workpath")(file_name) - env = get_env() - if env.TARGET == "pynq": - program_pynq(path) - elif env.TARGET == "ultra96": - program_ultra96(path) + bitstream = Bitstream(path) + bitstream.download() logging.info("Program FPGA with %s", file_name) @tvm.register_func("tvm.rpc.server.shutdown", override=True) diff --git a/vta/python/vta/exec/ultra96_utils.py b/vta/python/vta/exec/ultra96_utils.py deleted file mode 100644 index 1f14ef00fc279..0000000000000 --- a/vta/python/vta/exec/ultra96_utils.py +++ /dev/null @@ -1,115 +0,0 @@ -"""Programming utilities for Ultra-96. - -Provides functions to program the Ultra-96 FPGA. -""" -import os -import struct -import numpy as np - -def program_ultra96(bitfile_name): - """The method to download the bitstream onto PL. - Note - ---- - The class variables held by the singleton PL will also be updated. - Returns - ------- - None - """ - BS_FPGA_MAN = "/sys/class/fpga_manager/fpga0/firmware" - - if not os.path.exists(BS_FPGA_MAN): - raise RuntimeError("Could not find programmable device") - - bin_file = os.path.basename(bitfile_name).replace('.bit', '.bin') - bin_path = '/lib/firmware/' + bin_file - convert_bit_to_bin(bitfile_name, bin_path) - with open(BS_FPGA_MAN, 'w') as fd: - fd.write(bin_file) - -def convert_bit_to_bin(bitfile_name, bin_path): - """The method to convert a .bit file to .bin file. - A .bit file is generated by Vivado, but .bin files are needed - by the Zynq Ultrascale FPGA manager driver. Users must specify - the absolute path to the source .bit file, and the destination - .bin file and have read/write access to both paths. - Note - ---- - Imlemented based on: https://blog.aeste.my/?p=2892 - Returns - ------- - None - """ - bit_data = parse_bit_header(bitfile_name) - bit_buffer = np.frombuffer(bit_data['data'], dtype=np.int32, offset=0) - bin_buffer = bit_buffer.byteswap() - bin_buffer.tofile(bin_path, "") - -def parse_bit_header(bitfile_name): - """The method to parse the header of a bitstream. - The returned dictionary has the following keys: - "design": str, the Vivado project name that generated the bitstream; - "version": str, the Vivado tool version that generated the bitstream; - "part": str, the Xilinx part name that the bitstream targets; - "date": str, the date the bitstream was compiled on; - "time": str, the time the bitstream finished compilation; - "length": int, total length of the bitstream (in bytes); - "data": binary, binary data in .bit file format - Returns - ------- - Dict - A dictionary containing the header information. - Note - ---- - Implemented based on: https://blog.aeste.my/?p=2892 - """ - with open(bitfile_name, 'rb') as bitf: - finished = False - offset = 0 - contents = bitf.read() - bit_dict = {} - - # Strip the (2+n)-byte first field (2-bit length, n-bit data) - length = struct.unpack('>h', contents[offset:offset + 2])[0] - offset += 2 + length - - # Strip a two-byte unknown field (usually 1) - offset += 2 - - # Strip the remaining headers. 0x65 signals the bit data field - while not finished: - desc = contents[offset] - offset += 1 - - if desc != 0x65: - length = struct.unpack('>h', - contents[offset:offset + 2])[0] - offset += 2 - fmt = ">{}s".format(length) - data = struct.unpack(fmt, - contents[offset:offset + length])[0] - data = data.decode('ascii')[:-1] - offset += length - - if desc == 0x61: - s = data.split(";") - bit_dict['design'] = s[0] - bit_dict['version'] = s[2] - elif desc == 0x62: - bit_dict['part'] = data - elif desc == 0x63: - bit_dict['date'] = data - elif desc == 0x64: - bit_dict['time'] = data - elif desc == 0x65: - finished = True - length = struct.unpack('>i', - contents[offset:offset + 4])[0] - offset += 4 - # Expected length values can be verified in the chip TRM - bit_dict['length'] = str(length) - if length + offset != len(contents): - raise RuntimeError("Invalid length found") - bit_dict['data'] = contents[offset:offset + length] - else: - raise RuntimeError("Unknown field: {}".format(hex(desc))) - return bit_dict diff --git a/vta/python/vta/pkg_config.py b/vta/python/vta/pkg_config.py index af0eca7593f45..c0e4151793219 100644 --- a/vta/python/vta/pkg_config.py +++ b/vta/python/vta/pkg_config.py @@ -36,6 +36,7 @@ class PkgConfig(object): "LOG_BATCH", "LOG_BLOCK_IN", "LOG_BLOCK_OUT", + "LOG_BUS_WIDTH", "LOG_UOP_BUFF_SIZE", "LOG_INP_BUFF_SIZE", "LOG_WGT_BUFF_SIZE", @@ -72,7 +73,7 @@ def __init__(self, cfg, proj_root): elif self.target == "ultra96": self.ldflags = [ "-L/usr/lib", - "-lsds_lib"] + "-lcma"] else: self.ldflags = [] @@ -82,7 +83,7 @@ def cflags(self): @property def signature(self): - return "{}-{}_{}_{}_{}_{}_{}_{}_{}_{}_{}".format( + return "{}-{}_{}_{}_{}_{}_{}_{}_{}_{}_{}_{}".format( self.cfg_dict["TARGET"], self.cfg_dict["LOG_BATCH"], self.cfg_dict["LOG_BLOCK_IN"], @@ -90,6 +91,7 @@ def signature(self): self.cfg_dict["LOG_INP_WIDTH"], self.cfg_dict["LOG_WGT_WIDTH"], self.cfg_dict["LOG_OUT_WIDTH"], + self.cfg_dict["LOG_BUS_WIDTH"], self.cfg_dict["LOG_UOP_BUFF_SIZE"], self.cfg_dict["LOG_INP_BUFF_SIZE"], self.cfg_dict["LOG_WGT_BUFF_SIZE"], diff --git a/vta/src/runtime.cc b/vta/src/runtime.cc index 1c377fea61188..710273bfd2337 100644 --- a/vta/src/runtime.cc +++ b/vta/src/runtime.cc @@ -25,7 +25,7 @@ static_assert(VTA_UOP_WIDTH == sizeof(VTAUop) * 8, "VTA_UOP_WIDTH do not match VTAUop size"); /*! \brief Enable coherent access between VTA and CPU. */ -static const bool kBufferCoherent = false; +static const bool kBufferCoherent = true; /*! * \brief Data buffer represents data on CMA. diff --git a/vta/tests/hardware/common/test_lib.cc b/vta/tests/hardware/common/test_lib.cc index f6a810cff7e9f..80db7230ebff9 100644 --- a/vta/tests/hardware/common/test_lib.cc +++ b/vta/tests/hardware/common/test_lib.cc @@ -13,10 +13,10 @@ uint64_t vta( uint32_t insn_count, VTAGenericInsn *insns, VTAUop *uops, - axi_T *inputs, - axi_T *weights, - axi_T *biases, - axi_T *outputs) { + bus_T *inputs, + bus_T *weights, + bus_T *biases, + bus_T *outputs) { // Performance counter variables uint64_t t_fpga; struct timespec start, stop; @@ -564,45 +564,6 @@ void printParameters() { printf("VTA_ACC_ELEM_BYTES: %d\n", VTA_ACC_ELEM_BYTES); printf("VTA_BLOCK_IN: %d\n", VTA_BLOCK_IN); printf("VTA_BLOCK_OUT: %d\n", VTA_BLOCK_OUT); - printf("VTA_INSN_MEM_0 [%d-%d]\n", VTA_INSN_MEM_0_0, VTA_INSN_MEM_0_1); - printf("VTA_INSN_MEM_1 [%d]\n", VTA_INSN_MEM_1); - printf("VTA_INSN_MEM_2 [%d]\n", VTA_INSN_MEM_2); - printf("VTA_INSN_MEM_3 [%d]\n", VTA_INSN_MEM_3); - printf("VTA_INSN_MEM_4 [%d]\n", VTA_INSN_MEM_4); - printf("VTA_INSN_MEM_5 [%d-%d]\n", VTA_INSN_MEM_5_0, VTA_INSN_MEM_5_1); - printf("VTA_INSN_MEM_6 [%d-%d]\n", VTA_INSN_MEM_6_0, VTA_INSN_MEM_6_1); - printf("VTA_INSN_MEM_7 [%d-%d]\n", VTA_INSN_MEM_7_0, VTA_INSN_MEM_7_1); - printf("VTA_INSN_MEM_8 [%d-%d]\n", VTA_INSN_MEM_8_0, VTA_INSN_MEM_8_1); - printf("VTA_INSN_MEM_9 [%d-%d]\n", VTA_INSN_MEM_9_0, VTA_INSN_MEM_9_1); - printf("VTA_INSN_MEM_A [%d-%d]\n", VTA_INSN_MEM_A_0, VTA_INSN_MEM_A_1); - printf("VTA_INSN_MEM_B [%d-%d]\n", VTA_INSN_MEM_B_0, VTA_INSN_MEM_B_1); - printf("VTA_INSN_MEM_C [%d-%d]\n", VTA_INSN_MEM_C_0, VTA_INSN_MEM_C_1); - printf("VTA_INSN_MEM_D [%d-%d]\n", VTA_INSN_MEM_D_0, VTA_INSN_MEM_D_1); - printf("VTA_INSN_MEM_E [%d-%d]\n", VTA_INSN_MEM_E_0, VTA_INSN_MEM_E_1); - printf("VTA_INSN_GEM_0 [%d-%d]\n", VTA_INSN_GEM_0_0, VTA_INSN_GEM_0_1); - printf("VTA_INSN_GEM_1 [%d]\n", VTA_INSN_GEM_1); - printf("VTA_INSN_GEM_2 [%d]\n", VTA_INSN_GEM_2); - printf("VTA_INSN_GEM_3 [%d]\n", VTA_INSN_GEM_3); - printf("VTA_INSN_GEM_4 [%d]\n", VTA_INSN_GEM_4); - printf("VTA_INSN_GEM_5 [%d]\n", VTA_INSN_GEM_5); - printf("VTA_INSN_GEM_6 [%d-%d]\n", VTA_INSN_GEM_6_0, VTA_INSN_GEM_6_1); - printf("VTA_INSN_GEM_7 [%d-%d]\n", VTA_INSN_GEM_7_0, VTA_INSN_GEM_7_1); - printf("VTA_INSN_GEM_8 [%d-%d]\n", VTA_INSN_GEM_8_0, VTA_INSN_GEM_8_1); - printf("VTA_INSN_GEM_9 [%d-%d]\n", VTA_INSN_GEM_9_0, VTA_INSN_GEM_9_1); - printf("VTA_INSN_GEM_A [%d-%d]\n", VTA_INSN_GEM_A_0, VTA_INSN_GEM_A_1); - printf("VTA_INSN_GEM_B [%d-%d]\n", VTA_INSN_GEM_B_0, VTA_INSN_GEM_B_1); - printf("VTA_INSN_GEM_C [%d-%d]\n", VTA_INSN_GEM_C_0, VTA_INSN_GEM_C_1); - printf("VTA_INSN_GEM_D [%d-%d]\n", VTA_INSN_GEM_D_0, VTA_INSN_GEM_D_1); - printf("VTA_INSN_GEM_E [%d-%d]\n", VTA_INSN_GEM_E_0, VTA_INSN_GEM_E_1); - printf("VTA_INSN_GEM_F [%d-%d]\n", VTA_INSN_GEM_F_0, VTA_INSN_GEM_F_1); - printf("VTA_INSN_ALU_E [%d-%d]\n", VTA_INSN_ALU_E_0, VTA_INSN_ALU_E_1); - printf("VTA_INSN_ALU_F [%d]\n", VTA_INSN_ALU_F); - printf("VTA_INSN_ALU_G [%d-%d]\n", VTA_INSN_ALU_G_0, VTA_INSN_ALU_G_1); - printf("VTA_UOP_GEM_0 [%d-%d]\n", VTA_UOP_GEM_0_0, VTA_UOP_GEM_0_1); - printf("VTA_UOP_GEM_1 [%d-%d]\n", VTA_UOP_GEM_1_0, VTA_UOP_GEM_1_1); - printf("VTA_UOP_GEM_2 [%d-%d]\n", VTA_UOP_GEM_2_0, VTA_UOP_GEM_2_1); - printf("VTA_UOP_ALU_0 [%d-%d]\n", VTA_UOP_ALU_0_0, VTA_UOP_ALU_0_1); - printf("VTA_UOP_ALU_1 [%d-%d]\n", VTA_UOP_ALU_1_0, VTA_UOP_ALU_1_1); } void printInstruction(int num_insn, VTAGenericInsn *insns) { @@ -911,14 +872,14 @@ int alu_test(int opcode, bool use_imm, int batch, int vector_size, bool uop_comp } // Pack input buffer - axi_T *bias_buf = - static_cast(allocBuffer(VTA_ACC_ELEM_BYTES * batch * tx_size * input_sets)); - packBuffer( + bus_T *bias_buf = + static_cast(allocBuffer(VTA_ACC_ELEM_BYTES * batch * tx_size * input_sets)); + packBuffer( bias_buf, inputs, batch, vector_size * input_sets, VTA_BATCH, VTA_BLOCK_OUT); // Prepare output buffer - axi_T *output_buf = - static_cast(allocBuffer(VTA_OUT_ELEM_BYTES * batch * tx_size * input_sets)); + bus_T *output_buf = + static_cast(allocBuffer(VTA_OUT_ELEM_BYTES * batch * tx_size * input_sets)); #ifdef NO_SIM // Invoke the VTA @@ -931,15 +892,15 @@ int alu_test(int opcode, bool use_imm, int batch, int vector_size, bool uop_comp vta(ins_size, (volatile insn_T *) insn_buf, (volatile uop_T *) uop_buf, - (volatile axi_T *) NULL, - (volatile axi_T *) NULL, - (volatile axi_T *) bias_buf, - (volatile axi_T *) output_buf); + (volatile bus_T *) NULL, + (volatile bus_T *) NULL, + (volatile bus_T *) bias_buf, + (volatile bus_T *) output_buf); #endif // Unpack output buffer out_T **outputs = alloc2dArray(batch, vector_size); - unpackBuffer(outputs, + unpackBuffer(outputs, output_buf, batch, vector_size, @@ -1160,31 +1121,31 @@ int blocked_gemm_test(int batch, int channels, int block, bool uop_compression, } // Prepare the input buffer - axi_T *input_buf = static_cast(allocBuffer(VTA_INP_ELEM_BYTES * inp_size)); - packBuffer(input_buf, + bus_T *input_buf = static_cast(allocBuffer(VTA_INP_ELEM_BYTES * inp_size)); + packBuffer(input_buf, inputs, batch, in_feat, VTA_BATCH, VTA_BLOCK_IN); // Prepare the weight buffer - axi_T *weight_buf = static_cast(allocBuffer(VTA_WGT_ELEM_BYTES * wgt_size)); - packBuffer(weight_buf, + bus_T *weight_buf = static_cast(allocBuffer(VTA_WGT_ELEM_BYTES * wgt_size)); + packBuffer(weight_buf, weights, out_feat, in_feat, VTA_BLOCK_OUT, VTA_BLOCK_IN); // Prepare the bias buffer - axi_T *bias_buf = static_cast(allocBuffer(VTA_ACC_ELEM_BYTES * out_size)); - packBuffer(bias_buf, + bus_T *bias_buf = static_cast(allocBuffer(VTA_ACC_ELEM_BYTES * out_size)); + packBuffer(bias_buf, biases, batch, out_feat, VTA_BATCH, VTA_BLOCK_OUT); // Prepare the output buffer - axi_T *output_buf = static_cast(allocBuffer(VTA_INP_ELEM_BYTES * out_size)); + bus_T *output_buf = static_cast(allocBuffer(VTA_INP_ELEM_BYTES * out_size)); #ifdef NO_SIM // Invoke the VTA @@ -1204,15 +1165,15 @@ int blocked_gemm_test(int batch, int channels, int block, bool uop_compression, vta(ins_size, (volatile insn_T *) insn_buf, (volatile uop_T *) uop_buf, - (volatile axi_T *) input_buf, - (volatile axi_T *) weight_buf, - (volatile axi_T *) bias_buf, - (volatile axi_T *) output_buf); + (volatile bus_T *) input_buf, + (volatile bus_T *) weight_buf, + (volatile bus_T *) bias_buf, + (volatile bus_T *) output_buf); #endif // Unpack output data out_T **outputs = alloc2dArray(batch, out_feat); - unpackBuffer(outputs, + unpackBuffer(outputs, output_buf, batch, out_feat, @@ -1389,31 +1350,31 @@ int gemm_test(int batch, int in_channels, int out_channels, bool uop_compression } // Prepare the input buffer - axi_T *input_buf = static_cast(allocBuffer(VTA_INP_ELEM_BYTES * inp_size)); - packBuffer(input_buf, + bus_T *input_buf = static_cast(allocBuffer(VTA_INP_ELEM_BYTES * inp_size)); + packBuffer(input_buf, inputs, batch, in_channels, VTA_BATCH, VTA_BLOCK_IN); // Prepare the weight buffer - axi_T *weight_buf = static_cast(allocBuffer(VTA_WGT_ELEM_BYTES * wgt_size)); - packBuffer(weight_buf, + bus_T *weight_buf = static_cast(allocBuffer(VTA_WGT_ELEM_BYTES * wgt_size)); + packBuffer(weight_buf, weights, out_channels, in_channels, VTA_BLOCK_OUT, VTA_BLOCK_IN); // Prepare the bias buffer - axi_T *bias_buf = static_cast(allocBuffer(VTA_ACC_ELEM_BYTES * out_size)); - packBuffer(bias_buf, + bus_T *bias_buf = static_cast(allocBuffer(VTA_ACC_ELEM_BYTES * out_size)); + packBuffer(bias_buf, biases, batch, out_channels, VTA_BATCH, VTA_BLOCK_OUT); // Prepare the output buffer - axi_T *output_buf = static_cast(allocBuffer(VTA_OUT_ELEM_BYTES * out_size)); + bus_T *output_buf = static_cast(allocBuffer(VTA_OUT_ELEM_BYTES * out_size)); #ifdef NO_SIM // Invoke the VTA @@ -1433,15 +1394,15 @@ int gemm_test(int batch, int in_channels, int out_channels, bool uop_compression vta(ins_size, (volatile insn_T *) insn_buf, (volatile uop_T *) uop_buf, - (volatile axi_T *) input_buf, - (volatile axi_T *) weight_buf, - (volatile axi_T *) bias_buf, - (volatile axi_T *) output_buf); + (volatile bus_T *) input_buf, + (volatile bus_T *) weight_buf, + (volatile bus_T *) bias_buf, + (volatile bus_T *) output_buf); #endif // Unpack output data out_T **outputs = alloc2dArray(batch, out_channels); - unpackBuffer(outputs, + unpackBuffer(outputs, output_buf, batch, out_channels, diff --git a/vta/tests/hardware/common/test_lib.h b/vta/tests/hardware/common/test_lib.h index a58d7e9ceffc1..5a964e3b7d9d2 100644 --- a/vta/tests/hardware/common/test_lib.h +++ b/vta/tests/hardware/common/test_lib.h @@ -21,7 +21,7 @@ #include "../../../src/pynq/pynq_driver.h" #endif // VTA_TARGET_PYNQ -typedef uint64_t axi_T; +typedef uint64_t bus_T; typedef uint32_t uop_T; typedef int8_t wgt_T; typedef int8_t inp_T; diff --git a/vta/tests/python/integration/test_benchmark_topi_conv2d.py b/vta/tests/python/integration/test_benchmark_topi_conv2d.py index 21dfe26974038..3b9a71cb9e116 100644 --- a/vta/tests/python/integration/test_benchmark_topi_conv2d.py +++ b/vta/tests/python/integration/test_benchmark_topi_conv2d.py @@ -184,6 +184,7 @@ def run_vta_conv2d(env, remote, wl, target, check_correctness=True, print_ir=Fal 1, 1, env.BATCH, env.BLOCK_OUT) data = tvm.placeholder(data_shape, name="data", dtype=env.inp_dtype) bias = tvm.placeholder(bias_shape, name="kernel", dtype=env.acc_dtype) + factor = tvm.placeholder(bias_shape, name="kernel", dtype=env.acc_dtype) # Handle quantized inputs (less than 8 bits) # x_pack_factor = 1 << (3 - env.LOG_INP_WIDTH) @@ -205,6 +206,7 @@ def run_vta_conv2d(env, remote, wl, target, check_correctness=True, print_ir=Fal "NCHW%dn%dc" % (env.BATCH, env.BLOCK_IN), 'int32') res = topi.right_shift(res_conv, 8) res = topi.add(res, bias) + res = topi.multiply(res, factor) res = my_clip(res, 0, (1 << env.OUT_WIDTH-1)-1) res = topi.cast(res, "int8") @@ -217,7 +219,7 @@ def run_vta_conv2d(env, remote, wl, target, check_correctness=True, print_ir=Fal #skip_alu=skip_alu, #skip_gemm=skip_gemm) if print_ir: - print(vta.lower(s, [data, kernel_arg, bias, res], simple_mode=True)) + print(vta.lower(s, [data, kernel_arg, bias, factor, res], simple_mode=True)) # Handle quantized outputs (less than 8 bits) # o_pack_factor = 1 << (3 - env.LOG_OUT_WIDTH) @@ -249,15 +251,19 @@ def get_ref_data(): return a_np, w_np, b_np mod = vta.build(s, - [data, kernel_arg, bias, res], + [data, kernel_arg, bias, factor, res], target, env.target_host, name="conv2d") # Data in original format data_orig, kernel_orig, res_ref = get_ref_data() - bias_orig = (np.random.uniform(size=(wl.batch, wl.out_filter,)) * (1 << (env.INP_WIDTH + env.WGT_WIDTH - 2))) + bias_orig = np.random.uniform(size=(wl.batch, wl.out_filter,)) * (1 << (env.INP_WIDTH + env.WGT_WIDTH - 2)) bias_orig = bias_orig.astype("int32") bias_orig = np.abs(bias_orig) + factor_orig = (np.random.uniform(size=(wl.batch, wl.out_filter,)) * (1 << 7)) + factor_orig = factor_orig.astype("int32") + factor_orig = np.abs(factor_orig) + data_packed = data_orig.reshape( wl.batch//env.BATCH, env.BATCH, @@ -267,6 +273,9 @@ def get_ref_data(): wl.out_filter//env.BLOCK_OUT, env.BLOCK_OUT, wl.in_filter//env.BLOCK_IN, env.BLOCK_IN, wl.hkernel, wl.wkernel).transpose((0, 2, 4, 5, 1, 3)) + factor_packed = factor_orig.reshape( + wl.batch // env.BATCH, wl.out_filter // env.BLOCK_OUT, + 1, 1, env.BATCH, env.BLOCK_OUT) bias_packed = bias_orig.reshape( wl.batch // env.BATCH, wl.out_filter // env.BLOCK_OUT, 1, 1, env.BATCH, env.BLOCK_OUT) @@ -285,6 +294,7 @@ def get_ref_data(): res_np = np.zeros(res_shape).astype(res.dtype) data_arr = tvm.nd.array(data_qpacked, ctx) kernel_arr = tvm.nd.array(kernel_qpacked, ctx) + factor_arr = tvm.nd.array(factor_packed, ctx) bias_arr = tvm.nd.array(bias_packed, ctx) res_arr = tvm.nd.array(res_np, ctx) time_f = f.time_evaluator("conv2d", ctx, number=samples) @@ -300,16 +310,16 @@ def get_ref_data(): remote.get_function("vta.simulator.profiler_clear")() if profileOnly: remote.get_function("vta.simulator.profiler_debug_mode")(1) - cost = time_f(data_arr, kernel_arr, bias_arr, res_arr) + cost = time_f(data_arr, kernel_arr, bias_arr, factor_arr, res_arr) stats = json.loads(remote.get_function("vta.simulator.profiler_status")()) else: simulator.clear_stats() if profileOnly: simulator.debug_mode(1) - cost = time_f(data_arr, kernel_arr, bias_arr, res_arr) + cost = time_f(data_arr, kernel_arr, bias_arr, factor_arr, res_arr) stats = simulator.stats() else: - cost = time_f(data_arr, kernel_arr, bias_arr, res_arr) + cost = time_f(data_arr, kernel_arr, bias_arr, factor_arr, res_arr) # Check correctness correct = False @@ -323,12 +333,14 @@ def get_ref_data(): padding = wl.hpad res_ref = res_ref >> 8 res_ref += bias_orig.reshape(wl.out_filter, 1, 1) + res_ref *= factor_orig.reshape(wl.out_filter, 1, 1) res_ref = np.clip(res_ref, 0, (1 << env.OUT_WIDTH-1)-1) res_ref = res_ref.astype("int8") correct = np.allclose(res_unpack, res_ref) gops = (num_ops / cost.mean) / float(10 ** 9) - print("VTA TEST: Time cost = %g sec/op, %g GOPS\n" % (cost.mean, gops)) + status = "PASSED" if correct else "FAILED" + print("VTA TEST %s: Time cost = %g sec/op, %g GOPS" % (status, cost.mean, gops)) return correct, cost, stats diff --git a/vta/tutorials/resnet.py b/vta/tutorials/resnet.py index faa24e137c8d5..a7b492a31cc47 100644 --- a/vta/tutorials/resnet.py +++ b/vta/tutorials/resnet.py @@ -239,7 +239,7 @@ def generate_graph(graph_fn, params_fn, target): print(" #3:", synset[top_categories[-3]]) print(" #4:", synset[top_categories[-4]]) print(" #5:", synset[top_categories[-5]]) -print("Performed inference in {0:.2f}s".format(tcost.mean)) +print("Performed inference in {0:.1f}ms".format(tcost.mean*1000.0)) ######################################################################