diff --git a/Docs/som_clocks.dox b/Docs/som_clocks.dox index 8657525..27e67b8 100644 --- a/Docs/som_clocks.dox +++ b/Docs/som_clocks.dox @@ -43,11 +43,15 @@ It is also possible to provide an external input clock source to the FPGA. The FPGA can use the external input clock, routed to its pin `H8`, which is a primary clock pin (PCLK), usable for DDR I/O. -TODO: Hook an I2C core and integrate into the core SoM design +The FPGA is able to use the clock signals as a basis for implementing a timer +core. ## Zephyr integration +The timer cores are further providing Zephyr with timers, used for ensuring +a constant system tick interrupt part of RTOS scheduling. + The Si5351 PLL is not yet integrated into Zephyr as a driver. Instead, it is called from the user code to generate the appropriate clock. diff --git a/Docs/som_gpio.dox b/Docs/som_gpio.dox new file mode 100644 index 0000000..145b224 --- /dev/null +++ b/Docs/som_gpio.dox @@ -0,0 +1,6 @@ +/** @page "md_som_gpio" SoM GPIO + +TODO: Description of all the GPIO pin usage, including the enable control +signals or the signals not controlled by the FPGA. + +*/ diff --git a/Docs/som_i2c.dox b/Docs/som_i2c.dox new file mode 100644 index 0000000..198918c --- /dev/null +++ b/Docs/som_i2c.dox @@ -0,0 +1,5 @@ +/** @page md_som_i2c SoM I²C + +TODO: summary of all I2C buses and devices on the SoM. + +*/ diff --git a/Docs/syzygy/Makefile b/Docs/syzygy/Makefile new file mode 100644 index 0000000..e514232 --- /dev/null +++ b/Docs/syzygy/Makefile @@ -0,0 +1,19 @@ +SZG += szg_std.tsv +POD += szg_camera.tsv +POD += szg_dac_ad911x.tsv +POD += szg_adc_ltc226x.tsv +POD += szg_enet1g.tsv +POD += szg_mipi_8320.tsv +POD += pod_a.tsv +POD += pod_b.tsv + +all: syzygy.txt + +clean: + rm -f syzygy.tsv syzygy.txt + +syzygy.tsv: $(SZG) $(POD) Makefile summary.py + python3 summary.py $(SZG) $(POD) >$@ + +syzygy.txt: syzygy.tsv + column -t -s ' ' $< >$@ diff --git a/Docs/syzygy/pod_a.tsv b/Docs/syzygy/pod_a.tsv new file mode 100644 index 0000000..4c9f77e --- /dev/null +++ b/Docs/syzygy/pod_a.tsv @@ -0,0 +1,40 @@ +1 SCL SCL +2 +5V P5V +3 SDA SDA +4 R_GA I2C_ADR_SEL +5 S0_D0P DIFF0_P +6 S1_D1P DIFF1_PCLK_P +7 S2_D0N DIFF0_N +8 S3_D1N DIFF1_PCLK_N +9 S4_D2P DIFF2_P +10 S5_D3P DIFF3_PCLK_P +11 S6_D2N DIFF2_N +12 S7_D3N DIFF3_PCLK_N +13 S8_D4P DIFF4_PCLK_P +14 S9_D5P DIFF5_PCLK_P +15 S10_D4N DIFF4_PCLK_N +16 S11_D5N DIFF5_PCLK_N +17 S12_D6P +18 S13_D7P +19 S14_D6N +20 S15_D7N +21 S16 GPIO_0 +22 S17 GPIO_1 +23 S18 GPIO_2 +24 S19 GPIO_3 +25 S20 +26 S21 +27 S22 +28 S23 +29 S24 +30 S25 +31 S26 +32 S27 +33 P2C_CLKP +34 C2P_CLKP +35 P2C_CLKN +36 C2P_CLKN +37 RSVD +38 RSVD +39 VIO1 PVDD_3 +40 +3.3V P3V3D diff --git a/Docs/syzygy/pod_b.tsv b/Docs/syzygy/pod_b.tsv new file mode 100644 index 0000000..c8374d8 --- /dev/null +++ b/Docs/syzygy/pod_b.tsv @@ -0,0 +1,40 @@ +1 SCL SCL +2 +5V P5V +3 SDA SDA +4 R_GA I2C_ADR_SEL +5 S0_D0P DIFF6_P +6 S1_D1P DIFF7_PCLK_P +7 S2_D0N DIFF6_N +8 S3_D1N DIFF7_PCLK_N +9 S4_D2P DIFF8_P +10 S5_D3P DIFF9_PCLK_P +11 S6_D2N DIFF8_N +12 S7_D3N DIFF9_PCLK_N +13 S8_D4P DIFF10_P +14 S9_D5P DIFF11_PCLK_P +15 S10_D4N DIFF10_N +16 S11_D5N DIFF11_PCLK_N +17 S12_D6P DIFF12_P +18 S13_D7P DIFF13_PCLK_P +19 S14_D6N DIFF12_N +20 S15_D7N DIFF13_PCLK_N +21 S16 GPIO_N8_GPLL_T +22 S17 GPIO_M8_GPLL_C +23 S18 GPIO_G8_PCLK_C +24 S19 GPIO_H8_PCLK_T +25 S20 +26 S21 +27 S22 +28 S23 +29 S24 +30 S25 +31 S26 +32 S27 +33 P2C_CLKP +34 C2P_CLKP +35 P2C_CLKN +36 C2P_CLKN +37 RSVD +38 RSVD +39 VIO1 PVDD_2 +40 +3.3V P3V3D diff --git a/Docs/syzygy/summary.py b/Docs/syzygy/summary.py new file mode 100644 index 0000000..3912da4 --- /dev/null +++ b/Docs/syzygy/summary.py @@ -0,0 +1,43 @@ +import sys + +def read_tsv(path) -> dict: + table = {} + with open(path) as f: + for line in f: + row = line.strip().split('\t') + table[int(row[0])] = { "src": row[1:] } + return table + +def parse_pinout_table(table) -> None: + for k, v in table.items(): + v['pin_name'] = v['src'][0] + +def parse_pod_table(table) -> None: + for k, v in table.items(): + v['pin_name'] = v['src'][0] + v['pin_signal'] = v['src'][1] if len(v['src']) > 1 else '-' + +def merge_pod_table(pinout, pod, name) -> None: + for k, v in pod.items(): + n1 = pinout[k]['pin_name'].lower() + n2 = v['pin_name'].lower() + if not n1.startswith(n2) and not n1.endswith(n2): + print(f'warn: {n1} and {n2} do not match') + pinout[k][name] = v['pin_signal'] + +def main(argv): + pinout = read_tsv(argv[1]) + parse_pinout_table(pinout) + for path in argv[2:]: + pod = read_tsv(path) + parse_pod_table(pod) + merge_pod_table(pinout, pod, path) + print('\t\t', end='') + print('\t'.join(s[:-4] for s in argv[2:])) + for k, v in pinout.items(): + print(k, end='\t') + print(v['pin_name'], end='\t') + print('\t'.join([v[f] if f in v else '-' for f in argv[2:]])) + +if __name__ == "__main__": + main(sys.argv) diff --git a/Docs/syzygy/syzygy.tsv b/Docs/syzygy/syzygy.tsv new file mode 100644 index 0000000..e753852 --- /dev/null +++ b/Docs/syzygy/syzygy.tsv @@ -0,0 +1,41 @@ + szg_camera szg_dac_ad911x szg_adc_ltc226x szg_enet1g szg_mipi_8320 pod_a pod_b +1 SCL - - - - - SCL SCL +2 +5V - - - - - P5V P5V +3 SDA - - - - - SDA SDA +4 R_GA - - - - - I2C_ADR_SEL I2C_ADR_SEL +5 S0_D0P SLVS0_P DB0 OUT1A+ RX_CTL CAM1_CLK_P DIFF0_P DIFF6_P +6 S1_D1P FLASH DB1 FR+ RESET_ENET_N CAM2_LANE0_P DIFF1_PCLK_P DIFF7_PCLK_P +7 S2_D0N SLVS0_N DB2 OUT1A- TX_CTL CAM1_CLK_N DIFF0_N DIFF6_N +8 S3_D1N RESET_B DB3 FR- INT_N CAM2_LANE0_N DIFF1_PCLK_N DIFF7_PCLK_N +9 S4_D2P SLVS1_P DB4 OUT1B+ RXD3 CAM1_LANE0_P DIFF2_P DIFF8_P +10 S5_D3P TRIGGER DB5 OUT2A+ TXD0 CAM3_CLK_P DIFF3_PCLK_P DIFF9_PCLK_P +11 S6_D2N SLVS1_N DB6 OUT1B- RXD2 CAM1_LANE0_N DIFF2_N DIFF8_N +12 S7_D3N SHUTTER DB7 OUT2A- TXD1 CAM3_CLK_N DIFF3_PCLK_N DIFF9_PCLK_N +13 S8_D4P SLVS2_P DB8 SDO RXD1 CAM1_LANE1_P DIFF4_PCLK_P DIFF10_P +14 S9_D5P FOCUS_SDA DB9 OUT2B+ TXD2 CAM2_LANE1_P DIFF5_PCLK_P DIFF11_PCLK_P +15 S10_D4N SLVS2_N DB10 CS_B RXD0 CAM1_LANE1_N DIFF4_PCLK_N DIFF10_N +16 S11_D5N FOCUS_SCL DB11 OUT2B- TXD3 CAM2_LANE1_N - DIFF11_PCLK_N +17 S12_D6P SLVS3_P CS_B/PWRDN SCLK EEPROM_SCL CAM2_CLK_P - DIFF12_P +18 S13_D7P FOCUS_SDI SCLK/CLKMD - MDC CAM3_LANE0_P - DIFF13_PCLK_P +19 S14_D6N SLVS3_N SDIO/FORMAT SDI EEPROM_SDA CAM2_CLK_N - DIFF12_N +20 S15_D7N FOCUS_SDO OPAMP_ENABLE - MDIO CAM3_LANE0_N - DIFF13_PCLK_N +21 S16 SDATA RESET/PINMD - - CAM1_GPIO0_VIO GPIO_0 GPIO_N8_GPLL_T +22 S17 FOCUS_SCK - - - CAM1_SCL_VIO GPIO_1 GPIO_M8_GPLL_C +23 S18 SCLK - - - CAM1_GPIO1_VIO GPIO_2 GPIO_G8_PCLK_C +24 S19 FOCUS_SS_B - - - CAM1_SDA_VIO GPIO_3 GPIO_H8_PCLK_T +25 S20 SADDR - - - CAM2_GPIO0_VIO - - +26 S21 FOCUS_RST_B - - - CAM2_SCL_VIO - - +27 S22 PGOOD - - - CAM2_GPIO1_VIO - - +28 S23 - - - - CAM2_SDA_VIO - - +29 S24 - - - - CAM3_GPIO0_VIO - - +30 S25 - - - - CAM3_SCL_VIO - - +31 S26 - - - - CAM3_GPIO1_VIO - - +32 S27 - - - - CAM3_SDA_VIO - - +33 P2C_CLKP SLVSC_P DCLKIO DCO+ RX_CLK CAM3_LANE1_P - - +34 C2P_CLKP EXTCLK CLKIN ENC+ TX_CLK GPIO1_DIR - - +35 P2C_CLKN SLVSC_N - DCO- - CAM3_LANE1_N - - +36 C2P_CLKN - - ENC- - - - - +37 RSVD - - - - - - - +38 RSVD - - - - - - - +39 VIO1 - - - - - PVDD_3 PVDD_2 +40 +3.3V - - - - - P3V3D P3V3D diff --git a/Docs/syzygy/syzygy.txt b/Docs/syzygy/syzygy.txt new file mode 100644 index 0000000..6df1f30 --- /dev/null +++ b/Docs/syzygy/syzygy.txt @@ -0,0 +1,41 @@ + szg_camera szg_dac_ad911x szg_adc_ltc226x szg_enet1g szg_mipi_8320 pod_a pod_b +1 SCL - - - - - SCL SCL +2 +5V - - - - - P5V P5V +3 SDA - - - - - SDA SDA +4 R_GA - - - - - I2C_ADR_SEL I2C_ADR_SEL +5 S0_D0P SLVS0_P DB0 OUT1A+ RX_CTL CAM1_CLK_P DIFF0_P DIFF6_P +6 S1_D1P FLASH DB1 FR+ RESET_ENET_N CAM2_LANE0_P DIFF1_PCLK_P DIFF7_PCLK_P +7 S2_D0N SLVS0_N DB2 OUT1A- TX_CTL CAM1_CLK_N DIFF0_N DIFF6_N +8 S3_D1N RESET_B DB3 FR- INT_N CAM2_LANE0_N DIFF1_PCLK_N DIFF7_PCLK_N +9 S4_D2P SLVS1_P DB4 OUT1B+ RXD3 CAM1_LANE0_P DIFF2_P DIFF8_P +10 S5_D3P TRIGGER DB5 OUT2A+ TXD0 CAM3_CLK_P DIFF3_PCLK_P DIFF9_PCLK_P +11 S6_D2N SLVS1_N DB6 OUT1B- RXD2 CAM1_LANE0_N DIFF2_N DIFF8_N +12 S7_D3N SHUTTER DB7 OUT2A- TXD1 CAM3_CLK_N DIFF3_PCLK_N DIFF9_PCLK_N +13 S8_D4P SLVS2_P DB8 SDO RXD1 CAM1_LANE1_P DIFF4_PCLK_P DIFF10_P +14 S9_D5P FOCUS_SDA DB9 OUT2B+ TXD2 CAM2_LANE1_P DIFF5_PCLK_P DIFF11_PCLK_P +15 S10_D4N SLVS2_N DB10 CS_B RXD0 CAM1_LANE1_N DIFF4_PCLK_N DIFF10_N +16 S11_D5N FOCUS_SCL DB11 OUT2B- TXD3 CAM2_LANE1_N - DIFF11_PCLK_N +17 S12_D6P SLVS3_P CS_B/PWRDN SCLK EEPROM_SCL CAM2_CLK_P - DIFF12_P +18 S13_D7P FOCUS_SDI SCLK/CLKMD - MDC CAM3_LANE0_P - DIFF13_PCLK_P +19 S14_D6N SLVS3_N SDIO/FORMAT SDI EEPROM_SDA CAM2_CLK_N - DIFF12_N +20 S15_D7N FOCUS_SDO OPAMP_ENABLE - MDIO CAM3_LANE0_N - DIFF13_PCLK_N +21 S16 SDATA RESET/PINMD - - CAM1_GPIO0_VIO GPIO_0 GPIO_N8_GPLL_T +22 S17 FOCUS_SCK - - - CAM1_SCL_VIO GPIO_1 GPIO_M8_GPLL_C +23 S18 SCLK - - - CAM1_GPIO1_VIO GPIO_2 GPIO_G8_PCLK_C +24 S19 FOCUS_SS_B - - - CAM1_SDA_VIO GPIO_3 GPIO_H8_PCLK_T +25 S20 SADDR - - - CAM2_GPIO0_VIO - - +26 S21 FOCUS_RST_B - - - CAM2_SCL_VIO - - +27 S22 PGOOD - - - CAM2_GPIO1_VIO - - +28 S23 - - - - CAM2_SDA_VIO - - +29 S24 - - - - CAM3_GPIO0_VIO - - +30 S25 - - - - CAM3_SCL_VIO - - +31 S26 - - - - CAM3_GPIO1_VIO - - +32 S27 - - - - CAM3_SDA_VIO - - +33 P2C_CLKP SLVSC_P DCLKIO DCO+ RX_CLK CAM3_LANE1_P - - +34 C2P_CLKP EXTCLK CLKIN ENC+ TX_CLK GPIO1_DIR - - +35 P2C_CLKN SLVSC_N - DCO- - CAM3_LANE1_N - - +36 C2P_CLKN - - ENC- - - - - +37 RSVD - - - - - - - +38 RSVD - - - - - - - +39 VIO1 - - - - - PVDD_3 PVDD_2 +40 +3.3V - - - - - P3V3D P3V3D diff --git a/Docs/syzygy/szg_adc_ltc226x.tsv b/Docs/syzygy/szg_adc_ltc226x.tsv new file mode 100644 index 0000000..a3f9608 --- /dev/null +++ b/Docs/syzygy/szg_adc_ltc226x.tsv @@ -0,0 +1,18 @@ +5 D0P OUT1A+ +7 D0N OUT1A- +6 D1P FR+ +8 D1N FR- +9 D2P OUT1B+ +11 D2N OUT1B- +10 D3P OUT2A+ +12 D3N OUT2A- +13 S8 SDO +14 D5P OUT2B+ +16 D5N OUT2B- +15 S10 CS_B +17 S12 SCLK +19 S14 SDI +33 P2C_CLKp DCO+ +35 P2C_CLKn DCO- +34 C2P_CLKp ENC+ +36 C2P_CLKn ENC- diff --git a/Docs/syzygy/szg_camera.tsv b/Docs/syzygy/szg_camera.tsv new file mode 100644 index 0000000..d62f247 --- /dev/null +++ b/Docs/syzygy/szg_camera.tsv @@ -0,0 +1,26 @@ +5 D0P SLVS0_P +6 S1 FLASH +7 D0N SLVS0_N +8 S3 RESET_B +9 D2P SLVS1_P +10 S5 TRIGGER +11 D2N SLVS1_N +12 S7 SHUTTER +13 D4P SLVS2_P +14 S9 FOCUS_SDA For use with an optional Autofocus Lens mount. +15 D4N SLVS2_N +16 S11 FOCUS_SCL For use with an optional Autofocus Lens mount. +17 D6P SLVS3_P +18 S13 FOCUS_SDI For use with an optional Autofocus Lens mount. +19 D6N SLVS3_N +20 S15 FOCUS_SDO For use with an optional Autofocus Lens mount. +21 S16 SDATA +22 S17 FOCUS_SCK For use with an optional Autofocus Lens mount. +23 S18 SCLK +24 S19 FOCUS_SS_B For use with an optional Autofocus Lens mount. +25 S20 SADDR +26 S21 FOCUS_RST_B For use with an optional Autofocus Lens mount. +27 S22 PGOOD +33 P2C_CLKp SLVSC_P +34 C2P_CLKp EXTCLK +35 P2C_CLKn SLVSC_N diff --git a/Docs/syzygy/szg_dac_ad911x.tsv b/Docs/syzygy/szg_dac_ad911x.tsv new file mode 100644 index 0000000..e5ef368 --- /dev/null +++ b/Docs/syzygy/szg_dac_ad911x.tsv @@ -0,0 +1,19 @@ +5 S0 DB0 +6 S1 DB1 +7 S2 DB2 +8 S3 DB3 +9 S4 DB4 +10 S5 DB5 +11 S6 DB6 +12 S7 DB7 +13 S8 DB8 +14 S9 DB9 +15 S10 DB10 +16 S11 DB11 +17 S12 CS_B/PWRDN +18 S13 SCLK/CLKMD +19 S14 SDIO/FORMAT +20 S15 OPAMP_ENABLE Assert (1) to enable both DAC I and DAC Q outputs. Deassert (0) to place both op-amps in power-down. +21 S16 RESET/PINMD +33 P2C_CLKp DCLKIO Optional clock output (See schematics and DAC datasheet) +34 C2P_CLKp CLKIN Input clock to DAC through CLKIN level translator (U3) diff --git a/Docs/syzygy/szg_enet1g.tsv b/Docs/syzygy/szg_enet1g.tsv new file mode 100644 index 0000000..972eeab --- /dev/null +++ b/Docs/syzygy/szg_enet1g.tsv @@ -0,0 +1,18 @@ +5 D0P RX_CTL +7 D0N TX_CTL +6 D1P RESET_ENET_N +8 D1N INT_N +9 D2P RXD3 +11 D2N RXD2 +10 D3P TXD0 +12 D3N TXD1 +13 D4P RXD1 +15 D4N RXD0 +14 D5P TXD2 +16 D5N TXD3 +17 D6P EEPROM_SCL +19 D6N EEPROM_SDA +18 D7P MDC +20 D7N MDIO +33 P2C_CLKp RX_CLK +34 C2P_CLKp TX_CLK diff --git a/Docs/syzygy/szg_mipi_8320.tsv b/Docs/syzygy/szg_mipi_8320.tsv new file mode 100644 index 0000000..0960e3a --- /dev/null +++ b/Docs/syzygy/szg_mipi_8320.tsv @@ -0,0 +1,31 @@ +5 D0P CAM1_CLK_P +7 D0N CAM1_CLK_N +9 D2P CAM1_LANE0_P +11 D2N CAM1_LANE0_N +13 D4P CAM1_LANE1_P +15 D4N CAM1_LANE1_N +22 S17 CAM1_SCL_VIO +24 S19 CAM1_SDA_VIO +21 S16 CAM1_GPIO0_VIO +23 S18 CAM1_GPIO1_VIO +17 D6P CAM2_CLK_P +19 D6N CAM2_CLK_N +6 D1P CAM2_LANE0_P +8 D1N CAM2_LANE0_N +14 D5P CAM2_LANE1_P +16 D5N CAM2_LANE1_N +26 S21 CAM2_SCL_VIO +28 S23 CAM2_SDA_VIO +25 S20 CAM2_GPIO0_VIO +27 S22 CAM2_GPIO1_VIO +10 D3P CAM3_CLK_P +12 D3N CAM3_CLK_N +18 D7P CAM3_LANE0_P +20 D7N CAM3_LANE0_N +33 P2C_CLKp CAM3_LANE1_P +35 P2C_CLKn CAM3_LANE1_N +30 S25 CAM3_SCL_VIO +32 S27 CAM3_SDA_VIO +29 S24 CAM3_GPIO0_VIO +31 S26 CAM3_GPIO1_VIO +34 C2P_CLKp GPIO1_DIR diff --git a/Docs/syzygy/szg_std.tsv b/Docs/syzygy/szg_std.tsv new file mode 100644 index 0000000..d19d67c --- /dev/null +++ b/Docs/syzygy/szg_std.tsv @@ -0,0 +1,40 @@ +1 SCL +2 +5V +3 SDA +4 R_GA +5 S0_D0P +6 S1_D1P +7 S2_D0N +8 S3_D1N +9 S4_D2P +10 S5_D3P +11 S6_D2N +12 S7_D3N +13 S8_D4P +14 S9_D5P +15 S10_D4N +16 S11_D5N +17 S12_D6P +18 S13_D7P +19 S14_D6N +20 S15_D7N +21 S16 +22 S17 +23 S18 +24 S19 +25 S20 +26 S21 +27 S22 +28 S23 +29 S24 +30 S25 +31 S26 +32 S27 +33 P2C_CLKP +34 C2P_CLKP +35 P2C_CLKN +36 C2P_CLKN +37 RSVD +38 RSVD +39 VIO1 +40 +3.3V