From 28a5fd5fc73e6435c2eac46d6cc53f88c8b87ba1 Mon Sep 17 00:00:00 2001 From: Josuah Demangeon Date: Fri, 16 Feb 2024 16:27:49 +0100 Subject: [PATCH] RTL: LiteX: add a missing variable assignation for the pads --- RTL/python/litex_main_soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/RTL/python/litex_main_soc.py b/RTL/python/litex_main_soc.py index dc0be4e..6b96c45 100755 --- a/RTL/python/litex_main_soc.py +++ b/RTL/python/litex_main_soc.py @@ -283,7 +283,7 @@ def add_ahb_slave_port(self, origin, size=0x10000, id=0, width=32): self.bus.add_slave(name=f"ahb{id}", slave=port.bus, region=region) def add_wb_master_port(self, id=0, width=32): - self.platform.request("wishbone", id) + pads = self.platform.request("wishbone", id) port = VerilogWBPort(pads, width=width, mode="slave") self.submodules += port self.bus.add_master(name=f"wb{id}", master=port.bus)