diff --git a/Docs/som_clocks.md b/Docs/som_clocks.md
index adff2ef..7dc974d 100644
--- a/Docs/som_clocks.md
+++ b/Docs/som_clocks.md
@@ -27,8 +27,8 @@ and value for a given clock setup.
 
 ## Hardware integration
 
-The USB differential clock generation is already integrated internally
-in the SoM.
+The USB differential clock generation is already integrated in the SoM.
+Here is the description of how it works internally.
 
 The extra free output clock may be looped back to the external input clock pin,
 so that the PLL provides a clock with an arbitrary frequency directly to the FPGA.
@@ -40,6 +40,9 @@ It is also possible to provide an external input clock source to the FPGA.
 
 ## RTL integration
 
+The clocks are already integrated in the RTL.
+Here is the description of how it works internally.
+
 The FPGA can use the external input clock, routed to its pin `H8`, which is
 a primary clock pin (PCLK), usable for DDR I/O.
 
diff --git a/Docs/som_mipi.md b/Docs/som_mipi.md
index 5a83c86..c612f81 100644
--- a/Docs/som_mipi.md
+++ b/Docs/som_mipi.md
@@ -13,6 +13,8 @@ pairs available.
 
 ## Hardware integration
 
+The MIPI pins are capable of 1.2 Gbit/s I/O in differential mode.
+
 Each MIPI interface can have more or less differential pairs for the data lanes,
 and always one dedicated pair for the associated clock signal.