From 80f718b4a4af185f5359f4e9f993384738b8b654 Mon Sep 17 00:00:00 2001 From: Ramla-I Date: Fri, 6 Nov 2020 16:47:48 -0600 Subject: [PATCH 01/31] weird Cargo.lock changes --- Cargo.lock | 2560 ++++++++++++++++++++++++++-------------------------- 1 file changed, 1273 insertions(+), 1287 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index c693f31b58..42f6d55e9b 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -4,143 +4,145 @@ name = "acpi" version = "0.1.0" dependencies = [ - "acpi_table 0.1.0", - "acpi_table_handler 0.1.0", - "ap_start 0.1.0", - "apic 0.1.0", - "fadt 0.1.0", - "hpet 0.1.0", - "ioapic 0.1.0", - "irq_safety 0.1.1 (git+https://github.com/kevinaboos/irq_safety)", - "kernel_config 0.1.0", - "lazy_static 1.2.0 (registry+https://github.com/rust-lang/crates.io-index)", - "log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)", - "madt 0.1.0", - "memory 0.1.0", - "pause 0.1.0", - "pic 0.1.0", - "pit_clock 0.1.0", - "rsdp 0.1.0", - "rsdt 0.1.0", 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(git+https://github.com/kevinaboos/zero.git)" = "" -"checksum zerocopy 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)" = "6580539ad917b7c026220c4b3f2c08d52ce54d6ce0dc491e66002e35388fab46" -"checksum zerocopy-derive 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "d498dbd1fd7beb83c86709ae1c33ca50942889473473d287d56ce4770a18edfb" + "proc-macro2 1.0.24", + "syn 1.0.48", + "synstructure", +] diff --git a/libs/x86_64 b/libs/x86_64 index 937480ce5b..a14bb1a15a 160000 --- a/libs/x86_64 +++ b/libs/x86_64 @@ -1 +1 @@ -Subproject commit 937480ce5bb2899cd9e1834e8e0d6f88a3c9d091 +Subproject commit a14bb1a15adacf844e69e0615a30ab56284636e2 From c9d97219673eb1a5fc5b38e82f58bfa22e79ff9c Mon Sep 17 00:00:00 2001 From: Ramla-I Date: Tue, 23 Mar 2021 22:03:59 -0500 Subject: [PATCH 03/31] started crates --- Cargo.lock | 118 ++++++++++++++------- kernel/mellanox_ethernet/Cargo.toml | 21 ++++ kernel/mellanox_ethernet/src/lib.rs | 35 +++++++ kernel/mlx5/Cargo.toml | 64 ++++++++++++ kernel/mlx5/src/initialization_segment.rs | 11 ++ kernel/mlx5/src/lib.rs | 122 ++++++++++++++++++++++ kernel/mlx5/src/test_mlx5_driver.rs | 79 ++++++++++++++ 7 files changed, 415 insertions(+), 35 deletions(-) create mode 100644 kernel/mellanox_ethernet/Cargo.toml create mode 100644 kernel/mellanox_ethernet/src/lib.rs create mode 100644 kernel/mlx5/Cargo.toml create mode 100644 kernel/mlx5/src/initialization_segment.rs create mode 100644 kernel/mlx5/src/lib.rs create mode 100644 kernel/mlx5/src/test_mlx5_driver.rs diff --git a/Cargo.lock b/Cargo.lock index d66c6349b7..f3a2ea4d3d 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -11,7 +11,7 @@ dependencies = [ "fadt", "hpet", "ioapic", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -55,7 +55,7 @@ version = "0.1.0" dependencies = [ "apic", "interrupts", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -74,7 +74,7 @@ dependencies = [ "atomic", "atomic_linked_list", "bit_field 0.7.0", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -279,7 +279,7 @@ dependencies = [ "exceptions_full", "first_application", "interrupts", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "keycodes_ascii", "log", @@ -597,7 +597,7 @@ dependencies = [ "apic", "intel_ethernet", "interrupts", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -645,7 +645,7 @@ dependencies = [ name = "ethernet_smoltcp_device" version = "0.1.0" dependencies = [ - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "memory", @@ -742,7 +742,7 @@ name = "fault_log" version = "0.1.0" dependencies = [ "apic", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "memory", @@ -902,7 +902,7 @@ name = "heap" version = "0.1.0" dependencies = [ "block_allocator", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "log", "memory", @@ -914,7 +914,7 @@ name = "heapfile" version = "0.1.0" dependencies = [ "fs_node", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "memory", "spin", @@ -1000,7 +1000,7 @@ dependencies = [ "apic", "exceptions_early", "gdt", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "keyboard", "lazy_static", @@ -1043,6 +1043,16 @@ dependencies = [ "zerocopy", ] +[[package]] +name = "irq_safety" +version = "0.1.1" +source = "git+https://github.com/kevinaboos/irq_safety#d7903a8f064170fae58a3da477300469faaf28d2" +dependencies = [ + "owning_ref", + "spin", + "stable_deref_trait 1.1.1 (git+https://github.com/theseus-os/stable_deref_trait.git?branch=spin)", +] + [[package]] name = "irq_safety" version = "0.1.1" @@ -1073,7 +1083,7 @@ dependencies = [ "hpet", "intel_ethernet", "interrupts", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -1272,7 +1282,7 @@ dependencies = [ "acpi_table", "apic", "ioapic", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "memory", "pic", @@ -1291,7 +1301,7 @@ name = "mapper_spillful" version = "0.1.0" dependencies = [ "cfg-if", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -1301,6 +1311,17 @@ dependencies = [ "rbtree", ] +[[package]] +name = "mellanox_ethernet" +version = "0.1.0" +dependencies = [ + "bit_field 0.7.0", + "log", + "memory", + "volatile", + "zerocopy", +] + [[package]] name = "memchr" version = "2.1.3" @@ -1315,7 +1336,7 @@ name = "memfs" version = "0.1.0" dependencies = [ "fs_node", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "memory", "spin", @@ -1339,7 +1360,7 @@ dependencies = [ "bit_field 0.7.0", "bitflags", "frame_allocator", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -1359,7 +1380,7 @@ name = "memory_initialization" version = "0.1.0" dependencies = [ "heap", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "log", "memory", @@ -1403,6 +1424,33 @@ dependencies = [ "vfs_node", ] +[[package]] +name = "mlx5" +version = "0.1.0" +dependencies = [ + "apic", + "intel_ethernet", + "interrupts", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", + "kernel_config", + "lazy_static", + "log", + "memory", + "mpmc", + "network_interface_card", + "nic_buffers", + "nic_initialization", + "nic_queues", + "owning_ref", + "pci", + "pic", + "spin", + "static_assertions", + "volatile", + "x86_64", + "zerocopy", +] + [[package]] name = "mm_eval" version = "0.1.0" @@ -1484,7 +1532,7 @@ dependencies = [ "acpi", "ap_start", "apic", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "log", "madt", @@ -1507,7 +1555,7 @@ dependencies = [ "hashbrown", "heap", "intrusive-collections", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "log", "memory", @@ -1537,7 +1585,7 @@ version = "0.1.0" dependencies = [ "captain", "exceptions_early", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "log", "logger", @@ -1650,7 +1698,7 @@ dependencies = [ "hpet", "http_client", "httparse", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "itertools", "log", "network_manager", @@ -1842,7 +1890,7 @@ dependencies = [ "apic", "atomic", "bit_field 0.10.0", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "memory", @@ -2042,7 +2090,7 @@ version = "0.1.0" dependencies = [ "debugit", "hpet", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "scheduler", "spin", @@ -2111,7 +2159,7 @@ dependencies = [ name = "rtc" version = "0.1.0" dependencies = [ - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -2126,7 +2174,7 @@ name = "runqueue" version = "0.1.0" dependencies = [ "atomic_linked_list", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "runqueue_priority", @@ -2140,7 +2188,7 @@ name = "runqueue_priority" version = "0.1.0" dependencies = [ "atomic_linked_list", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "single_simd_task_optimization", @@ -2152,7 +2200,7 @@ name = "runqueue_round_robin" version = "0.1.0" dependencies = [ "atomic_linked_list", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "single_simd_task_optimization", @@ -2179,7 +2227,7 @@ name = "scheduler" version = "0.1.0" dependencies = [ "apic", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "runqueue", "scheduler_priority", @@ -2262,7 +2310,7 @@ checksum = "388a1df253eca08550bef6c72392cfe7c30914bf41df5269b68cbd6ff8f570a3" name = "serial_port" version = "0.1.0" dependencies = [ - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "port_io", ] @@ -2408,7 +2456,7 @@ dependencies = [ "fault_crate_swap", "fault_log", "fs_node", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "memory", @@ -2487,7 +2535,7 @@ version = "0.1.0" dependencies = [ "atomic_linked_list", "hpet", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "memory", @@ -2594,7 +2642,7 @@ version = "0.1.0" dependencies = [ "context_switch", "environment", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -2714,7 +2762,7 @@ name = "tlb_shootdown" version = "0.1.0" dependencies = [ "apic", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "memory", "pause", @@ -2861,7 +2909,7 @@ name = "virtual_nic" version = "0.1.0" dependencies = [ "intel_ethernet", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "network_interface_card", "nic_buffers", "nic_queues", @@ -2894,7 +2942,7 @@ dependencies = [ name = "wait_queue" version = "0.1.0" dependencies = [ - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "scheduler", "task", @@ -2961,7 +3009,7 @@ version = "0.1.2" dependencies = [ "bit_field 0.7.0", "bitflags", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/kevinaboos/irq_safety)", ] [[package]] diff --git a/kernel/mellanox_ethernet/Cargo.toml b/kernel/mellanox_ethernet/Cargo.toml new file mode 100644 index 0000000000..74c988a5be --- /dev/null +++ b/kernel/mellanox_ethernet/Cargo.toml @@ -0,0 +1,21 @@ +[package] +name = "mellanox_ethernet" +description = "defines structs and traits for SW objects unique to Mellanox NICs" +version = "0.1.0" +authors = ["Ramla-I "] +build = "../../build.rs" + +[dependencies] +volatile = "0.2.7" +bit_field = "0.7.0" +zerocopy = "0.3.0" + +[dependencies.memory] +path = "../memory" + +[dependencies.log] +version = "0.4.8" + + +[lib] +crate-type = ["rlib"] diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs new file mode 100644 index 0000000000..3aca4cc3c9 --- /dev/null +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -0,0 +1,35 @@ + #![no_std] + +// #[macro_use]extern crate log; +extern crate memory; +extern crate volatile; +extern crate bit_field; +extern crate zerocopy; + +const MAX_CMND_QUEUE_ENTRIES: usize = 64; + +struct CommandQueue { + entries: [CommandQueueEntry, MAX_CMND_QUEUE_ENTRIES] +} + +struct CommandQueueEntry { + type: u32, + input_length: u32, + input_mailbox_pointer: u64, + command_input_inline_data: u32, + command_output_inline_data: u32, + output_mailbox_pointer: u64, + output_length: u32, + status: u8, + _padding: u8, + signature: u8, + token: u8 +} + +struct UARPageFormat { + _padding1: u32, //0x00 - 0x1C + cmds_cq_ci: u32, + cqn: u32, + _padding2: + +} \ No newline at end of file diff --git a/kernel/mlx5/Cargo.toml b/kernel/mlx5/Cargo.toml new file mode 100644 index 0000000000..2a4e43d5cd --- /dev/null +++ b/kernel/mlx5/Cargo.toml @@ -0,0 +1,64 @@ +[package] +authors = ["Ramla Ijaz "] +name = "mlx5" +description = "Support for the Mellanox connectx-5 NIC and driver" +version = "0.1.0" +build = "../../build.rs" + +[dependencies] +spin = "0.4.10" +volatile = "0.2.7" +x86_64 = { path = "../../libs/x86_64" } # currently using our local copy, forked from Phil Opp's crate +owning_ref = { git = "https://github.com/theseus-os/owning-ref-rs" } +zerocopy = "0.3.0" +static_assertions = "1.1.0" + + +[dependencies.log] +version = "0.4.8" + +[dependencies.lazy_static] +features = ["spin_no_std", "nightly"] +version = "1.2.0" + +[dependencies.irq_safety] +git = "https://github.com/theseus-os/irq_safety" + +[dependencies.kernel_config] +path = "../kernel_config" + +[dependencies.memory] +path = "../memory" + +[dependencies.apic] +path = "../apic" + +[dependencies.pic] +path = "../pic" + +[dependencies.pci] +path = "../pci" + +[dependencies.interrupts] +path = "../interrupts" + +[dependencies.mpmc] +path = "../../libs/mpmc" + +[dependencies.network_interface_card] +path = "../network_interface_card" + +[dependencies.intel_ethernet] +path = "../intel_ethernet" + +[dependencies.nic_buffers] +path = "../nic_buffers" + +[dependencies.nic_queues] +path = "../nic_queues" + +[dependencies.nic_initialization] +path = "../nic_initialization" + +[lib] +crate-type = ["rlib"] diff --git a/kernel/mlx5/src/initialization_segment.rs b/kernel/mlx5/src/initialization_segment.rs new file mode 100644 index 0000000000..a5735fb6c3 --- /dev/null +++ b/kernel/mlx5/src/initialization_segment.rs @@ -0,0 +1,11 @@ + +struct InitializationSegment { + fw_rev_major: u16, + fw_rev_minor: u16, + fw_rev_subminor: u16, + cmd_interface_rev: u16, + cmdq_phy_addr: u32, + log_cmdq_stride_size-nic_interface-cmdq_phy_addr: u32, + command_doorbell_vector: u32, + _padding: [u8;x] +} \ No newline at end of file diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs new file mode 100644 index 0000000000..a01c0cae62 --- /dev/null +++ b/kernel/mlx5/src/lib.rs @@ -0,0 +1,122 @@ +#![no_std] + +#![allow(dead_code)] // to suppress warnings for unused functions/methods +#![allow(safe_packed_borrows)] // temporary, just to suppress unsafe packed borrows +#![feature(rustc_private)] +#![feature(abi_x86_interrupt)] + +#[macro_use] extern crate log; +#[macro_use] extern crate lazy_static; +#[macro_use] extern crate static_assertions; +extern crate volatile; +extern crate zerocopy; +extern crate alloc; +extern crate spin; +extern crate irq_safety; +extern crate kernel_config; +extern crate memory; +extern crate pci; +extern crate owning_ref; +extern crate interrupts; +extern crate pic; +extern crate x86_64; +extern crate mpmc; +extern crate network_interface_card; +extern crate apic; +extern crate intel_ethernet; +extern crate nic_buffers; +extern crate nic_queues; +extern crate nic_initialization; + +pub mod test_e1000_driver; +mod regs; +use regs::*; + +use spin::Once; +use alloc::vec::Vec; +use alloc::collections::VecDeque; +use irq_safety::MutexIrqSafe; +use alloc::boxed::Box; +use memory::{PhysicalAddress, MappedPages}; +use pci::{PciDevice, PCI_INTERRUPT_LINE, PciConfigSpaceAccessMechanism}; +use kernel_config::memory::PAGE_SIZE; +use owning_ref::BoxRefMut; +use interrupts::{eoi,register_interrupt}; +use x86_64::structures::idt::{ExceptionStackFrame}; +use network_interface_card:: NetworkInterfaceCard; +use nic_initialization::{allocate_memory, init_rx_buf_pool, init_rx_queue, init_tx_queue}; +use intel_ethernet::descriptors::{LegacyRxDescriptor, LegacyTxDescriptor}; +use nic_buffers::{TransmitBuffer, ReceiveBuffer, ReceivedFrame}; +use nic_queues::{RxQueue, TxQueue, RxQueueRegisters, TxQueueRegisters}; + +pub const INTEL_VEND: u16 = 0x8086; // Vendor ID for Intel +pub const E1000_DEV: u16 = 0x100E; // Device ID for the e1000 Qemu, Bochs, and VirtualBox emmulated NICs + +/// TODO: in the future, we should support multiple NICs all stored elsewhere, +/// e.g., on the PCI bus or somewhere else. +static E1000_NIC: Once> = Once::new(); + +/// Returns a reference to the E1000Nic wrapped in a MutexIrqSafe, +/// if it exists and has been initialized. +pub fn get_e1000_nic() -> Option<&'static MutexIrqSafe> { + E1000_NIC.try() +} + +/// How many ReceiveBuffers are preallocated for this driver to use. +const RX_BUFFER_POOL_SIZE: usize = 256; +lazy_static! { + /// The pool of pre-allocated receive buffers that are used by the E1000 NIC + /// and temporarily given to higher layers in the networking stack. + static ref RX_BUFFER_POOL: mpmc::Queue = mpmc::Queue::with_capacity(RX_BUFFER_POOL_SIZE); +} + + +/// Struct representing a connectx-5 network interface card. +pub struct ConnectX5Nic { + /// Type of BAR0 + bar_type: u8, + /// MMIO Base Address + mem_base: PhysicalAddress, + ///interrupt number + interrupt_num: u8, + /// The actual MAC address burnt into the hardware of this E1000 NIC. + mac_hardware: [u8; 6], + /// The optional spoofed MAC address to use in place of `mac_hardware` when transmitting. + mac_spoofed: Option<[u8; 6]>, + /// Receive queue with descriptors + rx_queue: RxQueue, + /// Transmit queue with descriptors + tx_queue: TxQueue, + /// memory-mapped control registers + regs: BoxRefMut, + /// memory-mapped registers holding the MAC address + mac_regs: BoxRefMut +} + + +/// Functions that setup the NIC struct and handle the sending and receiving of packets. +impl ConnectX5Nic { + /// Initializes the new E1000 network interface card that is connected as the given PciDevice. + pub fn init(mlx5_pci_dev: &PciDevice) -> Result<&'static MutexIrqSafe, &'static str> { + use pic::PIC_MASTER_OFFSET; + + let bar0 = mlx5_pci_dev.bars[0]; + // the initialization segment is located at offset 0 of the BAR + // Map pages of the initialization segment + + + // create command queues + + // write physical location of command queues to initialization segment + + // Read iniitalizing field from initialization segment until it is cleared + + // Execute ENABLE_HCA command + + // set the bus mastering bit for this PciDevice, which allows it to use DMA + e1000_pci_dev.pci_set_command_bus_master_bit(); + + + } + +} \ No newline at end of file diff --git a/kernel/mlx5/src/test_mlx5_driver.rs b/kernel/mlx5/src/test_mlx5_driver.rs new file mode 100644 index 0000000000..6be39e51a1 --- /dev/null +++ b/kernel/mlx5/src/test_mlx5_driver.rs @@ -0,0 +1,79 @@ +use super::{E1000_NIC, NetworkInterfaceCard, TransmitBuffer}; + +pub fn test_e1000_nic_driver(_: Option) { + match dhcp_request_packet() { + Ok(_) => debug!("test_e1000_nic_driver(): sent DHCP request packet successfully!"), + Err(e) => error!("test_e1000_nic_driver(): failed to send DHCP request packet: error {:?}", e), + }; +} + +#[repr(C, packed)] +pub struct arp_packet { + pub dest1: u16, //set to broadcast ff:ff:... + pub dest2: u16, + pub dest3: u16, + pub source1: u16, + pub source2: u16, + pub source3: u16, + pub packet_type: u16, + pub h_type: u16, + pub p_type: u16, + pub hlen: u8, + pub plen: u8, + pub oper: u16, + pub sha1: u16, //sender hw address, first 2 bytes + pub sha2: u16, // ", next 2 bytes + pub sha3: u16, // ", last 2 bytes + pub spa1: u16, // sender protocol address, first 2 B + pub spa2: u16, // ", last 2 B + pub tha1: u16, //target ", first + pub tha2: u16, // ", next + pub tha3: u16, // ", last + pub tpa1: u16, // ", first + pub tpa2: u16, // ", last +} + +//should test packet transmission and reception as QEMU DHCP server will respond + +//will only b able to see this Tx message in netdump.pcap if user is not mentioned in QEMU flags of Makefile +//QEMU_FLAGS += -net nic,vlan=0,model=e1000,macaddr=00:0b:82:01:fc:42 -net dump,file=netdump.pcap + +//will only receive a response if user is mentioned in qemu flags +//QEMU_FLAGS += -net nic,vlan=1,model=e1000,macaddr=00:0b:82:01:fc:42 -net user,vlan=1 -net dump,file=netdump.pcap + +//or else use a tap interface (default) +//QEMU_FLAGS += -device e1000,netdev=network0,mac=52:55:00:d1:55:01 -netdev tap,id=network0,ifname=tap0,script=no,downscript=no +//will receive a DHCP messgae from 00:1f:c6:9c:89:4c + +pub fn dhcp_request_packet() -> Result<(), &'static str> { + let packet: [u8; 314] = [ + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x1f, 0xc6, 0x9c, 0x89, 0x4c, 0x08, 0x00, 0x45, + 0x00, 0x01, 0x2c, 0xa8, 0x36, 0x00, 0x00, 0xfa, 0x11, 0x17, 0x8b, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0x00, 0x44, 0x00, 0x43, 0x01, 0x18, 0x59, 0x1f, 0x01, 0x01, 0x06, + 0x00, 0x00, 0x00, 0x3d, 0x1d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xc6, 0x9c, 0x89, + 0x4c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x82, 0x53, 0x63, 0x35, 0x01, 0x01, + 0x3d, 0x07, 0x01, 0x00, 0x1f, 0xc6, 0x9c, 0x89, 0x4c, 0x32, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x37, 0x04, 0x01, 0x03, 0x06, 0x2a, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ]; + let mut transmit_buffer = TransmitBuffer::new(packet.len() as u16)?; + { + let buffer: &mut [u8] = transmit_buffer.as_slice_mut(0, 314)?; + buffer.copy_from_slice(&packet); + } + let mut e1000_nc = E1000_NIC.try().ok_or("e1000 NIC hasn't been initialized yet")?.lock(); + e1000_nc.send_packet(transmit_buffer) +} From 9a4345abb03e724e65b893ef24ac466a20420a5d Mon Sep 17 00:00:00 2001 From: Ramla-I Date: Fri, 9 Apr 2021 17:00:32 -0500 Subject: [PATCH 04/31] initialization function --- Cargo.lock | 1 + kernel/mellanox_ethernet/src/lib.rs | 30 ++++-- kernel/mlx5/Cargo.toml | 3 + kernel/mlx5/src/lib.rs | 157 +++++++++++++++------------- 4 files changed, 109 insertions(+), 82 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 505d079eb8..50c22188a4 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1450,6 +1450,7 @@ dependencies = [ "kernel_config", "lazy_static", "log", + "mellanox_ethernet", "memory", "mpmc", "network_interface_card", diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index b67b803938..7734b1cdbb 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -21,7 +21,7 @@ use zerocopy::FromBytes; const MAX_CMND_QUEUE_ENTRIES: usize = 64; #[derive(FromBytes)] #[repr(C)] -struct InitializationSegment { +pub struct InitializationSegment { fw_rev_major: ReadOnly, fw_rev_minor: ReadOnly, fw_rev_subminor: ReadOnly, @@ -59,17 +59,25 @@ struct InitializationSegment { // const_assert_eq!(core::mem::size_of::(), 16396); impl InitializationSegment { - // pub fn set_physical_address_of_cmdq(pa: PhysicalAddress) { - - // } + pub fn num_cmdq_entries(&self) -> u8 { + (self.cmdq_phy_addr_low.read() >> 3) as u8 & 0x0F + } + + pub fn cmdq_entry_stride(&self) -> u8 { + (self.cmdq_phy_addr_low.read()) as u8 & 0x0F + } + pub fn set_physical_address_of_cmdq(&mut self, pa: PhysicalAddress) { + self.cmdq_phy_addr_high.write((pa.value() >> 32) as u32); + self.cmdq_phy_addr_low.write(pa.value() as u32); + } // pub fn set_doorbell(command_no: u8) { // } - // pub fn device_is_initializing() -> bool { - - // } + pub fn device_is_initializing(&self) -> bool { + self.initializing_state.read().get_bit(15) + } // pub fn initializing_state() -> InitializingState { @@ -88,13 +96,13 @@ pub enum InitializingState { /// The number of enties and the entry stride is retrieved from the initialization segment of the HCA BAR. /// It resides in a physically contiguous 4 KiB memory chunk. #[repr(C)] -struct CommandQueue { +pub struct CommandQueue { entries: Vec } #[derive(FromBytes)] #[repr(C)] -struct CommandQueueEntry { +pub struct CommandQueueEntry { type_of_transport: Volatile, input_length: Volatile, input_mailbox_pointer: Volatile, @@ -110,7 +118,7 @@ struct CommandQueueEntry { const_assert_eq!(core::mem::size_of::(), 64); -enum CommandDeliveryStatus { +pub enum CommandDeliveryStatus { Success = 0, SignatureErr = 1, TokenErr = 2, @@ -125,7 +133,7 @@ enum CommandDeliveryStatus { } #[derive(FromBytes)] #[repr(C)] -struct CommandInterfaceMailbox { +pub struct CommandInterfaceMailbox { mailbox_data: Volatile<[u8; 512]>, _padding1: [u8; 48], next_pointer: Volatile, diff --git a/kernel/mlx5/Cargo.toml b/kernel/mlx5/Cargo.toml index 2a4e43d5cd..5022fc48d6 100644 --- a/kernel/mlx5/Cargo.toml +++ b/kernel/mlx5/Cargo.toml @@ -60,5 +60,8 @@ path = "../nic_queues" [dependencies.nic_initialization] path = "../nic_initialization" +[dependencies.mellanox_ethernet] +path = "../mellanox_ethernet" + [lib] crate-type = ["rlib"] diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index 58f6987047..990aef3238 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -27,40 +27,39 @@ extern crate intel_ethernet; extern crate nic_buffers; extern crate nic_queues; extern crate nic_initialization; - -// pub mod test_e1000_driver; -// mod regs; -// use regs::*; - -// use spin::Once; -// use alloc::vec::Vec; -// use alloc::collections::VecDeque; -// use irq_safety::MutexIrqSafe; -// use alloc::boxed::Box; -// use memory::{PhysicalAddress, MappedPages}; -// use pci::{PciDevice, PCI_INTERRUPT_LINE, PciConfigSpaceAccessMechanism}; -// use kernel_config::memory::PAGE_SIZE; -// use owning_ref::BoxRefMut; -// use interrupts::{eoi,register_interrupt}; -// use x86_64::structures::idt::{ExceptionStackFrame}; -// use network_interface_card:: NetworkInterfaceCard; -// use nic_initialization::{allocate_memory, init_rx_buf_pool, init_rx_queue, init_tx_queue}; -// use intel_ethernet::descriptors::{LegacyRxDescriptor, LegacyTxDescriptor}; -// use nic_buffers::{TransmitBuffer, ReceiveBuffer, ReceivedFrame}; -// use nic_queues::{RxQueue, TxQueue, RxQueueRegisters, TxQueueRegisters}; - -// pub const INTEL_VEND: u16 = 0x8086; // Vendor ID for Intel -// pub const E1000_DEV: u16 = 0x100E; // Device ID for the e1000 Qemu, Bochs, and VirtualBox emmulated NICs - -// /// TODO: in the future, we should support multiple NICs all stored elsewhere, -// /// e.g., on the PCI bus or somewhere else. -// static E1000_NIC: Once> = Once::new(); - -// /// Returns a reference to the E1000Nic wrapped in a MutexIrqSafe, -// /// if it exists and has been initialized. -// pub fn get_e1000_nic() -> Option<&'static MutexIrqSafe> { -// E1000_NIC.try() -// } +extern crate mellanox_ethernet; + + +use spin::Once; +use alloc::vec::Vec; +use alloc::collections::VecDeque; +use irq_safety::MutexIrqSafe; +use alloc::boxed::Box; +use memory::{PhysicalAddress, MappedPages, create_contiguous_mapping}; +use pci::{PciDevice, PCI_INTERRUPT_LINE, PciConfigSpaceAccessMechanism}; +use kernel_config::memory::PAGE_SIZE; +use owning_ref::BoxRefMut; +use interrupts::{eoi,register_interrupt}; +use x86_64::structures::idt::{ExceptionStackFrame}; +use network_interface_card:: NetworkInterfaceCard; +use nic_initialization::{NIC_MAPPING_FLAGS, allocate_memory, init_rx_buf_pool, init_rx_queue, init_tx_queue}; +use intel_ethernet::descriptors::{LegacyRxDescriptor, LegacyTxDescriptor}; +use nic_buffers::{TransmitBuffer, ReceiveBuffer, ReceivedFrame}; +use nic_queues::{RxQueue, TxQueue, RxQueueRegisters, TxQueueRegisters}; +use mellanox_ethernet::{CommandQueueEntry, InitializationSegment}; + + +pub const MLX_VEND: u16 = 0x15B3; // Vendor ID for Mellanox +pub const CONNECTX5_DEV: u16 = 0x1017; // Device ID for the ConnectX-5 NIC + +/// Assuming one of these nics for now +static CONNECTX5_NIC: Once> = Once::new(); + +/// Returns a reference to the E1000Nic wrapped in a MutexIrqSafe, +/// if it exists and has been initialized. +pub fn get_mlx5_nic() -> Option<&'static MutexIrqSafe> { + CONNECTX5_NIC.try() +} // /// How many ReceiveBuffers are preallocated for this driver to use. // const RX_BUFFER_POOL_SIZE: usize = 256; @@ -71,52 +70,68 @@ extern crate nic_initialization; // } -// /// Struct representing a connectx-5 network interface card. -// pub struct ConnectX5Nic { -// /// Type of BAR0 -// bar_type: u8, -// /// MMIO Base Address -// mem_base: PhysicalAddress, -// ///interrupt number -// interrupt_num: u8, -// /// The actual MAC address burnt into the hardware of this E1000 NIC. -// mac_hardware: [u8; 6], -// /// The optional spoofed MAC address to use in place of `mac_hardware` when transmitting. -// mac_spoofed: Option<[u8; 6]>, -// /// Receive queue with descriptors -// rx_queue: RxQueue, -// /// Transmit queue with descriptors -// tx_queue: TxQueue, -// /// memory-mapped control registers -// regs: BoxRefMut, -// /// memory-mapped registers holding the MAC address -// mac_regs: BoxRefMut -// } +/// Struct representing a connectx-5 network interface card. +pub struct ConnectX5Nic { + /// Type of BAR0 + bar_type: u8, + /// MMIO Base Address + mem_base: PhysicalAddress, +} + +/// Functions that setup the NIC struct and handle the sending and receiving of packets. +impl ConnectX5Nic { + /// Initializes the new E1000 network interface card that is connected as the given PciDevice. + pub fn init(mlx5_pci_dev: &PciDevice) -> Result<(), &'static str> { //Result<&'static MutexIrqSafe, &'static str> { + use pic::PIC_MASTER_OFFSET; -// /// Functions that setup the NIC struct and handle the sending and receiving of packets. -// impl ConnectX5Nic { -// /// Initializes the new E1000 network interface card that is connected as the given PciDevice. -// pub fn init(mlx5_pci_dev: &PciDevice) -> Result<&'static MutexIrqSafe, &'static str> { -// use pic::PIC_MASTER_OFFSET; + let bar0 = mlx5_pci_dev.bars[0]; + // Determine the access mechanism from the base address register's bit 0 + let bar_type = (bar0 as u8) & 0x1; -// let bar0 = mlx5_pci_dev.bars[0]; -// // the initialization segment is located at offset 0 of the BAR -// // Map pages of the initialization segment + // If the base address is not memory mapped then exit + if bar_type == PciConfigSpaceAccessMechanism::IoPort as u8 { + error!("mlx5::init(): BAR0 is of I/O type"); + return Err("mlx5::init(): BAR0 is of I/O type") + } + + // memory mapped base address + let mem_base = mlx5_pci_dev.determine_mem_base(0)?; + // map pages to the physical address given by mem_base as that is the intialization segment + let mut init_segment = ConnectX5Nic::mapped_init_segment(mem_base)?; -// // create command queues + // find number of entries in command queue and stride + let max_cmdq_entries = init_segment.num_cmdq_entries() as usize; + let cmdq_stride = init_segment.cmdq_entry_stride(); + + // create command queue + let size_in_bytes_of_cmdq = max_cmdq_entries * core::mem::size_of::(); + + // cmdp needs to be aligned, check?? + let (cmdq_mapped_pages, cmdq_starting_phys_addr) = create_contiguous_mapping(size_in_bytes_of_cmdq, NIC_MAPPING_FLAGS)?; + + // cast our physically-contiguous MappedPages into a slice of command queue entries + let mut cmdq = BoxRefMut::new(Box::new(cmdq_mapped_pages)).try_map_mut(|mp| mp.as_slice_mut::(0, max_cmdq_entries))?; -// // write physical location of command queues to initialization segment + // write physical location of command queues to initialization segment + init_segment.set_physical_address_of_cmdq(cmdq_starting_phys_addr); -// // Read iniitalizing field from initialization segment until it is cleared + // Read iniitalizing field from initialization segment until it is cleared + while init_segment.device_is_initializing() {} + + // Execute ENABLE_HCA command -// // Execute ENABLE_HCA command + // set the bus mastering bit for this PciDevice, which allows it to use DMA + mlx5_pci_dev.pci_set_command_bus_master_bit(); -// // set the bus mastering bit for this PciDevice, which allows it to use DMA -// e1000_pci_dev.pci_set_command_bus_master_bit(); + Ok(()) -// } + } -// } \ No newline at end of file + fn mapped_init_segment(mem_base: PhysicalAddress) -> Result, &'static str> { + let mp = allocate_memory(mem_base, core::mem::size_of::())?; + BoxRefMut::new(Box::new(mp)).try_map_mut(|mp| mp.as_type_mut::(0)) + } +} \ No newline at end of file From 5fe1fe6bde9037a2bf36703731ced38b41406e65 Mon Sep 17 00:00:00 2001 From: Ramla-I Date: Mon, 12 Apr 2021 18:02:41 -0500 Subject: [PATCH 05/31] added functions for command interface --- kernel/mellanox_ethernet/src/lib.rs | 42 +++++++++++++++++++++++++---- kernel/mlx5/src/lib.rs | 2 +- 2 files changed, 38 insertions(+), 6 deletions(-) diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index 7734b1cdbb..b80c9a94cd 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -2,7 +2,7 @@ #![no_std] -// #[macro_use]extern crate log; +#[macro_use]extern crate log; extern crate memory; extern crate volatile; extern crate bit_field; @@ -100,22 +100,31 @@ pub struct CommandQueue { entries: Vec } -#[derive(FromBytes)] +#[derive(FromBytes, Default)] #[repr(C)] pub struct CommandQueueEntry { type_of_transport: Volatile, input_length: Volatile, input_mailbox_pointer: Volatile, - command_input_inline_data: Volatile, - command_output_inline_data: Volatile, + padding1: WriteOnly, + command_input_opcode: Volatile, + command_input_op_mod: Volatile, + padding2: WriteOnly, + command_input_inline_data: Volatile, + padding3: WriteOnly, + padding4: WriteOnly, + command_output_status: Volatile, + command_output_syndrome: Volatile, + command_output_inline_data: Volatile, output_mailbox_pointer: Volatile, output_length: Volatile, status: Volatile, - _padding: u8, + padding5: WriteOnly, signature: Volatile, token: Volatile } + const_assert_eq!(core::mem::size_of::(), 64); pub enum CommandDeliveryStatus { @@ -131,6 +140,17 @@ pub enum CommandDeliveryStatus { ReservedNotZero = 9, BadCommandType = 10 //Should this be 10 or 16?? } + +pub enum CommandOpcode { + QueryHcaCap = 0x100, + QueryAdapter = 0x101, + InitHca = 0x102, + TeardownHca = 0x103, + EnableHca = 0x104, + DisableHca = 0x105, + QueryPages = 0x107, + ManagePages = 0x108 +} #[derive(FromBytes)] #[repr(C)] pub struct CommandInterfaceMailbox { @@ -146,6 +166,18 @@ pub struct CommandInterfaceMailbox { const_assert_eq!(core::mem::size_of::(), 576); +pub fn init_cmdq_entry(entry: &mut CommandQueueEntry, command: CommandOpcode) { + match command { + CommandOpcode::InitHca => { + let mut init_hca = CommandQueueEntry::default(); + init_hca.command_input_opcode.write(CommandOpcode::InitHca as u16); + core::mem::swap(&mut init_hca, entry); + } + _=> { + debug!("unimplemented opcode"); + } + } +} // #[derive(FromBytes)] // #[repr(C)] // struct UARPageFormat { diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index 990aef3238..460cfc3c9d 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -117,7 +117,7 @@ impl ConnectX5Nic { // write physical location of command queues to initialization segment init_segment.set_physical_address_of_cmdq(cmdq_starting_phys_addr); - // Read iniitalizing field from initialization segment until it is cleared + // Read initalizing field from initialization segment until it is cleared while init_segment.device_is_initializing() {} // Execute ENABLE_HCA command From 2d80219ca65344d36fc6cbebdcf4618461182552 Mon Sep 17 00:00:00 2001 From: Ramla-I Date: Fri, 30 Apr 2021 15:48:23 -0500 Subject: [PATCH 06/31] updates --- kernel/mlx5/src/lib.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index 460cfc3c9d..4c0455b6cf 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -50,7 +50,7 @@ use mellanox_ethernet::{CommandQueueEntry, InitializationSegment}; pub const MLX_VEND: u16 = 0x15B3; // Vendor ID for Mellanox -pub const CONNECTX5_DEV: u16 = 0x1017; // Device ID for the ConnectX-5 NIC +pub const CONNECTX5_DEV: u16 = 0x1019; // Device ID for the ConnectX-5 NIC /// Assuming one of these nics for now static CONNECTX5_NIC: Once> = Once::new(); From b1d194af7b16e24ae4cab38812d6f57c842ab722 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Fri, 21 May 2021 13:49:01 -0700 Subject: [PATCH 07/31] ... --- Cargo.lock | 84 ++++++++++++++----------- kernel/device_manager/Cargo.toml | 2 + kernel/device_manager/src/lib.rs | 5 ++ kernel/mellanox_ethernet/Cargo.toml | 1 + kernel/mellanox_ethernet/src/lib.rs | 98 ++++++++++++++++++++++++++--- kernel/mlx5/src/lib.rs | 37 +++++++++-- 6 files changed, 177 insertions(+), 50 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 951800ee83..fb050cab21 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -11,7 +11,7 @@ dependencies = [ "fadt", "hpet", "ioapic", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -61,7 +61,7 @@ version = "0.1.0" dependencies = [ "apic", "interrupts", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -80,7 +80,7 @@ dependencies = [ "atomic", "atomic_linked_list", "bit_field 0.7.0", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -285,7 +285,7 @@ dependencies = [ "exceptions_full", "first_application", "interrupts", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "keycodes_ascii", "log", @@ -558,6 +558,7 @@ dependencies = [ "keyboard", "log", "memory", + "mlx5", "mouse", "mpmc", "network_manager", @@ -569,7 +570,7 @@ dependencies = [ name = "dfqueue" version = "0.1.0" dependencies = [ - "spin 0.9.0", + "spin 0.4.10", ] [[package]] @@ -603,7 +604,7 @@ dependencies = [ "apic", "intel_ethernet", "interrupts", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -651,7 +652,7 @@ dependencies = [ name = "ethernet_smoltcp_device" version = "0.1.0" dependencies = [ - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "memory", @@ -748,7 +749,7 @@ name = "fault_log" version = "0.1.0" dependencies = [ "apic", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "memory", @@ -908,7 +909,7 @@ name = "heap" version = "0.1.0" dependencies = [ "block_allocator", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "log", "memory", @@ -920,7 +921,7 @@ name = "heapfile" version = "0.1.0" dependencies = [ "fs_node", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "memory", "spin 0.9.0", @@ -1006,7 +1007,7 @@ dependencies = [ "apic", "exceptions_early", "gdt", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "keyboard", "lazy_static", @@ -1049,6 +1050,16 @@ dependencies = [ "zerocopy", ] +[[package]] +name = "irq_safety" +version = "0.1.1" +source = "git+https://github.com/kevinaboos/irq_safety#9c6d7633b0462b645f67b7f9928fdc26646a4c81" +dependencies = [ + "owning_ref", + "spin 0.9.0", + "stable_deref_trait 1.1.1 (git+https://github.com/theseus-os/stable_deref_trait.git?branch=spin)", +] + [[package]] name = "irq_safety" version = "0.1.1" @@ -1079,7 +1090,7 @@ dependencies = [ "hpet", "intel_ethernet", "interrupts", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -1286,7 +1297,7 @@ dependencies = [ name = "logger" version = "0.1.0" dependencies = [ - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "serial_port", "spin 0.9.0", @@ -1311,7 +1322,7 @@ dependencies = [ "acpi_table", "apic", "ioapic", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "memory", "pic", @@ -1330,7 +1341,7 @@ name = "mapper_spillful" version = "0.1.0" dependencies = [ "cfg-if", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -1347,6 +1358,7 @@ dependencies = [ "bit_field 0.7.0", "log", "memory", + "owning_ref", "static_assertions", "volatile", "zerocopy", @@ -1363,7 +1375,7 @@ name = "memfs" version = "0.1.0" dependencies = [ "fs_node", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "memory", "spin 0.9.0", @@ -1387,7 +1399,7 @@ dependencies = [ "bit_field 0.7.0", "bitflags", "frame_allocator", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -1407,7 +1419,7 @@ name = "memory_initialization" version = "0.1.0" dependencies = [ "heap", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "log", "memory", @@ -1560,7 +1572,7 @@ dependencies = [ "acpi", "ap_start", "apic", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "log", "madt", @@ -1583,7 +1595,7 @@ dependencies = [ "hashbrown", "heap", "intrusive-collections", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "log", "memory", @@ -1613,7 +1625,7 @@ version = "0.1.0" dependencies = [ "captain", "exceptions_early", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "log", "logger", @@ -1727,7 +1739,7 @@ dependencies = [ "hpet", "http_client", "httparse", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "itertools", "log", "network_manager", @@ -1919,7 +1931,7 @@ dependencies = [ "apic", "atomic", "bit_field 0.10.0", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "memory", @@ -2119,7 +2131,7 @@ version = "0.1.0" dependencies = [ "debugit", "hpet", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "scheduler", "spin 0.9.0", @@ -2188,7 +2200,7 @@ dependencies = [ name = "rtc" version = "0.1.0" dependencies = [ - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -2203,7 +2215,7 @@ name = "runqueue" version = "0.1.0" dependencies = [ "atomic_linked_list", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "runqueue_priority", @@ -2217,7 +2229,7 @@ name = "runqueue_priority" version = "0.1.0" dependencies = [ "atomic_linked_list", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "single_simd_task_optimization", @@ -2229,7 +2241,7 @@ name = "runqueue_round_robin" version = "0.1.0" dependencies = [ "atomic_linked_list", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "single_simd_task_optimization", @@ -2256,7 +2268,7 @@ name = "scheduler" version = "0.1.0" dependencies = [ "apic", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "runqueue", "scheduler_priority", @@ -2484,7 +2496,7 @@ dependencies = [ "fault_crate_swap", "fault_log", "fs_node", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "memory", @@ -2571,7 +2583,7 @@ version = "0.1.0" dependencies = [ "atomic_linked_list", "hpet", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "lazy_static", "log", "memory", @@ -2678,7 +2690,7 @@ version = "0.1.0" dependencies = [ "context_switch", "environment", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "kernel_config", "lazy_static", "log", @@ -2798,7 +2810,7 @@ name = "tlb_shootdown" version = "0.1.0" dependencies = [ "apic", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "memory", "pause", @@ -2945,7 +2957,7 @@ name = "virtual_nic" version = "0.1.0" dependencies = [ "intel_ethernet", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "network_interface_card", "nic_buffers", "nic_queues", @@ -2978,7 +2990,7 @@ dependencies = [ name = "wait_queue" version = "0.1.0" dependencies = [ - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/theseus-os/irq_safety)", "log", "scheduler", "task", @@ -3045,7 +3057,7 @@ version = "0.1.2" dependencies = [ "bit_field 0.7.0", "bitflags", - "irq_safety", + "irq_safety 0.1.1 (git+https://github.com/kevinaboos/irq_safety)", ] [[package]] diff --git a/kernel/device_manager/Cargo.toml b/kernel/device_manager/Cargo.toml index d6a5d8546c..98e78f495b 100644 --- a/kernel/device_manager/Cargo.toml +++ b/kernel/device_manager/Cargo.toml @@ -49,6 +49,8 @@ path = "../ethernet_smoltcp_device" [dependencies.ixgbe] path = "../ixgbe" +[dependencies.mlx5] +path = "../mlx5" [lib] crate-type = ["rlib"] diff --git a/kernel/device_manager/src/lib.rs b/kernel/device_manager/src/lib.rs index b509bc114d..0674fafde9 100644 --- a/kernel/device_manager/src/lib.rs +++ b/kernel/device_manager/src/lib.rs @@ -16,6 +16,7 @@ extern crate ethernet_smoltcp_device; extern crate mpmc; extern crate ixgbe; extern crate alloc; +extern crate mlx5; use mpmc::Queue; use event_types::Event; @@ -116,6 +117,10 @@ pub fn init(key_producer: Queue, mouse_producer: Queue) -> Result< ixgbe_devs.push(ixgbe_nic); continue; } + if dev.vendor_id == mlx5::MLX_VEND && dev.device_id == mlx5::CONNECTX5_DEV { + info!("mlx5 PCI device found at: {:?}", dev.location); + mlx5::ConnectX5Nic::init(dev)?; + } // here: check for and initialize other ethernet cards } diff --git a/kernel/mellanox_ethernet/Cargo.toml b/kernel/mellanox_ethernet/Cargo.toml index 4f3cf69c74..d485cca7be 100644 --- a/kernel/mellanox_ethernet/Cargo.toml +++ b/kernel/mellanox_ethernet/Cargo.toml @@ -10,6 +10,7 @@ volatile = "0.2.7" bit_field = "0.7.0" zerocopy = "0.3.0" static_assertions = "1.1.0" +owning_ref = { git = "https://github.com/theseus-os/owning-ref-rs" } [dependencies.memory] diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index b80c9a94cd..a23d931376 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -9,18 +9,19 @@ extern crate bit_field; extern crate zerocopy; extern crate alloc; #[macro_use] extern crate static_assertions; - +extern crate owning_ref; use alloc::vec::Vec; -use memory::{PhysicalAddress, PhysicalMemoryRegion}; +use memory::{PhysicalAddress, PhysicalMemoryRegion, MappedPages}; use volatile::{Volatile, ReadOnly, WriteOnly}; use bit_field::BitField; use zerocopy::FromBytes; +use owning_ref:: BoxRefMut; // Taken from HCA BAR const MAX_CMND_QUEUE_ENTRIES: usize = 64; #[derive(FromBytes)] -#[repr(C)] +#[repr(C,packed)] pub struct InitializationSegment { fw_rev_major: ReadOnly, fw_rev_minor: ReadOnly, @@ -29,7 +30,7 @@ pub struct InitializationSegment { _padding1: [u8; 8], cmdq_phy_addr_high: Volatile, cmdq_phy_addr_low: Volatile, - command_doorbell_vector: WriteOnly, + command_doorbell_vector: Volatile, _padding2a: [u8; 256], _padding2b: [u8; 128], _padding2c: [u8; 98], @@ -56,11 +57,11 @@ pub struct InitializationSegment { _padding6h: [u8; 4], } -// const_assert_eq!(core::mem::size_of::(), 16396); +// const_assert_eq!(core::mem::size_of::(), 16400); impl InitializationSegment { pub fn num_cmdq_entries(&self) -> u8 { - (self.cmdq_phy_addr_low.read() >> 3) as u8 & 0x0F + (self.cmdq_phy_addr_low.read() >> 4) as u8 & 0x0F } pub fn cmdq_entry_stride(&self) -> u8 { @@ -79,9 +80,26 @@ impl InitializationSegment { self.initializing_state.read().get_bit(15) } + pub fn pf_reset(&mut self) { + let val = self.cmdq_phy_addr_low.read(); + self.cmdq_phy_addr_low.write(val | (0x7 << 8)); + } + // pub fn initializing_state() -> InitializingState { // } + + pub fn post_command(&mut self, command_bit: usize) { + let val = self.command_doorbell_vector.read(); + self.command_doorbell_vector.write(val | (1 << command_bit)); + } + + pub fn print(&self) { + trace!("{:#X} {:#X} {:#X} {:#X}",self.fw_rev_major.read(), self.fw_rev_minor.read(), self.fw_rev_subminor.read(), self.cmd_interface_rev.read()); + trace!("{:#X} {:#X}",self.cmdq_phy_addr_high.read(), self.cmdq_phy_addr_low.read()); + trace!("{:#X}",self.command_doorbell_vector.read()); + trace!("{:#X}",self.initializing_state.read()); + } } pub enum InitializingState { @@ -97,7 +115,8 @@ pub enum InitializingState { /// It resides in a physically contiguous 4 KiB memory chunk. #[repr(C)] pub struct CommandQueue { - entries: Vec + pub entries: BoxRefMut, + pub current_entry: usize } #[derive(FromBytes, Default)] @@ -127,6 +146,68 @@ pub struct CommandQueueEntry { const_assert_eq!(core::mem::size_of::(), 64); +impl CommandQueueEntry { + pub fn init_cmdq_entry(&mut self, command: CommandOpcode) { + match command { + CommandOpcode::EnableHca => { + let mut init_hca = CommandQueueEntry::default(); + init_hca.type_of_transport.write(0x7 << 24); + init_hca.input_length.write(12); + init_hca.command_input_opcode.write(CommandOpcode::EnableHca as u16); + init_hca.change_ownership_to_hw(); + core::mem::swap(&mut init_hca, self); + } + CommandOpcode::InitHca => { + let mut init_hca = CommandQueueEntry::default(); + init_hca.type_of_transport.write(0x7 << 24); + init_hca.input_length.write(16); + init_hca.command_input_opcode.write(CommandOpcode::InitHca as u16); + init_hca.change_ownership_to_hw(); + core::mem::swap(&mut init_hca, self); + } + _=> { + debug!("unimplemented opcode"); + } + } + } + + pub fn change_ownership_to_hw(&mut self) { + self.status.write(1); + } + pub fn owned_by_hw(&self) -> bool { + self.status.read().get_bit(0) + } + pub fn status(&self) -> CommandDeliveryStatus { + let status = self.status.read() & 0xFE; + if status == 0 { + CommandDeliveryStatus::Success + } else if status == 1 { + CommandDeliveryStatus::SignatureErr + } else if status == 2 { + CommandDeliveryStatus::TokenErr + } else if status == 3 { + CommandDeliveryStatus::BadBlockNumber + } else if status == 4 { + CommandDeliveryStatus::BadOutputPointer + } else if status == 5 { + CommandDeliveryStatus::BadInputPointer + } else if status == 6 { + CommandDeliveryStatus::InternalErr + } else if status == 7 { + CommandDeliveryStatus::InputLenErr + } else if status == 8 { + CommandDeliveryStatus::OutputLenErr + } else if status == 9 { + CommandDeliveryStatus::ReservedNotZero + } else if status == 10 { + CommandDeliveryStatus::BadCommandType + } else { + CommandDeliveryStatus::Unknown + } + } +} + +#[derive(Debug)] pub enum CommandDeliveryStatus { Success = 0, SignatureErr = 1, @@ -138,7 +219,8 @@ pub enum CommandDeliveryStatus { InputLenErr = 7, OutputLenErr = 8, ReservedNotZero = 9, - BadCommandType = 10 //Should this be 10 or 16?? + BadCommandType = 10, //Should this be 10 or 16?? + Unknown, } pub enum CommandOpcode { diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index 4c0455b6cf..de9036c3f9 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -46,7 +46,7 @@ use nic_initialization::{NIC_MAPPING_FLAGS, allocate_memory, init_rx_buf_pool, i use intel_ethernet::descriptors::{LegacyRxDescriptor, LegacyTxDescriptor}; use nic_buffers::{TransmitBuffer, ReceiveBuffer, ReceivedFrame}; use nic_queues::{RxQueue, TxQueue, RxQueueRegisters, TxQueueRegisters}; -use mellanox_ethernet::{CommandQueueEntry, InitializationSegment}; +use mellanox_ethernet::{CommandQueueEntry, InitializationSegment, CommandQueue, CommandOpcode}; pub const MLX_VEND: u16 = 0x15B3; // Vendor ID for Mellanox @@ -94,36 +94,61 @@ impl ConnectX5Nic { error!("mlx5::init(): BAR0 is of I/O type"); return Err("mlx5::init(): BAR0 is of I/O type") } + trace!("init segment size = {}", core::mem::size_of::()); + + // set the bus mastering bit for this PciDevice, which allows it to use DMA + mlx5_pci_dev.pci_set_command_bus_master_bit(); + // memory mapped base address let mem_base = mlx5_pci_dev.determine_mem_base(0)?; - + trace!("mlx5 mem base = {}", mem_base); // map pages to the physical address given by mem_base as that is the intialization segment let mut init_segment = ConnectX5Nic::mapped_init_segment(mem_base)?; + // init_segment.pf_reset(); + init_segment.print(); + // find number of entries in command queue and stride let max_cmdq_entries = init_segment.num_cmdq_entries() as usize; + trace!("mlx5 cmdq entries = {}", max_cmdq_entries); let cmdq_stride = init_segment.cmdq_entry_stride(); + trace!("mlx5 cmdq stride = {}", cmdq_stride); // create command queue let size_in_bytes_of_cmdq = max_cmdq_entries * core::mem::size_of::(); + trace!("total size in bytes of cmdq = {}", size_in_bytes_of_cmdq); // cmdp needs to be aligned, check?? let (cmdq_mapped_pages, cmdq_starting_phys_addr) = create_contiguous_mapping(size_in_bytes_of_cmdq, NIC_MAPPING_FLAGS)?; + trace!("cmdq mem base = {}", cmdq_starting_phys_addr); // cast our physically-contiguous MappedPages into a slice of command queue entries - let mut cmdq = BoxRefMut::new(Box::new(cmdq_mapped_pages)).try_map_mut(|mp| mp.as_slice_mut::(0, max_cmdq_entries))?; + let mut cmdq = CommandQueue{ + entries: BoxRefMut::new(Box::new(cmdq_mapped_pages)).try_map_mut(|mp| mp.as_slice_mut::(0, max_cmdq_entries))?, + current_entry: 0 + }; // write physical location of command queues to initialization segment init_segment.set_physical_address_of_cmdq(cmdq_starting_phys_addr); // Read initalizing field from initialization segment until it is cleared while init_segment.device_is_initializing() {} + trace!("initializing field is cleared."); + - // Execute ENABLE_HCA command + // // Execute ENABLE_HCA command + // cmdq.entries[cmdq.current_entry].init_cmdq_entry(CommandOpcode::EnableHca); + + // // ring doorbell + // init_segment.post_command(cmdq.current_entry); + + // // wait for command to complete + // while cmdq.entries[cmdq.current_entry].owned_by_hw() {} + + // trace!("init hca status: {:?}", cmdq.entries[cmdq.current_entry].status()); + - // set the bus mastering bit for this PciDevice, which allows it to use DMA - mlx5_pci_dev.pci_set_command_bus_master_bit(); Ok(()) From 9f6e765c8766d57554c29f6e2eb667e93b42cbc7 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Mon, 31 May 2021 17:38:24 -0700 Subject: [PATCH 08/31] basic commands working --- Cargo.lock | 7 +- kernel/mellanox_ethernet/Cargo.toml | 8 +- kernel/mellanox_ethernet/src/lib.rs | 437 ++++++++++++++++++++-------- kernel/mlx5/src/lib.rs | 43 ++- 4 files changed, 353 insertions(+), 142 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index fb050cab21..61e97df08d 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -269,9 +269,9 @@ checksum = "980479e6fde23246dfb54d47580d66b4e99202e7579c5eaa9fe10ecb5ebd2182" [[package]] name = "byteorder" -version = "1.3.4" +version = "1.4.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "08c48aae112d48ed9f069b33538ea9e3e90aa263cfa3d1c24309612b1f7472de" +checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610" [[package]] name = "captain" @@ -1356,8 +1356,11 @@ name = "mellanox_ethernet" version = "0.1.0" dependencies = [ "bit_field 0.7.0", + "byteorder", + "kernel_config", "log", "memory", + "nic_initialization", "owning_ref", "static_assertions", "volatile", diff --git a/kernel/mellanox_ethernet/Cargo.toml b/kernel/mellanox_ethernet/Cargo.toml index d485cca7be..0a3ee6f094 100644 --- a/kernel/mellanox_ethernet/Cargo.toml +++ b/kernel/mellanox_ethernet/Cargo.toml @@ -11,11 +11,17 @@ bit_field = "0.7.0" zerocopy = "0.3.0" static_assertions = "1.1.0" owning_ref = { git = "https://github.com/theseus-os/owning-ref-rs" } - +byteorder = { version = "1.4.3", default-features = false } [dependencies.memory] path = "../memory" +[dependencies.nic_initialization] +path = "../nic_initialization" + +[dependencies.kernel_config] +path = "../kernel_config" + [dependencies.log] version = "0.4.8" diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index a23d931376..43ef6894be 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -10,43 +10,54 @@ extern crate zerocopy; extern crate alloc; #[macro_use] extern crate static_assertions; extern crate owning_ref; +extern crate byteorder; +extern crate nic_initialization; +extern crate kernel_config; + +use core::num; use alloc::vec::Vec; -use memory::{PhysicalAddress, PhysicalMemoryRegion, MappedPages}; +use memory::{PhysicalAddress, PhysicalMemoryRegion, MappedPages, create_contiguous_mapping}; use volatile::{Volatile, ReadOnly, WriteOnly}; use bit_field::BitField; -use zerocopy::FromBytes; +use zerocopy::*; +// {FromBytes, AsBytes, Unaligned}; +use byteorder::BigEndian; use owning_ref:: BoxRefMut; +use nic_initialization::NIC_MAPPING_FLAGS; +use kernel_config::memory::PAGE_SIZE; // Taken from HCA BAR const MAX_CMND_QUEUE_ENTRIES: usize = 64; #[derive(FromBytes)] #[repr(C,packed)] +/// The fields are stored in BE ordering, so that's why every 32 bits field seems to be opposite to the diagram in the manual pub struct InitializationSegment { - fw_rev_major: ReadOnly, - fw_rev_minor: ReadOnly, - fw_rev_subminor: ReadOnly, - cmd_interface_rev: ReadOnly, + fw_rev_minor: ReadOnly>, + fw_rev_major: ReadOnly>, + cmd_interface_rev: ReadOnly>, + fw_rev_subminor: ReadOnly>, _padding1: [u8; 8], - cmdq_phy_addr_high: Volatile, - cmdq_phy_addr_low: Volatile, - command_doorbell_vector: Volatile, + cmdq_phy_addr_high: Volatile>, + cmdq_phy_addr_low: Volatile>, + command_doorbell_vector: Volatile>, _padding2a: [u8; 256], _padding2b: [u8; 128], - _padding2c: [u8; 98], - initializing_state: ReadOnly, + _padding2c: [u8; 6], + initializing_state: ReadOnly>, health_buffer: Volatile<[u8; 64]>, - no_dram_nic_offset: ReadOnly, + no_dram_nic_offset: ReadOnly>, _padding3a: [u8; 2048], _padding3b: [u8; 1024], _padding3c: [u8; 256], _padding3d: [u8; 128], _padding3e: [u8; 60], - internal_timer: ReadOnly, + internal_timer_h: ReadOnly>, + internal_timer_l: ReadOnly>, _padding4: [u8; 8], - health_counter: ReadOnly, + health_counter: ReadOnly>, _padding5: [u8; 44], - real_time: ReadOnly, + real_time: ReadOnly>, _padding6a: [u8; 8192], _padding6b: [u8; 2048], _padding6c: [u8; 1024], @@ -61,44 +72,39 @@ pub struct InitializationSegment { impl InitializationSegment { pub fn num_cmdq_entries(&self) -> u8 { - (self.cmdq_phy_addr_low.read() >> 4) as u8 & 0x0F + let log = (self.cmdq_phy_addr_low.read().get() >> 4) & 0x0F; + 2_u8.pow(log) } pub fn cmdq_entry_stride(&self) -> u8 { - (self.cmdq_phy_addr_low.read()) as u8 & 0x0F - } - pub fn set_physical_address_of_cmdq(&mut self, pa: PhysicalAddress) { - self.cmdq_phy_addr_high.write((pa.value() >> 32) as u32); - self.cmdq_phy_addr_low.write(pa.value() as u32); + let val = self.cmdq_phy_addr_low.read().get() & 0x0F; + 2_u8.pow(val) } + pub fn set_physical_address_of_cmdq(&mut self, pa: PhysicalAddress) -> Result<(), &'static str> { + if pa.value() & 0xFFF != 0 { + return Err("cmdq physical address lower 12 bits must be zero."); + } - // pub fn set_doorbell(command_no: u8) { - - // } - - pub fn device_is_initializing(&self) -> bool { - self.initializing_state.read().get_bit(15) + self.cmdq_phy_addr_high.write(U32::new((pa.value() >> 32) as u32)); + let val = self.cmdq_phy_addr_low.read().get() & 0xFFF; + self.cmdq_phy_addr_low.write(U32::new(pa.value() as u32 | val)); + Ok(()) } - pub fn pf_reset(&mut self) { - let val = self.cmdq_phy_addr_low.read(); - self.cmdq_phy_addr_low.write(val | (0x7 << 8)); + pub fn device_is_initializing(&self) -> bool { + self.initializing_state.read().get().get_bit(31) } - // pub fn initializing_state() -> InitializingState { - - // } - pub fn post_command(&mut self, command_bit: usize) { - let val = self.command_doorbell_vector.read(); - self.command_doorbell_vector.write(val | (1 << command_bit)); + let val = self.command_doorbell_vector.read().get(); + self.command_doorbell_vector.write(U32::new(val | (1 << command_bit))); } pub fn print(&self) { - trace!("{:#X} {:#X} {:#X} {:#X}",self.fw_rev_major.read(), self.fw_rev_minor.read(), self.fw_rev_subminor.read(), self.cmd_interface_rev.read()); - trace!("{:#X} {:#X}",self.cmdq_phy_addr_high.read(), self.cmdq_phy_addr_low.read()); - trace!("{:#X}",self.command_doorbell_vector.read()); - trace!("{:#X}",self.initializing_state.read()); + trace!("{}.{}.{}, {}", self.fw_rev_major.read().get(), self.fw_rev_minor.read().get(), self.fw_rev_subminor.read().get(), self.cmd_interface_rev.read().get()); + trace!("{:#X} {:#X}", self.cmdq_phy_addr_high.read().get(), self.cmdq_phy_addr_low.read().get()); + trace!("{:#X}", self.command_doorbell_vector.read().get()); + trace!("{:#X}", self.initializing_state.read().get()); } } @@ -109,76 +115,127 @@ pub enum InitializingState { Abort = 3 } -/// Section 8.24.1 -/// A buffer of fixed-size entries that is used to pass commands to the HCA. -/// The number of enties and the entry stride is retrieved from the initialization segment of the HCA BAR. -/// It resides in a physically contiguous 4 KiB memory chunk. -#[repr(C)] -pub struct CommandQueue { - pub entries: BoxRefMut, - pub current_entry: usize -} - #[derive(FromBytes, Default)] #[repr(C)] pub struct CommandQueueEntry { - type_of_transport: Volatile, - input_length: Volatile, - input_mailbox_pointer: Volatile, - padding1: WriteOnly, - command_input_opcode: Volatile, - command_input_op_mod: Volatile, - padding2: WriteOnly, - command_input_inline_data: Volatile, - padding3: WriteOnly, - padding4: WriteOnly, - command_output_status: Volatile, - command_output_syndrome: Volatile, - command_output_inline_data: Volatile, - output_mailbox_pointer: Volatile, - output_length: Volatile, - status: Volatile, - padding5: WriteOnly, - signature: Volatile, - token: Volatile + type_of_transport: Volatile>, + input_length: Volatile>, + input_mailbox_pointer_h: Volatile>, + input_mailbox_pointer_l: Volatile>, + command_input_opcode: Volatile>, + command_input_op_mod: Volatile>, + command_input_inline_data_0: Volatile>, + command_input_inline_data_1: Volatile>, + command_output_status: Volatile>, + command_output_syndrome: Volatile>, + command_output_inline_data_0: Volatile>, + command_output_inline_data_1: Volatile>, + output_mailbox_pointer_h: Volatile>, + output_mailbox_pointer_l: Volatile>, + output_length: Volatile>, + token_signature_status_own: Volatile> } const_assert_eq!(core::mem::size_of::(), 64); +pub enum CommandTransportType { + PCIe = 0x7 << 24 +} + impl CommandQueueEntry { - pub fn init_cmdq_entry(&mut self, command: CommandOpcode) { - match command { - CommandOpcode::EnableHca => { - let mut init_hca = CommandQueueEntry::default(); - init_hca.type_of_transport.write(0x7 << 24); - init_hca.input_length.write(12); - init_hca.command_input_opcode.write(CommandOpcode::EnableHca as u16); - init_hca.change_ownership_to_hw(); - core::mem::swap(&mut init_hca, self); - } - CommandOpcode::InitHca => { - let mut init_hca = CommandQueueEntry::default(); - init_hca.type_of_transport.write(0x7 << 24); - init_hca.input_length.write(16); - init_hca.command_input_opcode.write(CommandOpcode::InitHca as u16); - init_hca.change_ownership_to_hw(); - core::mem::swap(&mut init_hca, self); - } - _=> { - debug!("unimplemented opcode"); - } + fn set_type_of_transport(&mut self, transport: CommandTransportType) { + self.type_of_transport.write(U32::new(CommandTransportType::PCIe as u32)); + } + + fn set_input_length_in_bytes(&mut self, length: u32) { + self.input_length.write(U32::new(length)) + } + + fn set_input_mailbox_pointer(&mut self, pa: PhysicalAddress) -> Result<(), &'static str> { + error!("Don't use this function yet! We don't fill out the mailbox fields"); + + if pa.value() & 0x1FF != 0 { + return Err("input mailbox pointer physical address lower 9 bits must be zero."); } + + self.input_mailbox_pointer_h.write(U32::new((pa.value() >> 32) as u32)); + let val = self.input_mailbox_pointer_l.read().get() & 0x1FF; + self.input_mailbox_pointer_l.write(U32::new(pa.value() as u32 | val)); + Ok(()) } - pub fn change_ownership_to_hw(&mut self) { - self.status.write(1); + // right now assume only 8 bytes of commands are passed + fn set_input_inline_data(&mut self, opcode: CommandOpcode, op_mod: Option, command0: Option, command1: Option) { + self.command_input_opcode.write(U32::new((opcode as u32) << 16)); + self.command_input_op_mod.write(U32::new(op_mod.unwrap_or(0) as u32)); + self.command_input_inline_data_0.write(U32::new(command0.unwrap_or(0))); + self.command_input_inline_data_1.write(U32::new(command1.unwrap_or(0))); + } - pub fn owned_by_hw(&self) -> bool { - self.status.read().get_bit(0) + + fn get_command_opcode(&self) -> CommandOpcode { + match self.command_input_opcode.read().get() >> 16 { + 0x100 => {CommandOpcode::QueryHcaCap}, + 0x101 => {CommandOpcode::QueryAdapter}, + 0x102 => {CommandOpcode::InitHca}, + 0x103 => {CommandOpcode::TeardownHca}, + 0x104 => {CommandOpcode::EnableHca}, + 0x105 => {CommandOpcode::DisableHca}, + 0x107 => {CommandOpcode::QueryPages}, + 0x108 => {CommandOpcode::ManagePages}, + 0x10A => {CommandOpcode::QueryIssi}, + 0x10B => {CommandOpcode::SetIssi}, + _ => {CommandOpcode::Unknown} + } + } + + // right now assume only 8 bytes of commands are passed + fn get_output_inline_data(&self) -> (u8, u32, u32, u32) { + ( + (self.command_output_status.read().get() >> 24) as u8, + self.command_output_syndrome.read().get(), + self.command_output_inline_data_0.read().get(), + self.command_output_inline_data_1.read().get() + ) + } + + fn set_output_mailbox_pointer(&mut self, mp: &mut MappedPages, pa: PhysicalAddress) -> Result<(), &'static str> { + error!("Don't use this function yet! We don't fill out the mailbox fields"); + + if pa.value() & 0x1FF != 0 { + return Err("output mailbox pointer physical address lower 9 bits must be zero."); + } + + self.output_mailbox_pointer_h.write(U32::new((pa.value() >> 32) as u32)); + let val = self.output_mailbox_pointer_l.read().get() & 0x1FF; + self.output_mailbox_pointer_l.write(U32::new(pa.value() as u32 | val)); + Ok(()) + } + + fn set_output_length_in_bytes(&mut self, length: u32) { + self.output_length.write(U32::new(length)); + } + + fn get_output_length_in_bytes(&self) -> u32 { + self.output_length.read().get() + } + + fn set_token(&mut self, token: u8) { + let val = self.token_signature_status_own.read().get(); + self.token_signature_status_own.write(U32::new(val | ((token as u32) << 24))); + } + + fn get_token(&self) -> u8 { + (self.token_signature_status_own.read().get() >> 24) as u8 + } + + fn get_signature(&self) -> u8 { + (self.token_signature_status_own.read().get() >> 16) as u8 } - pub fn status(&self) -> CommandDeliveryStatus { - let status = self.status.read() & 0xFE; + + pub fn get_status(&self) -> CommandDeliveryStatus { + let status = self.token_signature_status_own.read().get() & 0xFE; if status == 0 { CommandDeliveryStatus::Success } else if status == 1 { @@ -205,7 +262,28 @@ impl CommandQueueEntry { CommandDeliveryStatus::Unknown } } + + pub fn change_ownership_to_hw(&mut self) { + let ownership = self.token_signature_status_own.read().get() | 0x1; + self.token_signature_status_own.write(U32::new(ownership)); + } + + pub fn owned_by_hw(&self) -> bool { + self.token_signature_status_own.read().get().get_bit(0) + } +} + +#[derive(FromBytes)] +#[repr(C)] +struct CommandInterfaceMailbox { + mailbox_data: Volatile<[u8; 512]>, + _padding1: ReadOnly<[u8; 48]>, + next_pointer_h: Volatile>, + next_pointer_l: Volatile>, + bock_number: Volatile>, + token_ctrl_signature: Volatile> } +const_assert_eq!(core::mem::size_of::(), 576); #[derive(Debug)] pub enum CommandDeliveryStatus { @@ -223,6 +301,7 @@ pub enum CommandDeliveryStatus { Unknown, } +#[derive(PartialEq)] pub enum CommandOpcode { QueryHcaCap = 0x100, QueryAdapter = 0x101, @@ -231,35 +310,161 @@ pub enum CommandOpcode { EnableHca = 0x104, DisableHca = 0x105, QueryPages = 0x107, - ManagePages = 0x108 + ManagePages = 0x108, + QueryIssi = 0x10A, + SetIssi = 0x10B, + QuerySpecialContexts = 0x203, + Unknown } -#[derive(FromBytes)] + +/// Section 8.24.1 +/// A buffer of fixed-size entries that is used to pass commands to the HCA. +/// The number of enties and the entry stride is retrieved from the initialization segment of the HCA BAR. +/// It resides in a physically contiguous 4 KiB memory chunk. #[repr(C)] -pub struct CommandInterfaceMailbox { - mailbox_data: Volatile<[u8; 512]>, - _padding1: [u8; 48], - next_pointer: Volatile, - block_number: Volatile, - signature: Volatile, - ctrl_signature: Volatile, - token: Volatile, - _passing2: u8 +pub struct CommandQueue { + entries: BoxRefMut, + available_entries: [bool; MAX_CMND_QUEUE_ENTRIES], + token: u8, //taken from snabb, my assumption is that it is a random number that needs to be different for every command + mailbox_buffers_input: Vec<(MappedPages, PhysicalAddress)>, // A page, physical address of the page, and if it's in use + mailbox_buffers_output: Vec<(MappedPages, PhysicalAddress)> // A page, physical address of the page, and if it's in use } -const_assert_eq!(core::mem::size_of::(), 576); +const MAILBOX_SIZE_IN_BYTES: usize = 576; +const MAILBOX_DATA_SIZE_IN_BYTES: usize = 512; +const MAX_MAILBOX_BUFFERS: usize = PAGE_SIZE / MAILBOX_SIZE_IN_BYTES; + +impl CommandQueue { + + pub fn create(entries: BoxRefMut, num_cmdq_entries: usize) -> Result { + let mut available_entries = [false; MAX_CMND_QUEUE_ENTRIES]; + for i in 0..num_cmdq_entries { available_entries[i] = true; } + + // allocate one page to be the mailbox buffer per entry + let mut mailbox_buffers_input = Vec::with_capacity(num_cmdq_entries); + let mut mailbox_buffers_output = Vec::with_capacity(num_cmdq_entries); + for _ in 0..num_cmdq_entries { + let (mailbox_mp, mailbox_pa) = create_contiguous_mapping(PAGE_SIZE, NIC_MAPPING_FLAGS)?; + mailbox_buffers_input.push((mailbox_mp, mailbox_pa)); + + let (mailbox_mp, mailbox_pa) = create_contiguous_mapping(PAGE_SIZE, NIC_MAPPING_FLAGS)?; + mailbox_buffers_output.push((mailbox_mp, mailbox_pa)); + } + + Ok(CommandQueue{ entries, available_entries, token: 0xAA, mailbox_buffers_input, mailbox_buffers_output }) + } + + fn find_free_command_entry(&self) -> Option { + self.available_entries.iter().position(|&x| x == true) + } + + pub fn create_command(&mut self, opcode: CommandOpcode, op_mod: Option, allocated_pages: Option>) -> Result { + let entry_num = self.find_free_command_entry().ok_or("No command entry available")?; + + let mut cmdq_entry = CommandQueueEntry::default(); + cmdq_entry.set_type_of_transport(CommandTransportType::PCIe); + cmdq_entry.set_token(self.token); + cmdq_entry.change_ownership_to_hw(); + + match opcode { + CommandOpcode::EnableHca => { + cmdq_entry.set_input_length_in_bytes(12); + cmdq_entry.set_output_length_in_bytes(8); + cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); + } + CommandOpcode::QueryIssi => { + warn!("running query issi with smaller output length, may be an error"); + cmdq_entry.set_input_length_in_bytes(8); + cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); + } + CommandOpcode::SetIssi => { + warn!("setting to 1 by default, could be wrong"); + cmdq_entry.set_input_length_in_bytes(12); + cmdq_entry.set_output_length_in_bytes(8); + cmdq_entry.set_input_inline_data(opcode, op_mod, Some(1), None); + } + CommandOpcode::InitHca => { + cmdq_entry.set_input_length_in_bytes(12); + cmdq_entry.set_output_length_in_bytes(8); + cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); + } + CommandOpcode::QuerySpecialContexts => { + cmdq_entry.set_input_length_in_bytes(8); + cmdq_entry.set_output_length_in_bytes(16); + cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); + } + CommandOpcode::QueryPages => { + cmdq_entry.set_input_length_in_bytes(12); + cmdq_entry.set_output_length_in_bytes(16); + cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); + } + CommandOpcode::ManagePages => { + let pages_pa = allocated_pages.ok_or("No pages were passed to the manage pages command")?; + cmdq_entry.set_input_length_in_bytes(8); + cmdq_entry.set_output_length_in_bytes(16); + cmdq_entry.set_input_inline_data( + opcode, + op_mod, + None, + Some(pages_pa.len() as u32) + ); + } + _=> { + debug!("unimplemented opcode"); + } + } + + core::mem::swap(&mut cmdq_entry, &mut self.entries[entry_num]); + self.token = self.token.wrapping_add(1); + self.available_entries[entry_num] = false; + Ok(entry_num) + } -pub fn init_cmdq_entry(entry: &mut CommandQueueEntry, command: CommandOpcode) { - match command { - CommandOpcode::InitHca => { - let mut init_hca = CommandQueueEntry::default(); - init_hca.command_input_opcode.write(CommandOpcode::InitHca as u16); - core::mem::swap(&mut init_hca, entry); + fn init_manage_pages_input_mailbox_buffers(&mut self, entry_num: usize, pages: Vec) -> Result<(), &'static str>{ + + let mailbox_page = &mut self.mailbox_buffers_input[entry_num]; + const SIZE_PADDR_IN_BYTES: usize = 8; // each physical address takes 8 bytes in the mailbox + let num_mailboxes = (pages.len() * SIZE_PADDR_IN_BYTES) / MAILBOX_DATA_SIZE_IN_BYTES; + + if num_mailboxes > MAX_MAILBOX_BUFFERS { + return Err("Too many maiboxes required, TODO: allocate more than a page for mailboxes"); + } + + for mb_num in 0..num_mailboxes { + // let mailbox = mailbox_page.0.as_type_mut(mb_num * MAILBOX_SIZE_IN_BYTES)?; + + // let mailbox = CommandInterfaceMailbox::Default(); + + } + + Ok(()) + + } + + pub fn wait_for_command_completion(&mut self, entry_num: usize) -> CommandDeliveryStatus { + while self.entries[entry_num].owned_by_hw() {} + self.available_entries[entry_num] = true; + self.entries[entry_num].get_status() + } + + pub fn get_query_issi_command_output(&self, entry_num: usize) -> Result { + if self.entries[entry_num].owned_by_hw() { + error!("the command hasn't completed yet!"); + return Err("the command hasn't completed yet!"); } - _=> { - debug!("unimplemented opcode"); + + let opcode = self.entries[entry_num].get_command_opcode(); + if opcode != CommandOpcode::QueryIssi { + error!("Incorrect Command!"); + return Err("Incorrect Command!"); } + + let (_status, _syndrome, current_issi , _command1) = self.entries[entry_num].get_output_inline_data(); + Ok(current_issi as u16) } } + // #[derive(FromBytes)] // #[repr(C)] // struct UARPageFormat { diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index de9036c3f9..66fbd5db31 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -110,13 +110,17 @@ impl ConnectX5Nic { init_segment.print(); // find number of entries in command queue and stride - let max_cmdq_entries = init_segment.num_cmdq_entries() as usize; - trace!("mlx5 cmdq entries = {}", max_cmdq_entries); - let cmdq_stride = init_segment.cmdq_entry_stride(); + let cmdq_entries = init_segment.num_cmdq_entries() as usize; + trace!("mlx5 cmdq entries = {}", cmdq_entries); + let cmdq_stride = init_segment.cmdq_entry_stride() as usize; trace!("mlx5 cmdq stride = {}", cmdq_stride); - + + if cmdq_stride != core::mem::size_of::() { + error!("Command Queue layout is no longer accurate due to invalid assumption."); + return Err("Command Queue layout is no longer accurate due to invalid assumption."); + } // create command queue - let size_in_bytes_of_cmdq = max_cmdq_entries * core::mem::size_of::(); + let size_in_bytes_of_cmdq = cmdq_entries * cmdq_stride; trace!("total size in bytes of cmdq = {}", size_in_bytes_of_cmdq); // cmdp needs to be aligned, check?? @@ -124,31 +128,24 @@ impl ConnectX5Nic { trace!("cmdq mem base = {}", cmdq_starting_phys_addr); // cast our physically-contiguous MappedPages into a slice of command queue entries - let mut cmdq = CommandQueue{ - entries: BoxRefMut::new(Box::new(cmdq_mapped_pages)).try_map_mut(|mp| mp.as_slice_mut::(0, max_cmdq_entries))?, - current_entry: 0 - }; + let mut cmdq = CommandQueue::create( + BoxRefMut::new(Box::new(cmdq_mapped_pages)).try_map_mut(|mp| mp.as_slice_mut::(0, cmdq_entries))?, + cmdq_entries + )?; // write physical location of command queues to initialization segment - init_segment.set_physical_address_of_cmdq(cmdq_starting_phys_addr); + init_segment.set_physical_address_of_cmdq(cmdq_starting_phys_addr)?; // Read initalizing field from initialization segment until it is cleared - while init_segment.device_is_initializing() {} + while init_segment.device_is_initializing() { trace!("device is initializing");} trace!("initializing field is cleared."); - // // Execute ENABLE_HCA command - // cmdq.entries[cmdq.current_entry].init_cmdq_entry(CommandOpcode::EnableHca); - - // // ring doorbell - // init_segment.post_command(cmdq.current_entry); - - // // wait for command to complete - // while cmdq.entries[cmdq.current_entry].owned_by_hw() {} - - // trace!("init hca status: {:?}", cmdq.entries[cmdq.current_entry].status()); - - + // Execute ENABLE_HCA command + let cmdq_entry = cmdq.create_command(CommandOpcode::EnableHca)?; + init_segment.post_command(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry); + trace!("EnableHCA: {:?}", status); Ok(()) From fd531c8da8c10d8c054d5acf3636def01ac30866 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Tue, 15 Jun 2021 15:26:11 -0700 Subject: [PATCH 09/31] way too may init pages requested --- Cargo.lock | 1 + kernel/mellanox_ethernet/Cargo.toml | 2 +- kernel/mellanox_ethernet/src/lib.rs | 275 ++++++++++++++++++++++++++-- kernel/mlx5/src/lib.rs | 86 ++++++++- 4 files changed, 339 insertions(+), 25 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 507d6a526c..e7e1d21c98 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1360,6 +1360,7 @@ dependencies = [ "bit_field 0.7.0", "byteorder", "kernel_config", + "libm 0.2.1", "log", "memory", "nic_initialization", diff --git a/kernel/mellanox_ethernet/Cargo.toml b/kernel/mellanox_ethernet/Cargo.toml index 56c71c3fb5..f91730446f 100644 --- a/kernel/mellanox_ethernet/Cargo.toml +++ b/kernel/mellanox_ethernet/Cargo.toml @@ -12,7 +12,7 @@ zerocopy = "0.5.0" static_assertions = "1.1.0" owning_ref = { git = "https://github.com/theseus-os/owning-ref-rs" } byteorder = { version = "1.4.3", default-features = false } -# libm = "0.2.1" +libm = "0.2.1" [dependencies.memory] path = "../memory" diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index 30dba78d5d..27021d9450 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -15,7 +15,7 @@ extern crate owning_ref; extern crate byteorder; extern crate nic_initialization; extern crate kernel_config; -// extern crate libm; +extern crate libm; use core::{num, slice::SlicePattern}; @@ -29,6 +29,7 @@ use byteorder::BigEndian; use owning_ref:: BoxRefMut; use nic_initialization::NIC_MAPPING_FLAGS; use kernel_config::memory::PAGE_SIZE; +use core::fmt; // Taken from HCA BAR const MAX_CMND_QUEUE_ENTRIES: usize = 64; @@ -146,6 +147,27 @@ pub enum CommandTransportType { PCIe = 0x7 << 24 } +impl fmt::Debug for CommandQueueEntry { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "CQE:type of transport: {:#X} \n", self.type_of_transport.read().get())?; + write!(f, "CQE:input length: {} \n", self.input_length.read().get())?; + write!(f, "CQE:input_mailbox_ptr_h: {:#X} \n", self.input_mailbox_pointer_h.read().get())?; + write!(f, "CQE:input_mailbox_ptr_l: {:#X} \n", self.input_mailbox_pointer_l.read().get())?; + write!(f, "CQE:command_input_opcode: {:#X} \n", self.command_input_opcode.read().get())?; + write!(f, "CQE:command_input_op_mod: {:#X} \n", self.command_input_op_mod.read().get())?; + write!(f, "CQE:command_input_inline_data_0: {:#X} \n", self.command_input_inline_data_0.read().get())?; + write!(f, "CQE:command_input_inline_data_1: {:#X} \n", self.command_input_inline_data_1.read().get())?; + write!(f, "CQE:command_output_status: {:#X} \n", self.command_output_status.read().get())?; + write!(f, "CQE:command_output_syndrome: {:#X} \n", self.command_output_syndrome.read().get())?; + write!(f, "CQE:command_output_inline_data_0: {:#X} \n", self.command_output_inline_data_0.read().get())?; + write!(f, "CQE:command_output_inline_data_1: {:#X} \n", self.command_output_inline_data_1.read().get())?; + write!(f, "CQE:output_mailbox_pointer_h: {:#X} \n", self.output_mailbox_pointer_h.read().get())?; + write!(f, "CQE:output_mailbox_pointer_l: {:#X} \n", self.output_mailbox_pointer_l.read().get())?; + write!(f, "CQE:output_length: {} \n", self.output_length.read().get())?; + write!(f, "CQE:token_signature_status_own: {:#X} \n", self.token_signature_status_own.read().get()) + } +} + impl CommandQueueEntry { fn set_type_of_transport(&mut self, transport: CommandTransportType) { self.type_of_transport.write(U32::new(CommandTransportType::PCIe as u32)); @@ -298,6 +320,20 @@ impl CommandInterfaceMailbox { } } +impl fmt::Debug for CommandInterfaceMailbox { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + for i in 0..(512/4) { + let data = self.mailbox_data.read(); + write!(f, "mailbox data: {:#X} {:#X} {:#X} {:#X} \n", data[i*4], data[i*4+1], data[i*4+2], data[i*4 +3])?; + } + + // write!(f, "padding: {}", self._padding.read())?; + writeln!(f, "next pointer h: {:#X} \n", self.next_pointer_h.read().get())?; + writeln!(f, "next pointer l: {:#X} \n", self.next_pointer_l.read().get())?; + writeln!(f, "tokne ctrl signature: {:#X} \n", self.token_ctrl_signature.read().get()) + } +} + #[derive(Debug)] pub enum CommandDeliveryStatus { Success = 0, @@ -314,7 +350,7 @@ pub enum CommandDeliveryStatus { Unknown, } -#[derive(PartialEq)] +#[derive(PartialEq, Debug)] pub enum CommandOpcode { QueryHcaCap = 0x100, QueryAdapter = 0x101, @@ -327,6 +363,16 @@ pub enum CommandOpcode { QueryIssi = 0x10A, SetIssi = 0x10B, QuerySpecialContexts = 0x203, + CreateEq = 0x301, + AllocUar = 0x802, + AllocPd = 0x800, + AllocTransportDomain = 0x816, + CreateCq = 0x400, + CreateTis = 0x912, + CreateSq = 0x904, + ModifySq = 0x905, + CreateRq = 0x908, + ModifyRq = 0x909, Unknown } @@ -347,6 +393,9 @@ const MAILBOX_SIZE_IN_BYTES: usize = 576; const MAILBOX_DATA_SIZE_IN_BYTES: usize = 512; const MAX_MAILBOX_BUFFERS: usize = PAGE_SIZE / MAILBOX_SIZE_IN_BYTES; +const SIZE_PADDR_IN_BYTES: usize = 8; // each physical address takes 8 bytes in the mailbox +const SIZE_PADDR_H_IN_BYTES: usize = 4; // each physical address takes 8 bytes in the mailbox +const SIZE_PADDR_L_IN_BYTES: usize = 4; // each physical address takes 8 bytes in the mailbox pub enum ManagePagesOpmod { AllocationFail = 0, AllocationSuccess = 1, @@ -383,7 +432,14 @@ impl CommandQueue { self.available_entries.iter().position(|&x| x == true) } - pub fn create_command(&mut self, opcode: CommandOpcode, op_mod: Option, allocated_pages: Option>) -> Result { + pub fn create_command( + &mut self, opcode: CommandOpcode, + op_mod: Option, + allocated_pages: Option>, + uar: Option, + log_queue_size: Option + ) -> Result + { let entry_num = self.find_free_command_entry().ok_or("No command entry available")?; let mut cmdq_entry = CommandQueueEntry::default(); @@ -426,8 +482,8 @@ impl CommandQueue { } CommandOpcode::ManagePages => { let pages_pa = allocated_pages.ok_or("No pages were passed to the manage pages command")?; - cmdq_entry.set_input_length_in_bytes(24 + pages_pa.len() as u32 *8); // taken from snabb - cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_length_in_bytes(0x10 + pages_pa.len() as u32 *8); // taken from snabb + cmdq_entry.set_output_length_in_bytes(16); cmdq_entry.set_input_inline_data( opcode, op_mod, @@ -437,15 +493,38 @@ impl CommandQueue { self.init_manage_pages_input_mailbox_buffers(entry_num, pages_pa)?; let mailbox_ptr = self.mailbox_buffers_input[entry_num].1.value(); - cmdq_entry.output_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); - cmdq_entry.output_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); + cmdq_entry.input_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); + cmdq_entry.input_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); } + CommandOpcode::AllocUar => { + cmdq_entry.set_input_length_in_bytes(8); + cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); + }, + CommandOpcode::CreateEq => { + let pages_pa = allocated_pages.ok_or("No pages were passed to the create EQ command")?; + + cmdq_entry.set_input_length_in_bytes((0x110 + pages_pa.len()*8) as u32); + cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); + + self.create_page_request_eq( + entry_num, + pages_pa, + uar.ok_or("uar not specified in EQ creation")?, + log_queue_size.ok_or("queue size not specified in EQ creation")? + )?; + let mailbox_ptr = self.mailbox_buffers_input[entry_num].1.value(); + cmdq_entry.input_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); + cmdq_entry.input_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); + }, _=> { debug!("unimplemented opcode"); } } core::mem::swap(&mut cmdq_entry, &mut self.entries[entry_num]); + warn!("{:?}", &mut self.entries[entry_num]); self.token = self.token.wrapping_add(1); self.available_entries[entry_num] = false; Ok(entry_num) @@ -455,11 +534,8 @@ impl CommandQueue { let mailbox_page = &mut self.mailbox_buffers_input[entry_num]; let mailbox_starting_addr = mailbox_page.1; - const SIZE_PADDR_IN_BYTES: usize = 8; // each physical address takes 8 bytes in the mailbox - const SIZE_PADDR_H_IN_BYTES: usize = 4; // each physical address takes 8 bytes in the mailbox - const SIZE_PADDR_L_IN_BYTES: usize = 4; // each physical address takes 8 bytes in the mailbox - let num_mailboxes = 1; //libm::ceilf((pages.len() * SIZE_PADDR_IN_BYTES) as f32 / MAILBOX_DATA_SIZE_IN_BYTES as f32) as usize; + let num_mailboxes = libm::ceilf((pages.len() * SIZE_PADDR_IN_BYTES) as f32 / MAILBOX_DATA_SIZE_IN_BYTES as f32) as usize; let pages_per_mailbox = MAILBOX_DATA_SIZE_IN_BYTES / SIZE_PADDR_IN_BYTES; if num_mailboxes > MAX_MAILBOX_BUFFERS { @@ -502,6 +578,9 @@ impl CommandQueue { } mailbox.mailbox_data.write(data); + debug!("token: {}", self.token); + debug!("Mailbox {}", block_num); + debug!("{:?}", mailbox); } Ok(()) @@ -544,14 +623,172 @@ impl CommandQueue { let (_status, _syndrome, _function_id, num_pages) = self.entries[entry_num].get_output_inline_data(); Ok(num_pages) } + + pub fn get_uar(&self, entry_num: usize) -> Result { + if self.entries[entry_num].owned_by_hw() { + error!("the command hasn't completed yet!"); + return Err("the command hasn't completed yet!"); + } + + let opcode = self.entries[entry_num].get_command_opcode(); + if opcode != CommandOpcode::AllocUar { + error!("Incorrect Command: {:?}!", opcode); + return Err("Incorrect Command!"); + } + + let (_status, _syndrome, uar, _reserved) = self.entries[entry_num].get_output_inline_data(); + Ok(uar & 0xFF_FFFF) + } + + fn create_page_request_eq(&mut self, entry_num: usize, mut pages: Vec, uar: u32, log_eq_size: u8) -> Result<(), &'static str> { + + let mailbox_page = &mut self.mailbox_buffers_input[entry_num]; + let mailbox_starting_addr = mailbox_page.1; + + let size_of_mailbox_data = (0x110 - 0x10) + SIZE_PADDR_IN_BYTES * pages.len(); + + let num_mailboxes = libm::ceilf(size_of_mailbox_data as f32 / MAILBOX_DATA_SIZE_IN_BYTES as f32) as usize; + + if num_mailboxes > MAX_MAILBOX_BUFFERS { + return Err("Too many maiboxes required, TODO: allocate more than a page for mailboxes"); + } + + // In mailbox 0 we have to set up the eq_context and event_bitmask + // The Eq context lies at offset 0 of the first mailbox + let block_num=0; + // clear all fields of the mailbox + mailbox_page.0.as_type_mut::(block_num * MAILBOX_SIZE_IN_BYTES)?.clear_all_fields(); + + // initialize the event queue context + let eq_context = mailbox_page.0.as_type_mut::(0)?; + eq_context.init(uar, log_eq_size); + + // initialize the bitmask. this function only activates the page request event + let bitmask_offset_in_mailbox = 0x58 - 0x10; + let eq_bitmask = mailbox_page.0.as_type_mut::(bitmask_offset_in_mailbox)?; + const PAGE_REQUEST_BIT: u64 = 1 << 0xB; + *eq_bitmask = PAGE_REQUEST_BIT; + + // set the next pointer if required + if block_num != (num_mailboxes - 1){ + let mailbox = mailbox_page.0.as_type_mut::(block_num * MAILBOX_SIZE_IN_BYTES)?; + let mailbox_next_addr = mailbox_starting_addr.value() + ((block_num + 1) * MAILBOX_SIZE_IN_BYTES); + mailbox.next_pointer_h.write(U32::new((mailbox_next_addr >> 32) as u32)); + mailbox.next_pointer_l.write(U32::new((mailbox_next_addr & 0xFFFF_FFFF) as u32)); + } + + // Now use the remainder of the mailbox for page entries + let eq_pa_offset = 0x110 - 0x10; + let data = mailbox_page.0.as_type_mut::<[u8;256]>(eq_pa_offset)?; + let pages_in_mailbox_0 = (MAILBOX_DATA_SIZE_IN_BYTES - eq_pa_offset) / SIZE_PADDR_IN_BYTES; + + for page in 0..pages_in_mailbox_0 { + let paddr = pages.pop(); + match paddr { + Some(paddr) => { + let start_offset_h = page * SIZE_PADDR_IN_BYTES; + let end_offset_h = start_offset_h + SIZE_PADDR_H_IN_BYTES; + let addr = (paddr.value() >> 32) as u32; + data[start_offset_h..end_offset_h].copy_from_slice(&addr.to_be_bytes()); + + let start_offset_l = end_offset_h; + let end_offset_l = start_offset_l + SIZE_PADDR_L_IN_BYTES; + let addr = (paddr.value() & 0xFFFF_FFFF) as u32; + data[start_offset_l..end_offset_l].copy_from_slice(&addr.to_be_bytes()); + }, + None => { + trace!("breaking out of loop on mailbox: {} and page: {}", block_num, page); + break; + } + } + } + + for block_num in 1..num_mailboxes { + let mailbox = mailbox_page.0.as_type_mut::(block_num * MAILBOX_SIZE_IN_BYTES)?; + mailbox.clear_all_fields(); + + if block_num != (num_mailboxes - 1){ + let mailbox_next_addr = mailbox_starting_addr.value() + ((block_num + 1) * MAILBOX_SIZE_IN_BYTES); + mailbox.next_pointer_h.write(U32::new((mailbox_next_addr >> 32) as u32)); + mailbox.next_pointer_l.write(U32::new((mailbox_next_addr & 0xFFFF_FFFF) as u32)); + } + mailbox.block_number.write(U32::new(block_num as u32)); + mailbox.token_ctrl_signature.write(U32::new((self.token as u32) << 16)); + + let mut data = [0; 512]; + + let pages_per_mailbox = MAILBOX_DATA_SIZE_IN_BYTES / SIZE_PADDR_IN_BYTES; + + for page in 0..pages_per_mailbox { + let paddr = pages.pop(); + match paddr { + Some(paddr) => { + let start_offset_h = page * SIZE_PADDR_IN_BYTES; + let end_offset_h = start_offset_h + SIZE_PADDR_H_IN_BYTES; + let addr = (paddr.value() >> 32) as u32; + data[start_offset_h..end_offset_h].copy_from_slice(&addr.to_be_bytes()); + + let start_offset_l = end_offset_h; + let end_offset_l = start_offset_l + SIZE_PADDR_L_IN_BYTES; + let addr = (paddr.value() & 0xFFFF_FFFF) as u32; + data[start_offset_l..end_offset_l].copy_from_slice(&addr.to_be_bytes()); + }, + None => { + trace!("breaking out of loop on mailbox: {} and page: {}", block_num, page); + break; + } + } + } + + mailbox.mailbox_data.write(data); + debug!("token: {}", self.token); + debug!("Mailbox {}", block_num); + debug!("{:?}", mailbox); + } + + Ok(()) + } + + pub fn get_eq_number(&self, entry_num: usize) -> Result { + if self.entries[entry_num].owned_by_hw() { + error!("the command hasn't completed yet!"); + return Err("the command hasn't completed yet!"); + } + + let opcode = self.entries[entry_num].get_command_opcode(); + if opcode != CommandOpcode::CreateEq { + error!("Incorrect Command!"); + return Err("Incorrect Command!"); + } + + let (_status, _syndrome, eq_number, _reserved) = self.entries[entry_num].get_output_inline_data(); + Ok(eq_number as u8) + } } -// #[derive(FromBytes)] -// #[repr(C)] -// struct UARPageFormat { -// _padding1: u32, //0x00 - 0x1C -// cmds_cq_ci: u32, -// cqn: u32, -// _padding2: +#[derive(FromBytes)] +#[repr(C)] +struct EventQueueContext { + status: Volatile>, + _padding1: ReadOnly, + page_offset: Volatile>, + uar_log_eq_size: Volatile>, + _padding2: ReadOnly, + intr: Volatile>, + log_pg_size: Volatile>, + _padding3: ReadOnly, + consumer_counter: Volatile>, + producer_counter: Volatile>, + _padding4: ReadOnly<[u8;12]>, +} -// } +const_assert_eq!(core::mem::size_of::(), 64); + +impl EventQueueContext { + pub fn init(&mut self, uar_page: u32, log_eq_size: u8) { + let uar = uar_page & 0xFF_FFFF; + let size = ((log_eq_size & 0x1F) as u32) << 24; + self.uar_log_eq_size.write(U32::new(uar | size)); + self.log_pg_size.write(U32::new(0)); + } +} diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index fbab41deba..76b557c449 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -143,26 +143,26 @@ impl ConnectX5Nic { // Execute ENABLE_HCA command - let cmdq_entry = cmdq.create_command(CommandOpcode::EnableHca, None, None)?; + let cmdq_entry = cmdq.create_command(CommandOpcode::EnableHca, None, None, None, None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); trace!("EnableHCA: {:?}", status); // execute query ISSI - let cmdq_entry = cmdq.create_command(CommandOpcode::QueryIssi, None, None)?; + let cmdq_entry = cmdq.create_command(CommandOpcode::QueryIssi, None, None,None, None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); let issi = cmdq.get_query_issi_command_output(cmdq_entry)?; trace!("SetISSI: {:?}, issi version :{}", status, issi); // execute set ISSI - let cmdq_entry = cmdq.create_command(CommandOpcode::SetIssi, None, None)?; + let cmdq_entry = cmdq.create_command(CommandOpcode::SetIssi, None, None,None, None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); trace!("SetISSI: {:?}", status); // Query pages for boot - let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpmod::BootPages as u16), None)?; + let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpmod::BootPages as u16), None, None, None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); let num_boot_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; @@ -174,14 +174,90 @@ impl ConnectX5Nic { for _ in 0..num_boot_pages { let (page, pa) = create_contiguous_mapping(4096, NIC_MAPPING_FLAGS)?; boot_mp.push(page); + error!("pa: {:#X}", pa.value()); boot_pa.push(pa); } - let cmdq_entry = cmdq.create_command(CommandOpcode::ManagePages, Some(ManagePagesOpmod::AllocationSuccess as u16), Some(boot_pa))?; + let cmdq_entry = cmdq.create_command(CommandOpcode::ManagePages, Some(ManagePagesOpmod::AllocationSuccess as u16), Some(boot_pa), None, None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); trace!("Manage pages boot status: {:?}", status); + // Query pages for init + let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpmod::InitPages as u16), None, None, None)?; + init_segment.post_command(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry); + let mut num_init_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; + trace!("Query pages status: {:?}, init pages: {:?}", status, num_init_pages); + num_init_pages = 10; + + // Allocate pages for init + if num_init_pages != 0 { + let mut boot_mp = Vec::with_capacity(num_init_pages as usize); + let mut boot_pa = Vec::with_capacity(num_init_pages as usize); + for _ in 0..num_init_pages { + let (page, pa) = create_contiguous_mapping(4096, NIC_MAPPING_FLAGS)?; + boot_mp.push(page); + error!("pa: {:#X}", pa.value()); + boot_pa.push(pa); + } + let cmdq_entry = cmdq.create_command(CommandOpcode::ManagePages, Some(ManagePagesOpmod::AllocationSuccess as u16), Some(boot_pa), None, None)?; + init_segment.post_command(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry); + trace!("Manage pages init status: {:?}", status); + } + + // init_hca + let cmdq_entry = cmdq.create_command(CommandOpcode::InitHca, None, None, None, None)?; + init_segment.post_command(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry); + trace!("Init HCA status: {:?}", status); + + // // Query pages for regular + // let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpmod::RegularPages as u16), None, None, None)?; + // init_segment.post_command(cmdq_entry); + // let status = cmdq.wait_for_command_completion(cmdq_entry); + // let num_regular_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; + // trace!("Query pages status: {:?}, Regular pages: {:?}", status, num_regular_pages); + // // Allocate regular pages + // if num_regular_pages != 0 { + // let mut boot_mp = Vec::with_capacity(num_init_pages as usize); + // let mut boot_pa = Vec::with_capacity(num_init_pages as usize); + // for _ in 0..num_regular_pages { + // let (page, pa) = create_contiguous_mapping(4096, NIC_MAPPING_FLAGS)?; + // boot_mp.push(page); + // error!("pa: {:#X}", pa.value()); + // boot_pa.push(pa); + // } + // let cmdq_entry = cmdq.create_command(CommandOpcode::ManagePages, Some(ManagePagesOpmod::AllocationSuccess as u16), Some(boot_pa), None, None)?; + // init_segment.post_command(cmdq_entry); + // let status = cmdq.wait_for_command_completion(cmdq_entry); + // trace!("Manage pages regular status: {:?}", status); + // } + + // allocate uar + let cmdq_entry = cmdq.create_command(CommandOpcode::AllocUar, None, None, None, None)?; + init_segment.post_command(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry); + let uar = cmdq.get_uar(cmdq_entry)?; + trace!("UAR status: {:?}, UAR: {}", status, uar); + + // create EQ for a Page Request Event + // Allocate pages for EQ + let num_eq_pages = 1; + let mut eq_mp = Vec::with_capacity(num_eq_pages as usize); + let mut eq_pa = Vec::with_capacity(num_eq_pages as usize); + for _ in 0..num_eq_pages { + let (page, pa) = create_contiguous_mapping(4096, NIC_MAPPING_FLAGS)?; + eq_mp.push(page); + error!("pa: {:#X}", pa.value()); + eq_pa.push(pa); + } + let cmdq_entry = cmdq.create_command(CommandOpcode::CreateEq, None, Some(eq_pa), Some(uar), Some(7))?; + init_segment.post_command(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry); + let eq_number = cmdq.get_eq_number(cmdq_entry)?; + trace!("Create EQ status: {:?}, number: {}", status, eq_number); Ok(()) From 53c44a0b064ff998a9ac4b1fbfaceb8afbe930a3 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Sun, 20 Jun 2021 21:17:08 -0700 Subject: [PATCH 10/31] fixed output status issues --- book/src/pci_passthrough.md | 4 + kernel/mellanox_ethernet/src/lib.rs | 240 ++++++++++++++++++---------- kernel/mlx5/src/lib.rs | 40 ++--- 3 files changed, 178 insertions(+), 106 deletions(-) diff --git a/book/src/pci_passthrough.md b/book/src/pci_passthrough.md index 872d177474..404ccc5f78 100644 --- a/book/src/pci_passthrough.md +++ b/book/src/pci_passthrough.md @@ -52,6 +52,10 @@ e.g. `echo 15b3 1019 > /sys/bus/pci/drivers/vfio-pci/new_id` Now, QEMU can be launched with direct access to the device. +### Return device to the Host OS +`echo 1 >/sys/bus/pci/devices/0000:59:00.0/remove` +`echo 1 >/sys/bus/pci/rescan` + ### Note: access for unprivileged users To give access to an unprivileged user to this VFIO device, find the IOMMU group the device belongs to: ```sh diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index 27021d9450..d20b9efd4f 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -149,6 +149,7 @@ pub enum CommandTransportType { impl fmt::Debug for CommandQueueEntry { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "CQE\n")?; write!(f, "CQE:type of transport: {:#X} \n", self.type_of_transport.read().get())?; write!(f, "CQE:input length: {} \n", self.input_length.read().get())?; write!(f, "CQE:input_mailbox_ptr_h: {:#X} \n", self.input_mailbox_pointer_h.read().get())?; @@ -200,6 +201,7 @@ impl CommandQueueEntry { } fn get_command_opcode(&self) -> CommandOpcode { + trace!("{}", self.command_input_opcode.read().get() >> 16); match self.command_input_opcode.read().get() >> 16 { 0x100 => {CommandOpcode::QueryHcaCap}, 0x101 => {CommandOpcode::QueryAdapter}, @@ -259,7 +261,7 @@ impl CommandQueueEntry { (self.token_signature_status_own.read().get() >> 16) as u8 } - pub fn get_status(&self) -> CommandDeliveryStatus { + pub fn get_delivery_status(&self) -> CommandDeliveryStatus { let status = self.token_signature_status_own.read().get() & 0xFE; if status == 0 { CommandDeliveryStatus::Success @@ -296,6 +298,46 @@ impl CommandQueueEntry { pub fn owned_by_hw(&self) -> bool { self.token_signature_status_own.read().get().get_bit(0) } + + pub fn get_return_status(&self) -> CommandReturnStatus { + let (status, _syndrome, _, _) = self.get_output_inline_data(); + + if status == 0x0 { + CommandReturnStatus::OK + } else if status == 0x1 { + CommandReturnStatus::InternalError + } else if status == 0x2 { + CommandReturnStatus::BadOp + } else if status == 0x3 { + CommandReturnStatus::BadParam + } else if status == 0x4 { + CommandReturnStatus::BadSysState + } else if status == 0x5 { + CommandReturnStatus::BadResource + } else if status == 0x6 { + CommandReturnStatus::ResourceBusy + } else if status == 0x8 { + CommandReturnStatus::ExceedLim + } else if status == 0x9 { + CommandReturnStatus::BadResState + } else if status == 0xA { + CommandReturnStatus::BadIndex + } else if status == 0xF { + CommandReturnStatus::NoResources + } else if status == 0x50 { + CommandReturnStatus::BadInputLen + } else if status == 0x51 { + CommandReturnStatus::BadOutputLen + } else if status == 0x10 { + CommandReturnStatus::BadResourceState + } else if status == 0x30 { + CommandReturnStatus::BadPkt + } else if status == 0x40 { + CommandReturnStatus::BadSize + } else { + CommandReturnStatus::Unknown + } + } } #[derive(FromBytes)] @@ -376,6 +418,27 @@ pub enum CommandOpcode { Unknown } + +#[derive(Debug)] +pub enum CommandReturnStatus { + OK = 0x00, + InternalError = 0x01, + BadOp = 0x02, + BadParam = 0x03, + BadSysState = 0x04, + BadResource = 0x05, + ResourceBusy = 0x06, + ExceedLim = 0x08, + BadResState = 0x09, + BadIndex = 0x0A, + NoResources = 0x0F, + BadInputLen = 0x50, + BadOutputLen = 0x51, + BadResourceState = 0x10, + BadPkt = 0x30, + BadSize = 0x40, + Unknown +} /// Section 8.24.1 /// A buffer of fixed-size entries that is used to pass commands to the HCA. /// The number of enties and the entry stride is retrieved from the initialization segment of the HCA BAR. @@ -408,6 +471,12 @@ pub enum QueryPagesOpmod { RegularPages = 3 } +#[derive(PartialEq)] +enum MailboxType { + Input, + Output +} + impl CommandQueue { pub fn create(entries: BoxRefMut, num_cmdq_entries: usize) -> Result { @@ -456,8 +525,12 @@ impl CommandQueue { CommandOpcode::QueryIssi => { warn!("running query issi with smaller output length, may be an error"); cmdq_entry.set_input_length_in_bytes(8); - cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_output_length_in_bytes(112); cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); + + self.init_query_issi_output_mailbox_buffers(entry_num)?; + self.set_mailbox_pointer_in_cmd_entry(&mut cmdq_entry, entry_num, MailboxType::Output); + } CommandOpcode::SetIssi => { warn!("setting to 1 by default, could be wrong"); @@ -492,9 +565,7 @@ impl CommandQueue { ); self.init_manage_pages_input_mailbox_buffers(entry_num, pages_pa)?; - let mailbox_ptr = self.mailbox_buffers_input[entry_num].1.value(); - cmdq_entry.input_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); - cmdq_entry.input_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); + self.set_mailbox_pointer_in_cmd_entry(&mut cmdq_entry, entry_num, MailboxType::Input); } CommandOpcode::AllocUar => { cmdq_entry.set_input_length_in_bytes(8); @@ -514,14 +585,14 @@ impl CommandQueue { uar.ok_or("uar not specified in EQ creation")?, log_queue_size.ok_or("queue size not specified in EQ creation")? )?; - let mailbox_ptr = self.mailbox_buffers_input[entry_num].1.value(); - cmdq_entry.input_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); - cmdq_entry.input_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); + + self.set_mailbox_pointer_in_cmd_entry(&mut cmdq_entry, entry_num, MailboxType::Input); }, _=> { debug!("unimplemented opcode"); } } + core::mem::swap(&mut cmdq_entry, &mut self.entries[entry_num]); warn!("{:?}", &mut self.entries[entry_num]); @@ -530,29 +601,34 @@ impl CommandQueue { Ok(entry_num) } + fn set_mailbox_pointer_in_cmd_entry(&mut self, cmdq_entry: &mut CommandQueueEntry, entry_num: usize, mailbox_type: MailboxType) { + if mailbox_type == MailboxType::Input { + let mailbox_ptr = self.mailbox_buffers_input[entry_num].1.value(); + cmdq_entry.input_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); + cmdq_entry.input_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); + } else { + let mailbox_ptr = self.mailbox_buffers_output[entry_num].1.value(); + cmdq_entry.output_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); + cmdq_entry.output_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); + } + } + + fn init_query_issi_output_mailbox_buffers(&mut self, entry_num: usize) -> Result<(), &'static str> { + const NUM_MAILBOXES_QUERY_ISSI: usize = 1; + self.initialize_mailboxes(entry_num, NUM_MAILBOXES_QUERY_ISSI, MailboxType::Output)?; + Ok(()) + } + fn init_manage_pages_input_mailbox_buffers(&mut self, entry_num: usize, mut pages: Vec) -> Result<(), &'static str> { - let mailbox_page = &mut self.mailbox_buffers_input[entry_num]; - let mailbox_starting_addr = mailbox_page.1; - let num_mailboxes = libm::ceilf((pages.len() * SIZE_PADDR_IN_BYTES) as f32 / MAILBOX_DATA_SIZE_IN_BYTES as f32) as usize; - let pages_per_mailbox = MAILBOX_DATA_SIZE_IN_BYTES / SIZE_PADDR_IN_BYTES; + self.initialize_mailboxes(entry_num, num_mailboxes, MailboxType::Input)?; - if num_mailboxes > MAX_MAILBOX_BUFFERS { - return Err("Too many maiboxes required, TODO: allocate more than a page for mailboxes"); - } + let mailbox_page = &mut self.mailbox_buffers_input[entry_num]; + let pages_per_mailbox = MAILBOX_DATA_SIZE_IN_BYTES / SIZE_PADDR_IN_BYTES; for block_num in 0..num_mailboxes { let mailbox = mailbox_page.0.as_type_mut::(block_num * MAILBOX_SIZE_IN_BYTES)?; - mailbox.clear_all_fields(); - - if block_num != (num_mailboxes - 1){ - let mailbox_next_addr = mailbox_starting_addr.value() + ((block_num + 1) * MAILBOX_SIZE_IN_BYTES); - mailbox.next_pointer_h.write(U32::new((mailbox_next_addr >> 32) as u32)); - mailbox.next_pointer_l.write(U32::new((mailbox_next_addr & 0xFFFF_FFFF) as u32)); - } - mailbox.block_number.write(U32::new(block_num as u32)); - mailbox.token_ctrl_signature.write(U32::new((self.token as u32) << 16)); let mut data = [0; 512]; @@ -586,78 +662,66 @@ impl CommandQueue { Ok(()) } - pub fn wait_for_command_completion(&mut self, entry_num: usize) -> CommandDeliveryStatus { + pub fn wait_for_command_completion(&mut self, entry_num: usize) -> (CommandDeliveryStatus, CommandReturnStatus) { while self.entries[entry_num].owned_by_hw() {} self.available_entries[entry_num] = true; - self.entries[entry_num].get_status() + debug!("{:?}", self.entries[entry_num]); + (self.entries[entry_num].get_delivery_status(), self.entries[entry_num].get_return_status()) } - pub fn get_query_issi_command_output(&self, entry_num: usize) -> Result { + fn check_command_output_validity(&self, entry_num: usize, cmd_opcode: CommandOpcode) -> Result<(), &'static str> { if self.entries[entry_num].owned_by_hw() { error!("the command hasn't completed yet!"); return Err("the command hasn't completed yet!"); } - let opcode = self.entries[entry_num].get_command_opcode(); - if opcode != CommandOpcode::QueryIssi { - error!("Incorrect Command!"); + if self.entries[entry_num].get_command_opcode() != cmd_opcode { + error!("Incorrect Command!: {:?}", self.entries[entry_num].get_command_opcode()); return Err("Incorrect Command!"); } + Ok(()) + } + + pub fn get_query_issi_command_output(&self, entry_num: usize) -> Result<(u16, u8), &'static str> { + self.check_command_output_validity(entry_num, CommandOpcode::QueryIssi)?; + + // This offset is not correct! need to check! + const DATA_OFFSET_IN_MAILBOX: usize = 0x20 - 0x10; + let mailbox = &self.mailbox_buffers_output[entry_num].0; + debug!("{:?}", mailbox.as_type::(0)?); + let supported_issi = (mailbox.as_type::(DATA_OFFSET_IN_MAILBOX)?).to_le(); + let (_status, _syndrome, current_issi , _command1) = self.entries[entry_num].get_output_inline_data(); - Ok(current_issi as u16) + Ok((current_issi as u16, supported_issi as u8)) } pub fn get_query_pages_command_output(&self, entry_num: usize) -> Result { - if self.entries[entry_num].owned_by_hw() { - error!("the command hasn't completed yet!"); - return Err("the command hasn't completed yet!"); - } - - let opcode = self.entries[entry_num].get_command_opcode(); - if opcode != CommandOpcode::QueryPages { - error!("Incorrect Command!"); - return Err("Incorrect Command!"); - } + self.check_command_output_validity(entry_num, CommandOpcode::QueryPages)?; let (_status, _syndrome, _function_id, num_pages) = self.entries[entry_num].get_output_inline_data(); Ok(num_pages) } pub fn get_uar(&self, entry_num: usize) -> Result { - if self.entries[entry_num].owned_by_hw() { - error!("the command hasn't completed yet!"); - return Err("the command hasn't completed yet!"); - } - - let opcode = self.entries[entry_num].get_command_opcode(); - if opcode != CommandOpcode::AllocUar { - error!("Incorrect Command: {:?}!", opcode); - return Err("Incorrect Command!"); - } - + debug!("{:?}",self.entries[entry_num]); + self.check_command_output_validity(entry_num, CommandOpcode::AllocUar)?; let (_status, _syndrome, uar, _reserved) = self.entries[entry_num].get_output_inline_data(); Ok(uar & 0xFF_FFFF) } fn create_page_request_eq(&mut self, entry_num: usize, mut pages: Vec, uar: u32, log_eq_size: u8) -> Result<(), &'static str> { - let mailbox_page = &mut self.mailbox_buffers_input[entry_num]; - let mailbox_starting_addr = mailbox_page.1; - let size_of_mailbox_data = (0x110 - 0x10) + SIZE_PADDR_IN_BYTES * pages.len(); let num_mailboxes = libm::ceilf(size_of_mailbox_data as f32 / MAILBOX_DATA_SIZE_IN_BYTES as f32) as usize; + self.initialize_mailboxes(entry_num, num_mailboxes, MailboxType::Input)?; - if num_mailboxes > MAX_MAILBOX_BUFFERS { - return Err("Too many maiboxes required, TODO: allocate more than a page for mailboxes"); - } - + let mailbox_page = &mut self.mailbox_buffers_input[entry_num]; + // In mailbox 0 we have to set up the eq_context and event_bitmask // The Eq context lies at offset 0 of the first mailbox let block_num=0; - // clear all fields of the mailbox - mailbox_page.0.as_type_mut::(block_num * MAILBOX_SIZE_IN_BYTES)?.clear_all_fields(); // initialize the event queue context let eq_context = mailbox_page.0.as_type_mut::(0)?; @@ -669,14 +733,6 @@ impl CommandQueue { const PAGE_REQUEST_BIT: u64 = 1 << 0xB; *eq_bitmask = PAGE_REQUEST_BIT; - // set the next pointer if required - if block_num != (num_mailboxes - 1){ - let mailbox = mailbox_page.0.as_type_mut::(block_num * MAILBOX_SIZE_IN_BYTES)?; - let mailbox_next_addr = mailbox_starting_addr.value() + ((block_num + 1) * MAILBOX_SIZE_IN_BYTES); - mailbox.next_pointer_h.write(U32::new((mailbox_next_addr >> 32) as u32)); - mailbox.next_pointer_l.write(U32::new((mailbox_next_addr & 0xFFFF_FFFF) as u32)); - } - // Now use the remainder of the mailbox for page entries let eq_pa_offset = 0x110 - 0x10; let data = mailbox_page.0.as_type_mut::<[u8;256]>(eq_pa_offset)?; @@ -705,15 +761,6 @@ impl CommandQueue { for block_num in 1..num_mailboxes { let mailbox = mailbox_page.0.as_type_mut::(block_num * MAILBOX_SIZE_IN_BYTES)?; - mailbox.clear_all_fields(); - - if block_num != (num_mailboxes - 1){ - let mailbox_next_addr = mailbox_starting_addr.value() + ((block_num + 1) * MAILBOX_SIZE_IN_BYTES); - mailbox.next_pointer_h.write(U32::new((mailbox_next_addr >> 32) as u32)); - mailbox.next_pointer_l.write(U32::new((mailbox_next_addr & 0xFFFF_FFFF) as u32)); - } - mailbox.block_number.write(U32::new(block_num as u32)); - mailbox.token_ctrl_signature.write(U32::new((self.token as u32) << 16)); let mut data = [0; 512]; @@ -750,19 +797,38 @@ impl CommandQueue { } pub fn get_eq_number(&self, entry_num: usize) -> Result { - if self.entries[entry_num].owned_by_hw() { - error!("the command hasn't completed yet!"); - return Err("the command hasn't completed yet!"); + self.check_command_output_validity(entry_num, CommandOpcode::CreateEq)?; + + let (_status, _syndrome, eq_number, _reserved) = self.entries[entry_num].get_output_inline_data(); + Ok(eq_number as u8) + } + + /// Clears all mailboxes, then sets the token, block number and next address fields for all mailboxes + fn initialize_mailboxes(&mut self, entry_num: usize, num_mailboxes: usize, mailbox_type: MailboxType) -> Result<(), &'static str> { + let (mb_page, mb_starting_addr) = if mailbox_type == MailboxType::Input{ + &mut self.mailbox_buffers_input[entry_num] + } else { + &mut self.mailbox_buffers_output[entry_num] + }; + + if num_mailboxes > MAX_MAILBOX_BUFFERS { + return Err("Too many maiboxes required, TODO: allocate more than a page for mailboxes"); } - let opcode = self.entries[entry_num].get_command_opcode(); - if opcode != CommandOpcode::CreateEq { - error!("Incorrect Command!"); - return Err("Incorrect Command!"); + for block_num in 0..num_mailboxes { + let mailbox = mb_page.as_type_mut::(block_num * MAILBOX_SIZE_IN_BYTES)?; + mailbox.clear_all_fields(); + + if block_num != (num_mailboxes - 1){ + let mailbox_next_addr = mb_starting_addr.value() + ((block_num + 1) * MAILBOX_SIZE_IN_BYTES); + mailbox.next_pointer_h.write(U32::new((mailbox_next_addr >> 32) as u32)); + mailbox.next_pointer_l.write(U32::new((mailbox_next_addr & 0xFFFF_FFFF) as u32)); + } + mailbox.block_number.write(U32::new(block_num as u32)); + mailbox.token_ctrl_signature.write(U32::new((self.token as u32) << 16)); } - let (_status, _syndrome, eq_number, _reserved) = self.entries[entry_num].get_output_inline_data(); - Ok(eq_number as u8) + Ok(()) } } diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index 76b557c449..d2e8d417b5 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -152,8 +152,8 @@ impl ConnectX5Nic { let cmdq_entry = cmdq.create_command(CommandOpcode::QueryIssi, None, None,None, None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); - let issi = cmdq.get_query_issi_command_output(cmdq_entry)?; - trace!("SetISSI: {:?}, issi version :{}", status, issi); + let (current_issi, available_issi) = cmdq.get_query_issi_command_output(cmdq_entry)?; + trace!("QueryISSI: {:?}, issi version :{}, available: {:#X}", status, current_issi, available_issi); // execute set ISSI let cmdq_entry = cmdq.create_command(CommandOpcode::SetIssi, None, None,None, None)?; @@ -188,7 +188,7 @@ impl ConnectX5Nic { let status = cmdq.wait_for_command_completion(cmdq_entry); let mut num_init_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; trace!("Query pages status: {:?}, init pages: {:?}", status, num_init_pages); - num_init_pages = 10; + num_init_pages = 50; // Allocate pages for init if num_init_pages != 0 { @@ -239,25 +239,27 @@ impl ConnectX5Nic { let cmdq_entry = cmdq.create_command(CommandOpcode::AllocUar, None, None, None, None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); + trace!("UAR status: {:?}", status); + let uar = cmdq.get_uar(cmdq_entry)?; trace!("UAR status: {:?}, UAR: {}", status, uar); - // create EQ for a Page Request Event - // Allocate pages for EQ - let num_eq_pages = 1; - let mut eq_mp = Vec::with_capacity(num_eq_pages as usize); - let mut eq_pa = Vec::with_capacity(num_eq_pages as usize); - for _ in 0..num_eq_pages { - let (page, pa) = create_contiguous_mapping(4096, NIC_MAPPING_FLAGS)?; - eq_mp.push(page); - error!("pa: {:#X}", pa.value()); - eq_pa.push(pa); - } - let cmdq_entry = cmdq.create_command(CommandOpcode::CreateEq, None, Some(eq_pa), Some(uar), Some(7))?; - init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); - let eq_number = cmdq.get_eq_number(cmdq_entry)?; - trace!("Create EQ status: {:?}, number: {}", status, eq_number); + // // create EQ for a Page Request Event + // // Allocate pages for EQ + // let num_eq_pages = 1; + // let mut eq_mp = Vec::with_capacity(num_eq_pages as usize); + // let mut eq_pa = Vec::with_capacity(num_eq_pages as usize); + // for _ in 0..num_eq_pages { + // let (page, pa) = create_contiguous_mapping(4096, NIC_MAPPING_FLAGS)?; + // eq_mp.push(page); + // error!("pa: {:#X}", pa.value()); + // eq_pa.push(pa); + // } + // let cmdq_entry = cmdq.create_command(CommandOpcode::CreateEq, None, Some(eq_pa), Some(uar), Some(7))?; + // init_segment.post_command(cmdq_entry); + // let status = cmdq.wait_for_command_completion(cmdq_entry); + // let eq_number = cmdq.get_eq_number(cmdq_entry)?; + // trace!("Create EQ status: {:?}, number: {}", status, eq_number); Ok(()) From 0c6bb412a6937ce505d9a9258144b4c839bd93d9 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Tue, 29 Jun 2021 09:38:59 -0700 Subject: [PATCH 11/31] solved init pages issue, mailbox ptr has to be aligned --- kernel/mellanox_ethernet/src/lib.rs | 364 ++++++++++++++++++---------- kernel/mlx5/src/lib.rs | 14 +- 2 files changed, 242 insertions(+), 136 deletions(-) diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index d20b9efd4f..fdc905c850 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -9,7 +9,7 @@ extern crate memory; extern crate volatile; extern crate bit_field; extern crate zerocopy; -extern crate alloc; +#[macro_use] extern crate alloc; #[macro_use] extern crate static_assertions; extern crate owning_ref; extern crate byteorder; @@ -45,31 +45,18 @@ pub struct InitializationSegment { cmdq_phy_addr_high: Volatile>, cmdq_phy_addr_low: Volatile>, command_doorbell_vector: Volatile>, - _padding2a: [u8; 256], - _padding2b: [u8; 128], - _padding2c: [u8; 6], + _padding2: [u8; 390], initializing_state: ReadOnly>, health_buffer: Volatile<[u8; 64]>, no_dram_nic_offset: ReadOnly>, - _padding3a: [u8; 2048], - _padding3b: [u8; 1024], - _padding3c: [u8; 256], - _padding3d: [u8; 128], - _padding3e: [u8; 60], + _padding3: [u8; 3516], internal_timer_h: ReadOnly>, internal_timer_l: ReadOnly>, _padding4: [u8; 8], health_counter: ReadOnly>, _padding5: [u8; 44], real_time: ReadOnly>, - _padding6a: [u8; 8192], - _padding6b: [u8; 2048], - _padding6c: [u8; 1024], - _padding6d: [u8; 512], - _padding6e: [u8; 256], - _padding6f: [u8; 128], - _padding6g: [u8; 64], - _padding6h: [u8; 4], + _padding6: [u8; 12228], } // const_assert_eq!(core::mem::size_of::(), 16400); @@ -84,6 +71,7 @@ impl InitializationSegment { let val = self.cmdq_phy_addr_low.read().get() & 0x0F; 2_u8.pow(val) } + pub fn set_physical_address_of_cmdq(&mut self, pa: PhysicalAddress) -> Result<(), &'static str> { if pa.value() & 0xFFF != 0 { return Err("cmdq physical address lower 12 bits must be zero."); @@ -201,7 +189,6 @@ impl CommandQueueEntry { } fn get_command_opcode(&self) -> CommandOpcode { - trace!("{}", self.command_input_opcode.read().get() >> 16); match self.command_input_opcode.read().get() >> 16 { 0x100 => {CommandOpcode::QueryHcaCap}, 0x101 => {CommandOpcode::QueryAdapter}, @@ -372,7 +359,8 @@ impl fmt::Debug for CommandInterfaceMailbox { // write!(f, "padding: {}", self._padding.read())?; writeln!(f, "next pointer h: {:#X} \n", self.next_pointer_h.read().get())?; writeln!(f, "next pointer l: {:#X} \n", self.next_pointer_l.read().get())?; - writeln!(f, "tokne ctrl signature: {:#X} \n", self.token_ctrl_signature.read().get()) + writeln!(f, "block number: {:#X} \n", self.block_number.read().get())?; + writeln!(f, "token ctrl signature: {:#X} \n", self.token_ctrl_signature.read().get()) } } @@ -406,10 +394,12 @@ pub enum CommandOpcode { SetIssi = 0x10B, QuerySpecialContexts = 0x203, CreateEq = 0x301, + CreateCq = 0x400, + QueryVportState = 0x751, + QueryNicVportContext = 0x754, AllocUar = 0x802, AllocPd = 0x800, AllocTransportDomain = 0x816, - CreateCq = 0x400, CreateTis = 0x912, CreateSq = 0x904, ModifySq = 0x905, @@ -448,13 +438,12 @@ pub struct CommandQueue { entries: BoxRefMut, available_entries: [bool; MAX_CMND_QUEUE_ENTRIES], token: u8, //taken from snabb, my assumption is that it is a random number that needs to be different for every command - mailbox_buffers_input: Vec<(MappedPages, PhysicalAddress)>, // A page, physical address of the page, and if it's in use - mailbox_buffers_output: Vec<(MappedPages, PhysicalAddress)> // A page, physical address of the page, and if it's in use + mailbox_buffers_input: Vec>, // A page, physical address of the page, and if it's in use + mailbox_buffers_output: Vec> // A page, physical address of the page, and if it's in use } const MAILBOX_SIZE_IN_BYTES: usize = 576; const MAILBOX_DATA_SIZE_IN_BYTES: usize = 512; -const MAX_MAILBOX_BUFFERS: usize = PAGE_SIZE / MAILBOX_SIZE_IN_BYTES; const SIZE_PADDR_IN_BYTES: usize = 8; // each physical address takes 8 bytes in the mailbox const SIZE_PADDR_H_IN_BYTES: usize = 4; // each physical address takes 8 bytes in the mailbox @@ -477,6 +466,12 @@ enum MailboxType { Output } +enum QueryVportStateOpMod { + VnicVport = 0, + EswVport = 1, + Uplink = 2 +} + impl CommandQueue { pub fn create(entries: BoxRefMut, num_cmdq_entries: usize) -> Result { @@ -488,10 +483,10 @@ impl CommandQueue { let mut mailbox_buffers_output = Vec::with_capacity(num_cmdq_entries); for _ in 0..num_cmdq_entries { let (mailbox_mp, mailbox_pa) = create_contiguous_mapping(PAGE_SIZE, NIC_MAPPING_FLAGS)?; - mailbox_buffers_input.push((mailbox_mp, mailbox_pa)); + mailbox_buffers_input.push(vec!((mailbox_mp, mailbox_pa))); let (mailbox_mp, mailbox_pa) = create_contiguous_mapping(PAGE_SIZE, NIC_MAPPING_FLAGS)?; - mailbox_buffers_output.push((mailbox_mp, mailbox_pa)); + mailbox_buffers_output.push(vec!((mailbox_mp, mailbox_pa))); } Ok(CommandQueue{ entries, available_entries, token: 0xAA, mailbox_buffers_input, mailbox_buffers_output }) @@ -579,7 +574,7 @@ impl CommandQueue { cmdq_entry.set_output_length_in_bytes(12); cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); - self.create_page_request_eq( + self.create_page_request_event_queue( entry_num, pages_pa, uar.ok_or("uar not specified in EQ creation")?, @@ -588,12 +583,38 @@ impl CommandQueue { self.set_mailbox_pointer_in_cmd_entry(&mut cmdq_entry, entry_num, MailboxType::Input); }, + CommandOpcode::QueryVportState => { // only accesses your own vport + cmdq_entry.set_input_length_in_bytes(12); + cmdq_entry.set_output_length_in_bytes(16); + cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); + }, + CommandOpcode::QueryNicVportContext => { // only accesses your own vport + cmdq_entry.set_input_length_in_bytes(16); + cmdq_entry.set_output_length_in_bytes(16 + 0x100); + cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); + + self.init_nic_vport_context_output_mailbox_buffers(entry_num)?; + self.set_mailbox_pointer_in_cmd_entry(&mut cmdq_entry, entry_num, MailboxType::Output); + }, + CommandOpcode::AllocPd => { + cmdq_entry.set_input_length_in_bytes(8); + cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); + }, + CommandOpcode::AllocTransportDomain => { + cmdq_entry.set_input_length_in_bytes(8); + cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); + }, + CommandOpcode::QuerySpecialContexts => { + cmdq_entry.set_input_length_in_bytes(8); + cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); + }, _=> { debug!("unimplemented opcode"); } - } - - + } core::mem::swap(&mut cmdq_entry, &mut self.entries[entry_num]); warn!("{:?}", &mut self.entries[entry_num]); self.token = self.token.wrapping_add(1); @@ -603,11 +624,12 @@ impl CommandQueue { fn set_mailbox_pointer_in_cmd_entry(&mut self, cmdq_entry: &mut CommandQueueEntry, entry_num: usize, mailbox_type: MailboxType) { if mailbox_type == MailboxType::Input { - let mailbox_ptr = self.mailbox_buffers_input[entry_num].1.value(); + let mailbox_ptr = self.mailbox_buffers_input[entry_num][0].1.value(); + warn!("mailbox ptr in command entry: {:#X}", mailbox_ptr); cmdq_entry.input_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); cmdq_entry.input_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); } else { - let mailbox_ptr = self.mailbox_buffers_output[entry_num].1.value(); + let mailbox_ptr = self.mailbox_buffers_output[entry_num][0].1.value(); cmdq_entry.output_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); cmdq_entry.output_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); } @@ -624,37 +646,30 @@ impl CommandQueue { let num_mailboxes = libm::ceilf((pages.len() * SIZE_PADDR_IN_BYTES) as f32 / MAILBOX_DATA_SIZE_IN_BYTES as f32) as usize; self.initialize_mailboxes(entry_num, num_mailboxes, MailboxType::Input)?; - let mailbox_page = &mut self.mailbox_buffers_input[entry_num]; - let pages_per_mailbox = MAILBOX_DATA_SIZE_IN_BYTES / SIZE_PADDR_IN_BYTES; + let mailbox_pages = &mut self.mailbox_buffers_input[entry_num]; + let paddr_per_mailbox = MAILBOX_DATA_SIZE_IN_BYTES / SIZE_PADDR_IN_BYTES; - for block_num in 0..num_mailboxes { - let mailbox = mailbox_page.0.as_type_mut::(block_num * MAILBOX_SIZE_IN_BYTES)?; + for block_num in 0..num_mailboxes { + let (mb_page, mb_page_starting_addr) = &mut mailbox_pages[block_num]; + + let mailbox = mb_page.as_type_mut::(0)?; let mut data = [0; 512]; - for page in 0..pages_per_mailbox { + for page in 0..paddr_per_mailbox { let paddr = pages.pop(); match paddr { Some(paddr) => { - let start_offset_h = page * SIZE_PADDR_IN_BYTES; - let end_offset_h = start_offset_h + SIZE_PADDR_H_IN_BYTES; - let addr = (paddr.value() >> 32) as u32; - data[start_offset_h..end_offset_h].copy_from_slice(&addr.to_be_bytes()); - - let start_offset_l = end_offset_h; - let end_offset_l = start_offset_l + SIZE_PADDR_L_IN_BYTES; - let addr = (paddr.value() & 0xFFFF_FFFF) as u32; - data[start_offset_l..end_offset_l].copy_from_slice(&addr.to_be_bytes()); + Self::write_paddr_in_mailbox_data(page*SIZE_PADDR_IN_BYTES, paddr, &mut data); }, None => { - trace!("breaking out of loop on mailbox: {} and page: {}", block_num, page); + trace!("breaking out of loop on mailbox: {} and paddr: {}", block_num, page); break; } } } mailbox.mailbox_data.write(data); - debug!("token: {}", self.token); debug!("Mailbox {}", block_num); debug!("{:?}", mailbox); } @@ -688,8 +703,8 @@ impl CommandQueue { // This offset is not correct! need to check! const DATA_OFFSET_IN_MAILBOX: usize = 0x20 - 0x10; - let mailbox = &self.mailbox_buffers_output[entry_num].0; - debug!("{:?}", mailbox.as_type::(0)?); + let mailbox = &self.mailbox_buffers_output[entry_num][0].0; + debug!("Query ISSI mailbox {:?}", mailbox.as_type::(0)?); let supported_issi = (mailbox.as_type::(DATA_OFFSET_IN_MAILBOX)?).to_le(); let (_status, _syndrome, current_issi , _command1) = self.entries[entry_num].get_output_inline_data(); @@ -710,89 +725,74 @@ impl CommandQueue { Ok(uar & 0xFF_FFFF) } - fn create_page_request_eq(&mut self, entry_num: usize, mut pages: Vec, uar: u32, log_eq_size: u8) -> Result<(), &'static str> { + fn create_page_request_event_queue(&mut self, entry_num: usize, mut pages: Vec, uar: u32, log_eq_size: u8) -> Result<(), &'static str> { let size_of_mailbox_data = (0x110 - 0x10) + SIZE_PADDR_IN_BYTES * pages.len(); let num_mailboxes = libm::ceilf(size_of_mailbox_data as f32 / MAILBOX_DATA_SIZE_IN_BYTES as f32) as usize; self.initialize_mailboxes(entry_num, num_mailboxes, MailboxType::Input)?; - let mailbox_page = &mut self.mailbox_buffers_input[entry_num]; + let mailbox_pages = &mut self.mailbox_buffers_input[entry_num]; - // In mailbox 0 we have to set up the eq_context and event_bitmask - // The Eq context lies at offset 0 of the first mailbox - let block_num=0; - - // initialize the event queue context - let eq_context = mailbox_page.0.as_type_mut::(0)?; - eq_context.init(uar, log_eq_size); - - // initialize the bitmask. this function only activates the page request event - let bitmask_offset_in_mailbox = 0x58 - 0x10; - let eq_bitmask = mailbox_page.0.as_type_mut::(bitmask_offset_in_mailbox)?; - const PAGE_REQUEST_BIT: u64 = 1 << 0xB; - *eq_bitmask = PAGE_REQUEST_BIT; - - // Now use the remainder of the mailbox for page entries - let eq_pa_offset = 0x110 - 0x10; - let data = mailbox_page.0.as_type_mut::<[u8;256]>(eq_pa_offset)?; - let pages_in_mailbox_0 = (MAILBOX_DATA_SIZE_IN_BYTES - eq_pa_offset) / SIZE_PADDR_IN_BYTES; - - for page in 0..pages_in_mailbox_0 { - let paddr = pages.pop(); - match paddr { - Some(paddr) => { - let start_offset_h = page * SIZE_PADDR_IN_BYTES; - let end_offset_h = start_offset_h + SIZE_PADDR_H_IN_BYTES; - let addr = (paddr.value() >> 32) as u32; - data[start_offset_h..end_offset_h].copy_from_slice(&addr.to_be_bytes()); - - let start_offset_l = end_offset_h; - let end_offset_l = start_offset_l + SIZE_PADDR_L_IN_BYTES; - let addr = (paddr.value() & 0xFFFF_FFFF) as u32; - data[start_offset_l..end_offset_l].copy_from_slice(&addr.to_be_bytes()); - }, - None => { - trace!("breaking out of loop on mailbox: {} and page: {}", block_num, page); - break; + for block_num in 0..num_mailboxes { + let (mb_page, _mb_page_starting_addr) = &mut mailbox_pages[block_num]; + + if block_num == 0 { + // initialize the event queue context + let eq_context = mb_page.as_type_mut::(0)?; + eq_context.init(uar, log_eq_size); + + // initialize the bitmask. this function only activates the page request event + let bitmask_offset_in_mailbox = 0x58 - 0x10; + let eq_bitmask = mb_page.as_type_mut::(bitmask_offset_in_mailbox)?; + const PAGE_REQUEST_BIT: u64 = 1 << 0xB; + *eq_bitmask = PAGE_REQUEST_BIT; + + // Now use the remainder of the mailbox for page entries + let eq_pa_offset = 0x110 - 0x10; + let data = mb_page.as_type_mut::<[u8;256]>(eq_pa_offset)?; + let pages_in_mailbox_0 = (MAILBOX_DATA_SIZE_IN_BYTES - eq_pa_offset) / SIZE_PADDR_IN_BYTES; + + for page in 0..pages_in_mailbox_0 { + let paddr = pages.pop(); + match paddr { + Some(paddr) => { + Self::write_paddr_in_mailbox_data(page*SIZE_PADDR_IN_BYTES, paddr, data); + }, + None => { + trace!("breaking out of loop on mailbox: {} and page: {}", block_num, page); + break; + } + } } - } - } - - for block_num in 1..num_mailboxes { - let mailbox = mailbox_page.0.as_type_mut::(block_num * MAILBOX_SIZE_IN_BYTES)?; - - let mut data = [0; 512]; - - let pages_per_mailbox = MAILBOX_DATA_SIZE_IN_BYTES / SIZE_PADDR_IN_BYTES; - for page in 0..pages_per_mailbox { - let paddr = pages.pop(); - match paddr { - Some(paddr) => { - let start_offset_h = page * SIZE_PADDR_IN_BYTES; - let end_offset_h = start_offset_h + SIZE_PADDR_H_IN_BYTES; - let addr = (paddr.value() >> 32) as u32; - data[start_offset_h..end_offset_h].copy_from_slice(&addr.to_be_bytes()); - - let start_offset_l = end_offset_h; - let end_offset_l = start_offset_l + SIZE_PADDR_L_IN_BYTES; - let addr = (paddr.value() & 0xFFFF_FFFF) as u32; - data[start_offset_l..end_offset_l].copy_from_slice(&addr.to_be_bytes()); - }, - None => { - trace!("breaking out of loop on mailbox: {} and page: {}", block_num, page); - break; + debug!("Mailbox {}", block_num); + debug!("{:?}", mb_page.as_type_mut::(0)?); + + } else { + let mailbox = mb_page.as_type_mut::(0)?; + let paddr_per_mailbox = MAILBOX_DATA_SIZE_IN_BYTES / SIZE_PADDR_IN_BYTES; + let mut data = [0; 512]; + + for page in 0..paddr_per_mailbox { + let paddr = pages.pop(); + match paddr { + Some(paddr) => { + Self::write_paddr_in_mailbox_data(page*SIZE_PADDR_IN_BYTES, paddr, &mut data); + }, + None => { + trace!("breaking out of loop on mailbox: {} and paddr: {}", block_num, page); + break; + } } } - } - mailbox.mailbox_data.write(data); - debug!("token: {}", self.token); - debug!("Mailbox {}", block_num); - debug!("{:?}", mailbox); - } + mailbox.mailbox_data.write(data); + debug!("Mailbox {}", block_num); + debug!("{:?}", mailbox); + } + } Ok(()) } @@ -803,29 +803,114 @@ impl CommandQueue { Ok(eq_number as u8) } + fn get_vport_state(&self, entry_num: usize)-> Result<(u16, u8, u8), &'static str> { + self.check_command_output_validity(entry_num, CommandOpcode::QueryVportState)?; + + let (_status, _syndrome, _reserved, output) = self.entries[entry_num].get_output_inline_data(); + let max_tx_speed = (output >> 16) as u16; + let admin_state = (output as u8 & 0xF0) >> 4; + let state = (output as u8) & 0xF; + + Ok((max_tx_speed, admin_state, state)) + } + + fn init_nic_vport_context_output_mailbox_buffers(&mut self, entry_num: usize) -> Result<(), &'static str> { + const NUM_MAILBOXES_NIC_VPORT_CONTEXT: usize = 1; + self.initialize_mailboxes(entry_num, NUM_MAILBOXES_NIC_VPORT_CONTEXT, MailboxType::Output)?; + Ok(()) + } + + fn get_vport_context(&self, entry_num: usize)-> Result<(u16, [u8;6]), &'static str> { + self.check_command_output_validity(entry_num, CommandOpcode::QueryNicVportContext)?; + + let context = self.mailbox_buffers_output[entry_num][0].0.as_type::(0)?; + let mac_addr_h = context.permanent_address_h.read().get(); + let mac_addr_l = context.permanent_address_l.read().get(); + + let mut mac_addr = [0; 6]; + mac_addr[0] = mac_addr_l as u8; + mac_addr[1] = (mac_addr_l >> 8) as u8; + mac_addr[2] = (mac_addr_l >> 16) as u8; + mac_addr[3] = (mac_addr_l >> 24) as u8; + mac_addr[4] = mac_addr_h as u8; + mac_addr[5] = (mac_addr_h >> 8) as u8; + + + Ok((context.mtu.read().get() as u16, mac_addr)) + } + + pub fn get_protection_domain(&self, entry_num: usize) -> Result { + self.check_command_output_validity(entry_num, CommandOpcode::AllocPd)?; + let (_status, _syndrome, pd, _reserved) = self.entries[entry_num].get_output_inline_data(); + + Ok(pd & 0xFF_FFFF) + } + + pub fn get_transport_domain(&self, entry_num: usize) -> Result { + self.check_command_output_validity(entry_num, CommandOpcode::AllocTransportDomain)?; + let (_status, _syndrome, td, _reserved) = self.entries[entry_num].get_output_inline_data(); + + Ok(td & 0xFF_FFFF) + } + + pub fn get_reserved_lkey(&self, entry_num: usize) -> Result { + self.check_command_output_validity(entry_num, CommandOpcode::QuerySpecialContexts)?; + let (_status, _syndrome, _dump_fill_mkey, resd_lkey) = self.entries[entry_num].get_output_inline_data(); + + Ok(resd_lkey) + } + + fn write_paddr_in_mailbox_data(start_offset: usize, paddr: PhysicalAddress, data: &mut [u8]) { + let start_offset_h = start_offset; + let end_offset_h = start_offset_h + SIZE_PADDR_H_IN_BYTES; + let addr = (paddr.value() >> 32) as u32; + data[start_offset_h..end_offset_h].copy_from_slice(&addr.to_be_bytes()); + + let start_offset_l = end_offset_h; + let end_offset_l = start_offset_l + SIZE_PADDR_L_IN_BYTES; + let addr = (paddr.value() & 0xFFFF_FFFF) as u32; + data[start_offset_l..end_offset_l].copy_from_slice(&addr.to_be_bytes()); + } + /// Clears all mailboxes, then sets the token, block number and next address fields for all mailboxes fn initialize_mailboxes(&mut self, entry_num: usize, num_mailboxes: usize, mailbox_type: MailboxType) -> Result<(), &'static str> { - let (mb_page, mb_starting_addr) = if mailbox_type == MailboxType::Input{ + let mailbox_pages = if mailbox_type == MailboxType::Input{ &mut self.mailbox_buffers_input[entry_num] } else { &mut self.mailbox_buffers_output[entry_num] }; - if num_mailboxes > MAX_MAILBOX_BUFFERS { - return Err("Too many maiboxes required, TODO: allocate more than a page for mailboxes"); + // Adding extra mailbox pages + let available_mailboxes = mailbox_pages.len(); + if num_mailboxes > available_mailboxes { + let num_mailbox_pages_required = num_mailboxes - available_mailboxes; + trace!("Adding {} mailbox pages", num_mailbox_pages_required); + + for _ in 0..num_mailbox_pages_required { + mailbox_pages.push(create_contiguous_mapping(PAGE_SIZE, NIC_MAPPING_FLAGS)?); + } } for block_num in 0..num_mailboxes { - let mailbox = mb_page.as_type_mut::(block_num * MAILBOX_SIZE_IN_BYTES)?; + // record the next page address to set pointer for last mailbox (can't have two borrows in the same loop) + let next_mb_addr = if block_num < (num_mailboxes - 1) { + mailbox_pages[block_num + 1].1.value() + } else { + 0 + }; + + let (mb_page, mb_page_starting_addr) = &mut mailbox_pages[block_num]; + + trace!("Initializing mb: {}", block_num); + let mailbox = mb_page.as_type_mut::(0)?; mailbox.clear_all_fields(); - if block_num != (num_mailboxes - 1){ - let mailbox_next_addr = mb_starting_addr.value() + ((block_num + 1) * MAILBOX_SIZE_IN_BYTES); - mailbox.next_pointer_h.write(U32::new((mailbox_next_addr >> 32) as u32)); - mailbox.next_pointer_l.write(U32::new((mailbox_next_addr & 0xFFFF_FFFF) as u32)); - } mailbox.block_number.write(U32::new(block_num as u32)); mailbox.token_ctrl_signature.write(U32::new((self.token as u32) << 16)); + + mailbox.next_pointer_h.write(U32::new((next_mb_addr >> 32) as u32)); + mailbox.next_pointer_l.write(U32::new((next_mb_addr & 0xFFFF_FFFF) as u32)); + } Ok(()) @@ -858,3 +943,26 @@ impl EventQueueContext { self.log_pg_size.write(U32::new(0)); } } + +#[derive(FromBytes)] +#[repr(C)] +struct NicVportContext { + data1: Volatile>, + data2: Volatile>, + data3: Volatile>, + _padding0: ReadOnly<[u8; 24]>, + mtu: Volatile>, + system_image_guid: Volatile>, + port_guid: Volatile>, + node_guid: Volatile>, + max_qp_retry: Volatile>, + _padding1: ReadOnly<[u8; 36]>, + qkey_violation_counter: Volatile>, + _padding2: ReadOnly<[u8; 132]>, + list_info: Volatile>, + permanent_address_h: Volatile>, + permanent_address_l: Volatile>, + sw_network_metadata: Volatile>, +} + +const_assert_eq!(core::mem::size_of::(), 256); diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index d2e8d417b5..8c0d209242 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -188,8 +188,6 @@ impl ConnectX5Nic { let status = cmdq.wait_for_command_completion(cmdq_entry); let mut num_init_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; trace!("Query pages status: {:?}, init pages: {:?}", status, num_init_pages); - num_init_pages = 50; - // Allocate pages for init if num_init_pages != 0 { let mut boot_mp = Vec::with_capacity(num_init_pages as usize); @@ -236,13 +234,13 @@ impl ConnectX5Nic { // } // allocate uar - let cmdq_entry = cmdq.create_command(CommandOpcode::AllocUar, None, None, None, None)?; - init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); - trace!("UAR status: {:?}", status); + // let cmdq_entry = cmdq.create_command(CommandOpcode::AllocUar, None, None, None, None)?; + // init_segment.post_command(cmdq_entry); + // let status = cmdq.wait_for_command_completion(cmdq_entry); + // trace!("UAR status: {:?}", status); - let uar = cmdq.get_uar(cmdq_entry)?; - trace!("UAR status: {:?}, UAR: {}", status, uar); + // let uar = cmdq.get_uar(cmdq_entry)?; + // trace!("UAR status: {:?}, UAR: {}", status, uar); // // create EQ for a Page Request Event // // Allocate pages for EQ From cbd1791b104f6a5eb0621dde8913bb21e20eb8af Mon Sep 17 00:00:00 2001 From: ramla-i Date: Fri, 2 Jul 2021 16:02:23 -0700 Subject: [PATCH 12/31] completed documentation, needs a review --- Cargo.lock | 15 +- kernel/mellanox_ethernet/src/command_queue.rs | 744 ++++++++++++++ kernel/mellanox_ethernet/src/lib.rs | 934 +----------------- kernel/mlx5/Cargo.toml | 39 +- kernel/mlx5/src/lib.rs | 246 ++--- kernel/mlx5/src/test_mlx5_driver.rs | 79 -- 6 files changed, 893 insertions(+), 1164 deletions(-) create mode 100644 kernel/mellanox_ethernet/src/command_queue.rs delete mode 100644 kernel/mlx5/src/test_mlx5_driver.rs diff --git a/Cargo.lock b/Cargo.lock index 5f9401248a..222c91862d 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1359,7 +1359,7 @@ dependencies = [ "bit_field 0.7.0", "byteorder", "kernel_config", - "libm 0.2.1", + "libm", "log", "memory", "nic_initialization", @@ -1472,28 +1472,15 @@ dependencies = [ name = "mlx5" version = "0.1.0" dependencies = [ - "apic", - "intel_ethernet", - "interrupts", "irq_safety", "kernel_config", - "lazy_static", "log", "mellanox_ethernet", "memory", - "mpmc", - "network_interface_card", - "nic_buffers", "nic_initialization", - "nic_queues", "owning_ref", "pci", - "pic", "spin 0.9.0", - "static_assertions", - "volatile", - "x86_64", - "zerocopy", ] [[package]] diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs new file mode 100644 index 0000000000..28ee784755 --- /dev/null +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -0,0 +1,744 @@ + //! Defines the Command Queue that is used to pass commands from the driver to the NIC. + //! + //! Most information is taken from the PRM, Section 8.24: Command Interface and Chapter 23: Command Reference. + +use alloc::vec::Vec; +use memory::{PhysicalAddress, MappedPages, create_contiguous_mapping}; +use volatile::{Volatile, ReadOnly}; +use bit_field::BitField; +use zerocopy::*; +use byteorder::BigEndian; +use owning_ref:: BoxRefMut; +use nic_initialization::NIC_MAPPING_FLAGS; +use kernel_config::memory::PAGE_SIZE; +use core::fmt; + +/// Maximum number of entries in the command queue. +const MAX_CMND_QUEUE_ENTRIES: usize = 64; +/// Size of mailboxes, including both control fields and data. +const MAILBOX_SIZE_IN_BYTES: usize = 576; +/// Number of bytes in the mailbox that are actually used to pass data. +const MAILBOX_DATA_SIZE_IN_BYTES: usize = 512; +/// Mailboxes are aligned at 4 KiB, so they are always present at offset 0 in a page. +const MAILBOX_OFFSET_IN_PAGE: usize = 0; +/// Each physical address takes 8 bytes +const SIZE_PADDR_IN_BYTES: usize = 8; +/// When passing physical addresses to the NIC, we always send the higher 4 bytes in one field. +const SIZE_PADDR_H_IN_BYTES: usize = 4; +/// When passing physical addresses to the NIC, we always send the lower 4 bytes in one field. +const SIZE_PADDR_L_IN_BYTES: usize = 4; + +/// Type of transport that carries the command. +pub enum CommandTransportType { + PCIe = 0x7 << 24 +} + +#[derive(Debug)] +/// Return codes written by HW in the delivery status field of the command entry. +pub enum CommandDeliveryStatus { + Success = 0x0, + SignatureErr = 0x1, + TokenErr = 0x2, + BadBlockNumber = 0x3, + BadOutputPointer = 0x4, + BadInputPointer = 0x5, + InternalErr = 0x6, + InputLenErr = 0x7, + OutputLenErr = 0x8, + ReservedNotZero = 0x9, + BadCommandType = 0x10, //Should this be 10 or 16?? + Unknown, +} + +#[derive(PartialEq, Debug)] +/// Command opcode written by SW in opcode field of the input data in the command entry. +pub enum CommandOpcode { + QueryHcaCap = 0x100, + QueryAdapter = 0x101, + InitHca = 0x102, + TeardownHca = 0x103, + EnableHca = 0x104, + DisableHca = 0x105, + QueryPages = 0x107, + ManagePages = 0x108, + QueryIssi = 0x10A, + SetIssi = 0x10B, + QuerySpecialContexts = 0x203, + CreateEq = 0x301, + CreateCq = 0x400, + QueryVportState = 0x751, + QueryNicVportContext = 0x754, + AllocUar = 0x802, + AllocPd = 0x800, + AllocTransportDomain = 0x816, + CreateTis = 0x912, + CreateSq = 0x904, + ModifySq = 0x905, + CreateRq = 0x908, + ModifyRq = 0x909, + Unknown +} + +#[derive(Debug)] +/// Command status written by HW in status field of the output data in the command entry. +pub enum CommandReturnStatus { + OK = 0x00, + InternalError = 0x01, + BadOp = 0x02, + BadParam = 0x03, + BadSysState = 0x04, + BadResource = 0x05, + ResourceBusy = 0x06, + ExceedLim = 0x08, + BadResState = 0x09, + BadIndex = 0x0A, + NoResources = 0x0F, + BadInputLen = 0x50, + BadOutputLen = 0x51, + BadResourceState = 0x10, + BadPkt = 0x30, + BadSize = 0x40, + Unknown +} + +/// Possible values of the opcode modifer when the opcode is ManagePages +pub enum ManagePagesOpmod { + AllocationFail = 0, + AllocationSuccess = 1, + HcaReturnPages = 2 +} + +/// Possible values of the opcode modifer when the opcode is QueryPages +pub enum QueryPagesOpmod { + BootPages = 1, + InitPages = 2, + RegularPages = 3 +} + +#[derive(PartialEq)] +/// Mailboxes can be used for both input data passed to HW, and output data passed from HW to SW. +enum MailboxType { + Input, + Output +} + +/// A buffer of fixed-size entries that is used to pass commands to the HCA. +/// It resides in a physically contiguous 4 KiB memory chunk. +/// (Section 8.24.1: HCA Command Queue) +#[repr(C)] +pub struct CommandQueue { + /// Physically-contiguous command queue entries + entries: BoxRefMut, + /// Per-entry boolean flags to keep track of which entries are in use + available_entries: Vec, + /// A random number that needs to be different for every command, and the same for all mailboxes that are part of a command. + token: u8, + /// Pages used for input mailboxes + mailbox_buffers_input: Vec>, + /// Pages used for output mailboxes + mailbox_buffers_output: Vec> +} + +impl CommandQueue { + + /// Create a command queue object. + /// + /// # Arguments + /// * `entries`: physically contiguous memory that is mapped as a slice of command queue entries. + /// * `num_cmdq_entries`: number of entries in the queue. + pub fn create(entries: BoxRefMut, num_cmdq_entries: usize) -> Result { + + // initially, all command entries are available + let mut available_entries = Vec::with_capacity(num_cmdq_entries); + for _ in 0..num_cmdq_entries { available_entries.push(true); } + + // start off by pre-allocating one page for input and output mailboxes per entry + let mut mailbox_buffers_input = Vec::with_capacity(num_cmdq_entries); + let mut mailbox_buffers_output = Vec::with_capacity(num_cmdq_entries); + for _ in 0..num_cmdq_entries { + let (mailbox_mp, mailbox_pa) = create_contiguous_mapping(PAGE_SIZE, NIC_MAPPING_FLAGS)?; + mailbox_buffers_input.push(vec!((mailbox_mp, mailbox_pa))); + + let (mailbox_mp, mailbox_pa) = create_contiguous_mapping(PAGE_SIZE, NIC_MAPPING_FLAGS)?; + mailbox_buffers_output.push(vec!((mailbox_mp, mailbox_pa))); + } + + // Assign a random number to token, another OS (Snabb) starts off with 0xAA + let token = 0xAA; + + Ok(CommandQueue{ entries, available_entries, token, mailbox_buffers_input, mailbox_buffers_output }) + } + + /// Find an command queue entry that is not in use + fn find_free_command_entry(&self) -> Option { + self.available_entries.iter().position(|&x| x == true) + } + + /// Fill in the fields of a command queue entry. + /// At the end of the function, the command is ready to be posted using the doorbell in the initialization segment. + /// Returns an error if no entry is available to use. + /// + /// # Arguments + /// * `opcode`: opcode for command that the driver wants to execute + /// * `opmod`: opcode modifer, only applicable for certan commands + /// * `allocated_pages`: physical address of pages that need to be passed to the NIC. Only used in the MANAGE_PAGES command. + pub fn create_command( + &mut self, + opcode: CommandOpcode, + opmod: Option, + allocated_pages: Option>, + ) -> Result + { + let entry_num = self.find_free_command_entry().ok_or("No command entry available")?; + + // clear the fields of the command + let mut cmdq_entry = CommandQueueEntry::default(); + + // set the type of transport and token + cmdq_entry.set_type_of_transport(); + cmdq_entry.set_token(self.token); + + // set the ownership bit to HW-owned. + // This bit will be cleared when the command is complete. + cmdq_entry.change_ownership_to_hw(); + + match opcode { + CommandOpcode::EnableHca => { + cmdq_entry.set_input_length_in_bytes(12); + cmdq_entry.set_output_length_in_bytes(8); + cmdq_entry.set_input_inline_data(opcode, opmod, None, None); + } + CommandOpcode::QueryIssi => { + cmdq_entry.set_input_length_in_bytes(8); + cmdq_entry.set_output_length_in_bytes(112); + cmdq_entry.set_input_inline_data(opcode, opmod, None, None); + + self.init_query_issi_output_mailbox_buffers(entry_num)?; + self.set_mailbox_pointer_in_cmd_entry(&mut cmdq_entry, entry_num, MailboxType::Output); + } + CommandOpcode::SetIssi => { + warn!("setting to 1 by default, could be wrong"); + cmdq_entry.set_input_length_in_bytes(12); + cmdq_entry.set_output_length_in_bytes(8); + cmdq_entry.set_input_inline_data(opcode, opmod, Some(1), None); + } + CommandOpcode::InitHca => { + cmdq_entry.set_input_length_in_bytes(12); + cmdq_entry.set_output_length_in_bytes(8); + cmdq_entry.set_input_inline_data(opcode, opmod, None, None); + } + CommandOpcode::QuerySpecialContexts => { + cmdq_entry.set_input_length_in_bytes(8); + cmdq_entry.set_output_length_in_bytes(16); + cmdq_entry.set_input_inline_data(opcode, opmod, None, None); + } + CommandOpcode::QueryPages => { + cmdq_entry.set_input_length_in_bytes(12); + cmdq_entry.set_output_length_in_bytes(16); + cmdq_entry.set_input_inline_data(opcode, opmod, None, None); + } + CommandOpcode::ManagePages => { + let pages_pa = allocated_pages.ok_or("No pages were passed to the manage pages command")?; + cmdq_entry.set_input_length_in_bytes(0x10 + pages_pa.len() as u32 * SIZE_PADDR_IN_BYTES as u32); + cmdq_entry.set_output_length_in_bytes(16); + cmdq_entry.set_input_inline_data( + opcode, + opmod, + None, + Some(pages_pa.len() as u32) + ); + + self.init_manage_pages_input_mailbox_buffers(entry_num, pages_pa)?; + self.set_mailbox_pointer_in_cmd_entry(&mut cmdq_entry, entry_num, MailboxType::Input); + } + CommandOpcode::AllocUar => { + cmdq_entry.set_input_length_in_bytes(8); + cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_inline_data(opcode, opmod, None, None); + }, + CommandOpcode::QueryVportState => { // only accesses your own vport + cmdq_entry.set_input_length_in_bytes(12); + cmdq_entry.set_output_length_in_bytes(16); + cmdq_entry.set_input_inline_data(opcode, opmod, None, None); + }, + CommandOpcode::AllocPd => { + cmdq_entry.set_input_length_in_bytes(8); + cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_inline_data(opcode, opmod, None, None); + }, + CommandOpcode::AllocTransportDomain => { + cmdq_entry.set_input_length_in_bytes(8); + cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_inline_data(opcode, opmod, None, None); + }, + CommandOpcode::QuerySpecialContexts => { + cmdq_entry.set_input_length_in_bytes(8); + cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_inline_data(opcode, opmod, None, None); + }, + _=> { + error!("unimplemented opcode"); + return Err("Unimplemented opcode!"); + } + } + + // write command to actual place in memory + core::mem::swap(&mut cmdq_entry, &mut self.entries[entry_num]); + + // update token to be used in the next command + self.token = self.token.wrapping_add(1); + + // claim the command entry as in use + self.available_entries[entry_num] = false; + + Ok(entry_num) + } + + /// Sets the mailbox pointer in a command entry with the physical address of the first mailbox. + fn set_mailbox_pointer_in_cmd_entry(&mut self, cmdq_entry: &mut CommandQueueEntry, entry_num: usize, mailbox_type: MailboxType) { + if mailbox_type == MailboxType::Input { + let mailbox_ptr = self.mailbox_buffers_input[entry_num][0].1.value(); + cmdq_entry.input_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); + cmdq_entry.input_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); + } else { + let mailbox_ptr = self.mailbox_buffers_output[entry_num][0].1.value(); + cmdq_entry.output_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); + cmdq_entry.output_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); + } + } + + /// Initialize output mailboxes for the QUERY_ISSI command. + fn init_query_issi_output_mailbox_buffers(&mut self, entry_num: usize) -> Result<(), &'static str> { + const NUM_MAILBOXES_QUERY_ISSI: usize = 1; + self.initialize_mailboxes(entry_num, NUM_MAILBOXES_QUERY_ISSI, MailboxType::Output)?; + Ok(()) + } + + /// Initialize input mailboxes for the MANAGE_PAGES command. + /// We write that physical address of the pages passed to the NIC to the mailbox data field. + fn init_manage_pages_input_mailbox_buffers(&mut self, entry_num: usize, mut pages: Vec) -> Result<(), &'static str> { + + let num_mailboxes = libm::ceilf((pages.len() * SIZE_PADDR_IN_BYTES) as f32 / MAILBOX_DATA_SIZE_IN_BYTES as f32) as usize; + self.initialize_mailboxes(entry_num, num_mailboxes, MailboxType::Input)?; + + let mailbox_pages = &mut self.mailbox_buffers_input[entry_num]; + let paddr_per_mailbox = MAILBOX_DATA_SIZE_IN_BYTES / SIZE_PADDR_IN_BYTES; + + for block_num in 0..num_mailboxes { + let (mb_page, _mb_page_starting_addr) = &mut mailbox_pages[block_num]; + let mailbox = mb_page.as_type_mut::(MAILBOX_OFFSET_IN_PAGE)?; + + let mut data = [0; 512]; + for page in 0..paddr_per_mailbox { + match pages.pop() { + Some(paddr) => { + Self::write_paddr_in_mailbox_data(page * SIZE_PADDR_IN_BYTES, paddr, &mut data); + }, + None => { + trace!("breaking out of loop on mailbox: {} and paddr: {}", block_num, page); + break; + } + } + } + mailbox.mailbox_data.write(data); + } + + Ok(()) + } + + /// Waits for ownership bit to be cleared, and then returns the command delivery status and the command return status. + pub fn wait_for_command_completion(&mut self, entry_num: usize) -> (CommandDeliveryStatus, CommandReturnStatus) { + while self.entries[entry_num].owned_by_hw() {} + self.available_entries[entry_num] = true; + (self.entries[entry_num].get_delivery_status(), self.entries[entry_num].get_return_status()) + } + + /// Get the current ISSI version and the supported ISSI versions, which is the output of the QUERY_ISSI command. + pub fn get_query_issi_command_output(&self, entry_num: usize) -> Result<(u16, u8), &'static str> { + self.check_command_output_validity(entry_num, CommandOpcode::QueryIssi)?; + + // TODO: This offset is not correct! need to check! + const DATA_OFFSET_IN_MAILBOX: usize = 0x20 - 0x10; + let mailbox = &self.mailbox_buffers_output[entry_num][0].0; + let supported_issi = (mailbox.as_type::(DATA_OFFSET_IN_MAILBOX)?).to_le(); + + let (_status, _syndrome, current_issi , _command1) = self.entries[entry_num].get_output_inline_data(); + Ok((current_issi as u16, supported_issi as u8)) + } + + /// Get the number of pages requested by the NIC, which is the output of the QUERY_PAGES command. + pub fn get_query_pages_command_output(&self, entry_num: usize) -> Result { + self.check_command_output_validity(entry_num, CommandOpcode::QueryPages)?; + let (_status, _syndrome, _function_id, num_pages) = self.entries[entry_num].get_output_inline_data(); + Ok(num_pages) + } + + /// Get the User Access Region (UAR) number, which is the output of the ALLOC_UAR command. + pub fn get_uar(&self, entry_num: usize) -> Result { + self.check_command_output_validity(entry_num, CommandOpcode::AllocUar)?; + let (_status, _syndrome, uar, _reserved) = self.entries[entry_num].get_output_inline_data(); + Ok(uar & 0xFF_FFFF) + } + + /// Get the protection domain number, which is the output of the ALLOC_PD command. + pub fn get_protection_domain(&self, entry_num: usize) -> Result { + self.check_command_output_validity(entry_num, CommandOpcode::AllocPd)?; + let (_status, _syndrome, pd, _reserved) = self.entries[entry_num].get_output_inline_data(); + Ok(pd & 0xFF_FFFF) + } + + /// Get the transport domain number, which is the output of the ALLOC_TRANSPORT_DOMAIN command. + pub fn get_transport_domain(&self, entry_num: usize) -> Result { + self.check_command_output_validity(entry_num, CommandOpcode::AllocTransportDomain)?; + let (_status, _syndrome, td, _reserved) = self.entries[entry_num].get_output_inline_data(); + Ok(td & 0xFF_FFFF) + } + + /// Get the value of the reserved Lkey for Base Memory Management Extension, which is used when we are using physical addresses. + /// It is taken as the output of the QUERY_SPECIAL_CONTEXTS command. + pub fn get_reserved_lkey(&self, entry_num: usize) -> Result { + self.check_command_output_validity(entry_num, CommandOpcode::QuerySpecialContexts)?; + let (_status, _syndrome, _dump_fill_mkey, resd_lkey) = self.entries[entry_num].get_output_inline_data(); + Ok(resd_lkey) + } + + /// When retrieving the output data of a command, checks that the correct opcode is written and that the command has completed. + fn check_command_output_validity(&self, entry_num: usize, cmd_opcode: CommandOpcode) -> Result<(), &'static str> { + if self.entries[entry_num].owned_by_hw() { + error!("the command hasn't completed yet!"); + return Err("the command hasn't completed yet!"); + } + if self.entries[entry_num].get_command_opcode() != cmd_opcode { + error!("Incorrect Command!: {:?}", self.entries[entry_num].get_command_opcode()); + return Err("Incorrect Command!"); + } + Ok(()) + } + + /// Writes the physical address `paddr` to the given `start_offset` in the `data` buffer. + /// The format specified in the PRM is that the 4 higher bytes are written first at the starting address in big endian format, + /// then the four lower bytes are written in the next 4 bytes in big endian format. + fn write_paddr_in_mailbox_data(start_offset: usize, paddr: PhysicalAddress, data: &mut [u8]) { + let start_offset_h = start_offset; + let end_offset_h = start_offset_h + SIZE_PADDR_H_IN_BYTES; + let addr = (paddr.value() >> 32) as u32; + data[start_offset_h..end_offset_h].copy_from_slice(&addr.to_be_bytes()); + + let start_offset_l = end_offset_h; + let end_offset_l = start_offset_l + SIZE_PADDR_L_IN_BYTES; + let addr = (paddr.value() & 0xFFFF_FFFF) as u32; + data[start_offset_l..end_offset_l].copy_from_slice(&addr.to_be_bytes()); + } + + /// Clears fields of all mailboxes, then sets the token, block number and next address fields for all mailboxes. + fn initialize_mailboxes(&mut self, entry_num: usize, num_mailboxes: usize, mailbox_type: MailboxType) -> Result<(), &'static str> { + let mailbox_pages = if mailbox_type == MailboxType::Input{ + &mut self.mailbox_buffers_input[entry_num] + } else { + &mut self.mailbox_buffers_output[entry_num] + }; + + // Adding extra mailbox pages + let available_mailboxes = mailbox_pages.len(); + if num_mailboxes > available_mailboxes { + let num_mailbox_pages_required = num_mailboxes - available_mailboxes; + trace!("Adding {} mailbox pages", num_mailbox_pages_required); + + for _ in 0..num_mailbox_pages_required { + mailbox_pages.push(create_contiguous_mapping(PAGE_SIZE, NIC_MAPPING_FLAGS)?); + } + } + + for block_num in 0..num_mailboxes { + // record the next page address to set pointer for the next mailbox (can't have two borrows in the same loop) + let next_mb_addr = if block_num < (num_mailboxes - 1) { + mailbox_pages[block_num + 1].1.value() + } else { + 0 + }; + + let (mb_page, _mb_page_starting_addr) = &mut mailbox_pages[block_num]; + trace!("Initializing mb: {}", block_num); + + let mailbox = mb_page.as_type_mut::(MAILBOX_OFFSET_IN_PAGE)?; + mailbox.clear_all_fields(); + mailbox.block_number.write(U32::new(block_num as u32)); + mailbox.token_ctrl_signature.write(U32::new((self.token as u32) << 16)); + mailbox.next_pointer_h.write(U32::new((next_mb_addr >> 32) as u32)); + mailbox.next_pointer_l.write(U32::new((next_mb_addr & 0xFFFF_FFFF) as u32)); + } + + Ok(()) + } +} + +#[derive(FromBytes, Default)] +#[repr(C)] +/// Layout of a command passed to the NIC. +/// The fields include control information for the command as well as actual command input and output. +/// The first 16 bytes of the actual command input are part of the entry. The remaining data is written in mailboxes. +/// Similarly, the first 16 bytes of the command output are part of the entry and remaining data is written in mailboxes. +pub struct CommandQueueEntry { + /// Type of transport that carries the command + type_of_transport: Volatile>, + /// Input command length in bytes. + input_length: Volatile>, + /// Pointer to input mailbox, upper 4 bytes + input_mailbox_pointer_h: Volatile>, + /// Pointer to input mailbox, lower 4 bytes + input_mailbox_pointer_l: Volatile>, + /// Command opcode + command_input_opcode: Volatile>, + /// Opcode modifier for the command + command_input_opmod: Volatile>, + /// First 4 bytes of command input data. + command_input_inline_data_0: Volatile>, + /// Second 4 bytes of command input data. + command_input_inline_data_1: Volatile>, + /// Command return status + command_output_status: Volatile>, + /// Syndrome on the command, valid only if status = 0x0 + command_output_syndrome: Volatile>, + /// First 4 bytes of command output data, valid only if status = 0x0 + command_output_inline_data_0: Volatile>, + /// Second 4 bytes of command output data, valid only if status = 0x0 + command_output_inline_data_1: Volatile>, + /// Pointer to output mailbox, upper 4 bytes + output_mailbox_pointer_h: Volatile>, + /// Pointer to output mailbox, lower 4 bytes + output_mailbox_pointer_l: Volatile>, + /// Output command length in bytes + output_length: Volatile>, + /// * Token: Token of the command, should have the same value in the command and the mailbox blocks. + /// * Signature: 8 bit signature of the command queue entry. + /// * Status: command delivery status. + /// * Ownership: bit 0 of field. When set, indicates that HW owns the command entry. + token_signature_status_own: Volatile> +} + +const_assert_eq!(core::mem::size_of::(), 64); + +impl fmt::Debug for CommandQueueEntry { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "CQE:type of transport: {:#X} \n", self.type_of_transport.read().get())?; + write!(f, "CQE:input length: {} \n", self.input_length.read().get())?; + write!(f, "CQE:input_mailbox_ptr_h: {:#X} \n", self.input_mailbox_pointer_h.read().get())?; + write!(f, "CQE:input_mailbox_ptr_l: {:#X} \n", self.input_mailbox_pointer_l.read().get())?; + write!(f, "CQE:command_input_opcode: {:#X} \n", self.command_input_opcode.read().get())?; + write!(f, "CQE:command_input_opmod: {:#X} \n", self.command_input_opmod.read().get())?; + write!(f, "CQE:command_input_inline_data_0: {:#X} \n", self.command_input_inline_data_0.read().get())?; + write!(f, "CQE:command_input_inline_data_1: {:#X} \n", self.command_input_inline_data_1.read().get())?; + write!(f, "CQE:command_output_status: {:#X} \n", self.command_output_status.read().get())?; + write!(f, "CQE:command_output_syndrome: {:#X} \n", self.command_output_syndrome.read().get())?; + write!(f, "CQE:command_output_inline_data_0: {:#X} \n", self.command_output_inline_data_0.read().get())?; + write!(f, "CQE:command_output_inline_data_1: {:#X} \n", self.command_output_inline_data_1.read().get())?; + write!(f, "CQE:output_mailbox_pointer_h: {:#X} \n", self.output_mailbox_pointer_h.read().get())?; + write!(f, "CQE:output_mailbox_pointer_l: {:#X} \n", self.output_mailbox_pointer_l.read().get())?; + write!(f, "CQE:output_length: {} \n", self.output_length.read().get())?; + write!(f, "CQE:token_signature_status_own: {:#X} \n", self.token_signature_status_own.read().get()) + } +} + +impl CommandQueueEntry { + /// Sets the type of transport which carries the command as PCIe. + fn set_type_of_transport(&mut self) { + self.type_of_transport.write(U32::new(CommandTransportType::PCIe as u32)); + } + + /// Sets length of input data in bytes. + /// This value is different for every command, and can be taken from Chapter 23 of the PRM. + fn set_input_length_in_bytes(&mut self, length: u32) { + self.input_length.write(U32::new(length)) + } + + /// Sets the first 16 bytes of input data that are written inline in the command. + /// The valid values for each field are different for every command, and can be taken from Chapter 23 of the PRM. + /// + /// # Arguments + /// * `opcode`: value identifying which command has to be carried out + /// * `opmod`: opcode modifier. If None, field will be set to zero. + /// * `command0`: the first 4 bytes of actual command data. If None, field will be set to zero. + /// * `command1`: the second 4 bytes of actual command data. If None, field will be set to zero. + fn set_input_inline_data(&mut self, opcode: CommandOpcode, opmod: Option, command0: Option, command1: Option) { + self.command_input_opcode.write(U32::new((opcode as u32) << 16)); + self.command_input_opmod.write(U32::new(opmod.unwrap_or(0) as u32)); + self.command_input_inline_data_0.write(U32::new(command0.unwrap_or(0))); + self.command_input_inline_data_1.write(U32::new(command1.unwrap_or(0))); + } + + /// Returns the value written to the input opcode field of the command + fn get_command_opcode(&self) -> CommandOpcode { + match self.command_input_opcode.read().get() >> 16 { + 0x100 => {CommandOpcode::QueryHcaCap}, + 0x101 => {CommandOpcode::QueryAdapter}, + 0x102 => {CommandOpcode::InitHca}, + 0x103 => {CommandOpcode::TeardownHca}, + 0x104 => {CommandOpcode::EnableHca}, + 0x105 => {CommandOpcode::DisableHca}, + 0x107 => {CommandOpcode::QueryPages}, + 0x108 => {CommandOpcode::ManagePages}, + 0x10A => {CommandOpcode::QueryIssi}, + 0x10B => {CommandOpcode::SetIssi}, + _ => {CommandOpcode::Unknown} + } + } + + /// Returns the first 16 bytes of output data that are written inline in the command. + /// The valid values for each field are different for every command, and can be taken from Chapter 23 of the PRM. + fn get_output_inline_data(&self) -> (u8, u32, u32, u32) { + ( + (self.command_output_status.read().get() >> 24) as u8, + self.command_output_syndrome.read().get(), + self.command_output_inline_data_0.read().get(), + self.command_output_inline_data_1.read().get() + ) + } + + /// Sets length of output data in bytes. + /// This value is different for every command, and can be taken from Chapter 23 of the PRM. + fn set_output_length_in_bytes(&mut self, length: u32) { + self.output_length.write(U32::new(length)); + } + + /// Sets the token of the command. + /// This is a random value that should be the same in the command entry and all linked mailboxes. + fn set_token(&mut self, token: u8) { + let val = self.token_signature_status_own.read().get(); + self.token_signature_status_own.write(U32::new(val | ((token as u32) << 24))); + } + + /// Returns the status of command delivery. + /// This only informs us if the command was delivered to the NIC successfully, not if it was completed successfully. + pub fn get_delivery_status(&self) -> CommandDeliveryStatus { + let status = self.token_signature_status_own.read().get() & 0xFE; + if status == 0 { + CommandDeliveryStatus::Success + } else if status == 1 { + CommandDeliveryStatus::SignatureErr + } else if status == 2 { + CommandDeliveryStatus::TokenErr + } else if status == 3 { + CommandDeliveryStatus::BadBlockNumber + } else if status == 4 { + CommandDeliveryStatus::BadOutputPointer + } else if status == 5 { + CommandDeliveryStatus::BadInputPointer + } else if status == 6 { + CommandDeliveryStatus::InternalErr + } else if status == 7 { + CommandDeliveryStatus::InputLenErr + } else if status == 8 { + CommandDeliveryStatus::OutputLenErr + } else if status == 9 { + CommandDeliveryStatus::ReservedNotZero + } else if status == 10 { + CommandDeliveryStatus::BadCommandType + } else { + CommandDeliveryStatus::Unknown + } + } + + /// Sets the ownership bit so that HW can take control of the command entry + pub fn change_ownership_to_hw(&mut self) { + let ownership = self.token_signature_status_own.read().get() | 0x1; + self.token_signature_status_own.write(U32::new(ownership)); + } + + /// Returns true if the command is currently under the ownership of HW (SW should not touch the fields). + pub fn owned_by_hw(&self) -> bool { + self.token_signature_status_own.read().get().get_bit(0) + } + + /// Returns the status of command execution. + pub fn get_return_status(&self) -> CommandReturnStatus { + let (status, _syndrome, _, _) = self.get_output_inline_data(); + + if status == 0x0 { + CommandReturnStatus::OK + } else if status == 0x1 { + CommandReturnStatus::InternalError + } else if status == 0x2 { + CommandReturnStatus::BadOp + } else if status == 0x3 { + CommandReturnStatus::BadParam + } else if status == 0x4 { + CommandReturnStatus::BadSysState + } else if status == 0x5 { + CommandReturnStatus::BadResource + } else if status == 0x6 { + CommandReturnStatus::ResourceBusy + } else if status == 0x8 { + CommandReturnStatus::ExceedLim + } else if status == 0x9 { + CommandReturnStatus::BadResState + } else if status == 0xA { + CommandReturnStatus::BadIndex + } else if status == 0xF { + CommandReturnStatus::NoResources + } else if status == 0x50 { + CommandReturnStatus::BadInputLen + } else if status == 0x51 { + CommandReturnStatus::BadOutputLen + } else if status == 0x10 { + CommandReturnStatus::BadResourceState + } else if status == 0x30 { + CommandReturnStatus::BadPkt + } else if status == 0x40 { + CommandReturnStatus::BadSize + } else { + CommandReturnStatus::Unknown + } + } +} + + +#[derive(FromBytes)] +#[repr(C)] +/// Layout of mailbox used to pass extra input and output command data that desn't fit into the command entry. +struct CommandInterfaceMailbox { + /// Data in the mailbox + mailbox_data: Volatile<[u8; 512]>, + _padding: ReadOnly<[u8; 48]>, + /// MSBs of pointer to the next mailbox page (if needed). + /// If no additional block is needed, the pointer should be 0. + next_pointer_h: Volatile>, + /// LSBs of pointer to the next mailbox page (if needed). + /// If no additional block is needed, the pointer should be 0. + next_pointer_l: Volatile>, + /// Sequence number of the block. + /// Starting by 0 and increment for each block on the linked list of blocks. + block_number: Volatile>, + /// Token of the command. + /// Should have the same value in the command and the mailbox blocks. + token_ctrl_signature: Volatile> +} +const_assert_eq!(core::mem::size_of::(), MAILBOX_SIZE_IN_BYTES); + +impl CommandInterfaceMailbox { + /// Sets all fields of the mailbox to 0. + fn clear_all_fields(&mut self) { + self. mailbox_data.write([0;512]); + self.next_pointer_h.write(U32::new(0)); + self.next_pointer_l.write(U32::new(0)); + self.block_number.write(U32::new(0)); + self.token_ctrl_signature.write(U32::new(0)); + } +} + +impl fmt::Debug for CommandInterfaceMailbox { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + for i in 0..(512/4) { + let data = self.mailbox_data.read(); + write!(f, "mailbox data: {:#X} {:#X} {:#X} {:#X} \n", data[i*4], data[i*4+1], data[i*4+2], data[i*4 +3])?; + } + + write!(f, "next pointer h: {:#X} \n", self.next_pointer_h.read().get())?; + write!(f, "next pointer l: {:#X} \n", self.next_pointer_l.read().get())?; + write!(f, "block number: {:#X} \n", self.block_number.read().get())?; + write!(f, "token ctrl signature: {:#X} \n", self.token_ctrl_signature.read().get()) + } +} + + + + diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index fdc905c850..92df7ef5dc 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -1,58 +1,70 @@ - //! Note: Mellanox manual refers to the NIC as HCA. + //! This crate defines the layout of objects that make up the software interface between the Mellanox hardware and the driver, + //! as well as functions to access different fields of these objects. + //! + //! All information is taken from the Mellanox Adapters Programmer’s Reference Manual (PRM) [Rev 0.54], unless otherwise specified. #![no_std] #![feature(slice_pattern)] #![feature(core_intrinsics)] #[macro_use]extern crate log; +#[macro_use] extern crate alloc; +#[macro_use] extern crate static_assertions; extern crate memory; extern crate volatile; extern crate bit_field; extern crate zerocopy; -#[macro_use] extern crate alloc; -#[macro_use] extern crate static_assertions; extern crate owning_ref; extern crate byteorder; extern crate nic_initialization; extern crate kernel_config; extern crate libm; -use core::{num, slice::SlicePattern}; - -use alloc::vec::Vec; -use memory::{PhysicalAddress, PhysicalMemoryRegion, MappedPages, create_contiguous_mapping}; -use volatile::{Volatile, ReadOnly, WriteOnly}; +use memory::PhysicalAddress; +use volatile::{Volatile, ReadOnly}; use bit_field::BitField; use zerocopy::*; -// {FromBytes, AsBytes, Unaligned}; use byteorder::BigEndian; -use owning_ref:: BoxRefMut; -use nic_initialization::NIC_MAPPING_FLAGS; -use kernel_config::memory::PAGE_SIZE; use core::fmt; -// Taken from HCA BAR -const MAX_CMND_QUEUE_ENTRIES: usize = 64; +pub mod command_queue; + #[derive(FromBytes)] #[repr(C,packed)] -/// The fields are stored in BE ordering, so that's why every 32 bits field seems to be opposite to the diagram in the manual +/// The initialization segment is located at offset 0 of PCI BAR0. +/// It is used in the initialization procedure of the device, +/// and it contains the 32-bit command doorbell vector used to inform the HW when a command is ready to be processed. pub struct InitializationSegment { + /// Firmware Revision - Minor fw_rev_minor: ReadOnly>, + /// Firmware Revision - Major fw_rev_major: ReadOnly>, + /// Command Interface Interpreter Revision ID cmd_interface_rev: ReadOnly>, + /// Firmware Sub-minor version (Patch level) fw_rev_subminor: ReadOnly>, _padding1: [u8; 8], + /// MSBs of the physical address of the command queue record. cmdq_phy_addr_high: Volatile>, + /// LSBs of the physical address of the command queue record. cmdq_phy_addr_low: Volatile>, + /// Bit per command in the cmdq. + /// When the bit is set, that command entry in the queue is moved to HW ownership. command_doorbell_vector: Volatile>, _padding2: [u8; 390], + /// If bit 31 is set, the device is still initializing and driver should not post commands initializing_state: ReadOnly>, + /// Advanced debug information. health_buffer: Volatile<[u8; 64]>, + /// The offset in bytes, inside the initialization segment, where the NODNIC registers can be found. no_dram_nic_offset: ReadOnly>, _padding3: [u8; 3516], + /// MSBs of the current internal timer value internal_timer_h: ReadOnly>, + /// LSBs of the current internal timer value internal_timer_l: ReadOnly>, _padding4: [u8; 8], + /// Advanced debug information health_counter: ReadOnly>, _padding5: [u8; 44], real_time: ReadOnly>, @@ -62,907 +74,61 @@ pub struct InitializationSegment { // const_assert_eq!(core::mem::size_of::(), 16400); impl InitializationSegment { + /// Returns the number of entries in the command queue pub fn num_cmdq_entries(&self) -> u8 { let log = (self.cmdq_phy_addr_low.read().get() >> 4) & 0x0F; 2_u8.pow(log) } + /// Returns the stride of command queue entries (bytes between the start of consecutive entries) pub fn cmdq_entry_stride(&self) -> u8 { let val = self.cmdq_phy_addr_low.read().get() & 0x0F; 2_u8.pow(val) } - pub fn set_physical_address_of_cmdq(&mut self, pa: PhysicalAddress) -> Result<(), &'static str> { - if pa.value() & 0xFFF != 0 { + /// Sets the physical address of the command queue within the initialization segment. + /// Arguments + /// * `cmdq_physical_addr`: the starting physical address of the command queue, the lower 12 bits of which must be zero. + pub fn set_physical_address_of_cmdq(&mut self, cmdq_physical_addr: PhysicalAddress) -> Result<(), &'static str> { + if cmdq_physical_addr.value() & 0xFFF != 0 { return Err("cmdq physical address lower 12 bits must be zero."); } - self.cmdq_phy_addr_high.write(U32::new((pa.value() >> 32) as u32)); + self.cmdq_phy_addr_high.write(U32::new((cmdq_physical_addr.value() >> 32) as u32)); let val = self.cmdq_phy_addr_low.read().get() & 0xFFF; - self.cmdq_phy_addr_low.write(U32::new(pa.value() as u32 | val)); + self.cmdq_phy_addr_low.write(U32::new(cmdq_physical_addr.value() as u32 | val)); Ok(()) } + /// Returns true if the device is still initializing and driver should not pass any commands to the device. pub fn device_is_initializing(&self) -> bool { self.initializing_state.read().get().get_bit(31) } + /// Sets a bit in the command doorbell vector to inform HW that command needs to be executed. + /// + /// Arguments + /// * `command bit`: the command entry that needs to be executed. (e.g. bit 0 corresponds to entry at index 0). pub fn post_command(&mut self, command_bit: usize) { let val = self.command_doorbell_vector.read().get(); self.command_doorbell_vector.write(U32::new(val | (1 << command_bit))); } +} - pub fn print(&self) { - trace!("{}.{}.{}, {}", self.fw_rev_major.read().get(), self.fw_rev_minor.read().get(), self.fw_rev_subminor.read().get(), self.cmd_interface_rev.read().get()); - trace!("{:#X} {:#X}", self.cmdq_phy_addr_high.read().get(), self.cmdq_phy_addr_low.read().get()); - trace!("{:#X}", self.command_doorbell_vector.read().get()); - trace!("{:#X}", self.initializing_state.read().get()); +impl fmt::Debug for InitializationSegment { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + write!(f, "Initialization Segment \n")?; + write!(f, "Firmware: {}.{}.{}, command interface: {} \n", self.fw_rev_major.read().get(), self.fw_rev_minor.read().get(), self.fw_rev_subminor.read().get(), self.cmd_interface_rev.read().get())?; + write!(f, "Command queue address: {:#X} {:#X} \n", self.cmdq_phy_addr_high.read().get(), self.cmdq_phy_addr_low.read().get())?; + write!(f, "Command doorbell vector: {:#X} \n", self.command_doorbell_vector.read().get())?; + write!(f, "Initializing state: {:#X} \n", self.initializing_state.read().get()) } } +/// The possible values of the initialization state of the device pub enum InitializingState { NotAllowed = 0, WaitingPermetion = 1, // Is this a typo? WaitingResources = 2, Abort = 3 } - -#[derive(FromBytes, Default)] -#[repr(C)] -pub struct CommandQueueEntry { - type_of_transport: Volatile>, - input_length: Volatile>, - input_mailbox_pointer_h: Volatile>, - input_mailbox_pointer_l: Volatile>, - command_input_opcode: Volatile>, - command_input_op_mod: Volatile>, - command_input_inline_data_0: Volatile>, - command_input_inline_data_1: Volatile>, - command_output_status: Volatile>, - command_output_syndrome: Volatile>, - command_output_inline_data_0: Volatile>, - command_output_inline_data_1: Volatile>, - output_mailbox_pointer_h: Volatile>, - output_mailbox_pointer_l: Volatile>, - output_length: Volatile>, - token_signature_status_own: Volatile> -} - - -const_assert_eq!(core::mem::size_of::(), 64); - -pub enum CommandTransportType { - PCIe = 0x7 << 24 -} - -impl fmt::Debug for CommandQueueEntry { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - write!(f, "CQE\n")?; - write!(f, "CQE:type of transport: {:#X} \n", self.type_of_transport.read().get())?; - write!(f, "CQE:input length: {} \n", self.input_length.read().get())?; - write!(f, "CQE:input_mailbox_ptr_h: {:#X} \n", self.input_mailbox_pointer_h.read().get())?; - write!(f, "CQE:input_mailbox_ptr_l: {:#X} \n", self.input_mailbox_pointer_l.read().get())?; - write!(f, "CQE:command_input_opcode: {:#X} \n", self.command_input_opcode.read().get())?; - write!(f, "CQE:command_input_op_mod: {:#X} \n", self.command_input_op_mod.read().get())?; - write!(f, "CQE:command_input_inline_data_0: {:#X} \n", self.command_input_inline_data_0.read().get())?; - write!(f, "CQE:command_input_inline_data_1: {:#X} \n", self.command_input_inline_data_1.read().get())?; - write!(f, "CQE:command_output_status: {:#X} \n", self.command_output_status.read().get())?; - write!(f, "CQE:command_output_syndrome: {:#X} \n", self.command_output_syndrome.read().get())?; - write!(f, "CQE:command_output_inline_data_0: {:#X} \n", self.command_output_inline_data_0.read().get())?; - write!(f, "CQE:command_output_inline_data_1: {:#X} \n", self.command_output_inline_data_1.read().get())?; - write!(f, "CQE:output_mailbox_pointer_h: {:#X} \n", self.output_mailbox_pointer_h.read().get())?; - write!(f, "CQE:output_mailbox_pointer_l: {:#X} \n", self.output_mailbox_pointer_l.read().get())?; - write!(f, "CQE:output_length: {} \n", self.output_length.read().get())?; - write!(f, "CQE:token_signature_status_own: {:#X} \n", self.token_signature_status_own.read().get()) - } -} - -impl CommandQueueEntry { - fn set_type_of_transport(&mut self, transport: CommandTransportType) { - self.type_of_transport.write(U32::new(CommandTransportType::PCIe as u32)); - } - - fn set_input_length_in_bytes(&mut self, length: u32) { - self.input_length.write(U32::new(length)) - } - - fn set_input_mailbox_pointer(&mut self, pa: PhysicalAddress) -> Result<(), &'static str> { - error!("Don't use this function yet! We don't fill out the mailbox fields"); - - if pa.value() & 0x1FF != 0 { - return Err("input mailbox pointer physical address lower 9 bits must be zero."); - } - - self.input_mailbox_pointer_h.write(U32::new((pa.value() >> 32) as u32)); - let val = self.input_mailbox_pointer_l.read().get() & 0x1FF; - self.input_mailbox_pointer_l.write(U32::new(pa.value() as u32 | val)); - Ok(()) - } - - // right now assume only 8 bytes of commands are passed - fn set_input_inline_data(&mut self, opcode: CommandOpcode, op_mod: Option, command0: Option, command1: Option) { - self.command_input_opcode.write(U32::new((opcode as u32) << 16)); - self.command_input_op_mod.write(U32::new(op_mod.unwrap_or(0) as u32)); - self.command_input_inline_data_0.write(U32::new(command0.unwrap_or(0))); - self.command_input_inline_data_1.write(U32::new(command1.unwrap_or(0))); - - } - - fn get_command_opcode(&self) -> CommandOpcode { - match self.command_input_opcode.read().get() >> 16 { - 0x100 => {CommandOpcode::QueryHcaCap}, - 0x101 => {CommandOpcode::QueryAdapter}, - 0x102 => {CommandOpcode::InitHca}, - 0x103 => {CommandOpcode::TeardownHca}, - 0x104 => {CommandOpcode::EnableHca}, - 0x105 => {CommandOpcode::DisableHca}, - 0x107 => {CommandOpcode::QueryPages}, - 0x108 => {CommandOpcode::ManagePages}, - 0x10A => {CommandOpcode::QueryIssi}, - 0x10B => {CommandOpcode::SetIssi}, - _ => {CommandOpcode::Unknown} - } - } - - // right now assume only 8 bytes of commands are passed - fn get_output_inline_data(&self) -> (u8, u32, u32, u32) { - ( - (self.command_output_status.read().get() >> 24) as u8, - self.command_output_syndrome.read().get(), - self.command_output_inline_data_0.read().get(), - self.command_output_inline_data_1.read().get() - ) - } - - fn set_output_mailbox_pointer(&mut self, mp: &mut MappedPages, pa: PhysicalAddress) -> Result<(), &'static str> { - error!("Don't use this function yet! We don't fill out the mailbox fields"); - - if pa.value() & 0x1FF != 0 { - return Err("output mailbox pointer physical address lower 9 bits must be zero."); - } - - self.output_mailbox_pointer_h.write(U32::new((pa.value() >> 32) as u32)); - let val = self.output_mailbox_pointer_l.read().get() & 0x1FF; - self.output_mailbox_pointer_l.write(U32::new(pa.value() as u32 | val)); - Ok(()) - } - - fn set_output_length_in_bytes(&mut self, length: u32) { - self.output_length.write(U32::new(length)); - } - - fn get_output_length_in_bytes(&self) -> u32 { - self.output_length.read().get() - } - - fn set_token(&mut self, token: u8) { - let val = self.token_signature_status_own.read().get(); - self.token_signature_status_own.write(U32::new(val | ((token as u32) << 24))); - } - - fn get_token(&self) -> u8 { - (self.token_signature_status_own.read().get() >> 24) as u8 - } - - fn get_signature(&self) -> u8 { - (self.token_signature_status_own.read().get() >> 16) as u8 - } - - pub fn get_delivery_status(&self) -> CommandDeliveryStatus { - let status = self.token_signature_status_own.read().get() & 0xFE; - if status == 0 { - CommandDeliveryStatus::Success - } else if status == 1 { - CommandDeliveryStatus::SignatureErr - } else if status == 2 { - CommandDeliveryStatus::TokenErr - } else if status == 3 { - CommandDeliveryStatus::BadBlockNumber - } else if status == 4 { - CommandDeliveryStatus::BadOutputPointer - } else if status == 5 { - CommandDeliveryStatus::BadInputPointer - } else if status == 6 { - CommandDeliveryStatus::InternalErr - } else if status == 7 { - CommandDeliveryStatus::InputLenErr - } else if status == 8 { - CommandDeliveryStatus::OutputLenErr - } else if status == 9 { - CommandDeliveryStatus::ReservedNotZero - } else if status == 10 { - CommandDeliveryStatus::BadCommandType - } else { - CommandDeliveryStatus::Unknown - } - } - - pub fn change_ownership_to_hw(&mut self) { - let ownership = self.token_signature_status_own.read().get() | 0x1; - self.token_signature_status_own.write(U32::new(ownership)); - } - - pub fn owned_by_hw(&self) -> bool { - self.token_signature_status_own.read().get().get_bit(0) - } - - pub fn get_return_status(&self) -> CommandReturnStatus { - let (status, _syndrome, _, _) = self.get_output_inline_data(); - - if status == 0x0 { - CommandReturnStatus::OK - } else if status == 0x1 { - CommandReturnStatus::InternalError - } else if status == 0x2 { - CommandReturnStatus::BadOp - } else if status == 0x3 { - CommandReturnStatus::BadParam - } else if status == 0x4 { - CommandReturnStatus::BadSysState - } else if status == 0x5 { - CommandReturnStatus::BadResource - } else if status == 0x6 { - CommandReturnStatus::ResourceBusy - } else if status == 0x8 { - CommandReturnStatus::ExceedLim - } else if status == 0x9 { - CommandReturnStatus::BadResState - } else if status == 0xA { - CommandReturnStatus::BadIndex - } else if status == 0xF { - CommandReturnStatus::NoResources - } else if status == 0x50 { - CommandReturnStatus::BadInputLen - } else if status == 0x51 { - CommandReturnStatus::BadOutputLen - } else if status == 0x10 { - CommandReturnStatus::BadResourceState - } else if status == 0x30 { - CommandReturnStatus::BadPkt - } else if status == 0x40 { - CommandReturnStatus::BadSize - } else { - CommandReturnStatus::Unknown - } - } -} - -#[derive(FromBytes)] -#[repr(C)] -struct CommandInterfaceMailbox { - mailbox_data: Volatile<[u8; 512]>, - _padding: ReadOnly<[u8; 48]>, - next_pointer_h: Volatile>, - next_pointer_l: Volatile>, - block_number: Volatile>, - token_ctrl_signature: Volatile> -} -const_assert_eq!(core::mem::size_of::(), 576); - -impl CommandInterfaceMailbox { - fn clear_all_fields(&mut self) { - self. mailbox_data.write([0;512]); - self.next_pointer_h.write(U32::new(0)); - self.next_pointer_l.write(U32::new(0)); - self.block_number.write(U32::new(0)); - self.token_ctrl_signature.write(U32::new(0)); - } -} - -impl fmt::Debug for CommandInterfaceMailbox { - fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - for i in 0..(512/4) { - let data = self.mailbox_data.read(); - write!(f, "mailbox data: {:#X} {:#X} {:#X} {:#X} \n", data[i*4], data[i*4+1], data[i*4+2], data[i*4 +3])?; - } - - // write!(f, "padding: {}", self._padding.read())?; - writeln!(f, "next pointer h: {:#X} \n", self.next_pointer_h.read().get())?; - writeln!(f, "next pointer l: {:#X} \n", self.next_pointer_l.read().get())?; - writeln!(f, "block number: {:#X} \n", self.block_number.read().get())?; - writeln!(f, "token ctrl signature: {:#X} \n", self.token_ctrl_signature.read().get()) - } -} - -#[derive(Debug)] -pub enum CommandDeliveryStatus { - Success = 0, - SignatureErr = 1, - TokenErr = 2, - BadBlockNumber = 3, - BadOutputPointer = 4, - BadInputPointer = 5, - InternalErr = 6, - InputLenErr = 7, - OutputLenErr = 8, - ReservedNotZero = 9, - BadCommandType = 10, //Should this be 10 or 16?? - Unknown, -} - -#[derive(PartialEq, Debug)] -pub enum CommandOpcode { - QueryHcaCap = 0x100, - QueryAdapter = 0x101, - InitHca = 0x102, - TeardownHca = 0x103, - EnableHca = 0x104, - DisableHca = 0x105, - QueryPages = 0x107, - ManagePages = 0x108, - QueryIssi = 0x10A, - SetIssi = 0x10B, - QuerySpecialContexts = 0x203, - CreateEq = 0x301, - CreateCq = 0x400, - QueryVportState = 0x751, - QueryNicVportContext = 0x754, - AllocUar = 0x802, - AllocPd = 0x800, - AllocTransportDomain = 0x816, - CreateTis = 0x912, - CreateSq = 0x904, - ModifySq = 0x905, - CreateRq = 0x908, - ModifyRq = 0x909, - Unknown -} - - -#[derive(Debug)] -pub enum CommandReturnStatus { - OK = 0x00, - InternalError = 0x01, - BadOp = 0x02, - BadParam = 0x03, - BadSysState = 0x04, - BadResource = 0x05, - ResourceBusy = 0x06, - ExceedLim = 0x08, - BadResState = 0x09, - BadIndex = 0x0A, - NoResources = 0x0F, - BadInputLen = 0x50, - BadOutputLen = 0x51, - BadResourceState = 0x10, - BadPkt = 0x30, - BadSize = 0x40, - Unknown -} -/// Section 8.24.1 -/// A buffer of fixed-size entries that is used to pass commands to the HCA. -/// The number of enties and the entry stride is retrieved from the initialization segment of the HCA BAR. -/// It resides in a physically contiguous 4 KiB memory chunk. -#[repr(C)] -pub struct CommandQueue { - entries: BoxRefMut, - available_entries: [bool; MAX_CMND_QUEUE_ENTRIES], - token: u8, //taken from snabb, my assumption is that it is a random number that needs to be different for every command - mailbox_buffers_input: Vec>, // A page, physical address of the page, and if it's in use - mailbox_buffers_output: Vec> // A page, physical address of the page, and if it's in use -} - -const MAILBOX_SIZE_IN_BYTES: usize = 576; -const MAILBOX_DATA_SIZE_IN_BYTES: usize = 512; - -const SIZE_PADDR_IN_BYTES: usize = 8; // each physical address takes 8 bytes in the mailbox -const SIZE_PADDR_H_IN_BYTES: usize = 4; // each physical address takes 8 bytes in the mailbox -const SIZE_PADDR_L_IN_BYTES: usize = 4; // each physical address takes 8 bytes in the mailbox -pub enum ManagePagesOpmod { - AllocationFail = 0, - AllocationSuccess = 1, - HcaReturnPages = 2 -} - -pub enum QueryPagesOpmod { - BootPages = 1, - InitPages = 2, - RegularPages = 3 -} - -#[derive(PartialEq)] -enum MailboxType { - Input, - Output -} - -enum QueryVportStateOpMod { - VnicVport = 0, - EswVport = 1, - Uplink = 2 -} - -impl CommandQueue { - - pub fn create(entries: BoxRefMut, num_cmdq_entries: usize) -> Result { - let mut available_entries = [false; MAX_CMND_QUEUE_ENTRIES]; - for i in 0..num_cmdq_entries { available_entries[i] = true; } - - // allocate one page to be the mailbox buffer per entry - let mut mailbox_buffers_input = Vec::with_capacity(num_cmdq_entries); - let mut mailbox_buffers_output = Vec::with_capacity(num_cmdq_entries); - for _ in 0..num_cmdq_entries { - let (mailbox_mp, mailbox_pa) = create_contiguous_mapping(PAGE_SIZE, NIC_MAPPING_FLAGS)?; - mailbox_buffers_input.push(vec!((mailbox_mp, mailbox_pa))); - - let (mailbox_mp, mailbox_pa) = create_contiguous_mapping(PAGE_SIZE, NIC_MAPPING_FLAGS)?; - mailbox_buffers_output.push(vec!((mailbox_mp, mailbox_pa))); - } - - Ok(CommandQueue{ entries, available_entries, token: 0xAA, mailbox_buffers_input, mailbox_buffers_output }) - } - - fn find_free_command_entry(&self) -> Option { - self.available_entries.iter().position(|&x| x == true) - } - - pub fn create_command( - &mut self, opcode: CommandOpcode, - op_mod: Option, - allocated_pages: Option>, - uar: Option, - log_queue_size: Option - ) -> Result - { - let entry_num = self.find_free_command_entry().ok_or("No command entry available")?; - - let mut cmdq_entry = CommandQueueEntry::default(); - cmdq_entry.set_type_of_transport(CommandTransportType::PCIe); - cmdq_entry.set_token(self.token); - cmdq_entry.change_ownership_to_hw(); - - match opcode { - CommandOpcode::EnableHca => { - cmdq_entry.set_input_length_in_bytes(12); - cmdq_entry.set_output_length_in_bytes(8); - cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); - } - CommandOpcode::QueryIssi => { - warn!("running query issi with smaller output length, may be an error"); - cmdq_entry.set_input_length_in_bytes(8); - cmdq_entry.set_output_length_in_bytes(112); - cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); - - self.init_query_issi_output_mailbox_buffers(entry_num)?; - self.set_mailbox_pointer_in_cmd_entry(&mut cmdq_entry, entry_num, MailboxType::Output); - - } - CommandOpcode::SetIssi => { - warn!("setting to 1 by default, could be wrong"); - cmdq_entry.set_input_length_in_bytes(12); - cmdq_entry.set_output_length_in_bytes(8); - cmdq_entry.set_input_inline_data(opcode, op_mod, Some(1), None); - } - CommandOpcode::InitHca => { - cmdq_entry.set_input_length_in_bytes(12); - cmdq_entry.set_output_length_in_bytes(8); - cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); - } - CommandOpcode::QuerySpecialContexts => { - cmdq_entry.set_input_length_in_bytes(8); - cmdq_entry.set_output_length_in_bytes(16); - cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); - } - CommandOpcode::QueryPages => { - cmdq_entry.set_input_length_in_bytes(12); - cmdq_entry.set_output_length_in_bytes(16); - cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); - } - CommandOpcode::ManagePages => { - let pages_pa = allocated_pages.ok_or("No pages were passed to the manage pages command")?; - cmdq_entry.set_input_length_in_bytes(0x10 + pages_pa.len() as u32 *8); // taken from snabb - cmdq_entry.set_output_length_in_bytes(16); - cmdq_entry.set_input_inline_data( - opcode, - op_mod, - None, - Some(pages_pa.len() as u32) - ); - - self.init_manage_pages_input_mailbox_buffers(entry_num, pages_pa)?; - self.set_mailbox_pointer_in_cmd_entry(&mut cmdq_entry, entry_num, MailboxType::Input); - } - CommandOpcode::AllocUar => { - cmdq_entry.set_input_length_in_bytes(8); - cmdq_entry.set_output_length_in_bytes(12); - cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); - }, - CommandOpcode::CreateEq => { - let pages_pa = allocated_pages.ok_or("No pages were passed to the create EQ command")?; - - cmdq_entry.set_input_length_in_bytes((0x110 + pages_pa.len()*8) as u32); - cmdq_entry.set_output_length_in_bytes(12); - cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); - - self.create_page_request_event_queue( - entry_num, - pages_pa, - uar.ok_or("uar not specified in EQ creation")?, - log_queue_size.ok_or("queue size not specified in EQ creation")? - )?; - - self.set_mailbox_pointer_in_cmd_entry(&mut cmdq_entry, entry_num, MailboxType::Input); - }, - CommandOpcode::QueryVportState => { // only accesses your own vport - cmdq_entry.set_input_length_in_bytes(12); - cmdq_entry.set_output_length_in_bytes(16); - cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); - }, - CommandOpcode::QueryNicVportContext => { // only accesses your own vport - cmdq_entry.set_input_length_in_bytes(16); - cmdq_entry.set_output_length_in_bytes(16 + 0x100); - cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); - - self.init_nic_vport_context_output_mailbox_buffers(entry_num)?; - self.set_mailbox_pointer_in_cmd_entry(&mut cmdq_entry, entry_num, MailboxType::Output); - }, - CommandOpcode::AllocPd => { - cmdq_entry.set_input_length_in_bytes(8); - cmdq_entry.set_output_length_in_bytes(12); - cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); - }, - CommandOpcode::AllocTransportDomain => { - cmdq_entry.set_input_length_in_bytes(8); - cmdq_entry.set_output_length_in_bytes(12); - cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); - }, - CommandOpcode::QuerySpecialContexts => { - cmdq_entry.set_input_length_in_bytes(8); - cmdq_entry.set_output_length_in_bytes(12); - cmdq_entry.set_input_inline_data(opcode, op_mod, None, None); - }, - _=> { - debug!("unimplemented opcode"); - } - } - core::mem::swap(&mut cmdq_entry, &mut self.entries[entry_num]); - warn!("{:?}", &mut self.entries[entry_num]); - self.token = self.token.wrapping_add(1); - self.available_entries[entry_num] = false; - Ok(entry_num) - } - - fn set_mailbox_pointer_in_cmd_entry(&mut self, cmdq_entry: &mut CommandQueueEntry, entry_num: usize, mailbox_type: MailboxType) { - if mailbox_type == MailboxType::Input { - let mailbox_ptr = self.mailbox_buffers_input[entry_num][0].1.value(); - warn!("mailbox ptr in command entry: {:#X}", mailbox_ptr); - cmdq_entry.input_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); - cmdq_entry.input_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); - } else { - let mailbox_ptr = self.mailbox_buffers_output[entry_num][0].1.value(); - cmdq_entry.output_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); - cmdq_entry.output_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); - } - } - - fn init_query_issi_output_mailbox_buffers(&mut self, entry_num: usize) -> Result<(), &'static str> { - const NUM_MAILBOXES_QUERY_ISSI: usize = 1; - self.initialize_mailboxes(entry_num, NUM_MAILBOXES_QUERY_ISSI, MailboxType::Output)?; - Ok(()) - } - - fn init_manage_pages_input_mailbox_buffers(&mut self, entry_num: usize, mut pages: Vec) -> Result<(), &'static str> { - - let num_mailboxes = libm::ceilf((pages.len() * SIZE_PADDR_IN_BYTES) as f32 / MAILBOX_DATA_SIZE_IN_BYTES as f32) as usize; - self.initialize_mailboxes(entry_num, num_mailboxes, MailboxType::Input)?; - - let mailbox_pages = &mut self.mailbox_buffers_input[entry_num]; - let paddr_per_mailbox = MAILBOX_DATA_SIZE_IN_BYTES / SIZE_PADDR_IN_BYTES; - - for block_num in 0..num_mailboxes { - let (mb_page, mb_page_starting_addr) = &mut mailbox_pages[block_num]; - - let mailbox = mb_page.as_type_mut::(0)?; - - let mut data = [0; 512]; - - for page in 0..paddr_per_mailbox { - let paddr = pages.pop(); - match paddr { - Some(paddr) => { - Self::write_paddr_in_mailbox_data(page*SIZE_PADDR_IN_BYTES, paddr, &mut data); - }, - None => { - trace!("breaking out of loop on mailbox: {} and paddr: {}", block_num, page); - break; - } - } - } - - mailbox.mailbox_data.write(data); - debug!("Mailbox {}", block_num); - debug!("{:?}", mailbox); - } - - Ok(()) - } - - pub fn wait_for_command_completion(&mut self, entry_num: usize) -> (CommandDeliveryStatus, CommandReturnStatus) { - while self.entries[entry_num].owned_by_hw() {} - self.available_entries[entry_num] = true; - debug!("{:?}", self.entries[entry_num]); - (self.entries[entry_num].get_delivery_status(), self.entries[entry_num].get_return_status()) - } - - fn check_command_output_validity(&self, entry_num: usize, cmd_opcode: CommandOpcode) -> Result<(), &'static str> { - if self.entries[entry_num].owned_by_hw() { - error!("the command hasn't completed yet!"); - return Err("the command hasn't completed yet!"); - } - - if self.entries[entry_num].get_command_opcode() != cmd_opcode { - error!("Incorrect Command!: {:?}", self.entries[entry_num].get_command_opcode()); - return Err("Incorrect Command!"); - } - - Ok(()) - } - - pub fn get_query_issi_command_output(&self, entry_num: usize) -> Result<(u16, u8), &'static str> { - self.check_command_output_validity(entry_num, CommandOpcode::QueryIssi)?; - - // This offset is not correct! need to check! - const DATA_OFFSET_IN_MAILBOX: usize = 0x20 - 0x10; - let mailbox = &self.mailbox_buffers_output[entry_num][0].0; - debug!("Query ISSI mailbox {:?}", mailbox.as_type::(0)?); - let supported_issi = (mailbox.as_type::(DATA_OFFSET_IN_MAILBOX)?).to_le(); - - let (_status, _syndrome, current_issi , _command1) = self.entries[entry_num].get_output_inline_data(); - Ok((current_issi as u16, supported_issi as u8)) - } - - pub fn get_query_pages_command_output(&self, entry_num: usize) -> Result { - self.check_command_output_validity(entry_num, CommandOpcode::QueryPages)?; - - let (_status, _syndrome, _function_id, num_pages) = self.entries[entry_num].get_output_inline_data(); - Ok(num_pages) - } - - pub fn get_uar(&self, entry_num: usize) -> Result { - debug!("{:?}",self.entries[entry_num]); - self.check_command_output_validity(entry_num, CommandOpcode::AllocUar)?; - let (_status, _syndrome, uar, _reserved) = self.entries[entry_num].get_output_inline_data(); - Ok(uar & 0xFF_FFFF) - } - - fn create_page_request_event_queue(&mut self, entry_num: usize, mut pages: Vec, uar: u32, log_eq_size: u8) -> Result<(), &'static str> { - - let size_of_mailbox_data = (0x110 - 0x10) + SIZE_PADDR_IN_BYTES * pages.len(); - - let num_mailboxes = libm::ceilf(size_of_mailbox_data as f32 / MAILBOX_DATA_SIZE_IN_BYTES as f32) as usize; - self.initialize_mailboxes(entry_num, num_mailboxes, MailboxType::Input)?; - - let mailbox_pages = &mut self.mailbox_buffers_input[entry_num]; - - for block_num in 0..num_mailboxes { - let (mb_page, _mb_page_starting_addr) = &mut mailbox_pages[block_num]; - - if block_num == 0 { - // initialize the event queue context - let eq_context = mb_page.as_type_mut::(0)?; - eq_context.init(uar, log_eq_size); - - // initialize the bitmask. this function only activates the page request event - let bitmask_offset_in_mailbox = 0x58 - 0x10; - let eq_bitmask = mb_page.as_type_mut::(bitmask_offset_in_mailbox)?; - const PAGE_REQUEST_BIT: u64 = 1 << 0xB; - *eq_bitmask = PAGE_REQUEST_BIT; - - // Now use the remainder of the mailbox for page entries - let eq_pa_offset = 0x110 - 0x10; - let data = mb_page.as_type_mut::<[u8;256]>(eq_pa_offset)?; - let pages_in_mailbox_0 = (MAILBOX_DATA_SIZE_IN_BYTES - eq_pa_offset) / SIZE_PADDR_IN_BYTES; - - for page in 0..pages_in_mailbox_0 { - let paddr = pages.pop(); - match paddr { - Some(paddr) => { - Self::write_paddr_in_mailbox_data(page*SIZE_PADDR_IN_BYTES, paddr, data); - }, - None => { - trace!("breaking out of loop on mailbox: {} and page: {}", block_num, page); - break; - } - } - } - - debug!("Mailbox {}", block_num); - debug!("{:?}", mb_page.as_type_mut::(0)?); - - } else { - let mailbox = mb_page.as_type_mut::(0)?; - let paddr_per_mailbox = MAILBOX_DATA_SIZE_IN_BYTES / SIZE_PADDR_IN_BYTES; - let mut data = [0; 512]; - - for page in 0..paddr_per_mailbox { - let paddr = pages.pop(); - match paddr { - Some(paddr) => { - Self::write_paddr_in_mailbox_data(page*SIZE_PADDR_IN_BYTES, paddr, &mut data); - }, - None => { - trace!("breaking out of loop on mailbox: {} and paddr: {}", block_num, page); - break; - } - } - } - - mailbox.mailbox_data.write(data); - - debug!("Mailbox {}", block_num); - debug!("{:?}", mailbox); - } - } - Ok(()) - } - - pub fn get_eq_number(&self, entry_num: usize) -> Result { - self.check_command_output_validity(entry_num, CommandOpcode::CreateEq)?; - - let (_status, _syndrome, eq_number, _reserved) = self.entries[entry_num].get_output_inline_data(); - Ok(eq_number as u8) - } - - fn get_vport_state(&self, entry_num: usize)-> Result<(u16, u8, u8), &'static str> { - self.check_command_output_validity(entry_num, CommandOpcode::QueryVportState)?; - - let (_status, _syndrome, _reserved, output) = self.entries[entry_num].get_output_inline_data(); - let max_tx_speed = (output >> 16) as u16; - let admin_state = (output as u8 & 0xF0) >> 4; - let state = (output as u8) & 0xF; - - Ok((max_tx_speed, admin_state, state)) - } - - fn init_nic_vport_context_output_mailbox_buffers(&mut self, entry_num: usize) -> Result<(), &'static str> { - const NUM_MAILBOXES_NIC_VPORT_CONTEXT: usize = 1; - self.initialize_mailboxes(entry_num, NUM_MAILBOXES_NIC_VPORT_CONTEXT, MailboxType::Output)?; - Ok(()) - } - - fn get_vport_context(&self, entry_num: usize)-> Result<(u16, [u8;6]), &'static str> { - self.check_command_output_validity(entry_num, CommandOpcode::QueryNicVportContext)?; - - let context = self.mailbox_buffers_output[entry_num][0].0.as_type::(0)?; - let mac_addr_h = context.permanent_address_h.read().get(); - let mac_addr_l = context.permanent_address_l.read().get(); - - let mut mac_addr = [0; 6]; - mac_addr[0] = mac_addr_l as u8; - mac_addr[1] = (mac_addr_l >> 8) as u8; - mac_addr[2] = (mac_addr_l >> 16) as u8; - mac_addr[3] = (mac_addr_l >> 24) as u8; - mac_addr[4] = mac_addr_h as u8; - mac_addr[5] = (mac_addr_h >> 8) as u8; - - - Ok((context.mtu.read().get() as u16, mac_addr)) - } - - pub fn get_protection_domain(&self, entry_num: usize) -> Result { - self.check_command_output_validity(entry_num, CommandOpcode::AllocPd)?; - let (_status, _syndrome, pd, _reserved) = self.entries[entry_num].get_output_inline_data(); - - Ok(pd & 0xFF_FFFF) - } - - pub fn get_transport_domain(&self, entry_num: usize) -> Result { - self.check_command_output_validity(entry_num, CommandOpcode::AllocTransportDomain)?; - let (_status, _syndrome, td, _reserved) = self.entries[entry_num].get_output_inline_data(); - - Ok(td & 0xFF_FFFF) - } - - pub fn get_reserved_lkey(&self, entry_num: usize) -> Result { - self.check_command_output_validity(entry_num, CommandOpcode::QuerySpecialContexts)?; - let (_status, _syndrome, _dump_fill_mkey, resd_lkey) = self.entries[entry_num].get_output_inline_data(); - - Ok(resd_lkey) - } - - fn write_paddr_in_mailbox_data(start_offset: usize, paddr: PhysicalAddress, data: &mut [u8]) { - let start_offset_h = start_offset; - let end_offset_h = start_offset_h + SIZE_PADDR_H_IN_BYTES; - let addr = (paddr.value() >> 32) as u32; - data[start_offset_h..end_offset_h].copy_from_slice(&addr.to_be_bytes()); - - let start_offset_l = end_offset_h; - let end_offset_l = start_offset_l + SIZE_PADDR_L_IN_BYTES; - let addr = (paddr.value() & 0xFFFF_FFFF) as u32; - data[start_offset_l..end_offset_l].copy_from_slice(&addr.to_be_bytes()); - } - - /// Clears all mailboxes, then sets the token, block number and next address fields for all mailboxes - fn initialize_mailboxes(&mut self, entry_num: usize, num_mailboxes: usize, mailbox_type: MailboxType) -> Result<(), &'static str> { - let mailbox_pages = if mailbox_type == MailboxType::Input{ - &mut self.mailbox_buffers_input[entry_num] - } else { - &mut self.mailbox_buffers_output[entry_num] - }; - - // Adding extra mailbox pages - let available_mailboxes = mailbox_pages.len(); - if num_mailboxes > available_mailboxes { - let num_mailbox_pages_required = num_mailboxes - available_mailboxes; - trace!("Adding {} mailbox pages", num_mailbox_pages_required); - - for _ in 0..num_mailbox_pages_required { - mailbox_pages.push(create_contiguous_mapping(PAGE_SIZE, NIC_MAPPING_FLAGS)?); - } - } - - for block_num in 0..num_mailboxes { - // record the next page address to set pointer for last mailbox (can't have two borrows in the same loop) - let next_mb_addr = if block_num < (num_mailboxes - 1) { - mailbox_pages[block_num + 1].1.value() - } else { - 0 - }; - - let (mb_page, mb_page_starting_addr) = &mut mailbox_pages[block_num]; - - trace!("Initializing mb: {}", block_num); - let mailbox = mb_page.as_type_mut::(0)?; - mailbox.clear_all_fields(); - - mailbox.block_number.write(U32::new(block_num as u32)); - mailbox.token_ctrl_signature.write(U32::new((self.token as u32) << 16)); - - mailbox.next_pointer_h.write(U32::new((next_mb_addr >> 32) as u32)); - mailbox.next_pointer_l.write(U32::new((next_mb_addr & 0xFFFF_FFFF) as u32)); - - } - - Ok(()) - } -} - -#[derive(FromBytes)] -#[repr(C)] -struct EventQueueContext { - status: Volatile>, - _padding1: ReadOnly, - page_offset: Volatile>, - uar_log_eq_size: Volatile>, - _padding2: ReadOnly, - intr: Volatile>, - log_pg_size: Volatile>, - _padding3: ReadOnly, - consumer_counter: Volatile>, - producer_counter: Volatile>, - _padding4: ReadOnly<[u8;12]>, -} - -const_assert_eq!(core::mem::size_of::(), 64); - -impl EventQueueContext { - pub fn init(&mut self, uar_page: u32, log_eq_size: u8) { - let uar = uar_page & 0xFF_FFFF; - let size = ((log_eq_size & 0x1F) as u32) << 24; - self.uar_log_eq_size.write(U32::new(uar | size)); - self.log_pg_size.write(U32::new(0)); - } -} - -#[derive(FromBytes)] -#[repr(C)] -struct NicVportContext { - data1: Volatile>, - data2: Volatile>, - data3: Volatile>, - _padding0: ReadOnly<[u8; 24]>, - mtu: Volatile>, - system_image_guid: Volatile>, - port_guid: Volatile>, - node_guid: Volatile>, - max_qp_retry: Volatile>, - _padding1: ReadOnly<[u8; 36]>, - qkey_violation_counter: Volatile>, - _padding2: ReadOnly<[u8; 132]>, - list_info: Volatile>, - permanent_address_h: Volatile>, - permanent_address_l: Volatile>, - sw_network_metadata: Volatile>, -} - -const_assert_eq!(core::mem::size_of::(), 256); diff --git a/kernel/mlx5/Cargo.toml b/kernel/mlx5/Cargo.toml index 7b01d937af..009b7dcc28 100644 --- a/kernel/mlx5/Cargo.toml +++ b/kernel/mlx5/Cargo.toml @@ -7,61 +7,28 @@ build = "../../build.rs" [dependencies] spin = "0.9.0" -volatile = "0.2.7" -x86_64 = { path = "../../libs/x86_64" } # currently using our local copy, forked from Phil Opp's crate owning_ref = { git = "https://github.com/theseus-os/owning-ref-rs" } -zerocopy = "0.5.0" -static_assertions = "1.1.0" - [dependencies.log] version = "0.4.8" -[dependencies.lazy_static] -features = ["spin_no_std", "nightly"] -version = "1.2.0" - [dependencies.irq_safety] git = "https://github.com/theseus-os/irq_safety" -[dependencies.kernel_config] -path = "../kernel_config" - [dependencies.memory] path = "../memory" -[dependencies.apic] -path = "../apic" - -[dependencies.pic] -path = "../pic" - [dependencies.pci] path = "../pci" -[dependencies.interrupts] -path = "../interrupts" - -[dependencies.mpmc] -path = "../../libs/mpmc" - -[dependencies.network_interface_card] -path = "../network_interface_card" - -[dependencies.intel_ethernet] -path = "../intel_ethernet" - -[dependencies.nic_buffers] -path = "../nic_buffers" - -[dependencies.nic_queues] -path = "../nic_queues" - [dependencies.nic_initialization] path = "../nic_initialization" [dependencies.mellanox_ethernet] path = "../mellanox_ethernet" +[dependencies.kernel_config] +path = "../kernel_config" + [lib] crate-type = ["rlib"] diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index 8c0d209242..a35bf192fc 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -1,168 +1,142 @@ -#![no_std] +//! A mlx5 driver for a ConnectX-5 100GbE Network Interface Card. +//! +//! Currently we only support reading the device PCI space, mapping the initialization segment, +//! and setting up a command queue to pass commands to the NIC. +#![no_std] #![allow(dead_code)] // to suppress warnings for unused functions/methods -#![allow(safe_packed_borrows)] // temporary, just to suppress unsafe packed borrows -#![feature(rustc_private)] -#![feature(abi_x86_interrupt)] #[macro_use] extern crate log; -#[macro_use] extern crate lazy_static; -#[macro_use] extern crate static_assertions; -extern crate volatile; -extern crate zerocopy; extern crate alloc; extern crate spin; extern crate irq_safety; -extern crate kernel_config; extern crate memory; extern crate pci; extern crate owning_ref; -extern crate interrupts; -extern crate pic; -extern crate x86_64; -extern crate mpmc; -extern crate network_interface_card; -extern crate apic; -extern crate intel_ethernet; -extern crate nic_buffers; -extern crate nic_queues; extern crate nic_initialization; extern crate mellanox_ethernet; +extern crate kernel_config; - -use memory::allocate_pages; use spin::Once; -use alloc::vec::Vec; -use alloc::collections::VecDeque; +use alloc::{ + vec::Vec, + boxed::Box +}; use irq_safety::MutexIrqSafe; -use alloc::boxed::Box; use memory::{PhysicalAddress, MappedPages, create_contiguous_mapping}; -use pci::{PciDevice, PCI_INTERRUPT_LINE, PciConfigSpaceAccessMechanism}; -use kernel_config::memory::PAGE_SIZE; +use pci::PciDevice; use owning_ref::BoxRefMut; -use interrupts::{eoi,register_interrupt}; -use x86_64::structures::idt::{ExceptionStackFrame}; -use network_interface_card:: NetworkInterfaceCard; -use nic_initialization::{NIC_MAPPING_FLAGS, allocate_memory, init_rx_buf_pool, init_rx_queue, init_tx_queue}; -use intel_ethernet::descriptors::{LegacyRxDescriptor, LegacyTxDescriptor}; -use nic_buffers::{TransmitBuffer, ReceiveBuffer, ReceivedFrame}; -use nic_queues::{RxQueue, TxQueue, RxQueueRegisters, TxQueueRegisters}; -use mellanox_ethernet::{CommandQueueEntry, InitializationSegment, CommandQueue, CommandOpcode, ManagePagesOpmod, QueryPagesOpmod}; +use nic_initialization::{NIC_MAPPING_FLAGS, allocate_memory}; +use mellanox_ethernet::{ + InitializationSegment, + command_queue::{CommandQueueEntry, CommandQueue, CommandOpcode, ManagePagesOpmod, QueryPagesOpmod} +}; +use kernel_config::memory::PAGE_SIZE; pub const MLX_VEND: u16 = 0x15B3; // Vendor ID for Mellanox pub const CONNECTX5_DEV: u16 = 0x1019; // Device ID for the ConnectX-5 NIC -/// Assuming one of these nics for now +/// The singleton connectx-5 NIC. +/// TODO: Allow for multiple NICs static CONNECTX5_NIC: Once> = Once::new(); -/// Returns a reference to the E1000Nic wrapped in a MutexIrqSafe, +/// Returns a reference to the NIC wrapped in a MutexIrqSafe, /// if it exists and has been initialized. pub fn get_mlx5_nic() -> Option<&'static MutexIrqSafe> { CONNECTX5_NIC.get() } -// /// How many ReceiveBuffers are preallocated for this driver to use. -// const RX_BUFFER_POOL_SIZE: usize = 256; -// lazy_static! { -// /// The pool of pre-allocated receive buffers that are used by the E1000 NIC -// /// and temporarily given to higher layers in the networking stack. -// static ref RX_BUFFER_POOL: mpmc::Queue = mpmc::Queue::with_capacity(RX_BUFFER_POOL_SIZE); -// } - - -/// Struct representing a connectx-5 network interface card. +/// Struct representing a ConnectX-5 network interface card. pub struct ConnectX5Nic { - /// Type of BAR0 - bar_type: u8, - /// MMIO Base Address + /// Initialization segment base address mem_base: PhysicalAddress, + /// Initialization Segment + init_segment: BoxRefMut, + /// Command Queue + command_queue: CommandQueue, + /// Boot pages passed to the NIC. Once transferred, they should not be accessed by the driver. + boot_pages: Vec, + /// Init pages passed to the NIC. Once transferred, they should not be accessed by the driver. + init_pages: Vec, } -/// Functions that setup the NIC struct and handle the sending and receiving of packets. +/// Functions that setup the NIC struct. impl ConnectX5Nic { - /// Initializes the new E1000 network interface card that is connected as the given PciDevice. - pub fn init(mlx5_pci_dev: &PciDevice) -> Result<(), &'static str> { //Result<&'static MutexIrqSafe, &'static str> { - use pic::PIC_MASTER_OFFSET; - let bar0 = mlx5_pci_dev.bars[0]; - // Determine the access mechanism from the base address register's bit 0 - let bar_type = (bar0 as u8) & 0x1; - - // If the base address is not memory mapped then exit - if bar_type == PciConfigSpaceAccessMechanism::IoPort as u8 { - error!("mlx5::init(): BAR0 is of I/O type"); - return Err("mlx5::init(): BAR0 is of I/O type") - } - trace!("init segment size = {}", core::mem::size_of::()); - + /// Initializes the new ConnectX-5 network interface card that is connected as the given PciDevice. + /// (steps taken from Section 7.2: HCA Driver Start-up) + pub fn init(mlx5_pci_dev: &PciDevice) -> Result<&'static MutexIrqSafe, &'static str> { // set the bus mastering bit for this PciDevice, which allows it to use DMA mlx5_pci_dev.pci_set_command_bus_master_bit(); - // memory mapped base address + // retrieve the memory-mapped base address of the initialization segment let mem_base = mlx5_pci_dev.determine_mem_base(0)?; trace!("mlx5 mem base = {}", mem_base); + // map pages to the physical address given by mem_base as that is the intialization segment - let mut init_segment = ConnectX5Nic::mapped_init_segment(mem_base)?; + let mut init_segment = ConnectX5Nic::map_init_segment(mem_base)?; - // init_segment.pf_reset(); - init_segment.print(); + trace!("{:?}", init_segment); // find number of entries in command queue and stride - let cmdq_entries = init_segment.num_cmdq_entries() as usize; - trace!("mlx5 cmdq entries = {}", cmdq_entries); + let num_cmdq_entries = init_segment.num_cmdq_entries() as usize; + trace!("mlx5 cmdq entries = {}", num_cmdq_entries); + + // find command queue entry stride, the number of bytes between the start of two adjacent entries. let cmdq_stride = init_segment.cmdq_entry_stride() as usize; trace!("mlx5 cmdq stride = {}", cmdq_stride); - if cmdq_stride != core::mem::size_of::() { + // We assume that the stride is equal to the size of the entry. + if cmdq_stride != core::mem::size_of::() { error!("Command Queue layout is no longer accurate due to invalid assumption."); return Err("Command Queue layout is no longer accurate due to invalid assumption."); } + // create command queue - let size_in_bytes_of_cmdq = cmdq_entries * cmdq_stride; + let size_in_bytes_of_cmdq = num_cmdq_entries * cmdq_stride; trace!("total size in bytes of cmdq = {}", size_in_bytes_of_cmdq); - // cmdp needs to be aligned, check?? + // allocate mapped pages for the command queue let (cmdq_mapped_pages, cmdq_starting_phys_addr) = create_contiguous_mapping(size_in_bytes_of_cmdq, NIC_MAPPING_FLAGS)?; trace!("cmdq mem base = {}", cmdq_starting_phys_addr); // cast our physically-contiguous MappedPages into a slice of command queue entries let mut cmdq = CommandQueue::create( - BoxRefMut::new(Box::new(cmdq_mapped_pages)).try_map_mut(|mp| mp.as_slice_mut::(0, cmdq_entries))?, - cmdq_entries + BoxRefMut::new(Box::new(cmdq_mapped_pages)).try_map_mut(|mp| mp.as_slice_mut::(0, num_cmdq_entries))?, + num_cmdq_entries )?; - // write physical location of command queues to initialization segment + // write physical location of command queue to initialization segment init_segment.set_physical_address_of_cmdq(cmdq_starting_phys_addr)?; // Read initalizing field from initialization segment until it is cleared - while init_segment.device_is_initializing() { trace!("device is initializing");} + while init_segment.device_is_initializing() { trace!("device is initializing"); } trace!("initializing field is cleared."); - // Execute ENABLE_HCA command - let cmdq_entry = cmdq.create_command(CommandOpcode::EnableHca, None, None, None, None)?; + let cmdq_entry = cmdq.create_command(CommandOpcode::EnableHca, None, None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); trace!("EnableHCA: {:?}", status); - // execute query ISSI - let cmdq_entry = cmdq.create_command(CommandOpcode::QueryIssi, None, None,None, None)?; + // execute QUERY_ISSI + let cmdq_entry = cmdq.create_command(CommandOpcode::QueryIssi, None, None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); let (current_issi, available_issi) = cmdq.get_query_issi_command_output(cmdq_entry)?; trace!("QueryISSI: {:?}, issi version :{}, available: {:#X}", status, current_issi, available_issi); - // execute set ISSI - let cmdq_entry = cmdq.create_command(CommandOpcode::SetIssi, None, None,None, None)?; + // execute SET_ISSI + let cmdq_entry = cmdq.create_command(CommandOpcode::SetIssi, None, None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); trace!("SetISSI: {:?}", status); // Query pages for boot - let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpmod::BootPages as u16), None, None, None)?; + let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpmod::BootPages as u16), None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); let num_boot_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; @@ -172,99 +146,69 @@ impl ConnectX5Nic { let mut boot_mp = Vec::with_capacity(num_boot_pages as usize); let mut boot_pa = Vec::with_capacity(num_boot_pages as usize); for _ in 0..num_boot_pages { - let (page, pa) = create_contiguous_mapping(4096, NIC_MAPPING_FLAGS)?; + let (page, pa) = create_contiguous_mapping(PAGE_SIZE, NIC_MAPPING_FLAGS)?; boot_mp.push(page); - error!("pa: {:#X}", pa.value()); boot_pa.push(pa); } - let cmdq_entry = cmdq.create_command(CommandOpcode::ManagePages, Some(ManagePagesOpmod::AllocationSuccess as u16), Some(boot_pa), None, None)?; + + // execute MANAGE_PAGES command to transfer boot pages to device + let cmdq_entry = cmdq.create_command( + CommandOpcode::ManagePages, + Some(ManagePagesOpmod::AllocationSuccess as u16), + Some(boot_pa) + )?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); trace!("Manage pages boot status: {:?}", status); // Query pages for init - let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpmod::InitPages as u16), None, None, None)?; + let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpmod::InitPages as u16), None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); - let mut num_init_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; + let num_init_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; trace!("Query pages status: {:?}, init pages: {:?}", status, num_init_pages); - // Allocate pages for init + + let mut init_mp = Vec::with_capacity(num_init_pages as usize); if num_init_pages != 0 { - let mut boot_mp = Vec::with_capacity(num_init_pages as usize); - let mut boot_pa = Vec::with_capacity(num_init_pages as usize); + // Allocate pages for init + let mut init_pa = Vec::with_capacity(num_init_pages as usize); for _ in 0..num_init_pages { - let (page, pa) = create_contiguous_mapping(4096, NIC_MAPPING_FLAGS)?; - boot_mp.push(page); - error!("pa: {:#X}", pa.value()); - boot_pa.push(pa); + let (page, pa) = create_contiguous_mapping(PAGE_SIZE, NIC_MAPPING_FLAGS)?; + init_mp.push(page); + init_pa.push(pa); } - let cmdq_entry = cmdq.create_command(CommandOpcode::ManagePages, Some(ManagePagesOpmod::AllocationSuccess as u16), Some(boot_pa), None, None)?; + + // execute MANAGE_PAGES command to transfer init pages to device + let cmdq_entry = cmdq.create_command( + CommandOpcode::ManagePages, + Some(ManagePagesOpmod::AllocationSuccess as u16), + Some(init_pa) + )?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); trace!("Manage pages init status: {:?}", status); } - // init_hca - let cmdq_entry = cmdq.create_command(CommandOpcode::InitHca, None, None, None, None)?; + // execute INIT_HCA + let cmdq_entry = cmdq.create_command(CommandOpcode::InitHca, None, None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); trace!("Init HCA status: {:?}", status); - // // Query pages for regular - // let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpmod::RegularPages as u16), None, None, None)?; - // init_segment.post_command(cmdq_entry); - // let status = cmdq.wait_for_command_completion(cmdq_entry); - // let num_regular_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; - // trace!("Query pages status: {:?}, Regular pages: {:?}", status, num_regular_pages); - - // // Allocate regular pages - // if num_regular_pages != 0 { - // let mut boot_mp = Vec::with_capacity(num_init_pages as usize); - // let mut boot_pa = Vec::with_capacity(num_init_pages as usize); - // for _ in 0..num_regular_pages { - // let (page, pa) = create_contiguous_mapping(4096, NIC_MAPPING_FLAGS)?; - // boot_mp.push(page); - // error!("pa: {:#X}", pa.value()); - // boot_pa.push(pa); - // } - // let cmdq_entry = cmdq.create_command(CommandOpcode::ManagePages, Some(ManagePagesOpmod::AllocationSuccess as u16), Some(boot_pa), None, None)?; - // init_segment.post_command(cmdq_entry); - // let status = cmdq.wait_for_command_completion(cmdq_entry); - // trace!("Manage pages regular status: {:?}", status); - // } - - // allocate uar - // let cmdq_entry = cmdq.create_command(CommandOpcode::AllocUar, None, None, None, None)?; - // init_segment.post_command(cmdq_entry); - // let status = cmdq.wait_for_command_completion(cmdq_entry); - // trace!("UAR status: {:?}", status); - - // let uar = cmdq.get_uar(cmdq_entry)?; - // trace!("UAR status: {:?}, UAR: {}", status, uar); - - // // create EQ for a Page Request Event - // // Allocate pages for EQ - // let num_eq_pages = 1; - // let mut eq_mp = Vec::with_capacity(num_eq_pages as usize); - // let mut eq_pa = Vec::with_capacity(num_eq_pages as usize); - // for _ in 0..num_eq_pages { - // let (page, pa) = create_contiguous_mapping(4096, NIC_MAPPING_FLAGS)?; - // eq_mp.push(page); - // error!("pa: {:#X}", pa.value()); - // eq_pa.push(pa); - // } - // let cmdq_entry = cmdq.create_command(CommandOpcode::CreateEq, None, Some(eq_pa), Some(uar), Some(7))?; - // init_segment.post_command(cmdq_entry); - // let status = cmdq.wait_for_command_completion(cmdq_entry); - // let eq_number = cmdq.get_eq_number(cmdq_entry)?; - // trace!("Create EQ status: {:?}, number: {}", status, eq_number); - - Ok(()) - - + let mlx5_nic = ConnectX5Nic { + mem_base: mem_base, + init_segment: init_segment, + command_queue: cmdq, + boot_pages: boot_mp, + init_pages: init_mp + }; + + let nic_ref = CONNECTX5_NIC.call_once(|| MutexIrqSafe::new(mlx5_nic)); + Ok(nic_ref) } - fn mapped_init_segment(mem_base: PhysicalAddress) -> Result, &'static str> { + /// Returns the memory-mapped initialization segment of the NIC + fn map_init_segment(mem_base: PhysicalAddress) -> Result, &'static str> { let mp = allocate_memory(mem_base, core::mem::size_of::())?; BoxRefMut::new(Box::new(mp)).try_map_mut(|mp| mp.as_type_mut::(0)) } diff --git a/kernel/mlx5/src/test_mlx5_driver.rs b/kernel/mlx5/src/test_mlx5_driver.rs deleted file mode 100644 index 6be39e51a1..0000000000 --- a/kernel/mlx5/src/test_mlx5_driver.rs +++ /dev/null @@ -1,79 +0,0 @@ -use super::{E1000_NIC, NetworkInterfaceCard, TransmitBuffer}; - -pub fn test_e1000_nic_driver(_: Option) { - match dhcp_request_packet() { - Ok(_) => debug!("test_e1000_nic_driver(): sent DHCP request packet successfully!"), - Err(e) => error!("test_e1000_nic_driver(): failed to send DHCP request packet: error {:?}", e), - }; -} - -#[repr(C, packed)] -pub struct arp_packet { - pub dest1: u16, //set to broadcast ff:ff:... - pub dest2: u16, - pub dest3: u16, - pub source1: u16, - pub source2: u16, - pub source3: u16, - pub packet_type: u16, - pub h_type: u16, - pub p_type: u16, - pub hlen: u8, - pub plen: u8, - pub oper: u16, - pub sha1: u16, //sender hw address, first 2 bytes - pub sha2: u16, // ", next 2 bytes - pub sha3: u16, // ", last 2 bytes - pub spa1: u16, // sender protocol address, first 2 B - pub spa2: u16, // ", last 2 B - pub tha1: u16, //target ", first - pub tha2: u16, // ", next - pub tha3: u16, // ", last - pub tpa1: u16, // ", first - pub tpa2: u16, // ", last -} - -//should test packet transmission and reception as QEMU DHCP server will respond - -//will only b able to see this Tx message in netdump.pcap if user is not mentioned in QEMU flags of Makefile -//QEMU_FLAGS += -net nic,vlan=0,model=e1000,macaddr=00:0b:82:01:fc:42 -net dump,file=netdump.pcap - -//will only receive a response if user is mentioned in qemu flags -//QEMU_FLAGS += -net nic,vlan=1,model=e1000,macaddr=00:0b:82:01:fc:42 -net user,vlan=1 -net dump,file=netdump.pcap - -//or else use a tap interface (default) -//QEMU_FLAGS += -device e1000,netdev=network0,mac=52:55:00:d1:55:01 -netdev tap,id=network0,ifname=tap0,script=no,downscript=no -//will receive a DHCP messgae from 00:1f:c6:9c:89:4c - -pub fn dhcp_request_packet() -> Result<(), &'static str> { - let packet: [u8; 314] = [ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x1f, 0xc6, 0x9c, 0x89, 0x4c, 0x08, 0x00, 0x45, - 0x00, 0x01, 0x2c, 0xa8, 0x36, 0x00, 0x00, 0xfa, 0x11, 0x17, 0x8b, 0x00, 0x00, 0x00, 0x00, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x44, 0x00, 0x43, 0x01, 0x18, 0x59, 0x1f, 0x01, 0x01, 0x06, - 0x00, 0x00, 0x00, 0x3d, 0x1d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xc6, 0x9c, 0x89, - 0x4c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x82, 0x53, 0x63, 0x35, 0x01, 0x01, - 0x3d, 0x07, 0x01, 0x00, 0x1f, 0xc6, 0x9c, 0x89, 0x4c, 0x32, 0x04, 0x00, 0x00, 0x00, 0x00, - 0x37, 0x04, 0x01, 0x03, 0x06, 0x2a, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - ]; - let mut transmit_buffer = TransmitBuffer::new(packet.len() as u16)?; - { - let buffer: &mut [u8] = transmit_buffer.as_slice_mut(0, 314)?; - buffer.copy_from_slice(&packet); - } - let mut e1000_nc = E1000_NIC.try().ok_or("e1000 NIC hasn't been initialized yet")?.lock(); - e1000_nc.send_packet(transmit_buffer) -} From 4db082683ee2879aa3f4159753f930db21978fd9 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Tue, 6 Jul 2021 10:12:11 -0700 Subject: [PATCH 13/31] updated comments --- kernel/mellanox_ethernet/src/command_queue.rs | 4 +-- kernel/mellanox_ethernet/src/lib.rs | 28 +++++++++++-------- kernel/mlx5/src/lib.rs | 12 +++++--- 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs index 28ee784755..06550630f3 100644 --- a/kernel/mellanox_ethernet/src/command_queue.rs +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -1,6 +1,4 @@ //! Defines the Command Queue that is used to pass commands from the driver to the NIC. - //! - //! Most information is taken from the PRM, Section 8.24: Command Interface and Chapter 23: Command Reference. use alloc::vec::Vec; use memory::{PhysicalAddress, MappedPages, create_contiguous_mapping}; @@ -180,7 +178,7 @@ impl CommandQueue { /// /// # Arguments /// * `opcode`: opcode for command that the driver wants to execute - /// * `opmod`: opcode modifer, only applicable for certan commands + /// * `opmod`: opcode modifer, only applicable for certain commands /// * `allocated_pages`: physical address of pages that need to be passed to the NIC. Only used in the MANAGE_PAGES command. pub fn create_command( &mut self, diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index 92df7ef5dc..e7a1d49ab7 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -1,11 +1,14 @@ - //! This crate defines the layout of objects that make up the software interface between the Mellanox hardware and the driver, - //! as well as functions to access different fields of these objects. - //! - //! All information is taken from the Mellanox Adapters Programmer’s Reference Manual (PRM) [Rev 0.54], unless otherwise specified. +//! This crate defines the layout of memory objects that make up the software interface between the Mellanox hardware and the driver, +//! as well as functions to access different fields of these objects. +//! +//! The Mellanox ethernet card is referred to as both the NIC (Network Interface Card) and the HCA (Host Channel Adapter). +//! +//! All information is taken from the Mellanox Adapters Programmer’s Reference Manual (PRM) [Rev 0.54], unless otherwise specified. #![no_std] #![feature(slice_pattern)] #![feature(core_intrinsics)] + #![allow(dead_code)] // to suppress warnings for unused functions/methods #[macro_use]extern crate log; #[macro_use] extern crate alloc; @@ -74,20 +77,21 @@ pub struct InitializationSegment { // const_assert_eq!(core::mem::size_of::(), 16400); impl InitializationSegment { - /// Returns the number of entries in the command queue + /// Returns the maximum number of entries that can be in the command queue pub fn num_cmdq_entries(&self) -> u8 { let log = (self.cmdq_phy_addr_low.read().get() >> 4) & 0x0F; 2_u8.pow(log) } - /// Returns the stride of command queue entries (bytes between the start of consecutive entries) + /// Returns the required stride of command queue entries (bytes between the start of consecutive entries) pub fn cmdq_entry_stride(&self) -> u8 { let val = self.cmdq_phy_addr_low.read().get() & 0x0F; 2_u8.pow(val) } /// Sets the physical address of the command queue within the initialization segment. - /// Arguments + /// + /// # Arguments /// * `cmdq_physical_addr`: the starting physical address of the command queue, the lower 12 bits of which must be zero. pub fn set_physical_address_of_cmdq(&mut self, cmdq_physical_addr: PhysicalAddress) -> Result<(), &'static str> { if cmdq_physical_addr.value() & 0xFFF != 0 { @@ -100,14 +104,14 @@ impl InitializationSegment { Ok(()) } - /// Returns true if the device is still initializing and driver should not pass any commands to the device. + /// Returns true if the device is still initializing, and driver should not pass any commands to the device. pub fn device_is_initializing(&self) -> bool { self.initializing_state.read().get().get_bit(31) } - /// Sets a bit in the command doorbell vector to inform HW that command needs to be executed. + /// Sets a bit in the command doorbell vector to inform HW that the command needs to be executed. /// - /// Arguments + /// # Arguments /// * `command bit`: the command entry that needs to be executed. (e.g. bit 0 corresponds to entry at index 0). pub fn post_command(&mut self, command_bit: usize) { let val = self.command_doorbell_vector.read().get(); @@ -125,10 +129,10 @@ impl fmt::Debug for InitializationSegment { } } -/// The possible values of the initialization state of the device +/// The possible values of the initialization state of the device as taken from the intialization segment. pub enum InitializingState { NotAllowed = 0, - WaitingPermetion = 1, // Is this a typo? + WaitingPermetion = 1, // Is this a typo in the PRM? WaitingResources = 2, Abort = 3 } diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index a35bf192fc..27e753311c 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -2,6 +2,9 @@ //! //! Currently we only support reading the device PCI space, mapping the initialization segment, //! and setting up a command queue to pass commands to the NIC. +//! +//! All information is taken from the Mellanox Adapters Programmer’s Reference Manual (PRM) [Rev 0.54], +//! unless otherwise specified. #![no_std] #![allow(dead_code)] // to suppress warnings for unused functions/methods @@ -33,9 +36,10 @@ use mellanox_ethernet::{ }; use kernel_config::memory::PAGE_SIZE; - -pub const MLX_VEND: u16 = 0x15B3; // Vendor ID for Mellanox -pub const CONNECTX5_DEV: u16 = 0x1019; // Device ID for the ConnectX-5 NIC +/// Vendor ID for Mellanox +pub const MLX_VEND: u16 = 0x15B3; +/// Device ID for the ConnectX-5 NIC +pub const CONNECTX5_DEV: u16 = 0x1019; /// The singleton connectx-5 NIC. /// TODO: Allow for multiple NICs @@ -66,7 +70,7 @@ pub struct ConnectX5Nic { impl ConnectX5Nic { /// Initializes the new ConnectX-5 network interface card that is connected as the given PciDevice. - /// (steps taken from Section 7.2: HCA Driver Start-up) + /// (steps taken from the PRM, Section 7.2: HCA Driver Start-up) pub fn init(mlx5_pci_dev: &PciDevice) -> Result<&'static MutexIrqSafe, &'static str> { // set the bus mastering bit for this PciDevice, which allows it to use DMA From a9641ed59a0c5924f5953a73ed61b805711fe843 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Tue, 6 Jul 2021 10:18:51 -0700 Subject: [PATCH 14/31] cleaned code --- kernel/mellanox_ethernet/src/command_queue.rs | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs index 06550630f3..8f85c64777 100644 --- a/kernel/mellanox_ethernet/src/command_queue.rs +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -294,15 +294,13 @@ impl CommandQueue { /// Sets the mailbox pointer in a command entry with the physical address of the first mailbox. fn set_mailbox_pointer_in_cmd_entry(&mut self, cmdq_entry: &mut CommandQueueEntry, entry_num: usize, mailbox_type: MailboxType) { - if mailbox_type == MailboxType::Input { - let mailbox_ptr = self.mailbox_buffers_input[entry_num][0].1.value(); - cmdq_entry.input_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); - cmdq_entry.input_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); + let mailbox_ptr = if mailbox_type == MailboxType::Input { + self.mailbox_buffers_input[entry_num][0].1.value() } else { - let mailbox_ptr = self.mailbox_buffers_output[entry_num][0].1.value(); - cmdq_entry.output_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); - cmdq_entry.output_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); - } + self.mailbox_buffers_output[entry_num][0].1.value() + }; + cmdq_entry.input_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); + cmdq_entry.input_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); } /// Initialize output mailboxes for the QUERY_ISSI command. @@ -692,7 +690,7 @@ impl CommandQueueEntry { #[derive(FromBytes)] #[repr(C)] -/// Layout of mailbox used to pass extra input and output command data that desn't fit into the command entry. +/// Layout of mailbox used to pass extra input and output command data that doesn't fit into the command entry. struct CommandInterfaceMailbox { /// Data in the mailbox mailbox_data: Volatile<[u8; 512]>, From b60bfb47ba0954fe34ba625e82c5c09c39d1cc63 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Tue, 6 Jul 2021 10:38:42 -0700 Subject: [PATCH 15/31] updated pci passthrough book --- book/src/running/virtual_machine/pci_passthrough.md | 7 +++++-- kernel/mlx5/src/lib.rs | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/book/src/running/virtual_machine/pci_passthrough.md b/book/src/running/virtual_machine/pci_passthrough.md index 404ccc5f78..6578cd975c 100644 --- a/book/src/running/virtual_machine/pci_passthrough.md +++ b/book/src/running/virtual_machine/pci_passthrough.md @@ -53,8 +53,11 @@ e.g. `echo 15b3 1019 > /sys/bus/pci/drivers/vfio-pci/new_id` Now, QEMU can be launched with direct access to the device. ### Return device to the Host OS -`echo 1 >/sys/bus/pci/devices/0000:59:00.0/remove` -`echo 1 >/sys/bus/pci/rescan` +To reset the device, you can either reboot the system or return the device to the host OS using the following commands (replacing $slot_info with the value previously retrieved): +```sh +echo 1 >/sys/bus/pci/devices/$slot_info/remove +echo 1 >/sys/bus/pci/rescan +``` ### Note: access for unprivileged users To give access to an unprivileged user to this VFIO device, find the IOMMU group the device belongs to: diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index 27e753311c..e6924c2722 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -216,4 +216,4 @@ impl ConnectX5Nic { let mp = allocate_memory(mem_base, core::mem::size_of::())?; BoxRefMut::new(Box::new(mp)).try_map_mut(|mp| mp.as_type_mut::(0)) } -} \ No newline at end of file +} From 5d7767ca35b8a8238f04665ae38d8a72bd0553e5 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Fri, 16 Jul 2021 15:21:05 -0700 Subject: [PATCH 16/31] PR improvements --- .../virtual_machine/pci_passthrough.md | 2 +- kernel/mellanox_ethernet/src/command_queue.rs | 89 +++++++++---------- kernel/mellanox_ethernet/src/lib.rs | 28 +++--- kernel/mlx5/Cargo.toml | 2 +- kernel/mlx5/src/lib.rs | 10 +-- 5 files changed, 66 insertions(+), 65 deletions(-) diff --git a/book/src/running/virtual_machine/pci_passthrough.md b/book/src/running/virtual_machine/pci_passthrough.md index 6578cd975c..6a68ef92a8 100644 --- a/book/src/running/virtual_machine/pci_passthrough.md +++ b/book/src/running/virtual_machine/pci_passthrough.md @@ -53,7 +53,7 @@ e.g. `echo 15b3 1019 > /sys/bus/pci/drivers/vfio-pci/new_id` Now, QEMU can be launched with direct access to the device. ### Return device to the Host OS -To reset the device, you can either reboot the system or return the device to the host OS using the following commands (replacing $slot_info with the value previously retrieved): +To reset the device, you can either reboot the system or return the device to the host OS using the following commands (replacing `$slot_info` with the value previously retrieved): ```sh echo 1 >/sys/bus/pci/devices/$slot_info/remove echo 1 >/sys/bus/pci/rescan diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs index 8f85c64777..f08775e4a4 100644 --- a/kernel/mellanox_ethernet/src/command_queue.rs +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -2,7 +2,7 @@ use alloc::vec::Vec; use memory::{PhysicalAddress, MappedPages, create_contiguous_mapping}; -use volatile::{Volatile, ReadOnly}; +use volatile::Volatile; use bit_field::BitField; use zerocopy::*; use byteorder::BigEndian; @@ -11,10 +11,6 @@ use nic_initialization::NIC_MAPPING_FLAGS; use kernel_config::memory::PAGE_SIZE; use core::fmt; -/// Maximum number of entries in the command queue. -const MAX_CMND_QUEUE_ENTRIES: usize = 64; -/// Size of mailboxes, including both control fields and data. -const MAILBOX_SIZE_IN_BYTES: usize = 576; /// Number of bytes in the mailbox that are actually used to pass data. const MAILBOX_DATA_SIZE_IN_BYTES: usize = 512; /// Mailboxes are aligned at 4 KiB, so they are always present at offset 0 in a page. @@ -31,8 +27,8 @@ pub enum CommandTransportType { PCIe = 0x7 << 24 } +/// Return codes written by HW in the delivery status field [CommandQueueEntry::token_signature_status_own] of the command entry. #[derive(Debug)] -/// Return codes written by HW in the delivery status field of the command entry. pub enum CommandDeliveryStatus { Success = 0x0, SignatureErr = 0x1, @@ -44,12 +40,12 @@ pub enum CommandDeliveryStatus { InputLenErr = 0x7, OutputLenErr = 0x8, ReservedNotZero = 0x9, - BadCommandType = 0x10, //Should this be 10 or 16?? + BadCommandType = 0x10, Unknown, } -#[derive(PartialEq, Debug)] /// Command opcode written by SW in opcode field of the input data in the command entry. +#[derive(PartialEq, Debug)] pub enum CommandOpcode { QueryHcaCap = 0x100, QueryAdapter = 0x101, @@ -77,8 +73,8 @@ pub enum CommandOpcode { Unknown } -#[derive(Debug)] /// Command status written by HW in status field of the output data in the command entry. +#[derive(Debug)] pub enum CommandReturnStatus { OK = 0x00, InternalError = 0x01, @@ -100,21 +96,21 @@ pub enum CommandReturnStatus { } /// Possible values of the opcode modifer when the opcode is ManagePages -pub enum ManagePagesOpmod { +pub enum ManagePagesOpMod { AllocationFail = 0, AllocationSuccess = 1, HcaReturnPages = 2 } /// Possible values of the opcode modifer when the opcode is QueryPages -pub enum QueryPagesOpmod { +pub enum QueryPagesOpMod { BootPages = 1, InitPages = 2, RegularPages = 3 } -#[derive(PartialEq)] /// Mailboxes can be used for both input data passed to HW, and output data passed from HW to SW. +#[derive(PartialEq)] enum MailboxType { Input, Output @@ -141,14 +137,13 @@ impl CommandQueue { /// Create a command queue object. /// - /// # Arguments + /// ## Arguments /// * `entries`: physically contiguous memory that is mapped as a slice of command queue entries. /// * `num_cmdq_entries`: number of entries in the queue. pub fn create(entries: BoxRefMut, num_cmdq_entries: usize) -> Result { // initially, all command entries are available - let mut available_entries = Vec::with_capacity(num_cmdq_entries); - for _ in 0..num_cmdq_entries { available_entries.push(true); } + let available_entries = vec![true; num_cmdq_entries]; // start off by pre-allocating one page for input and output mailboxes per entry let mut mailbox_buffers_input = Vec::with_capacity(num_cmdq_entries); @@ -176,10 +171,10 @@ impl CommandQueue { /// At the end of the function, the command is ready to be posted using the doorbell in the initialization segment. /// Returns an error if no entry is available to use. /// - /// # Arguments + /// ## Arguments /// * `opcode`: opcode for command that the driver wants to execute /// * `opmod`: opcode modifer, only applicable for certain commands - /// * `allocated_pages`: physical address of pages that need to be passed to the NIC. Only used in the MANAGE_PAGES command. + /// * `allocated_pages`: physical address of pages that need to be passed to the NIC. Only used in the [`CommandOpcode::ManagePages`] command. pub fn create_command( &mut self, opcode: CommandOpcode, @@ -468,12 +463,12 @@ impl CommandQueue { } } -#[derive(FromBytes, Default)] -#[repr(C)] /// Layout of a command passed to the NIC. /// The fields include control information for the command as well as actual command input and output. /// The first 16 bytes of the actual command input are part of the entry. The remaining data is written in mailboxes. /// Similarly, the first 16 bytes of the command output are part of the entry and remaining data is written in mailboxes. +#[derive(FromBytes, Default)] +#[repr(C)] pub struct CommandQueueEntry { /// Type of transport that carries the command type_of_transport: Volatile>, @@ -516,22 +511,24 @@ const_assert_eq!(core::mem::size_of::(), 64); impl fmt::Debug for CommandQueueEntry { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - write!(f, "CQE:type of transport: {:#X} \n", self.type_of_transport.read().get())?; - write!(f, "CQE:input length: {} \n", self.input_length.read().get())?; - write!(f, "CQE:input_mailbox_ptr_h: {:#X} \n", self.input_mailbox_pointer_h.read().get())?; - write!(f, "CQE:input_mailbox_ptr_l: {:#X} \n", self.input_mailbox_pointer_l.read().get())?; - write!(f, "CQE:command_input_opcode: {:#X} \n", self.command_input_opcode.read().get())?; - write!(f, "CQE:command_input_opmod: {:#X} \n", self.command_input_opmod.read().get())?; - write!(f, "CQE:command_input_inline_data_0: {:#X} \n", self.command_input_inline_data_0.read().get())?; - write!(f, "CQE:command_input_inline_data_1: {:#X} \n", self.command_input_inline_data_1.read().get())?; - write!(f, "CQE:command_output_status: {:#X} \n", self.command_output_status.read().get())?; - write!(f, "CQE:command_output_syndrome: {:#X} \n", self.command_output_syndrome.read().get())?; - write!(f, "CQE:command_output_inline_data_0: {:#X} \n", self.command_output_inline_data_0.read().get())?; - write!(f, "CQE:command_output_inline_data_1: {:#X} \n", self.command_output_inline_data_1.read().get())?; - write!(f, "CQE:output_mailbox_pointer_h: {:#X} \n", self.output_mailbox_pointer_h.read().get())?; - write!(f, "CQE:output_mailbox_pointer_l: {:#X} \n", self.output_mailbox_pointer_l.read().get())?; - write!(f, "CQE:output_length: {} \n", self.output_length.read().get())?; - write!(f, "CQE:token_signature_status_own: {:#X} \n", self.token_signature_status_own.read().get()) + f.debug_struct("CommandQueueEntry") + .field("type of transport", &self.type_of_transport.read().get()) + .field("input length", &self.input_length.read().get()) + .field("input_mailbox_ptr_h", &self.input_mailbox_pointer_h.read().get()) + .field("input_mailbox_ptr_l", &self.input_mailbox_pointer_l.read().get()) + .field("command_input_opcode",&self.command_input_opcode.read().get()) + .field("command_input_opmod",&self.command_input_opmod.read().get()) + .field("command_input_inline_data_0",&self.command_input_inline_data_0.read().get()) + .field("command_input_inline_data_1",&self.command_input_inline_data_1.read().get()) + .field("command_output_status",&self.command_output_status.read().get()) + .field("command_output_syndrome",&self.command_output_syndrome.read().get()) + .field("command_output_inline_data_0",&self.command_output_inline_data_0.read().get()) + .field("command_output_inline_data_1",&self.command_output_inline_data_1.read().get()) + .field("output_mailbox_pointer_h",&self.output_mailbox_pointer_h.read().get()) + .field("output_mailbox_pointer_l",&self.output_mailbox_pointer_l.read().get()) + .field("output_length",&self.output_length.read().get()) + .field("token_signature_status_own",&self.token_signature_status_own.read().get()) + .finish() } } @@ -550,7 +547,7 @@ impl CommandQueueEntry { /// Sets the first 16 bytes of input data that are written inline in the command. /// The valid values for each field are different for every command, and can be taken from Chapter 23 of the PRM. /// - /// # Arguments + /// ## Arguments /// * `opcode`: value identifying which command has to be carried out /// * `opmod`: opcode modifier. If None, field will be set to zero. /// * `command0`: the first 4 bytes of actual command data. If None, field will be set to zero. @@ -688,13 +685,13 @@ impl CommandQueueEntry { } +/// Layout of mailbox used to pass extra input and output command data that doesn't fit into the command entry. #[derive(FromBytes)] #[repr(C)] -/// Layout of mailbox used to pass extra input and output command data that doesn't fit into the command entry. struct CommandInterfaceMailbox { /// Data in the mailbox mailbox_data: Volatile<[u8; 512]>, - _padding: ReadOnly<[u8; 48]>, + _padding: [u8; 48], /// MSBs of pointer to the next mailbox page (if needed). /// If no additional block is needed, the pointer should be 0. next_pointer_h: Volatile>, @@ -723,15 +720,13 @@ impl CommandInterfaceMailbox { impl fmt::Debug for CommandInterfaceMailbox { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - for i in 0..(512/4) { - let data = self.mailbox_data.read(); - write!(f, "mailbox data: {:#X} {:#X} {:#X} {:#X} \n", data[i*4], data[i*4+1], data[i*4+2], data[i*4 +3])?; - } - - write!(f, "next pointer h: {:#X} \n", self.next_pointer_h.read().get())?; - write!(f, "next pointer l: {:#X} \n", self.next_pointer_l.read().get())?; - write!(f, "block number: {:#X} \n", self.block_number.read().get())?; - write!(f, "token ctrl signature: {:#X} \n", self.token_ctrl_signature.read().get()) + f.debug_struct("CommandQueueEntry") + .field("mailbox_data", &self.mailbox_data.read()) + .field("next pointer h", &self.next_pointer_h.read().get()) + .field("next pointer l", &self.next_pointer_l.read().get()) + .field("block number", &self.block_number.read().get()) + .field("token ctrl signature", &self.token_ctrl_signature.read().get()) + .finish() } } diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index e7a1d49ab7..0b803f29d7 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -3,12 +3,13 @@ //! //! The Mellanox ethernet card is referred to as both the NIC (Network Interface Card) and the HCA (Host Channel Adapter). //! -//! All information is taken from the Mellanox Adapters Programmer’s Reference Manual (PRM) [Rev 0.54], unless otherwise specified. +//! All information is taken from the Mellanox Adapters Programmer’s Reference Manual (PRM) [Rev 0.54], unless otherwise specified. +//! While this version of the manual was acquired by directly contacting Nvidia through their support site (``), +//! an older version of the manual can be found at ``. #![no_std] #![feature(slice_pattern)] #![feature(core_intrinsics)] - #![allow(dead_code)] // to suppress warnings for unused functions/methods #[macro_use]extern crate log; #[macro_use] extern crate alloc; @@ -32,11 +33,11 @@ use core::fmt; pub mod command_queue; -#[derive(FromBytes)] -#[repr(C,packed)] /// The initialization segment is located at offset 0 of PCI BAR0. /// It is used in the initialization procedure of the device, /// and it contains the 32-bit command doorbell vector used to inform the HW when a command is ready to be processed. +#[derive(FromBytes)] +#[repr(C,packed)] pub struct InitializationSegment { /// Firmware Revision - Minor fw_rev_minor: ReadOnly>, @@ -91,7 +92,7 @@ impl InitializationSegment { /// Sets the physical address of the command queue within the initialization segment. /// - /// # Arguments + /// ## Arguments /// * `cmdq_physical_addr`: the starting physical address of the command queue, the lower 12 bits of which must be zero. pub fn set_physical_address_of_cmdq(&mut self, cmdq_physical_addr: PhysicalAddress) -> Result<(), &'static str> { if cmdq_physical_addr.value() & 0xFFF != 0 { @@ -111,7 +112,7 @@ impl InitializationSegment { /// Sets a bit in the command doorbell vector to inform HW that the command needs to be executed. /// - /// # Arguments + /// ## Arguments /// * `command bit`: the command entry that needs to be executed. (e.g. bit 0 corresponds to entry at index 0). pub fn post_command(&mut self, command_bit: usize) { let val = self.command_doorbell_vector.read().get(); @@ -121,11 +122,16 @@ impl InitializationSegment { impl fmt::Debug for InitializationSegment { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { - write!(f, "Initialization Segment \n")?; - write!(f, "Firmware: {}.{}.{}, command interface: {} \n", self.fw_rev_major.read().get(), self.fw_rev_minor.read().get(), self.fw_rev_subminor.read().get(), self.cmd_interface_rev.read().get())?; - write!(f, "Command queue address: {:#X} {:#X} \n", self.cmdq_phy_addr_high.read().get(), self.cmdq_phy_addr_low.read().get())?; - write!(f, "Command doorbell vector: {:#X} \n", self.command_doorbell_vector.read().get())?; - write!(f, "Initializing state: {:#X} \n", self.initializing_state.read().get()) + f.debug_struct("InitializationSegment") + .field("Firmware Rev Major", &self.fw_rev_major.read().get()) //, + .field("Firmware Rev Minor",&self.fw_rev_minor.read().get()) + .field("Firmware Rev Subminor",&self.fw_rev_subminor.read().get()) + .field("Command Interface Rev",&self.cmd_interface_rev.read().get()) + .field("Command queue address high", &self.cmdq_phy_addr_high.read().get()) + .field("Command queue address low", &self.cmdq_phy_addr_low.read().get()) + .field("Command doorbell vector", &self.command_doorbell_vector.read().get()) + .field("Initializing state", &self.initializing_state.read().get()) + .finish() } } diff --git a/kernel/mlx5/Cargo.toml b/kernel/mlx5/Cargo.toml index 009b7dcc28..ef47379f34 100644 --- a/kernel/mlx5/Cargo.toml +++ b/kernel/mlx5/Cargo.toml @@ -1,7 +1,7 @@ [package] authors = ["Ramla Ijaz "] name = "mlx5" -description = "Support for the Mellanox connectx-5 NIC and driver" +description = "Driver for the Mellanox ConnectX-5 NIC" version = "0.1.0" build = "../../build.rs" diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index e6924c2722..4395f41ff1 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -32,7 +32,7 @@ use owning_ref::BoxRefMut; use nic_initialization::{NIC_MAPPING_FLAGS, allocate_memory}; use mellanox_ethernet::{ InitializationSegment, - command_queue::{CommandQueueEntry, CommandQueue, CommandOpcode, ManagePagesOpmod, QueryPagesOpmod} + command_queue::{CommandQueueEntry, CommandQueue, CommandOpcode, ManagePagesOpMod, QueryPagesOpMod} }; use kernel_config::memory::PAGE_SIZE; @@ -140,7 +140,7 @@ impl ConnectX5Nic { trace!("SetISSI: {:?}", status); // Query pages for boot - let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpmod::BootPages as u16), None)?; + let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpMod::BootPages as u16), None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); let num_boot_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; @@ -158,7 +158,7 @@ impl ConnectX5Nic { // execute MANAGE_PAGES command to transfer boot pages to device let cmdq_entry = cmdq.create_command( CommandOpcode::ManagePages, - Some(ManagePagesOpmod::AllocationSuccess as u16), + Some(ManagePagesOpMod::AllocationSuccess as u16), Some(boot_pa) )?; init_segment.post_command(cmdq_entry); @@ -166,7 +166,7 @@ impl ConnectX5Nic { trace!("Manage pages boot status: {:?}", status); // Query pages for init - let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpmod::InitPages as u16), None)?; + let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpMod::InitPages as u16), None)?; init_segment.post_command(cmdq_entry); let status = cmdq.wait_for_command_completion(cmdq_entry); let num_init_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; @@ -185,7 +185,7 @@ impl ConnectX5Nic { // execute MANAGE_PAGES command to transfer init pages to device let cmdq_entry = cmdq.create_command( CommandOpcode::ManagePages, - Some(ManagePagesOpmod::AllocationSuccess as u16), + Some(ManagePagesOpMod::AllocationSuccess as u16), Some(init_pa) )?; init_segment.post_command(cmdq_entry); From 528a3ef60e72a2b816a602f2d4198443d0287a38 Mon Sep 17 00:00:00 2001 From: Ramla-I Date: Mon, 19 Jul 2021 15:49:06 -0500 Subject: [PATCH 17/31] pr fixes --- kernel/mellanox_ethernet/src/command_queue.rs | 281 ++++++++++-------- kernel/mellanox_ethernet/src/lib.rs | 24 +- kernel/mlx5/src/lib.rs | 2 +- 3 files changed, 178 insertions(+), 129 deletions(-) diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs index f08775e4a4..787cb30bed 100644 --- a/kernel/mellanox_ethernet/src/command_queue.rs +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -11,6 +11,9 @@ use nic_initialization::NIC_MAPPING_FLAGS; use kernel_config::memory::PAGE_SIZE; use core::fmt; +/// Size of mailboxes, including both control fields and data. +#[allow(dead_code)] +const MAILBOX_SIZE_IN_BYTES: usize = 576; /// Number of bytes in the mailbox that are actually used to pass data. const MAILBOX_DATA_SIZE_IN_BYTES: usize = 512; /// Mailboxes are aligned at 4 KiB, so they are always present at offset 0 in a page. @@ -27,7 +30,8 @@ pub enum CommandTransportType { PCIe = 0x7 << 24 } -/// Return codes written by HW in the delivery status field [CommandQueueEntry::token_signature_status_own] of the command entry. +/// Return codes written by HW in the delivery status field of the command entry. +/// See [`CommandQueueEntry::token_signature_status_own`]. #[derive(Debug)] pub enum CommandDeliveryStatus { Success = 0x0, @@ -44,7 +48,27 @@ pub enum CommandDeliveryStatus { Unknown, } +impl From for CommandDeliveryStatus { + fn from(status: u32) -> Self { + match status { + 0 => Self::Success, + 1 => Self::SignatureErr, + 2 => Self::TokenErr, + 3 => Self::BadBlockNumber, + 4 => Self::BadOutputPointer, + 5 => Self::BadInputPointer, + 6 => Self::InternalErr, + 7 => Self::InputLenErr, + 8 => Self::OutputLenErr, + 9 => Self::ReservedNotZero, + 10 => Self::BadCommandType, + _ => Self::Unknown + } + } +} + /// Command opcode written by SW in opcode field of the input data in the command entry. +/// See [`CommandQueueEntry::command_input_opcode`]. #[derive(PartialEq, Debug)] pub enum CommandOpcode { QueryHcaCap = 0x100, @@ -62,18 +86,95 @@ pub enum CommandOpcode { CreateCq = 0x400, QueryVportState = 0x751, QueryNicVportContext = 0x754, - AllocUar = 0x802, AllocPd = 0x800, + AllocUar = 0x802, AllocTransportDomain = 0x816, - CreateTis = 0x912, CreateSq = 0x904, ModifySq = 0x905, CreateRq = 0x908, ModifyRq = 0x909, + CreateTis = 0x912, Unknown } +impl CommandOpcode { + fn input_bytes(&self, num_pages: Option) -> Result { + let len = match self { + Self::InitHca => 12, + Self::EnableHca => 12, + Self::QueryPages => 12, + Self::ManagePages => { + let num_pages = num_pages.ok_or("No pages passed to the manage pages command")? as u32; + 0x10 + num_pages * SIZE_PADDR_IN_BYTES as u32 + } + Self::QueryIssi => 8, + Self::SetIssi => 12, + Self::QuerySpecialContexts => 8, + Self::QueryVportState => 12, + Self::AllocUar => 8, + Self::AllocPd => 8, + Self::AllocTransportDomain => 8, + _ => { + return Err("Input length has not been set for this opcode."); + } + }; + Ok(len) + } + + fn output_bytes(&self) -> Result { + let len = match self { + Self::InitHca => 8, + Self::EnableHca => 8, + Self::QueryPages => 16, + Self::ManagePages => 16, + Self::QueryIssi => 112, + Self::SetIssi => 8, + Self::QuerySpecialContexts => 12, + Self::QueryVportState => 16, + Self::AllocUar => 12, + Self::AllocPd => 12, + Self::AllocTransportDomain => 12, + _ => { + return Err("Output length has not been set for this opcode."); + } + }; + Ok(len) + } +} + +impl From for CommandOpcode { + fn from(opcode: u32) -> Self { + match opcode { + 0x100 => Self::QueryHcaCap, + 0x101 => Self::QueryAdapter, + 0x102 => Self::InitHca, + 0x103 => Self::TeardownHca, + 0x104 => Self::EnableHca, + 0x105 => Self::DisableHca, + 0x107 => Self::QueryPages, + 0x108 => Self::ManagePages, + 0x10A => Self::QueryIssi, + 0x10B => Self::SetIssi, + 0x203 => Self::QuerySpecialContexts, + 0x301 => Self::CreateEq, + 0x400 => Self::CreateCq, + 0x751 => Self::QueryVportState, + 0x754 => Self::QueryNicVportContext, + 0x800 => Self::AllocPd, + 0x802 => Self::AllocUar, + 0x816 => Self::AllocTransportDomain, + 0x904 => Self::CreateSq, + 0x905 => Self::ModifySq, + 0x908 => Self::CreateRq, + 0x909 => Self::ModifyRq, + 0x912 => Self::CreateTis, + _ => Self::Unknown + } + } +} + /// Command status written by HW in status field of the output data in the command entry. +/// See [`CommandQueueEntry::command_output_status`]. #[derive(Debug)] pub enum CommandReturnStatus { OK = 0x00, @@ -95,14 +196,37 @@ pub enum CommandReturnStatus { Unknown } -/// Possible values of the opcode modifer when the opcode is ManagePages +impl From for CommandReturnStatus { + fn from(status: u8) -> Self { + match status{ + 0x0 => Self::OK, + 0x1 => Self::InternalError, + 0x2 => Self::BadOp, + 0x3 => Self::BadParam, + 0x4 => Self::BadSysState, + 0x5 => Self::BadResource, + 0x6 => Self::ResourceBusy, + 0x8 => Self::ExceedLim, + 0x9 => Self::BadResState, + 0xA => Self::BadIndex, + 0xF => Self::NoResources, + 0x50 => Self::BadInputLen, + 0x51 => Self::BadOutputLen, + 0x10 => Self::BadResourceState, + 0x30 => Self::BadPkt, + 0x40 => Self::BadSize, + _ => Self::Unknown + } + } +} +/// Possible values of the opcode modifer when the opcode is [`CommandOpcode::ManagePages`]. pub enum ManagePagesOpMod { AllocationFail = 0, AllocationSuccess = 1, HcaReturnPages = 2 } -/// Possible values of the opcode modifer when the opcode is QueryPages +/// Possible values of the opcode modifer when the opcode is [`CommandOpcode::QueryPages`]. pub enum QueryPagesOpMod { BootPages = 1, InitPages = 2, @@ -116,6 +240,8 @@ enum MailboxType { Output } + + /// A buffer of fixed-size entries that is used to pass commands to the HCA. /// It resides in a physically contiguous 4 KiB memory chunk. /// (Section 8.24.1: HCA Command Queue) @@ -172,7 +298,7 @@ impl CommandQueue { /// Returns an error if no entry is available to use. /// /// ## Arguments - /// * `opcode`: opcode for command that the driver wants to execute + /// * `opcode`: [`CommandOpcode`] for the command that the driver wants to execute /// * `opmod`: opcode modifer, only applicable for certain commands /// * `allocated_pages`: physical address of pages that need to be passed to the NIC. Only used in the [`CommandOpcode::ManagePages`] command. pub fn create_command( @@ -197,13 +323,13 @@ impl CommandQueue { match opcode { CommandOpcode::EnableHca => { - cmdq_entry.set_input_length_in_bytes(12); - cmdq_entry.set_output_length_in_bytes(8); + cmdq_entry.set_input_length_in_bytes(opcode.input_bytes(None)?); + cmdq_entry.set_output_length_in_bytes(opcode.output_bytes()?); cmdq_entry.set_input_inline_data(opcode, opmod, None, None); } CommandOpcode::QueryIssi => { - cmdq_entry.set_input_length_in_bytes(8); - cmdq_entry.set_output_length_in_bytes(112); + cmdq_entry.set_input_length_in_bytes(opcode.input_bytes(None)?); + cmdq_entry.set_output_length_in_bytes(opcode.output_bytes()?); cmdq_entry.set_input_inline_data(opcode, opmod, None, None); self.init_query_issi_output_mailbox_buffers(entry_num)?; @@ -211,29 +337,29 @@ impl CommandQueue { } CommandOpcode::SetIssi => { warn!("setting to 1 by default, could be wrong"); - cmdq_entry.set_input_length_in_bytes(12); - cmdq_entry.set_output_length_in_bytes(8); + cmdq_entry.set_input_length_in_bytes(opcode.input_bytes(None)?); + cmdq_entry.set_output_length_in_bytes(opcode.output_bytes()?); cmdq_entry.set_input_inline_data(opcode, opmod, Some(1), None); } CommandOpcode::InitHca => { - cmdq_entry.set_input_length_in_bytes(12); - cmdq_entry.set_output_length_in_bytes(8); + cmdq_entry.set_input_length_in_bytes(opcode.input_bytes(None)?); + cmdq_entry.set_output_length_in_bytes(opcode.output_bytes()?); cmdq_entry.set_input_inline_data(opcode, opmod, None, None); } CommandOpcode::QuerySpecialContexts => { - cmdq_entry.set_input_length_in_bytes(8); - cmdq_entry.set_output_length_in_bytes(16); + cmdq_entry.set_input_length_in_bytes(opcode.input_bytes(None)?); + cmdq_entry.set_output_length_in_bytes(opcode.output_bytes()?); cmdq_entry.set_input_inline_data(opcode, opmod, None, None); } CommandOpcode::QueryPages => { - cmdq_entry.set_input_length_in_bytes(12); - cmdq_entry.set_output_length_in_bytes(16); + cmdq_entry.set_input_length_in_bytes(opcode.input_bytes(None)?); + cmdq_entry.set_output_length_in_bytes(opcode.output_bytes()?); cmdq_entry.set_input_inline_data(opcode, opmod, None, None); } CommandOpcode::ManagePages => { let pages_pa = allocated_pages.ok_or("No pages were passed to the manage pages command")?; - cmdq_entry.set_input_length_in_bytes(0x10 + pages_pa.len() as u32 * SIZE_PADDR_IN_BYTES as u32); - cmdq_entry.set_output_length_in_bytes(16); + cmdq_entry.set_input_length_in_bytes(opcode.input_bytes(Some(pages_pa.len()))?); + cmdq_entry.set_output_length_in_bytes(opcode.output_bytes()?); cmdq_entry.set_input_inline_data( opcode, opmod, @@ -245,28 +371,23 @@ impl CommandQueue { self.set_mailbox_pointer_in_cmd_entry(&mut cmdq_entry, entry_num, MailboxType::Input); } CommandOpcode::AllocUar => { - cmdq_entry.set_input_length_in_bytes(8); - cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_length_in_bytes(opcode.input_bytes(None)?); + cmdq_entry.set_output_length_in_bytes(opcode.output_bytes()?); cmdq_entry.set_input_inline_data(opcode, opmod, None, None); }, CommandOpcode::QueryVportState => { // only accesses your own vport - cmdq_entry.set_input_length_in_bytes(12); - cmdq_entry.set_output_length_in_bytes(16); + cmdq_entry.set_input_length_in_bytes(opcode.input_bytes(None)?); + cmdq_entry.set_output_length_in_bytes(opcode.output_bytes()?); cmdq_entry.set_input_inline_data(opcode, opmod, None, None); }, CommandOpcode::AllocPd => { - cmdq_entry.set_input_length_in_bytes(8); - cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_length_in_bytes(opcode.input_bytes(None)?); + cmdq_entry.set_output_length_in_bytes(opcode.output_bytes()?); cmdq_entry.set_input_inline_data(opcode, opmod, None, None); }, CommandOpcode::AllocTransportDomain => { - cmdq_entry.set_input_length_in_bytes(8); - cmdq_entry.set_output_length_in_bytes(12); - cmdq_entry.set_input_inline_data(opcode, opmod, None, None); - }, - CommandOpcode::QuerySpecialContexts => { - cmdq_entry.set_input_length_in_bytes(8); - cmdq_entry.set_output_length_in_bytes(12); + cmdq_entry.set_input_length_in_bytes(opcode.input_bytes(None)?); + cmdq_entry.set_output_length_in_bytes(opcode.output_bytes()?); cmdq_entry.set_input_inline_data(opcode, opmod, None, None); }, _=> { @@ -298,14 +419,14 @@ impl CommandQueue { cmdq_entry.input_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); } - /// Initialize output mailboxes for the QUERY_ISSI command. + /// Initialize output mailboxes for the [`CommandOpcode::QueryIssi`] command. fn init_query_issi_output_mailbox_buffers(&mut self, entry_num: usize) -> Result<(), &'static str> { const NUM_MAILBOXES_QUERY_ISSI: usize = 1; self.initialize_mailboxes(entry_num, NUM_MAILBOXES_QUERY_ISSI, MailboxType::Output)?; Ok(()) } - /// Initialize input mailboxes for the MANAGE_PAGES command. + /// Initialize input mailboxes for the [`CommandOpcode::ManagePages`] command. /// We write that physical address of the pages passed to the NIC to the mailbox data field. fn init_manage_pages_input_mailbox_buffers(&mut self, entry_num: usize, mut pages: Vec) -> Result<(), &'static str> { @@ -344,7 +465,7 @@ impl CommandQueue { (self.entries[entry_num].get_delivery_status(), self.entries[entry_num].get_return_status()) } - /// Get the current ISSI version and the supported ISSI versions, which is the output of the QUERY_ISSI command. + /// Get the current ISSI version and the supported ISSI versions, which is the output of the [`CommandOpcode::QueryIssi`] command. pub fn get_query_issi_command_output(&self, entry_num: usize) -> Result<(u16, u8), &'static str> { self.check_command_output_validity(entry_num, CommandOpcode::QueryIssi)?; @@ -357,28 +478,28 @@ impl CommandQueue { Ok((current_issi as u16, supported_issi as u8)) } - /// Get the number of pages requested by the NIC, which is the output of the QUERY_PAGES command. + /// Get the number of pages requested by the NIC, which is the output of the [`CommandOpcode::QueryPages`] command. pub fn get_query_pages_command_output(&self, entry_num: usize) -> Result { self.check_command_output_validity(entry_num, CommandOpcode::QueryPages)?; let (_status, _syndrome, _function_id, num_pages) = self.entries[entry_num].get_output_inline_data(); Ok(num_pages) } - /// Get the User Access Region (UAR) number, which is the output of the ALLOC_UAR command. + /// Get the User Access Region (UAR) number, which is the output of the [`CommandOpcode::AllocUar`] command. pub fn get_uar(&self, entry_num: usize) -> Result { self.check_command_output_validity(entry_num, CommandOpcode::AllocUar)?; let (_status, _syndrome, uar, _reserved) = self.entries[entry_num].get_output_inline_data(); Ok(uar & 0xFF_FFFF) } - /// Get the protection domain number, which is the output of the ALLOC_PD command. + /// Get the protection domain number, which is the output of the [`CommandOpcode::AllocPd`] command. pub fn get_protection_domain(&self, entry_num: usize) -> Result { self.check_command_output_validity(entry_num, CommandOpcode::AllocPd)?; let (_status, _syndrome, pd, _reserved) = self.entries[entry_num].get_output_inline_data(); Ok(pd & 0xFF_FFFF) } - /// Get the transport domain number, which is the output of the ALLOC_TRANSPORT_DOMAIN command. + /// Get the transport domain number, which is the output of the [`CommandOpcode::AllocTransportDomain`] command. pub fn get_transport_domain(&self, entry_num: usize) -> Result { self.check_command_output_validity(entry_num, CommandOpcode::AllocTransportDomain)?; let (_status, _syndrome, td, _reserved) = self.entries[entry_num].get_output_inline_data(); @@ -386,7 +507,7 @@ impl CommandQueue { } /// Get the value of the reserved Lkey for Base Memory Management Extension, which is used when we are using physical addresses. - /// It is taken as the output of the QUERY_SPECIAL_CONTEXTS command. + /// It is taken as the output of the [`CommandOpcode::QuerySpecialContexts`] command. pub fn get_reserved_lkey(&self, entry_num: usize) -> Result { self.check_command_output_validity(entry_num, CommandOpcode::QuerySpecialContexts)?; let (_status, _syndrome, _dump_fill_mkey, resd_lkey) = self.entries[entry_num].get_output_inline_data(); @@ -561,19 +682,7 @@ impl CommandQueueEntry { /// Returns the value written to the input opcode field of the command fn get_command_opcode(&self) -> CommandOpcode { - match self.command_input_opcode.read().get() >> 16 { - 0x100 => {CommandOpcode::QueryHcaCap}, - 0x101 => {CommandOpcode::QueryAdapter}, - 0x102 => {CommandOpcode::InitHca}, - 0x103 => {CommandOpcode::TeardownHca}, - 0x104 => {CommandOpcode::EnableHca}, - 0x105 => {CommandOpcode::DisableHca}, - 0x107 => {CommandOpcode::QueryPages}, - 0x108 => {CommandOpcode::ManagePages}, - 0x10A => {CommandOpcode::QueryIssi}, - 0x10B => {CommandOpcode::SetIssi}, - _ => {CommandOpcode::Unknown} - } + (self.command_input_opcode.read().get() >> 16).into() } /// Returns the first 16 bytes of output data that are written inline in the command. @@ -603,32 +712,7 @@ impl CommandQueueEntry { /// Returns the status of command delivery. /// This only informs us if the command was delivered to the NIC successfully, not if it was completed successfully. pub fn get_delivery_status(&self) -> CommandDeliveryStatus { - let status = self.token_signature_status_own.read().get() & 0xFE; - if status == 0 { - CommandDeliveryStatus::Success - } else if status == 1 { - CommandDeliveryStatus::SignatureErr - } else if status == 2 { - CommandDeliveryStatus::TokenErr - } else if status == 3 { - CommandDeliveryStatus::BadBlockNumber - } else if status == 4 { - CommandDeliveryStatus::BadOutputPointer - } else if status == 5 { - CommandDeliveryStatus::BadInputPointer - } else if status == 6 { - CommandDeliveryStatus::InternalErr - } else if status == 7 { - CommandDeliveryStatus::InputLenErr - } else if status == 8 { - CommandDeliveryStatus::OutputLenErr - } else if status == 9 { - CommandDeliveryStatus::ReservedNotZero - } else if status == 10 { - CommandDeliveryStatus::BadCommandType - } else { - CommandDeliveryStatus::Unknown - } + (self.token_signature_status_own.read().get() & 0xFE).into() } /// Sets the ownership bit so that HW can take control of the command entry @@ -645,42 +729,7 @@ impl CommandQueueEntry { /// Returns the status of command execution. pub fn get_return_status(&self) -> CommandReturnStatus { let (status, _syndrome, _, _) = self.get_output_inline_data(); - - if status == 0x0 { - CommandReturnStatus::OK - } else if status == 0x1 { - CommandReturnStatus::InternalError - } else if status == 0x2 { - CommandReturnStatus::BadOp - } else if status == 0x3 { - CommandReturnStatus::BadParam - } else if status == 0x4 { - CommandReturnStatus::BadSysState - } else if status == 0x5 { - CommandReturnStatus::BadResource - } else if status == 0x6 { - CommandReturnStatus::ResourceBusy - } else if status == 0x8 { - CommandReturnStatus::ExceedLim - } else if status == 0x9 { - CommandReturnStatus::BadResState - } else if status == 0xA { - CommandReturnStatus::BadIndex - } else if status == 0xF { - CommandReturnStatus::NoResources - } else if status == 0x50 { - CommandReturnStatus::BadInputLen - } else if status == 0x51 { - CommandReturnStatus::BadOutputLen - } else if status == 0x10 { - CommandReturnStatus::BadResourceState - } else if status == 0x30 { - CommandReturnStatus::BadPkt - } else if status == 0x40 { - CommandReturnStatus::BadSize - } else { - CommandReturnStatus::Unknown - } + status.into() } } diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index 0b803f29d7..7bf5acf411 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -37,7 +37,7 @@ pub mod command_queue; /// It is used in the initialization procedure of the device, /// and it contains the 32-bit command doorbell vector used to inform the HW when a command is ready to be processed. #[derive(FromBytes)] -#[repr(C,packed)] +#[repr(packed)] pub struct InitializationSegment { /// Firmware Revision - Minor fw_rev_minor: ReadOnly>, @@ -55,27 +55,27 @@ pub struct InitializationSegment { /// Bit per command in the cmdq. /// When the bit is set, that command entry in the queue is moved to HW ownership. command_doorbell_vector: Volatile>, - _padding2: [u8; 390], + _padding2: [u8; 484], /// If bit 31 is set, the device is still initializing and driver should not post commands initializing_state: ReadOnly>, /// Advanced debug information. - health_buffer: Volatile<[u8; 64]>, + _health_buffer: Volatile<[u8; 64]>, /// The offset in bytes, inside the initialization segment, where the NODNIC registers can be found. - no_dram_nic_offset: ReadOnly>, + _no_dram_nic_offset: ReadOnly>, _padding3: [u8; 3516], /// MSBs of the current internal timer value - internal_timer_h: ReadOnly>, + _internal_timer_h: ReadOnly>, /// LSBs of the current internal timer value - internal_timer_l: ReadOnly>, + _internal_timer_l: ReadOnly>, _padding4: [u8; 8], /// Advanced debug information - health_counter: ReadOnly>, + _health_counter: ReadOnly>, _padding5: [u8; 44], - real_time: ReadOnly>, + _real_time: ReadOnly>, _padding6: [u8; 12228], } -// const_assert_eq!(core::mem::size_of::(), 16400); +const_assert_eq!(core::mem::size_of::(), 16400); impl InitializationSegment { /// Returns the maximum number of entries that can be in the command queue @@ -110,7 +110,7 @@ impl InitializationSegment { self.initializing_state.read().get().get_bit(31) } - /// Sets a bit in the command doorbell vector to inform HW that the command needs to be executed. + /// Sets a bit in the [`InitializationSegment::command_doorbell_vector`] to inform HW that the command needs to be executed. /// /// ## Arguments /// * `command bit`: the command entry that needs to be executed. (e.g. bit 0 corresponds to entry at index 0). @@ -123,7 +123,7 @@ impl InitializationSegment { impl fmt::Debug for InitializationSegment { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.debug_struct("InitializationSegment") - .field("Firmware Rev Major", &self.fw_rev_major.read().get()) //, + .field("Firmware Rev Major", &self.fw_rev_major.read().get()) .field("Firmware Rev Minor",&self.fw_rev_minor.read().get()) .field("Firmware Rev Subminor",&self.fw_rev_subminor.read().get()) .field("Command Interface Rev",&self.cmd_interface_rev.read().get()) @@ -138,7 +138,7 @@ impl fmt::Debug for InitializationSegment { /// The possible values of the initialization state of the device as taken from the intialization segment. pub enum InitializingState { NotAllowed = 0, - WaitingPermetion = 1, // Is this a typo in the PRM? + WaitingPermetion = 1, WaitingResources = 2, Abort = 3 } diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index 4395f41ff1..637186e1be 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -7,7 +7,6 @@ //! unless otherwise specified. #![no_std] -#![allow(dead_code)] // to suppress warnings for unused functions/methods #[macro_use] extern crate log; extern crate alloc; @@ -52,6 +51,7 @@ pub fn get_mlx5_nic() -> Option<&'static MutexIrqSafe> { } /// Struct representing a ConnectX-5 network interface card. +#[allow(dead_code)] pub struct ConnectX5Nic { /// Initialization segment base address mem_base: PhysicalAddress, From 1f06fac6746b83c640b8cf77730196d4d01398a5 Mon Sep 17 00:00:00 2001 From: Ramla-I Date: Fri, 23 Jul 2021 11:40:50 -0500 Subject: [PATCH 18/31] doc changes --- kernel/mellanox_ethernet/src/command_queue.rs | 3 ++- kernel/mellanox_ethernet/src/lib.rs | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs index a059f4d7f3..2dfaf614e8 100644 --- a/kernel/mellanox_ethernet/src/command_queue.rs +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -30,6 +30,7 @@ pub enum CommandTransportType { PCIe = 0x7 << 24 } +/// Possible reasons for failure when executing a command pub enum CommandQueueError { /// All command entries are currently being used NoCommandEntryAvailable, @@ -41,7 +42,7 @@ pub enum CommandQueueError { IncorrectCommandOpcode, /// Trying to access the command entry before HW is done processing it CommandNotCompleted, - /// Offset in a page is too large for mapping as a mailbox + /// Offset in a page is too large to map a [`CommandInterfaceMailbox`] to that offset InvalidMailboxOffset, /// A call to create a [`MappedPages`] failed PageAllocationFailed, diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index 7bf5acf411..60ba5c92fa 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -4,8 +4,8 @@ //! The Mellanox ethernet card is referred to as both the NIC (Network Interface Card) and the HCA (Host Channel Adapter). //! //! All information is taken from the Mellanox Adapters Programmer’s Reference Manual (PRM) [Rev 0.54], unless otherwise specified. -//! While this version of the manual was acquired by directly contacting Nvidia through their support site (``), -//! an older version of the manual can be found at ``. +//! While this version of the manual was acquired by directly contacting Nvidia through their support site (), +//! an older version of the manual can be found at . #![no_std] #![feature(slice_pattern)] From 13140ba389204e783964baf2b986bcf833f90063 Mon Sep 17 00:00:00 2001 From: Ramla-I Date: Fri, 23 Jul 2021 12:32:13 -0500 Subject: [PATCH 19/31] used num_enum to derive from --- Cargo.lock | 33 ++++ kernel/mellanox_ethernet/Cargo.toml | 4 + kernel/mellanox_ethernet/src/command_queue.rs | 181 ++++++++++-------- kernel/mellanox_ethernet/src/lib.rs | 1 + kernel/mlx5/src/lib.rs | 16 +- 5 files changed, 143 insertions(+), 92 deletions(-) diff --git a/Cargo.lock b/Cargo.lock index 0c15b1d598..7f8dafe58a 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -561,6 +561,17 @@ dependencies = [ "terminal_print", ] +[[package]] +name = "derivative" +version = "2.2.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "fcc3dd5e9e9c0b295d6e1e4d811fb6f157d5ffd784b8d202fc62eac8035a770b" +dependencies = [ + "proc-macro2", + "quote", + "syn", +] + [[package]] name = "derive_more" version = "0.99.14" @@ -1396,6 +1407,7 @@ dependencies = [ "log", "memory", "nic_initialization", + "num_enum", "owning_ref", "static_assertions", "volatile", @@ -1751,6 +1763,27 @@ dependencies = [ "terminal_print", ] +[[package]] +name = "num_enum" +version = "0.5.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "e5adf0198d427ee515335639f275e806ca01acf9f07d7cf14bb36a10532a6169" +dependencies = [ + "derivative", + "num_enum_derive", +] + +[[package]] +name = "num_enum_derive" +version = "0.5.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "b1def5a3f69d4707d8a040b12785b98029a39e8c610ae685c7f6265669767482" +dependencies = [ + "proc-macro2", + "quote", + "syn", +] + [[package]] name = "opaque-debug" version = "0.2.1" diff --git a/kernel/mellanox_ethernet/Cargo.toml b/kernel/mellanox_ethernet/Cargo.toml index f91730446f..b9ca326431 100644 --- a/kernel/mellanox_ethernet/Cargo.toml +++ b/kernel/mellanox_ethernet/Cargo.toml @@ -14,6 +14,10 @@ owning_ref = { git = "https://github.com/theseus-os/owning-ref-rs" } byteorder = { version = "1.4.3", default-features = false } libm = "0.2.1" +[dependencies.num_enum] +version = "0.5.2" +default-features = false + [dependencies.memory] path = "../memory" diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs index 2dfaf614e8..6d6ec8e875 100644 --- a/kernel/mellanox_ethernet/src/command_queue.rs +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -10,6 +10,8 @@ use owning_ref:: BoxRefMut; use nic_initialization::NIC_MAPPING_FLAGS; use kernel_config::memory::PAGE_SIZE; use core::fmt; +use num_enum::TryFromPrimitive; +use core::convert::TryFrom; /// Size of mailboxes, including both control fields and data. #[allow(dead_code)] @@ -40,6 +42,10 @@ pub enum CommandQueueError { MissingInput, /// Opcode value in the command entry is not what was expected IncorrectCommandOpcode, + /// Delivery status value in the command entry is not what was expected + InvalidCommandDeliveryStatus, + /// Return status value in the command entry is not what was expected + InvalidCommandReturnStatus, /// Trying to access the command entry before HW is done processing it CommandNotCompleted, /// Offset in a page is too large to map a [`CommandInterfaceMailbox`] to that offset @@ -59,6 +65,8 @@ impl From for &'static str { CommandQueueError::MissingInputPages => "No pages were passed to the command", CommandQueueError::MissingInput => "An input was not passed to a command that required it", CommandQueueError::IncorrectCommandOpcode => "Incorrect command opcode", + CommandQueueError::InvalidCommandDeliveryStatus => "Invalid command delivery status", + CommandQueueError::InvalidCommandReturnStatus => "Invalid command return status", CommandQueueError::CommandNotCompleted => "Command not complete yet", CommandQueueError::InvalidMailboxOffset => "Invalid offset for mailbox in a page", CommandQueueError::PageAllocationFailed => "Failed to allocate MappedPages", @@ -71,7 +79,8 @@ impl From for &'static str { /// Return codes written by HW in the delivery status field of the command entry. /// See [`CommandQueueEntry::token_signature_status_own`]. -#[derive(Debug)] +#[derive(Debug, TryFromPrimitive)] +#[repr(u32)] pub enum CommandDeliveryStatus { Success = 0x0, SignatureErr = 0x1, @@ -87,28 +96,29 @@ pub enum CommandDeliveryStatus { Unknown, } -impl From for CommandDeliveryStatus { - fn from(status: u32) -> Self { - match status { - 0 => Self::Success, - 1 => Self::SignatureErr, - 2 => Self::TokenErr, - 3 => Self::BadBlockNumber, - 4 => Self::BadOutputPointer, - 5 => Self::BadInputPointer, - 6 => Self::InternalErr, - 7 => Self::InputLenErr, - 8 => Self::OutputLenErr, - 9 => Self::ReservedNotZero, - 10 => Self::BadCommandType, - _ => Self::Unknown - } - } -} +// impl From for CommandDeliveryStatus { +// fn from(status: u32) -> Self { +// match status { +// 0 => Self::Success, +// 1 => Self::SignatureErr, +// 2 => Self::TokenErr, +// 3 => Self::BadBlockNumber, +// 4 => Self::BadOutputPointer, +// 5 => Self::BadInputPointer, +// 6 => Self::InternalErr, +// 7 => Self::InputLenErr, +// 8 => Self::OutputLenErr, +// 9 => Self::ReservedNotZero, +// 10 => Self::BadCommandType, +// _ => Self::Unknown +// } +// } +// } /// Command opcode written by SW in opcode field of the input data in the command entry. /// See [`CommandQueueEntry::command_input_opcode`]. -#[derive(PartialEq, Debug)] +#[derive(PartialEq, Debug, TryFromPrimitive)] +#[repr(u32)] pub enum CommandOpcode { QueryHcaCap = 0x100, QueryAdapter = 0x101, @@ -181,40 +191,41 @@ impl CommandOpcode { } } -impl From for CommandOpcode { - fn from(opcode: u32) -> Self { - match opcode { - 0x100 => Self::QueryHcaCap, - 0x101 => Self::QueryAdapter, - 0x102 => Self::InitHca, - 0x103 => Self::TeardownHca, - 0x104 => Self::EnableHca, - 0x105 => Self::DisableHca, - 0x107 => Self::QueryPages, - 0x108 => Self::ManagePages, - 0x10A => Self::QueryIssi, - 0x10B => Self::SetIssi, - 0x203 => Self::QuerySpecialContexts, - 0x301 => Self::CreateEq, - 0x400 => Self::CreateCq, - 0x751 => Self::QueryVportState, - 0x754 => Self::QueryNicVportContext, - 0x800 => Self::AllocPd, - 0x802 => Self::AllocUar, - 0x816 => Self::AllocTransportDomain, - 0x904 => Self::CreateSq, - 0x905 => Self::ModifySq, - 0x908 => Self::CreateRq, - 0x909 => Self::ModifyRq, - 0x912 => Self::CreateTis, - _ => Self::Unknown - } - } -} +// impl From for CommandOpcode { +// fn from(opcode: u32) -> Self { +// match opcode { +// 0x100 => Self::QueryHcaCap, +// 0x101 => Self::QueryAdapter, +// 0x102 => Self::InitHca, +// 0x103 => Self::TeardownHca, +// 0x104 => Self::EnableHca, +// 0x105 => Self::DisableHca, +// 0x107 => Self::QueryPages, +// 0x108 => Self::ManagePages, +// 0x10A => Self::QueryIssi, +// 0x10B => Self::SetIssi, +// 0x203 => Self::QuerySpecialContexts, +// 0x301 => Self::CreateEq, +// 0x400 => Self::CreateCq, +// 0x751 => Self::QueryVportState, +// 0x754 => Self::QueryNicVportContext, +// 0x800 => Self::AllocPd, +// 0x802 => Self::AllocUar, +// 0x816 => Self::AllocTransportDomain, +// 0x904 => Self::CreateSq, +// 0x905 => Self::ModifySq, +// 0x908 => Self::CreateRq, +// 0x909 => Self::ModifyRq, +// 0x912 => Self::CreateTis, +// _ => Self::Unknown +// } +// } +// } /// Command status written by HW in status field of the output data in the command entry. /// See [`CommandQueueEntry::command_output_status`]. -#[derive(Debug)] +#[derive(Debug, TryFromPrimitive)] +#[repr(u8)] pub enum CommandReturnStatus { OK = 0x00, InternalError = 0x01, @@ -235,29 +246,30 @@ pub enum CommandReturnStatus { Unknown } -impl From for CommandReturnStatus { - fn from(status: u8) -> Self { - match status{ - 0x0 => Self::OK, - 0x1 => Self::InternalError, - 0x2 => Self::BadOp, - 0x3 => Self::BadParam, - 0x4 => Self::BadSysState, - 0x5 => Self::BadResource, - 0x6 => Self::ResourceBusy, - 0x8 => Self::ExceedLim, - 0x9 => Self::BadResState, - 0xA => Self::BadIndex, - 0xF => Self::NoResources, - 0x50 => Self::BadInputLen, - 0x51 => Self::BadOutputLen, - 0x10 => Self::BadResourceState, - 0x30 => Self::BadPkt, - 0x40 => Self::BadSize, - _ => Self::Unknown - } - } -} +// impl From for CommandReturnStatus { +// fn from(status: u8) -> Self { +// match status{ +// 0x0 => Self::OK, +// 0x1 => Self::InternalError, +// 0x2 => Self::BadOp, +// 0x3 => Self::BadParam, +// 0x4 => Self::BadSysState, +// 0x5 => Self::BadResource, +// 0x6 => Self::ResourceBusy, +// 0x8 => Self::ExceedLim, +// 0x9 => Self::BadResState, +// 0xA => Self::BadIndex, +// 0xF => Self::NoResources, +// 0x50 => Self::BadInputLen, +// 0x51 => Self::BadOutputLen, +// 0x10 => Self::BadResourceState, +// 0x30 => Self::BadPkt, +// 0x40 => Self::BadSize, +// _ => Self::Unknown +// } +// } +// } + /// Possible values of the opcode modifer when the opcode is [`CommandOpcode::ManagePages`]. pub enum ManagePagesOpMod { AllocationFail = 0, @@ -499,10 +511,10 @@ impl CommandQueue { } /// Waits for ownership bit to be cleared, and then returns the command delivery status and the command return status. - pub fn wait_for_command_completion(&mut self, entry_num: usize) -> (CommandDeliveryStatus, CommandReturnStatus) { + pub fn wait_for_command_completion(&mut self, entry_num: usize) -> Result<(CommandDeliveryStatus, CommandReturnStatus), CommandQueueError> { while self.entries[entry_num].owned_by_hw() {} self.available_entries[entry_num] = true; - (self.entries[entry_num].get_delivery_status(), self.entries[entry_num].get_return_status()) + Ok((self.entries[entry_num].get_delivery_status()?, self.entries[entry_num].get_return_status()?)) } /// Get the current ISSI version and the supported ISSI versions, which is the output of the [`CommandOpcode::QueryIssi`] command. @@ -563,8 +575,8 @@ impl CommandQueue { error!("the command hasn't completed yet!"); return Err(CommandQueueError::CommandNotCompleted); } - if self.entries[entry_num].get_command_opcode() != cmd_opcode { - error!("Incorrect Command!: {:?}", self.entries[entry_num].get_command_opcode()); + if self.entries[entry_num].get_command_opcode()? != cmd_opcode { + error!("Incorrect Command!: {:?}", self.entries[entry_num].get_command_opcode()?); return Err(CommandQueueError::IncorrectCommandOpcode); } Ok(()) @@ -728,8 +740,8 @@ impl CommandQueueEntry { } /// Returns the value written to the input opcode field of the command - fn get_command_opcode(&self) -> CommandOpcode { - (self.command_input_opcode.read().get() >> 16).into() + fn get_command_opcode(&self) -> Result { + CommandOpcode::try_from(self.command_input_opcode.read().get() >> 16).map_err(|_e| CommandQueueError::IncorrectCommandOpcode) } /// Returns the first 16 bytes of output data that are written inline in the command. @@ -758,8 +770,9 @@ impl CommandQueueEntry { /// Returns the status of command delivery. /// This only informs us if the command was delivered to the NIC successfully, not if it was completed successfully. - pub fn get_delivery_status(&self) -> CommandDeliveryStatus { - (self.token_signature_status_own.read().get() & 0xFE).into() + pub fn get_delivery_status(&self) -> Result { + CommandDeliveryStatus::try_from(self.token_signature_status_own.read().get() & 0xFE) + .map_err(|_e| CommandQueueError::InvalidCommandDeliveryStatus) } /// Sets the ownership bit so that HW can take control of the command entry @@ -774,9 +787,9 @@ impl CommandQueueEntry { } /// Returns the status of command execution. - pub fn get_return_status(&self) -> CommandReturnStatus { + pub fn get_return_status(&self) -> Result { let (status, _syndrome, _, _) = self.get_output_inline_data(); - status.into() + CommandReturnStatus::try_from(status).map_err(|_e| CommandQueueError::InvalidCommandReturnStatus) } } diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index 60ba5c92fa..f304026b59 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -23,6 +23,7 @@ extern crate byteorder; extern crate nic_initialization; extern crate kernel_config; extern crate libm; +extern crate num_enum; use memory::PhysicalAddress; use volatile::{Volatile, ReadOnly}; diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index 637186e1be..0bb9a60022 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -123,26 +123,26 @@ impl ConnectX5Nic { // Execute ENABLE_HCA command let cmdq_entry = cmdq.create_command(CommandOpcode::EnableHca, None, None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; trace!("EnableHCA: {:?}", status); // execute QUERY_ISSI let cmdq_entry = cmdq.create_command(CommandOpcode::QueryIssi, None, None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; let (current_issi, available_issi) = cmdq.get_query_issi_command_output(cmdq_entry)?; trace!("QueryISSI: {:?}, issi version :{}, available: {:#X}", status, current_issi, available_issi); // execute SET_ISSI let cmdq_entry = cmdq.create_command(CommandOpcode::SetIssi, None, None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; trace!("SetISSI: {:?}", status); // Query pages for boot let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpMod::BootPages as u16), None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; let num_boot_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; trace!("Query pages status: {:?}, Boot pages: {:?}", status, num_boot_pages); @@ -162,13 +162,13 @@ impl ConnectX5Nic { Some(boot_pa) )?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; trace!("Manage pages boot status: {:?}", status); // Query pages for init let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpMod::InitPages as u16), None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; let num_init_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; trace!("Query pages status: {:?}, init pages: {:?}", status, num_init_pages); @@ -189,14 +189,14 @@ impl ConnectX5Nic { Some(init_pa) )?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; trace!("Manage pages init status: {:?}", status); } // execute INIT_HCA let cmdq_entry = cmdq.create_command(CommandOpcode::InitHca, None, None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; trace!("Init HCA status: {:?}", status); let mlx5_nic = ConnectX5Nic { From b7c4505b41e64414e1904129a4ca7ef579e898b1 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Fri, 23 Jul 2021 11:05:21 -0700 Subject: [PATCH 20/31] debug --- kernel/mellanox_ethernet/src/command_queue.rs | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs index 6d6ec8e875..9947176464 100644 --- a/kernel/mellanox_ethernet/src/command_queue.rs +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -741,7 +741,9 @@ impl CommandQueueEntry { /// Returns the value written to the input opcode field of the command fn get_command_opcode(&self) -> Result { - CommandOpcode::try_from(self.command_input_opcode.read().get() >> 16).map_err(|_e| CommandQueueError::IncorrectCommandOpcode) + let opcode = self.command_input_opcode.read().get() >> 16; + debug!("command opcode: {:#X}", opcode); + CommandOpcode::try_from(opcode).map_err(|_e| CommandQueueError::IncorrectCommandOpcode) } /// Returns the first 16 bytes of output data that are written inline in the command. @@ -771,7 +773,9 @@ impl CommandQueueEntry { /// Returns the status of command delivery. /// This only informs us if the command was delivered to the NIC successfully, not if it was completed successfully. pub fn get_delivery_status(&self) -> Result { - CommandDeliveryStatus::try_from(self.token_signature_status_own.read().get() & 0xFE) + let status = self.token_signature_status_own.read().get() & 0xFE; + debug!("delivery status: {:#X}", status); + CommandDeliveryStatus::try_from(status) .map_err(|_e| CommandQueueError::InvalidCommandDeliveryStatus) } @@ -789,6 +793,7 @@ impl CommandQueueEntry { /// Returns the status of command execution. pub fn get_return_status(&self) -> Result { let (status, _syndrome, _, _) = self.get_output_inline_data(); + debug!("return status: {:#X}", status); CommandReturnStatus::try_from(status).map_err(|_e| CommandQueueError::InvalidCommandReturnStatus) } } From 730002491037e9fb5c75a078b4ea3e2b011137b2 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Fri, 23 Jul 2021 12:21:46 -0700 Subject: [PATCH 21/31] fixed incorrect functions to write to command queue entry --- kernel/mellanox_ethernet/src/command_queue.rs | 51 +++++++++---------- kernel/mlx5/src/lib.rs | 16 +++--- 2 files changed, 33 insertions(+), 34 deletions(-) diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs index 9947176464..61c1df5d89 100644 --- a/kernel/mellanox_ethernet/src/command_queue.rs +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -117,7 +117,7 @@ pub enum CommandDeliveryStatus { /// Command opcode written by SW in opcode field of the input data in the command entry. /// See [`CommandQueueEntry::command_input_opcode`]. -#[derive(PartialEq, Debug, TryFromPrimitive)] +#[derive(PartialEq, Debug, TryFromPrimitive, Copy, Clone)] #[repr(u32)] pub enum CommandOpcode { QueryHcaCap = 0x100, @@ -387,7 +387,7 @@ impl CommandQueue { self.set_mailbox_pointer_in_cmd_entry(&mut cmdq_entry, entry_num, MailboxType::Output); } CommandOpcode::SetIssi => { - warn!("setting to 1 by default, could be wrong"); + // setting to 1 by default cmdq_entry.set_input_length_in_bytes(opcode.input_bytes(None)?); cmdq_entry.set_output_length_in_bytes(opcode.output_bytes()?); cmdq_entry.set_input_inline_data(opcode, opmod, Some(1), None); @@ -445,8 +445,8 @@ impl CommandQueue { error!("unimplemented opcode"); return Err(CommandQueueError::UnimplementedOpcode); } - } - + } + // write command to actual place in memory core::mem::swap(&mut cmdq_entry, &mut self.entries[entry_num]); @@ -461,13 +461,16 @@ impl CommandQueue { /// Sets the mailbox pointer in a command entry with the physical address of the first mailbox. fn set_mailbox_pointer_in_cmd_entry(&mut self, cmdq_entry: &mut CommandQueueEntry, entry_num: usize, mailbox_type: MailboxType) { - let mailbox_ptr = if mailbox_type == MailboxType::Input { - self.mailbox_buffers_input[entry_num][0].1.value() + if mailbox_type == MailboxType::Input { + let mailbox_ptr = self.mailbox_buffers_input[entry_num][0].1.value(); + cmdq_entry.input_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); + cmdq_entry.input_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); } else { - self.mailbox_buffers_output[entry_num][0].1.value() + let mailbox_ptr = self.mailbox_buffers_output[entry_num][0].1.value(); + cmdq_entry.output_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); + cmdq_entry.output_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); }; - cmdq_entry.input_mailbox_pointer_h.write(U32::new((mailbox_ptr >> 32) as u32)); - cmdq_entry.input_mailbox_pointer_l.write(U32::new((mailbox_ptr & 0xFFFF_FFFF) as u32)); + } /// Initialize output mailboxes for the [`CommandOpcode::QueryIssi`] command. @@ -499,7 +502,7 @@ impl CommandQueue { Self::write_paddr_in_mailbox_data(page * SIZE_PADDR_IN_BYTES, paddr, &mut data); }, None => { - trace!("breaking out of loop on mailbox: {} and paddr: {}", block_num, page); + // trace!("breaking out of loop on mailbox: {} and paddr: {}", block_num, page); break; } } @@ -511,10 +514,10 @@ impl CommandQueue { } /// Waits for ownership bit to be cleared, and then returns the command delivery status and the command return status. - pub fn wait_for_command_completion(&mut self, entry_num: usize) -> Result<(CommandDeliveryStatus, CommandReturnStatus), CommandQueueError> { + pub fn wait_for_command_completion(&mut self, entry_num: usize) -> (CommandDeliveryStatus, CommandReturnStatus) { while self.entries[entry_num].owned_by_hw() {} self.available_entries[entry_num] = true; - Ok((self.entries[entry_num].get_delivery_status()?, self.entries[entry_num].get_return_status()?)) + (self.entries[entry_num].get_delivery_status(), self.entries[entry_num].get_return_status()) } /// Get the current ISSI version and the supported ISSI versions, which is the output of the [`CommandOpcode::QueryIssi`] command. @@ -575,8 +578,8 @@ impl CommandQueue { error!("the command hasn't completed yet!"); return Err(CommandQueueError::CommandNotCompleted); } - if self.entries[entry_num].get_command_opcode()? != cmd_opcode { - error!("Incorrect Command!: {:?}", self.entries[entry_num].get_command_opcode()?); + if self.entries[entry_num].get_command_opcode() != cmd_opcode { + error!("Incorrect Command!: {:?}", self.entries[entry_num].get_command_opcode()); return Err(CommandQueueError::IncorrectCommandOpcode); } Ok(()) @@ -628,7 +631,7 @@ impl CommandQueue { }; let (mb_page, _mb_page_starting_addr) = &mut mailbox_pages[block_num]; - trace!("Initializing mb: {}", block_num); + // trace!("Initializing mb: {}", block_num); let mailbox = mb_page.as_type_mut::(MAILBOX_OFFSET_IN_PAGE) .map_err(|_e| CommandQueueError::InvalidMailboxOffset)?; @@ -740,10 +743,9 @@ impl CommandQueueEntry { } /// Returns the value written to the input opcode field of the command - fn get_command_opcode(&self) -> Result { + fn get_command_opcode(&self) -> CommandOpcode { let opcode = self.command_input_opcode.read().get() >> 16; - debug!("command opcode: {:#X}", opcode); - CommandOpcode::try_from(opcode).map_err(|_e| CommandQueueError::IncorrectCommandOpcode) + CommandOpcode::try_from(opcode).unwrap_or(CommandOpcode::Unknown) } /// Returns the first 16 bytes of output data that are written inline in the command. @@ -772,11 +774,9 @@ impl CommandQueueEntry { /// Returns the status of command delivery. /// This only informs us if the command was delivered to the NIC successfully, not if it was completed successfully. - pub fn get_delivery_status(&self) -> Result { - let status = self.token_signature_status_own.read().get() & 0xFE; - debug!("delivery status: {:#X}", status); - CommandDeliveryStatus::try_from(status) - .map_err(|_e| CommandQueueError::InvalidCommandDeliveryStatus) + pub fn get_delivery_status(&self) -> CommandDeliveryStatus { + let status = (self.token_signature_status_own.read().get() & 0xFE) >> 1; + CommandDeliveryStatus::try_from(status).unwrap_or(CommandDeliveryStatus::Unknown) } /// Sets the ownership bit so that HW can take control of the command entry @@ -791,10 +791,9 @@ impl CommandQueueEntry { } /// Returns the status of command execution. - pub fn get_return_status(&self) -> Result { + pub fn get_return_status(&self) -> CommandReturnStatus { let (status, _syndrome, _, _) = self.get_output_inline_data(); - debug!("return status: {:#X}", status); - CommandReturnStatus::try_from(status).map_err(|_e| CommandQueueError::InvalidCommandReturnStatus) + CommandReturnStatus::try_from(status).unwrap_or(CommandReturnStatus::Unknown) } } diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index 0bb9a60022..637186e1be 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -123,26 +123,26 @@ impl ConnectX5Nic { // Execute ENABLE_HCA command let cmdq_entry = cmdq.create_command(CommandOpcode::EnableHca, None, None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry)?; + let status = cmdq.wait_for_command_completion(cmdq_entry); trace!("EnableHCA: {:?}", status); // execute QUERY_ISSI let cmdq_entry = cmdq.create_command(CommandOpcode::QueryIssi, None, None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry)?; + let status = cmdq.wait_for_command_completion(cmdq_entry); let (current_issi, available_issi) = cmdq.get_query_issi_command_output(cmdq_entry)?; trace!("QueryISSI: {:?}, issi version :{}, available: {:#X}", status, current_issi, available_issi); // execute SET_ISSI let cmdq_entry = cmdq.create_command(CommandOpcode::SetIssi, None, None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry)?; + let status = cmdq.wait_for_command_completion(cmdq_entry); trace!("SetISSI: {:?}", status); // Query pages for boot let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpMod::BootPages as u16), None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry)?; + let status = cmdq.wait_for_command_completion(cmdq_entry); let num_boot_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; trace!("Query pages status: {:?}, Boot pages: {:?}", status, num_boot_pages); @@ -162,13 +162,13 @@ impl ConnectX5Nic { Some(boot_pa) )?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry)?; + let status = cmdq.wait_for_command_completion(cmdq_entry); trace!("Manage pages boot status: {:?}", status); // Query pages for init let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpMod::InitPages as u16), None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry)?; + let status = cmdq.wait_for_command_completion(cmdq_entry); let num_init_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; trace!("Query pages status: {:?}, init pages: {:?}", status, num_init_pages); @@ -189,14 +189,14 @@ impl ConnectX5Nic { Some(init_pa) )?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry)?; + let status = cmdq.wait_for_command_completion(cmdq_entry); trace!("Manage pages init status: {:?}", status); } // execute INIT_HCA let cmdq_entry = cmdq.create_command(CommandOpcode::InitHca, None, None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry)?; + let status = cmdq.wait_for_command_completion(cmdq_entry); trace!("Init HCA status: {:?}", status); let mlx5_nic = ConnectX5Nic { From 3039ddb8c11c3e0df2c65194c2ee9ffb6db08c43 Mon Sep 17 00:00:00 2001 From: Ramla-I Date: Fri, 23 Jul 2021 14:29:25 -0500 Subject: [PATCH 22/31] removed unused code --- kernel/mellanox_ethernet/src/command_queue.rs | 78 ------------------- 1 file changed, 78 deletions(-) diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs index 61c1df5d89..3079bcec38 100644 --- a/kernel/mellanox_ethernet/src/command_queue.rs +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -42,10 +42,6 @@ pub enum CommandQueueError { MissingInput, /// Opcode value in the command entry is not what was expected IncorrectCommandOpcode, - /// Delivery status value in the command entry is not what was expected - InvalidCommandDeliveryStatus, - /// Return status value in the command entry is not what was expected - InvalidCommandReturnStatus, /// Trying to access the command entry before HW is done processing it CommandNotCompleted, /// Offset in a page is too large to map a [`CommandInterfaceMailbox`] to that offset @@ -65,8 +61,6 @@ impl From for &'static str { CommandQueueError::MissingInputPages => "No pages were passed to the command", CommandQueueError::MissingInput => "An input was not passed to a command that required it", CommandQueueError::IncorrectCommandOpcode => "Incorrect command opcode", - CommandQueueError::InvalidCommandDeliveryStatus => "Invalid command delivery status", - CommandQueueError::InvalidCommandReturnStatus => "Invalid command return status", CommandQueueError::CommandNotCompleted => "Command not complete yet", CommandQueueError::InvalidMailboxOffset => "Invalid offset for mailbox in a page", CommandQueueError::PageAllocationFailed => "Failed to allocate MappedPages", @@ -96,24 +90,6 @@ pub enum CommandDeliveryStatus { Unknown, } -// impl From for CommandDeliveryStatus { -// fn from(status: u32) -> Self { -// match status { -// 0 => Self::Success, -// 1 => Self::SignatureErr, -// 2 => Self::TokenErr, -// 3 => Self::BadBlockNumber, -// 4 => Self::BadOutputPointer, -// 5 => Self::BadInputPointer, -// 6 => Self::InternalErr, -// 7 => Self::InputLenErr, -// 8 => Self::OutputLenErr, -// 9 => Self::ReservedNotZero, -// 10 => Self::BadCommandType, -// _ => Self::Unknown -// } -// } -// } /// Command opcode written by SW in opcode field of the input data in the command entry. /// See [`CommandQueueEntry::command_input_opcode`]. @@ -191,36 +167,6 @@ impl CommandOpcode { } } -// impl From for CommandOpcode { -// fn from(opcode: u32) -> Self { -// match opcode { -// 0x100 => Self::QueryHcaCap, -// 0x101 => Self::QueryAdapter, -// 0x102 => Self::InitHca, -// 0x103 => Self::TeardownHca, -// 0x104 => Self::EnableHca, -// 0x105 => Self::DisableHca, -// 0x107 => Self::QueryPages, -// 0x108 => Self::ManagePages, -// 0x10A => Self::QueryIssi, -// 0x10B => Self::SetIssi, -// 0x203 => Self::QuerySpecialContexts, -// 0x301 => Self::CreateEq, -// 0x400 => Self::CreateCq, -// 0x751 => Self::QueryVportState, -// 0x754 => Self::QueryNicVportContext, -// 0x800 => Self::AllocPd, -// 0x802 => Self::AllocUar, -// 0x816 => Self::AllocTransportDomain, -// 0x904 => Self::CreateSq, -// 0x905 => Self::ModifySq, -// 0x908 => Self::CreateRq, -// 0x909 => Self::ModifyRq, -// 0x912 => Self::CreateTis, -// _ => Self::Unknown -// } -// } -// } /// Command status written by HW in status field of the output data in the command entry. /// See [`CommandQueueEntry::command_output_status`]. @@ -246,29 +192,6 @@ pub enum CommandReturnStatus { Unknown } -// impl From for CommandReturnStatus { -// fn from(status: u8) -> Self { -// match status{ -// 0x0 => Self::OK, -// 0x1 => Self::InternalError, -// 0x2 => Self::BadOp, -// 0x3 => Self::BadParam, -// 0x4 => Self::BadSysState, -// 0x5 => Self::BadResource, -// 0x6 => Self::ResourceBusy, -// 0x8 => Self::ExceedLim, -// 0x9 => Self::BadResState, -// 0xA => Self::BadIndex, -// 0xF => Self::NoResources, -// 0x50 => Self::BadInputLen, -// 0x51 => Self::BadOutputLen, -// 0x10 => Self::BadResourceState, -// 0x30 => Self::BadPkt, -// 0x40 => Self::BadSize, -// _ => Self::Unknown -// } -// } -// } /// Possible values of the opcode modifer when the opcode is [`CommandOpcode::ManagePages`]. pub enum ManagePagesOpMod { @@ -292,7 +215,6 @@ enum MailboxType { } - /// A buffer of fixed-size entries that is used to pass commands to the HCA. /// It resides in a physically contiguous 4 KiB memory chunk. /// (Section 8.24.1: HCA Command Queue) From 6ca8a238970dd774a60d5d826615eaf1eda87ea7 Mon Sep 17 00:00:00 2001 From: Ramla-I Date: Fri, 23 Jul 2021 14:37:28 -0500 Subject: [PATCH 23/31] removed comment --- kernel/mellanox_ethernet/src/command_queue.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs index 3079bcec38..a6631305a1 100644 --- a/kernel/mellanox_ethernet/src/command_queue.rs +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -446,7 +446,6 @@ impl CommandQueue { pub fn get_query_issi_command_output(&self, entry_num: usize) -> Result<(u16, u8), CommandQueueError> { self.check_command_output_validity(entry_num, CommandOpcode::QueryIssi)?; - // TODO: This offset is not correct! need to check! const DATA_OFFSET_IN_MAILBOX: usize = 0x20 - 0x10; let mailbox = &self.mailbox_buffers_output[entry_num][0].0; let supported_issi = ( From 9ab39ee8a21ac4e1286402ccba3236fc28dd245b Mon Sep 17 00:00:00 2001 From: Ramla-I Date: Fri, 23 Jul 2021 14:38:11 -0500 Subject: [PATCH 24/31] removed white space --- kernel/mellanox_ethernet/src/command_queue.rs | 4 ---- 1 file changed, 4 deletions(-) diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs index a6631305a1..58348b7408 100644 --- a/kernel/mellanox_ethernet/src/command_queue.rs +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -763,7 +763,3 @@ impl fmt::Debug for CommandInterfaceMailbox { .finish() } } - - - - From e62652ad55428dfa4fd8ec4fc259c101b86fd8c3 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Mon, 26 Jul 2021 20:29:32 -0700 Subject: [PATCH 25/31] removed {} from around return statements --- kernel/mellanox_ethernet/src/command_queue.rs | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs index 58348b7408..4c664e66ba 100644 --- a/kernel/mellanox_ethernet/src/command_queue.rs +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -139,9 +139,7 @@ impl CommandOpcode { Self::AllocUar => 8, Self::AllocPd => 8, Self::AllocTransportDomain => 8, - _ => { - return Err(CommandQueueError::NotImplemented); - } + _ => return Err(CommandQueueError::NotImplemented) }; Ok(len) } @@ -159,9 +157,7 @@ impl CommandOpcode { Self::AllocUar => 12, Self::AllocPd => 12, Self::AllocTransportDomain => 12, - _ => { - return Err(CommandQueueError::NotImplemented); - } + _ => return Err(CommandQueueError::NotImplemented) }; Ok(len) } From acab8fc55aa1cfc6a3a7e5ec28f42b303f2e9840 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Tue, 27 Jul 2021 14:05:28 -0700 Subject: [PATCH 26/31] removed unknown from enums --- kernel/mellanox_ethernet/src/command_queue.rs | 36 ++++++++++++------- kernel/mlx5/src/lib.rs | 16 ++++----- 2 files changed, 32 insertions(+), 20 deletions(-) diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mellanox_ethernet/src/command_queue.rs index 4c664e66ba..94c8cc33b0 100644 --- a/kernel/mellanox_ethernet/src/command_queue.rs +++ b/kernel/mellanox_ethernet/src/command_queue.rs @@ -42,6 +42,12 @@ pub enum CommandQueueError { MissingInput, /// Opcode value in the command entry is not what was expected IncorrectCommandOpcode, + /// Opcode in the command entry is not a valid value + InvalidCommandOpcode, + /// Delivery status in the command entry is not a valid value + InvalidCommandDeliveryStatus, + /// Return status in the command entry is not a valid value + InvalidCommandReturnStatus, /// Trying to access the command entry before HW is done processing it CommandNotCompleted, /// Offset in a page is too large to map a [`CommandInterfaceMailbox`] to that offset @@ -61,6 +67,10 @@ impl From for &'static str { CommandQueueError::MissingInputPages => "No pages were passed to the command", CommandQueueError::MissingInput => "An input was not passed to a command that required it", CommandQueueError::IncorrectCommandOpcode => "Incorrect command opcode", + CommandQueueError::InvalidCommandOpcode => "Invalid command opcode. This could be because the value is invalid, + or because the driver currently doesn't support the opcode.", + CommandQueueError::InvalidCommandDeliveryStatus => "Invalid command delivery status", + CommandQueueError::InvalidCommandReturnStatus => "Invalid command return status", CommandQueueError::CommandNotCompleted => "Command not complete yet", CommandQueueError::InvalidMailboxOffset => "Invalid offset for mailbox in a page", CommandQueueError::PageAllocationFailed => "Failed to allocate MappedPages", @@ -87,7 +97,6 @@ pub enum CommandDeliveryStatus { OutputLenErr = 0x8, ReservedNotZero = 0x9, BadCommandType = 0x10, - Unknown, } @@ -119,7 +128,6 @@ pub enum CommandOpcode { CreateRq = 0x908, ModifyRq = 0x909, CreateTis = 0x912, - Unknown } impl CommandOpcode { @@ -185,7 +193,6 @@ pub enum CommandReturnStatus { BadResourceState = 0x10, BadPkt = 0x30, BadSize = 0x40, - Unknown } @@ -432,10 +439,12 @@ impl CommandQueue { } /// Waits for ownership bit to be cleared, and then returns the command delivery status and the command return status. - pub fn wait_for_command_completion(&mut self, entry_num: usize) -> (CommandDeliveryStatus, CommandReturnStatus) { + pub fn wait_for_command_completion(&mut self, entry_num: usize) -> Result<(CommandDeliveryStatus, CommandReturnStatus), CommandQueueError> { while self.entries[entry_num].owned_by_hw() {} self.available_entries[entry_num] = true; - (self.entries[entry_num].get_delivery_status(), self.entries[entry_num].get_return_status()) + let delivery_status = self.entries[entry_num].get_delivery_status().ok_or(CommandQueueError::InvalidCommandDeliveryStatus)?; + let return_status = self.entries[entry_num].get_return_status().ok_or(CommandQueueError::InvalidCommandReturnStatus)?; + Ok((delivery_status, return_status)) } /// Get the current ISSI version and the supported ISSI versions, which is the output of the [`CommandOpcode::QueryIssi`] command. @@ -495,7 +504,7 @@ impl CommandQueue { error!("the command hasn't completed yet!"); return Err(CommandQueueError::CommandNotCompleted); } - if self.entries[entry_num].get_command_opcode() != cmd_opcode { + if self.entries[entry_num].get_command_opcode().ok_or(CommandQueueError::InvalidCommandOpcode)? != cmd_opcode { error!("Incorrect Command!: {:?}", self.entries[entry_num].get_command_opcode()); return Err(CommandQueueError::IncorrectCommandOpcode); } @@ -660,9 +669,10 @@ impl CommandQueueEntry { } /// Returns the value written to the input opcode field of the command - fn get_command_opcode(&self) -> CommandOpcode { + /// A `None` returned value indicates that there was no valid value in the bitfield. + fn get_command_opcode(&self) -> Option { let opcode = self.command_input_opcode.read().get() >> 16; - CommandOpcode::try_from(opcode).unwrap_or(CommandOpcode::Unknown) + CommandOpcode::try_from(opcode).ok() } /// Returns the first 16 bytes of output data that are written inline in the command. @@ -691,9 +701,10 @@ impl CommandQueueEntry { /// Returns the status of command delivery. /// This only informs us if the command was delivered to the NIC successfully, not if it was completed successfully. - pub fn get_delivery_status(&self) -> CommandDeliveryStatus { + /// A `None` returned value indicates that there was no valid value in the bitfield. + pub fn get_delivery_status(&self) -> Option { let status = (self.token_signature_status_own.read().get() & 0xFE) >> 1; - CommandDeliveryStatus::try_from(status).unwrap_or(CommandDeliveryStatus::Unknown) + CommandDeliveryStatus::try_from(status).ok() } /// Sets the ownership bit so that HW can take control of the command entry @@ -708,9 +719,10 @@ impl CommandQueueEntry { } /// Returns the status of command execution. - pub fn get_return_status(&self) -> CommandReturnStatus { + /// A `None` returned value indicates that there was no valid value in the bitfield. + pub fn get_return_status(&self) -> Option { let (status, _syndrome, _, _) = self.get_output_inline_data(); - CommandReturnStatus::try_from(status).unwrap_or(CommandReturnStatus::Unknown) + CommandReturnStatus::try_from(status).ok() } } diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index 637186e1be..0bb9a60022 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -123,26 +123,26 @@ impl ConnectX5Nic { // Execute ENABLE_HCA command let cmdq_entry = cmdq.create_command(CommandOpcode::EnableHca, None, None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; trace!("EnableHCA: {:?}", status); // execute QUERY_ISSI let cmdq_entry = cmdq.create_command(CommandOpcode::QueryIssi, None, None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; let (current_issi, available_issi) = cmdq.get_query_issi_command_output(cmdq_entry)?; trace!("QueryISSI: {:?}, issi version :{}, available: {:#X}", status, current_issi, available_issi); // execute SET_ISSI let cmdq_entry = cmdq.create_command(CommandOpcode::SetIssi, None, None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; trace!("SetISSI: {:?}", status); // Query pages for boot let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpMod::BootPages as u16), None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; let num_boot_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; trace!("Query pages status: {:?}, Boot pages: {:?}", status, num_boot_pages); @@ -162,13 +162,13 @@ impl ConnectX5Nic { Some(boot_pa) )?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; trace!("Manage pages boot status: {:?}", status); // Query pages for init let cmdq_entry = cmdq.create_command(CommandOpcode::QueryPages, Some(QueryPagesOpMod::InitPages as u16), None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; let num_init_pages = cmdq.get_query_pages_command_output(cmdq_entry)?; trace!("Query pages status: {:?}, init pages: {:?}", status, num_init_pages); @@ -189,14 +189,14 @@ impl ConnectX5Nic { Some(init_pa) )?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; trace!("Manage pages init status: {:?}", status); } // execute INIT_HCA let cmdq_entry = cmdq.create_command(CommandOpcode::InitHca, None, None)?; init_segment.post_command(cmdq_entry); - let status = cmdq.wait_for_command_completion(cmdq_entry); + let status = cmdq.wait_for_command_completion(cmdq_entry)?; trace!("Init HCA status: {:?}", status); let mlx5_nic = ConnectX5Nic { From f92bd2df18068097a484c8cb180775fa02054ede Mon Sep 17 00:00:00 2001 From: Kevin Boos <1139460+kevinaboos@users.noreply.github.com> Date: Wed, 28 Jul 2021 11:08:18 -0700 Subject: [PATCH 27/31] fix spacing in book file --- book/src/running/virtual_machine/pci_passthrough.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/book/src/running/virtual_machine/pci_passthrough.md b/book/src/running/virtual_machine/pci_passthrough.md index ec80a636ee..95cb45a826 100644 --- a/book/src/running/virtual_machine/pci_passthrough.md +++ b/book/src/running/virtual_machine/pci_passthrough.md @@ -55,8 +55,8 @@ Now, QEMU can be launched with direct access to the device. ### Return device to the Host OS To reset the device, you can either reboot the system or return the device to the host OS using the following commands (replacing `$slot_info` with the value previously retrieved): ```sh -echo 1 >/sys/bus/pci/devices/$slot_info/remove -echo 1 >/sys/bus/pci/rescan +echo 1 > /sys/bus/pci/devices/$slot_info/remove +echo 1 > /sys/bus/pci/rescan ``` ### Note: access for unprivileged users From 798bb350f53a1ad8a6acec56371d923095dff75d Mon Sep 17 00:00:00 2001 From: Kevin Boos <1139460+kevinaboos@users.noreply.github.com> Date: Wed, 28 Jul 2021 11:15:20 -0700 Subject: [PATCH 28/31] remove false doc link --- kernel/mlx5/src/lib.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index 0bb9a60022..5be8dd3aa6 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -3,7 +3,7 @@ //! Currently we only support reading the device PCI space, mapping the initialization segment, //! and setting up a command queue to pass commands to the NIC. //! -//! All information is taken from the Mellanox Adapters Programmer’s Reference Manual (PRM) [Rev 0.54], +//! All information is taken from the Mellanox Adapters Programmer’s Reference Manual (PRM) Rev 0.54, //! unless otherwise specified. #![no_std] From b8716effb68b07f016ac986caf9ac25fbf021ad9 Mon Sep 17 00:00:00 2001 From: ramla-i Date: Wed, 28 Jul 2021 11:34:07 -0700 Subject: [PATCH 29/31] renamed mellanox crate --- Cargo.lock | 38 +++++++++---------- kernel/mlx5/Cargo.toml | 4 +- kernel/mlx5/src/lib.rs | 4 +- .../Cargo.toml | 2 +- .../src/command_queue.rs | 0 .../src/lib.rs | 0 6 files changed, 24 insertions(+), 24 deletions(-) rename kernel/{mellanox_ethernet => mlx_ethernet}/Cargo.toml (96%) rename kernel/{mellanox_ethernet => mlx_ethernet}/src/command_queue.rs (100%) rename kernel/{mellanox_ethernet => mlx_ethernet}/src/lib.rs (100%) diff --git a/Cargo.lock b/Cargo.lock index 7f8dafe58a..c698dffba8 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1396,24 +1396,6 @@ dependencies = [ "rbtree", ] -[[package]] -name = "mellanox_ethernet" -version = "0.1.0" -dependencies = [ - "bit_field 0.7.0", - "byteorder", - "kernel_config", - "libm", - "log", - "memory", - "nic_initialization", - "num_enum", - "owning_ref", - "static_assertions", - "volatile", - "zerocopy", -] - [[package]] name = "memchr" version = "2.3.4" @@ -1520,14 +1502,32 @@ dependencies = [ "irq_safety", "kernel_config", "log", - "mellanox_ethernet", "memory", + "mlx_ethernet", "nic_initialization", "owning_ref", "pci", "spin 0.9.0", ] +[[package]] +name = "mlx_ethernet" +version = "0.1.0" +dependencies = [ + "bit_field 0.7.0", + "byteorder", + "kernel_config", + "libm", + "log", + "memory", + "nic_initialization", + "num_enum", + "owning_ref", + "static_assertions", + "volatile", + "zerocopy", +] + [[package]] name = "mm_eval" version = "0.1.0" diff --git a/kernel/mlx5/Cargo.toml b/kernel/mlx5/Cargo.toml index ef47379f34..3ed5e75f51 100644 --- a/kernel/mlx5/Cargo.toml +++ b/kernel/mlx5/Cargo.toml @@ -24,8 +24,8 @@ path = "../pci" [dependencies.nic_initialization] path = "../nic_initialization" -[dependencies.mellanox_ethernet] -path = "../mellanox_ethernet" +[dependencies.mlx_ethernet] +path = "../mlx_ethernet" [dependencies.kernel_config] path = "../kernel_config" diff --git a/kernel/mlx5/src/lib.rs b/kernel/mlx5/src/lib.rs index 0bb9a60022..667f683cf6 100644 --- a/kernel/mlx5/src/lib.rs +++ b/kernel/mlx5/src/lib.rs @@ -16,7 +16,7 @@ extern crate memory; extern crate pci; extern crate owning_ref; extern crate nic_initialization; -extern crate mellanox_ethernet; +extern crate mlx_ethernet; extern crate kernel_config; use spin::Once; @@ -29,7 +29,7 @@ use memory::{PhysicalAddress, MappedPages, create_contiguous_mapping}; use pci::PciDevice; use owning_ref::BoxRefMut; use nic_initialization::{NIC_MAPPING_FLAGS, allocate_memory}; -use mellanox_ethernet::{ +use mlx_ethernet::{ InitializationSegment, command_queue::{CommandQueueEntry, CommandQueue, CommandOpcode, ManagePagesOpMod, QueryPagesOpMod} }; diff --git a/kernel/mellanox_ethernet/Cargo.toml b/kernel/mlx_ethernet/Cargo.toml similarity index 96% rename from kernel/mellanox_ethernet/Cargo.toml rename to kernel/mlx_ethernet/Cargo.toml index b9ca326431..dce4e35bb0 100644 --- a/kernel/mellanox_ethernet/Cargo.toml +++ b/kernel/mlx_ethernet/Cargo.toml @@ -1,5 +1,5 @@ [package] -name = "mellanox_ethernet" +name = "mlx_ethernet" description = "defines structs and traits for SW objects unique to Mellanox NICs" version = "0.1.0" authors = ["Ramla-I "] diff --git a/kernel/mellanox_ethernet/src/command_queue.rs b/kernel/mlx_ethernet/src/command_queue.rs similarity index 100% rename from kernel/mellanox_ethernet/src/command_queue.rs rename to kernel/mlx_ethernet/src/command_queue.rs diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mlx_ethernet/src/lib.rs similarity index 100% rename from kernel/mellanox_ethernet/src/lib.rs rename to kernel/mlx_ethernet/src/lib.rs From ecd6a2a3bc07a86787d66980f17ed43d541f925d Mon Sep 17 00:00:00 2001 From: Kevin Boos Date: Wed, 28 Jul 2021 11:49:46 -0700 Subject: [PATCH 30/31] allow private doc links --- kernel/mellanox_ethernet/src/lib.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/mellanox_ethernet/src/lib.rs b/kernel/mellanox_ethernet/src/lib.rs index f304026b59..0eebea28c1 100644 --- a/kernel/mellanox_ethernet/src/lib.rs +++ b/kernel/mellanox_ethernet/src/lib.rs @@ -8,6 +8,7 @@ //! an older version of the manual can be found at . #![no_std] + #![allow(rustdoc::private_intra_doc_links)] #![feature(slice_pattern)] #![feature(core_intrinsics)] From 7dd12ab0043eb05ae8b5c6f30c315919828538d6 Mon Sep 17 00:00:00 2001 From: Kevin Boos Date: Wed, 28 Jul 2021 12:17:05 -0700 Subject: [PATCH 31/31] build private intra-doc links for all Theseus crates --- Makefile | 2 +- kernel/mlx_ethernet/src/lib.rs | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 280bc39784..4eeae317d0 100644 --- a/Makefile +++ b/Makefile @@ -461,7 +461,7 @@ RUSTDOC_OUT_FILE := $(RUSTDOC_OUT)/___Theseus_Crates___/index.html ## The entire project is built as normal using the `cargo doc` command (`rustdoc` under the hood). docs: doc doc: check_rustc - @cargo doc --workspace --no-deps $(addprefix --exclude , $(APP_CRATE_NAMES)) + @RUSTDOCFLAGS="$$RUSTDOCFLAGS -A private_intra_doc_links" cargo doc --workspace --no-deps $(addprefix --exclude , $(APP_CRATE_NAMES)) @rustdoc --output target/doc --crate-name "___Theseus_Crates___" $(ROOT_DIR)/kernel/_doc_root.rs @rm -rf $(RUSTDOC_OUT) @mkdir -p $(RUSTDOC_OUT) diff --git a/kernel/mlx_ethernet/src/lib.rs b/kernel/mlx_ethernet/src/lib.rs index 0eebea28c1..f304026b59 100644 --- a/kernel/mlx_ethernet/src/lib.rs +++ b/kernel/mlx_ethernet/src/lib.rs @@ -8,7 +8,6 @@ //! an older version of the manual can be found at . #![no_std] - #![allow(rustdoc::private_intra_doc_links)] #![feature(slice_pattern)] #![feature(core_intrinsics)]