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stm32f767xx.hxx
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stm32f767xx.hxx
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// regbits_stm: regbits implementations for STM MCUs
// Copyright (C) 2019,2020 Mark R. Rubin
//
// This file is part of regbits_stm.
//
// The regbits_stm program is free software: you can redistribute it
// and/or modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation, either version 3 of
// the License, or (at your option) any later version.
//
// The regbits_stm program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty
// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// (LICENSE.txt) along with the regbits_stm program. If not, see
// <https://www.gnu.org/licenses/gpl.html>
#ifndef STM32F767XX_HXX
#define STM32F767XX_HXX
#include <stdint.h>
#include <regbits.hxx>
#if REGBITS_MAJOR_VERSION == 1
#if REGBITS_MINOR_VERSION < 0
#warning REGBITS_MINOR_VERSION >= 0 with required REGBITS_MAJOR_VERSION == 1
#endif
#else
#error REGBITS_MAJOR_VERSION != 1
#endif
#define STM32F767XX_MAJOR_VERSION 1
#define STM32F767XX_MINOR_VERSION 2
#define STM32F767XX_MICRO_VERSION 0
namespace stm32f767xx {
using namespace regbits;
struct Rcc {
struct Cr {
using pos_t = Pos<uint32_t, Cr>;
static constexpr pos_t HSION_POS = pos_t( 0),
HSIRDY_POS = pos_t( 1),
HSITRIM_POS = pos_t( 3),
HSICAL_POS = pos_t( 8),
HSEON_POS = pos_t(16),
HSERDY_POS = pos_t(17),
HSEBYP_POS = pos_t(18),
CSSON_POS = pos_t(19),
PLLON_POS = pos_t(24),
PLLRDY_POS = pos_t(25),
PLLI2SON_POS = pos_t(26),
PLLI2SRDY_POS = pos_t(27),
PLLSAION_POS = pos_t(28),
PLLSAIRDY_POS = pos_t(29);
using bits_t = Bits<uint32_t, Cr>;
static constexpr bits_t HSION = bits_t(1, HSION_POS ),
HSIRDY = bits_t(1, HSIRDY_POS ),
HSEON = bits_t(1, HSEON_POS ),
HSERDY = bits_t(1, HSERDY_POS ),
HSEBYP = bits_t(1, HSEBYP_POS ),
CSSON = bits_t(1, CSSON_POS ),
PLLON = bits_t(1, PLLON_POS ),
PLLRDY = bits_t(1, PLLRDY_POS ),
PLLI2SON = bits_t(1, PLLI2SON_POS ),
PLLI2SRDY = bits_t(1, PLLI2SRDY_POS),
PLLSAION = bits_t(1, PLLSAION_POS ),
PLLSAIRDY = bits_t(1, PLLSAIRDY_POS);
static const uint32_t HSITRIM_MASK = 0x1f,
HSICAL_MASK = 0xff;
using mskd_t = Mskd<uint32_t, Cr>;
using shft_t = Shft<uint32_t, Cr>;
REGBITS_MSKD_RANGE("Rcc::Cr",
HSITRIM,
hsitrim,
HSITRIM_MASK,
HSITRIM_POS,
HSITRIM_MASK);
REGBITS_MSKD_RANGE("Rcc::Cr",
HSICAL,
hsical,
HSICAL_MASK,
HSICAL_POS,
HSICAL_MASK);
}; // struct Cr
using cr_t = Reg<uint32_t, Cr>;
cr_t cr;
struct Pllcfgr {
using pos_t = Pos<uint32_t, Pllcfgr>;
static constexpr pos_t PLLM_POS = pos_t( 0),
PLLN_POS = pos_t( 6),
PLLP_POS = pos_t(16),
PLLSRC_POS = pos_t(22),
PLLSRC_HSE_POS = pos_t(22),
PLLQ_POS = pos_t(24),
PLLR_POS = pos_t(28);
using bits_t = Bits<uint32_t, Pllcfgr>;
static constexpr bits_t PLLSRC = bits_t(1, PLLSRC_POS );
static const uint32_t PLLM_MASK = 0b000111111,
PLLN_MASK = 0b111111111,
PLLP_MASK = 0b000000011,
PLLQ_MASK = 0b000001111,
PLLR_MASK = 0b000000111;
static const uint32_t PLLN_MAX = 432;
using mskd_t = Mskd<uint32_t, Pllcfgr>;
using shft_t = Shft<uint32_t, Pllcfgr>;
REGBITS_MSKD_RANGE("Rcc::Pllcfgr",
PLLM,
pllm,
PLLM_MASK,
PLLM_POS,
PLLM_MASK);
REGBITS_MSKD_RANGE("Rcc::Pllcfgr",
PLLN,
plln,
PLLN_MASK,
PLLN_POS,
PLLN_MAX);
static constexpr mskd_t PLLP_2 = mskd_t(PLLP_MASK, 0b00, PLLP_POS),
PLLP_4 = mskd_t(PLLP_MASK, 0b01, PLLP_POS),
PLLP_6 = mskd_t(PLLP_MASK, 0b10, PLLP_POS),
PLLP_8 = mskd_t(PLLP_MASK, 0b11, PLLP_POS),
// PLLQ 0 and 1 illegal values
PLLQ_2 = mskd_t(PLLQ_MASK, 2, PLLQ_POS),
PLLQ_3 = mskd_t(PLLQ_MASK, 3, PLLQ_POS),
PLLQ_4 = mskd_t(PLLQ_MASK, 4, PLLQ_POS),
PLLQ_5 = mskd_t(PLLQ_MASK, 5, PLLQ_POS),
PLLQ_6 = mskd_t(PLLQ_MASK, 6, PLLQ_POS),
PLLQ_7 = mskd_t(PLLQ_MASK, 7, PLLQ_POS),
PLLQ_8 = mskd_t(PLLQ_MASK, 8, PLLQ_POS),
PLLQ_9 = mskd_t(PLLQ_MASK, 9, PLLQ_POS),
PLLQ_10 = mskd_t(PLLQ_MASK, 10, PLLQ_POS ),
PLLQ_11 = mskd_t(PLLQ_MASK, 11, PLLQ_POS ),
PLLQ_12 = mskd_t(PLLQ_MASK, 12, PLLQ_POS ),
PLLQ_13 = mskd_t(PLLQ_MASK, 13, PLLQ_POS ),
PLLQ_14 = mskd_t(PLLQ_MASK, 14, PLLQ_POS ),
PLLQ_15 = mskd_t(PLLQ_MASK, 15, PLLQ_POS ),
// PLLR 0 and 1 illegal values
PLLR_2 = mskd_t(PLLR_MASK, 2, PLLR_POS),
PLLR_3 = mskd_t(PLLR_MASK, 3, PLLR_POS),
PLLR_4 = mskd_t(PLLR_MASK, 4, PLLR_POS),
PLLR_5 = mskd_t(PLLR_MASK, 5, PLLR_POS),
PLLR_6 = mskd_t(PLLR_MASK, 6, PLLR_POS),
PLLR_7 = mskd_t(PLLR_MASK, 7, PLLR_POS);
}; // struct Pllcfgr
using pllcfgr_t = Reg<uint32_t, Pllcfgr>;
pllcfgr_t pllcfgr;
struct Cfgr {
using pos_t = Pos<uint32_t, Cfgr>;
static constexpr pos_t SW_POS = pos_t( 0),
SWS_POS = pos_t( 2),
HPRE_POS = pos_t( 4),
PPRE1_POS = pos_t(10),
PPRE2_POS = pos_t(13),
RTCPRE_POS = pos_t(16),
MCO1_POS = pos_t(21),
I2SSRC_POS = pos_t(23),
MCO1PRE_POS = pos_t(24),
MCO2PRE_POS = pos_t(27),
MCO2_POS = pos_t(30);
static const uint32_t SW_MASK = 0x3 ,
SWS_MASK = 0x3 ,
HPRE_MASK = 0b1111 ,
PPRE1_MASK = 0b111 ,
PPRE2_MASK = 0b111 ,
RTCPRE_MASK = 0b11111,
I2SSRC_MASK = 1 ,
MCO1_MASK = 0b11 ,
MCO1PRE_MASK = 0b111 ,
MCO2PRE_MASK = 0b111 ;
using mskd_t = Mskd<uint32_t, Cfgr>;
static constexpr mskd_t
SW_HSI = mskd_t(SW_MASK, 0x0, SW_POS),
SW_HSE = mskd_t(SW_MASK, 0x1, SW_POS),
SW_PLL = mskd_t(SW_MASK, 0x2, SW_POS),
SWS_HSI = mskd_t(SWS_MASK, 0x0, SWS_POS),
SWS_HSE = mskd_t(SWS_MASK, 0x1, SWS_POS),
SWS_PLL = mskd_t(SWS_MASK, 0x2, SWS_POS),
HPRE_DIV_NONE = mskd_t(HPRE_MASK, 0b0000, HPRE_POS),
HPRE_DIV_1 = mskd_t(HPRE_MASK, 0b0000, HPRE_POS),
HPRE_DIV_2 = mskd_t(HPRE_MASK, 0b1000, HPRE_POS),
HPRE_DIV_4 = mskd_t(HPRE_MASK, 0b1001, HPRE_POS),
HPRE_DIV_8 = mskd_t(HPRE_MASK, 0b1010, HPRE_POS),
HPRE_DIV_16 = mskd_t(HPRE_MASK, 0b1011, HPRE_POS),
HPRE_DIV_64 = mskd_t(HPRE_MASK, 0b1100, HPRE_POS),
HPRE_DIV_128 = mskd_t(HPRE_MASK, 0b1101, HPRE_POS),
HPRE_DIV_256 = mskd_t(HPRE_MASK, 0b1110, HPRE_POS),
HPRE_DIV_512 = mskd_t(HPRE_MASK, 0b1111, HPRE_POS),
PPRE1_DIV_1 = mskd_t(PPRE1_MASK, 0b000, PPRE1_POS),
PPRE1_DIV_2 = mskd_t(PPRE1_MASK, 0b100, PPRE1_POS),
PPRE1_DIV_4 = mskd_t(PPRE1_MASK, 0b101, PPRE1_POS),
PPRE1_DIV_8 = mskd_t(PPRE1_MASK, 0b110, PPRE1_POS),
PPRE1_DIV_16 = mskd_t(PPRE1_MASK, 0b111, PPRE1_POS),
PPRE2_DIV_1 = mskd_t(PPRE2_MASK, 0b000, PPRE2_POS),
PPRE2_DIV_2 = mskd_t(PPRE2_MASK, 0b100, PPRE2_POS),
PPRE2_DIV_4 = mskd_t(PPRE2_MASK, 0b101, PPRE2_POS),
PPRE2_DIV_8 = mskd_t(PPRE2_MASK, 0b110, PPRE2_POS),
PPRE2_DIV_16 = mskd_t(PPRE2_MASK, 0b111, PPRE2_POS),
RTCPRE_NONE_0 = mskd_t(RTCPRE_MASK, 0, RTCPRE_POS),
RTCPRE_NONE_1 = mskd_t(RTCPRE_MASK, 1, RTCPRE_POS),
RTCPRE_DIV_2 = mskd_t(RTCPRE_MASK, 2, RTCPRE_POS),
RTCPRE_DIV_3 = mskd_t(RTCPRE_MASK, 3, RTCPRE_POS),
RTCPRE_DIV_4 = mskd_t(RTCPRE_MASK, 4, RTCPRE_POS),
RTCPRE_DIV_5 = mskd_t(RTCPRE_MASK, 5, RTCPRE_POS),
RTCPRE_DIV_6 = mskd_t(RTCPRE_MASK, 6, RTCPRE_POS),
RTCPRE_DIV_7 = mskd_t(RTCPRE_MASK, 7, RTCPRE_POS),
RTCPRE_DIV_8 = mskd_t(RTCPRE_MASK, 8, RTCPRE_POS),
RTCPRE_DIV_9 = mskd_t(RTCPRE_MASK, 9, RTCPRE_POS),
RTCPRE_DIV_10 = mskd_t(RTCPRE_MASK, 10, RTCPRE_POS),
RTCPRE_DIV_11 = mskd_t(RTCPRE_MASK, 11, RTCPRE_POS),
RTCPRE_DIV_12 = mskd_t(RTCPRE_MASK, 12, RTCPRE_POS),
RTCPRE_DIV_13 = mskd_t(RTCPRE_MASK, 13, RTCPRE_POS),
RTCPRE_DIV_14 = mskd_t(RTCPRE_MASK, 14, RTCPRE_POS),
RTCPRE_DIV_15 = mskd_t(RTCPRE_MASK, 15, RTCPRE_POS),
RTCPRE_DIV_16 = mskd_t(RTCPRE_MASK, 16, RTCPRE_POS),
RTCPRE_DIV_17 = mskd_t(RTCPRE_MASK, 17, RTCPRE_POS),
RTCPRE_DIV_18 = mskd_t(RTCPRE_MASK, 18, RTCPRE_POS),
RTCPRE_DIV_19 = mskd_t(RTCPRE_MASK, 19, RTCPRE_POS),
RTCPRE_DIV_20 = mskd_t(RTCPRE_MASK, 20, RTCPRE_POS),
RTCPRE_DIV_21 = mskd_t(RTCPRE_MASK, 21, RTCPRE_POS),
RTCPRE_DIV_22 = mskd_t(RTCPRE_MASK, 22, RTCPRE_POS),
RTCPRE_DIV_23 = mskd_t(RTCPRE_MASK, 23, RTCPRE_POS),
RTCPRE_DIV_24 = mskd_t(RTCPRE_MASK, 24, RTCPRE_POS),
RTCPRE_DIV_25 = mskd_t(RTCPRE_MASK, 25, RTCPRE_POS),
RTCPRE_DIV_26 = mskd_t(RTCPRE_MASK, 26, RTCPRE_POS),
RTCPRE_DIV_27 = mskd_t(RTCPRE_MASK, 27, RTCPRE_POS),
RTCPRE_DIV_28 = mskd_t(RTCPRE_MASK, 28, RTCPRE_POS),
RTCPRE_DIV_29 = mskd_t(RTCPRE_MASK, 29, RTCPRE_POS),
RTCPRE_DIV_30 = mskd_t(RTCPRE_MASK, 30, RTCPRE_POS),
RTCPRE_DIV_31 = mskd_t(RTCPRE_MASK, 31, RTCPRE_POS),
I2SSRC_PLL = mskd_t(I2SSRC_MASK, 0, I2SSRC_POS),
I2SSRC_EXT = mskd_t(I2SSRC_MASK, 1, I2SSRC_POS),
MCO1_HSI = mskd_t(MCO1_MASK, 0b00, MCO1_POS),
MCO1_LSE = mskd_t(MCO1_MASK, 0b01, MCO1_POS),
MCO1_HSE = mskd_t(MCO1_MASK, 0b10, MCO1_POS),
MCO1_PLL = mskd_t(MCO1_MASK, 0b11, MCO1_POS),
MCO1PRE_DIV_1 = mskd_t(MCO1PRE_MASK, 0b000, MCO1PRE_POS),
MCO1PRE_DIV_2 = mskd_t(MCO1PRE_MASK, 0b100, MCO1PRE_POS),
MCO1PRE_DIV_3 = mskd_t(MCO1PRE_MASK, 0b101, MCO1PRE_POS),
MCO1PRE_DIV_4 = mskd_t(MCO1PRE_MASK, 0b110, MCO1PRE_POS),
MCO1PRE_DIV_5 = mskd_t(MCO1PRE_MASK, 0b111, MCO1PRE_POS),
MCO2PRE_DIV_1 = mskd_t(MCO2PRE_MASK, 0b000, MCO2PRE_POS),
MCO2PRE_DIV_2 = mskd_t(MCO2PRE_MASK, 0b100, MCO2PRE_POS),
MCO2PRE_DIV_3 = mskd_t(MCO2PRE_MASK, 0b101, MCO2PRE_POS),
MCO2PRE_DIV_4 = mskd_t(MCO2PRE_MASK, 0b110, MCO2PRE_POS),
MCO2PRE_DIV_5 = mskd_t(MCO2PRE_MASK, 0b111, MCO2PRE_POS);
}; // struct Cfgr
using cfgr_t = Reg<uint32_t, Cfgr>;
cfgr_t cfgr;
struct Cir {
using pos_t = Pos<uint32_t, Cir>;
static constexpr pos_t LSIRDYF_POS = pos_t( 0),
LSERDYF_POS = pos_t( 1),
HSIRDYF_POS = pos_t( 2),
HSERDYF_POS = pos_t( 3),
PLLRDYF_POS = pos_t( 4),
PLLI2SRDYF_POS = pos_t( 5),
PLLSAIRDYF_POS = pos_t( 6),
CSSF_POS = pos_t( 7),
LSIRDYIE_POS = pos_t( 8),
LSERDYIE_POS = pos_t( 9),
HSIRDYIE_POS = pos_t(10),
HSERDYIE_POS = pos_t(11),
PLLRDYIE_POS = pos_t(12),
PLLI2SRDYIE_POS = pos_t(13),
PLLSAIRDYIE_POS = pos_t(14),
LSIRDYC_POS = pos_t(16),
LSERDYC_POS = pos_t(17),
HSIRDYC_POS = pos_t(18),
HSERDYC_POS = pos_t(19),
PLLRDYC_POS = pos_t(20),
PLLI2SRDYC_POS = pos_t(21),
PLLSAIRDYC_POS = pos_t(22),
CSSC_POS = pos_t(23);
using bits_t = Bits<uint32_t, Cir>;
static constexpr bits_t LSIRDYF = bits_t(1, LSIRDYF_POS ),
LSERDYF = bits_t(1, LSERDYF_POS ),
HSIRDYF = bits_t(1, HSIRDYF_POS ),
HSERDYF = bits_t(1, HSERDYF_POS ),
PLLRDYF = bits_t(1, PLLRDYF_POS ),
PLLI2SRDYF = bits_t(1, PLLI2SRDYF_POS ),
PLLSAIRDYF = bits_t(1, PLLSAIRDYF_POS ),
CSSF = bits_t(1, CSSF_POS ),
LSIRDYIE = bits_t(1, LSIRDYIE_POS ),
LSERDYIE = bits_t(1, LSERDYIE_POS ),
HSIRDYIE = bits_t(1, HSIRDYIE_POS ),
HSERDYIE = bits_t(1, HSERDYIE_POS ),
PLLRDYIE = bits_t(1, PLLRDYIE_POS ),
PLLI2SRDYIE = bits_t(1, PLLI2SRDYIE_POS),
PLLSAIRDYIE = bits_t(1, PLLSAIRDYIE_POS),
LSIRDYC = bits_t(1, LSIRDYC_POS ),
LSERDYC = bits_t(1, LSERDYC_POS ),
HSIRDYC = bits_t(1, HSIRDYC_POS ),
HSERDYC = bits_t(1, HSERDYC_POS ),
PLLRDYC = bits_t(1, PLLRDYC_POS ),
PLLI2SRDYC = bits_t(1, PLLI2SRDYC_POS ),
PLLSAIRDYC = bits_t(1, PLLSAIRDYC_POS ),
CSSC = bits_t(1, CSSC_POS );
}; // struct Cir
using cir_t = Reg<uint32_t, Cir>;
cir_t cir;
struct Ahb1rstr {
using pos_t = Pos<uint32_t, Ahb1rstr>;
static constexpr pos_t GPIOA_POS = pos_t( 0),
GPIOB_POS = pos_t( 1),
GPIOC_POS = pos_t( 2),
GPIOD_POS = pos_t( 3),
GPIOE_POS = pos_t( 4),
GPIOF_POS = pos_t( 5),
GPIOG_POS = pos_t( 6),
GPIOH_POS = pos_t( 7),
GPIOI_POS = pos_t( 8),
GPIOJ_POS = pos_t( 9),
GPIOK_POS = pos_t(10),
CRC_POS = pos_t(12),
DMA1_POS = pos_t(21),
DMA2_POS = pos_t(22),
DMA2D_POS = pos_t(23),
ETHMAC_POS = pos_t(25),
OTGH_POS = pos_t(29);
using bits_t = Bits<uint32_t, Ahb1rstr>;
static constexpr bits_t GPIOA = bits_t(1, GPIOA_POS ),
GPIOB = bits_t(1, GPIOB_POS ),
GPIOC = bits_t(1, GPIOC_POS ),
GPIOD = bits_t(1, GPIOD_POS ),
GPIOE = bits_t(1, GPIOE_POS ),
GPIOF = bits_t(1, GPIOF_POS ),
GPIOG = bits_t(1, GPIOG_POS ),
GPIOH = bits_t(1, GPIOH_POS ),
GPIOI = bits_t(1, GPIOI_POS ),
GPIOJ = bits_t(1, GPIOJ_POS ),
GPIOK = bits_t(1, GPIOK_POS ),
CRC = bits_t(1, CRC_POS ),
DMA1 = bits_t(1, DMA1_POS ),
DMA2 = bits_t(1, DMA2_POS ),
DMA2D = bits_t(1, DMA2D_POS ),
ETHMAC = bits_t(1, ETHMAC_POS ),
OTGH = bits_t(1, OTGH_POS );
}; // struct Ahb1rstr
using ahb1rstr_t = Reg<uint32_t, Ahb1rstr>;
ahb1rstr_t ahb1rstr;
struct Ahb2rstr {
using pos_t = Pos<uint32_t, Ahb2rstr>;
static constexpr pos_t DCMIRST_POS = pos_t(0),
JPEGRST_POS = pos_t(1),
RNGRST_POS = pos_t(6),
OTGFSRST_POS = pos_t(7);
using bits_t = Bits<uint32_t, Ahb2rstr>;
static constexpr bits_t DCMIRST = bits_t(1, DCMIRST_POS ),
JPEGRST = bits_t(1, JPEGRST_POS ),
RNGRST = bits_t(1, RNGRST_POS ),
OTGFSRST = bits_t(1, OTGFSRST_POS);
}; // struct Ahb2rstr
using ahb2rstr_t = Reg<uint32_t, Ahb2rstr>;
ahb2rstr_t ahb2rstr;
struct Ahb3rstr {
using pos_t = Pos<uint32_t, Ahb3rstr>;
static constexpr pos_t FMCRST_POS = pos_t(0),
QSPIRST_POS = pos_t(1);
using bits_t = Bits<uint32_t, Ahb3rstr>;
static constexpr bits_t FMCRST = bits_t(1, FMCRST_POS ),
QSPIRST = bits_t(1, QSPIRST_POS );
}; // struct Ahb3rstr
using ahb3rstr_t = Reg<uint32_t, Ahb3rstr>;
ahb3rstr_t ahb3rstr;
private: uint32_t _reserved0; public:
struct Apb1rstr {
using pos_t = Pos<uint32_t, Apb1rstr>;
static constexpr pos_t TIM2_POS = pos_t( 0),
TIM3_POS = pos_t( 1),
TIM4_POS = pos_t( 2),
TIM5_POS = pos_t( 3),
TIM6_POS = pos_t( 4),
TIM7_POS = pos_t( 5),
TIM12_POS = pos_t( 6),
TIM13_POS = pos_t( 7),
TIM14_POS = pos_t( 8),
LPTIM1_POS = pos_t( 9),
WWDG_POS = pos_t(11),
CAN3_POS = pos_t(13),
SPI2_POS = pos_t(14),
SPI3_POS = pos_t(15),
SPDIFRX_POS = pos_t(16),
USART2_POS = pos_t(17),
USART3_POS = pos_t(18),
UART4_POS = pos_t(19),
UART5_POS = pos_t(20),
I2C1_POS = pos_t(21),
I2C2_POS = pos_t(22),
I2C3_POS = pos_t(23),
I2C4_POS = pos_t(24),
CAN1_POS = pos_t(25),
CAN2_POS = pos_t(26),
CEC_POS = pos_t(27),
PWR_POS = pos_t(28),
DAC_POS = pos_t(29),
UART7_POS = pos_t(30),
UART8_POS = pos_t(31);
using bits_t = Bits<uint32_t, Apb1rstr>;
static constexpr bits_t TIM2 = bits_t(1, TIM2_POS ),
TIM3 = bits_t(1, TIM3_POS ),
TIM4 = bits_t(1, TIM4_POS ),
TIM5 = bits_t(1, TIM5_POS ),
TIM6 = bits_t(1, TIM6_POS ),
TIM7 = bits_t(1, TIM7_POS ),
TIM12 = bits_t(1, TIM12_POS ),
TIM13 = bits_t(1, TIM13_POS ),
TIM14 = bits_t(1, TIM14_POS ),
LPTIM1 = bits_t(1, LPTIM1_POS ),
WWDG = bits_t(1, WWDG_POS ),
CAN3 = bits_t(1, CAN3_POS ),
SPI2 = bits_t(1, SPI2_POS ),
SPI3 = bits_t(1, SPI3_POS ),
SPDIFRX = bits_t(1, SPDIFRX_POS ),
USART2 = bits_t(1, USART2_POS ),
USART3 = bits_t(1, USART3_POS ),
UART4 = bits_t(1, UART4_POS ),
UART5 = bits_t(1, UART5_POS ),
I2C1 = bits_t(1, I2C1_POS ),
I2C2 = bits_t(1, I2C2_POS ),
I2C3 = bits_t(1, I2C3_POS ),
I2C4 = bits_t(1, I2C4_POS ),
CAN1 = bits_t(1, CAN1_POS ),
CAN2 = bits_t(1, CAN2_POS ),
CEC = bits_t(1, CEC_POS ),
PWR = bits_t(1, PWR_POS ),
DAC = bits_t(1, DAC_POS ),
UART7 = bits_t(1, UART7_POS ),
UART8 = bits_t(1, UART8_POS );
}; // struct Apb1rstr
using apb1rstr_t = Reg<uint32_t, Apb1rstr>;
apb1rstr_t apb1rstr;
struct Apb2rstr {
using pos_t = Pos<uint32_t, Apb2rstr>;
static constexpr pos_t TIM1_POS = pos_t( 0),
TIM8_POS = pos_t( 1),
USART1_POS = pos_t( 4),
USART6_POS = pos_t( 5),
SDMMC2_POS = pos_t( 7),
ADC_POS = pos_t( 8),
SDMMC1_POS = pos_t(11),
SPI1_POS = pos_t(12),
SPI4_POS = pos_t(13),
SYSCFG_POS = pos_t(14),
TIM9_POS = pos_t(16),
TIM10_POS = pos_t(17),
TIM11_POS = pos_t(18),
SPI5_POS = pos_t(20),
SPI6_POS = pos_t(21),
SAI1_POS = pos_t(22),
SAI2_POS = pos_t(23),
LTDC_POS = pos_t(26),
DFSDM1_POS = pos_t(29),
MDIO_POS = pos_t(30);
using bits_t = Bits<uint32_t, Apb2rstr>;
static constexpr bits_t TIM1 = bits_t(1, TIM1_POS ),
TIM8 = bits_t(1, TIM8_POS ),
USART1 = bits_t(1, USART1_POS ),
USART6 = bits_t(1, USART6_POS ),
SDMMC2 = bits_t(1, SDMMC2_POS ),
ADC = bits_t(1, ADC_POS ),
SDMMC1 = bits_t(1, SDMMC1_POS ),
SPI1 = bits_t(1, SPI1_POS ),
SPI4 = bits_t(1, SPI4_POS ),
SYSCFG = bits_t(1, SYSCFG_POS ),
TIM9 = bits_t(1, TIM9_POS ),
TIM10 = bits_t(1, TIM10_POS ),
TIM11 = bits_t(1, TIM11_POS ),
SPI5 = bits_t(1, SPI5_POS ),
SPI6 = bits_t(1, SPI6_POS ),
SAI1 = bits_t(1, SAI1_POS ),
SAI2 = bits_t(1, SAI2_POS ),
LTDC = bits_t(1, LTDC_POS ),
DFSDM1 = bits_t(1, DFSDM1_POS ),
MDIO = bits_t(1, MDIO_POS );
}; // struct Apb2rstr
using apb2rstr_t = Reg<uint32_t, Apb2rstr>;
apb2rstr_t apb2rstr;
private: uint32_t _reserved1[2]; public:
struct Ahb1enr {
using pos_t = Pos<uint32_t, Ahb1enr>;
static constexpr pos_t GPIOA_POS = pos_t( 0),
GPIOB_POS = pos_t( 1),
GPIOC_POS = pos_t( 2),
GPIOD_POS = pos_t( 3),
GPIOE_POS = pos_t( 4),
GPIOF_POS = pos_t( 5),
GPIOG_POS = pos_t( 6),
GPIOH_POS = pos_t( 7),
GPIOI_POS = pos_t( 8),
GPIOJ_POS = pos_t( 9),
GPIOK_POS = pos_t(10),
CRC_POS = pos_t(12),
BKPSRAM_POS = pos_t(18),
DTCMRAM_POS = pos_t(20),
DMA1_POS = pos_t(21),
DMA2_POS = pos_t(22),
DMA2D_POS = pos_t(23),
ETHMAC_POS = pos_t(25),
ETHMACTX_POS = pos_t(26),
ETHMACRX_POS = pos_t(27),
ETHMACPTP_POS = pos_t(28),
OTGHS_POS = pos_t(29),
OTGHSULPI_POS = pos_t(30);
using bits_t = Bits<uint32_t, Ahb1enr>;
static constexpr bits_t GPIOA = bits_t(1, GPIOA_POS ),
GPIOB = bits_t(1, GPIOB_POS ),
GPIOC = bits_t(1, GPIOC_POS ),
GPIOD = bits_t(1, GPIOD_POS ),
GPIOE = bits_t(1, GPIOE_POS ),
GPIOF = bits_t(1, GPIOF_POS ),
GPIOG = bits_t(1, GPIOG_POS ),
GPIOH = bits_t(1, GPIOH_POS ),
GPIOI = bits_t(1, GPIOI_POS ),
GPIOJ = bits_t(1, GPIOJ_POS ),
GPIOK = bits_t(1, GPIOK_POS ),
CRC = bits_t(1, CRC_POS ),
BKPSRAM = bits_t(1, BKPSRAM_POS ),
DTCMRAM = bits_t(1, DTCMRAM_POS ),
DMA1 = bits_t(1, DMA1_POS ),
DMA2 = bits_t(1, DMA2_POS ),
DMA2D = bits_t(1, DMA2D_POS ),
ETHMAC = bits_t(1, ETHMAC_POS ),
ETHMACTX = bits_t(1, ETHMACTX_POS ),
ETHMACRX = bits_t(1, ETHMACRX_POS ),
ETHMACPTP = bits_t(1, ETHMACPTP_POS),
OTGHS = bits_t(1, OTGHS_POS ),
OTGHSULPI = bits_t(1, OTGHSULPI_POS);
}; // struct Ahb1enr
using ahb1enr_t = Reg<uint32_t, Ahb1enr>;
ahb1enr_t ahb1enr;
struct Ahb2enr {
using pos_t = Pos<uint32_t, Ahb2enr>;
static constexpr pos_t DCMI_POS = pos_t(0),
JPEG_POS = pos_t(1),
RNG_POS = pos_t(6),
OTGFS_POS = pos_t(7);
using bits_t = Bits<uint32_t, Ahb2enr>;
static constexpr bits_t DCMI = bits_t(1, DCMI_POS ),
JPEG = bits_t(1, JPEG_POS ),
RNG = bits_t(1, RNG_POS ),
OTGFS = bits_t(1, OTGFS_POS );
}; // struct Ahb2enr
using ahb2enr_t = Reg<uint32_t, Ahb2enr>;
ahb2enr_t ahb2enr;
struct Ahb3enr {
using pos_t = Pos<uint32_t, Ahb3enr>;
static constexpr pos_t FMC_POS = pos_t(0),
QSPI_POS = pos_t(1);
using bits_t = Bits<uint32_t, Ahb3enr>;
static constexpr bits_t FMC = bits_t(1, FMC_POS ),
QSPI = bits_t(1, QSPI_POS );
}; // struct Ahb3enr
using ahb3enr_t = Reg<uint32_t, Ahb3enr>;
ahb3enr_t ahb3enr;
private: uint32_t _reserved2; public:
struct Apb1enr {
using pos_t = Pos<uint32_t, Apb1enr>;
static constexpr pos_t TIM2_POS = pos_t( 0),
TIM3_POS = pos_t( 1),
TIM4_POS = pos_t( 2),
TIM5_POS = pos_t( 3),
TIM6_POS = pos_t( 4),
TIM7_POS = pos_t( 5),
TIM12_POS = pos_t( 6),
TIM13_POS = pos_t( 7),
TIM14_POS = pos_t( 8),
LPTIM1_POS = pos_t( 9),
RTC_POS = pos_t(10),
WWDG_POS = pos_t(11),
CAN3_POS = pos_t(13),
SPI2_POS = pos_t(14),
SPI3_POS = pos_t(15),
SPDIFRX_POS = pos_t(16),
USART2_POS = pos_t(17),
USART3_POS = pos_t(18),
UART4_POS = pos_t(19),
UART5_POS = pos_t(20),
I2C1_POS = pos_t(21),
I2C2_POS = pos_t(22),
I2C3_POS = pos_t(23),
I2C4_POS = pos_t(24),
CAN1_POS = pos_t(25),
CAN2_POS = pos_t(26),
CEC_POS = pos_t(27),
PWR_POS = pos_t(28),
DAC_POS = pos_t(29),
UART7_POS = pos_t(30),
UART8_POS = pos_t(31);
using bits_t = Bits<uint32_t, Apb1enr>;
static constexpr bits_t TIM2 = bits_t(1, TIM2_POS ),
TIM3 = bits_t(1, TIM3_POS ),
TIM4 = bits_t(1, TIM4_POS ),
TIM5 = bits_t(1, TIM5_POS ),
TIM6 = bits_t(1, TIM6_POS ),
TIM7 = bits_t(1, TIM7_POS ),
TIM12 = bits_t(1, TIM12_POS ),
TIM13 = bits_t(1, TIM13_POS ),
TIM14 = bits_t(1, TIM14_POS ),
LPTIM1 = bits_t(1, LPTIM1_POS ),
RTC = bits_t(1, RTC_POS ),
WWDG = bits_t(1, WWDG_POS ),
CAN3 = bits_t(1, CAN3_POS ),
SPI2 = bits_t(1, SPI2_POS ),
SPI3 = bits_t(1, SPI3_POS ),
SPDIFRX = bits_t(1, SPDIFRX_POS ),
USART2 = bits_t(1, USART2_POS ),
USART3 = bits_t(1, USART3_POS ),
UART4 = bits_t(1, UART4_POS ),
UART5 = bits_t(1, UART5_POS ),
I2C1 = bits_t(1, I2C1_POS ),
I2C2 = bits_t(1, I2C2_POS ),
I2C3 = bits_t(1, I2C3_POS ),
I2C4 = bits_t(1, I2C4_POS ),
CAN1 = bits_t(1, CAN1_POS ),
CAN2 = bits_t(1, CAN2_POS ),
CEC = bits_t(1, CEC_POS ),
PWR = bits_t(1, PWR_POS ),
DAC = bits_t(1, DAC_POS ),
UART7 = bits_t(1, UART7_POS ),
UART8 = bits_t(1, UART8_POS );
}; // struct Apb1enr
using apb1enr_t = Reg<uint32_t, Apb1enr>;
apb1enr_t apb1enr;
struct Apb2enr {
using pos_t = Pos<uint32_t, Apb2enr>;
static constexpr pos_t TIM1_POS = pos_t( 0),
TIM8_POS = pos_t( 1),
USART1_POS = pos_t( 4),
USART6_POS = pos_t( 5),
SDMMC2_POS = pos_t( 7),
ADC1_POS = pos_t( 8),
ADC2_POS = pos_t( 9),
ADC3_POS = pos_t(10),
SDMMC1_POS = pos_t(11),
SPI1_POS = pos_t(12),
SPI4_POS = pos_t(13),
SYSCFG_POS = pos_t(14),
TIM9_POS = pos_t(16),
TIM10_POS = pos_t(17),
TIM11_POS = pos_t(18),
SPI5_POS = pos_t(20),
SPI6_POS = pos_t(21),
SAI1_POS = pos_t(22),
SAI2_POS = pos_t(23),
LTDC_POS = pos_t(26),
DFSDM1_POS = pos_t(29),
MDIO_POS = pos_t(30);
using bits_t = Bits<uint32_t, Apb2enr>;
static constexpr bits_t TIM1 = bits_t(1, TIM1_POS ),
TIM8 = bits_t(1, TIM8_POS ),
USART1 = bits_t(1, USART1_POS ),
USART6 = bits_t(1, USART6_POS ),
SDMMC2 = bits_t(1, SDMMC2_POS ),
ADC1 = bits_t(1, ADC1_POS ),
ADC2 = bits_t(1, ADC2_POS ),
ADC3 = bits_t(1, ADC3_POS ),
SDMMC1 = bits_t(1, SDMMC1_POS ),
SPI1 = bits_t(1, SPI1_POS ),
SPI4 = bits_t(1, SPI4_POS ),
SYSCFG = bits_t(1, SYSCFG_POS ),
TIM9 = bits_t(1, TIM9_POS ),
TIM10 = bits_t(1, TIM10_POS ),
TIM11 = bits_t(1, TIM11_POS ),
SPI5 = bits_t(1, SPI5_POS ),
SPI6 = bits_t(1, SPI6_POS ),
SAI1 = bits_t(1, SAI1_POS ),
SAI2 = bits_t(1, SAI2_POS ),
LTDC = bits_t(1, LTDC_POS ),
DFSDM1 = bits_t(1, DFSDM1_POS ),
MDIO = bits_t(1, MDIO_POS );
}; // struct Apb2enr
using apb2enr_t = Reg<uint32_t, Apb2enr>;
apb2enr_t apb2enr;
private: uint32_t _reserved3[2]; public:
struct Ahb1lpenr {
using pos_t = Pos<uint32_t, Ahb1lpenr>;
static constexpr pos_t GPIOALP_POS = pos_t( 0),
GPIOBLP_POS = pos_t( 1),
GPIOCLP_POS = pos_t( 2),
GPIODLP_POS = pos_t( 3),
GPIOELP_POS = pos_t( 4),
GPIOFLP_POS = pos_t( 5),
GPIOGLP_POS = pos_t( 6),
GPIOHLP_POS = pos_t( 7),
GPIOILP_POS = pos_t( 8),
GPIOJLP_POS = pos_t( 9),
GPIOKLP_POS = pos_t(10),
CRCLP_POS = pos_t(12),
AXILP_POS = pos_t(13),
FLITFLP_POS = pos_t(15),
SRAM1LP_POS = pos_t(16),
SRAM2LP_POS = pos_t(17),
BKPSRAMLP_POS = pos_t(18),
DTCMLP_POS = pos_t(20),
DMA1LP_POS = pos_t(21),
DMA2LP_POS = pos_t(22),
DMA2DLP_POS = pos_t(23),
ETHMACLP_POS = pos_t(25),
ETHMACTXLP_POS = pos_t(26),
ETHMACRXLP_POS = pos_t(27),
ETHMACPTPLP_POS = pos_t(28),
OTGHSLP_POS = pos_t(29),
OTGHSULPILP_POS = pos_t(30);
using bits_t = Bits<uint32_t, Ahb1lpenr>;
static constexpr bits_t GPIOALP = bits_t(1, GPIOALP_POS ),
GPIOBLP = bits_t(1, GPIOBLP_POS ),
GPIOCLP = bits_t(1, GPIOCLP_POS ),
GPIODLP = bits_t(1, GPIODLP_POS ),
GPIOELP = bits_t(1, GPIOELP_POS ),
GPIOFLP = bits_t(1, GPIOFLP_POS ),
GPIOGLP = bits_t(1, GPIOGLP_POS ),
GPIOHLP = bits_t(1, GPIOHLP_POS ),
GPIOILP = bits_t(1, GPIOILP_POS ),
GPIOJLP = bits_t(1, GPIOJLP_POS ),
GPIOKLP = bits_t(1, GPIOKLP_POS ),
CRCLP = bits_t(1, CRCLP_POS ),
AXILP = bits_t(1, AXILP_POS ),
FLITFLP = bits_t(1, FLITFLP_POS ),
SRAM1LP = bits_t(1, SRAM1LP_POS ),
SRAM2LP = bits_t(1, SRAM2LP_POS ),
BKPSRAMLP = bits_t(1, BKPSRAMLP_POS ),
DTCMLP = bits_t(1, DTCMLP_POS ),
DMA1LP = bits_t(1, DMA1LP_POS ),
DMA2LP = bits_t(1, DMA2LP_POS ),
DMA2DLP = bits_t(1, DMA2DLP_POS ),
ETHMACLP = bits_t(1, ETHMACLP_POS ),
ETHMACTXLP = bits_t(1, ETHMACTXLP_POS ),
ETHMACRXLP = bits_t(1, ETHMACRXLP_POS ),
ETHMACPTPLP = bits_t(1, ETHMACPTPLP_POS),
OTGHSLP = bits_t(1, OTGHSLP_POS ),
OTGHSULPILP = bits_t(1, OTGHSULPILP_POS);
}; // struct Ahb1lpenr
using ahb1lpenr_t = Reg<uint32_t, Ahb1lpenr>;
ahb1lpenr_t ahb1lpenr;
struct Ahb2lpenr {
using pos_t = Pos<uint32_t, Ahb2lpenr>;
static constexpr pos_t DCMILP_POS = pos_t(0),
JPEGLP_POS = pos_t(1),
RNGLP_POS = pos_t(6),
OTGFSLP_POS = pos_t(7);
using bits_t = Bits<uint32_t, Ahb2lpenr>;
static constexpr bits_t DCMILP = bits_t(1, DCMILP_POS ),
JPEGLP = bits_t(1, JPEGLP_POS ),
RNGLP = bits_t(1, RNGLP_POS ),
OTGFSLP = bits_t(1, OTGFSLP_POS );
}; // struct Ahb2lpenr
using ahb2lpenr_t = Reg<uint32_t, Ahb2lpenr>;
ahb2lpenr_t ahb2lpenr;
struct Ahb3lpenr {
using pos_t = Pos<uint32_t, Ahb3lpenr>;
static constexpr pos_t FMCLPEN_POS = pos_t( 0),
QSPILPEN_POS = pos_t( 1);
using bits_t = Bits<uint32_t, Ahb3lpenr>;
static constexpr bits_t FMCLPEN = bits_t(1, FMCLPEN_POS),
QSPILPEN = bits_t(1, QSPILPEN_POS);
}; // struct Ahb3lpenr
using Ahb3lpenr_t = Reg<uint32_t, Ahb3lpenr>;
Ahb3lpenr_t Ahb3lpenr;
private: uint32_t _reserved4; public:
struct Apb1lpenr {
using pos_t = Pos<uint32_t, Apb1lpenr>;
static constexpr pos_t FMCLP_POS = pos_t( 0),
QSPILP_POS = pos_t( 1),
TIM2LP_POS = pos_t( 0),
TIM3LP_POS = pos_t( 1),
TIM4LP_POS = pos_t( 2),
TIM5LP_POS = pos_t( 3),
TIM6LP_POS = pos_t( 4),
TIM7LP_POS = pos_t( 5),
TIM12LP_POS = pos_t( 6),
TIM13LP_POS = pos_t( 7),
TIM14LP_POS = pos_t( 8),
LPTIM1LP_POS = pos_t( 9),
RTCLP_POS = pos_t(10),
WWDGLP_POS = pos_t(11),
CAN3LP_POS = pos_t(13),
SPI2LP_POS = pos_t(14),
SPI3LP_POS = pos_t(15),
SPDIFRXLP_POS = pos_t(16),
USART2LP_POS = pos_t(17),
USART3LP_POS = pos_t(18),
UART4LP_POS = pos_t(19),
UART5LP_POS = pos_t(20),
I2C1LP_POS = pos_t(21),
I2C2LP_POS = pos_t(22),
I2C3LP_POS = pos_t(23),
I2C4LP_POS = pos_t(24),
CAN1LP_POS = pos_t(25),
CAN2LP_POS = pos_t(26),
CECLP_POS = pos_t(27),
PWRLP_POS = pos_t(28),
DACLP_POS = pos_t(29),
UART7LP_POS = pos_t(30),
UART8LP_POS = pos_t(31);
using bits_t = Bits<uint32_t, Apb1lpenr>;
static constexpr bits_t FMCLP = bits_t(1, FMCLP_POS ),
QSPILP = bits_t(1, QSPILP_POS ),
TIM2LP = bits_t(1, TIM2LP_POS ),
TIM3LP = bits_t(1, TIM3LP_POS ),
TIM4LP = bits_t(1, TIM4LP_POS ),
TIM5LP = bits_t(1, TIM5LP_POS ),
TIM6LP = bits_t(1, TIM6LP_POS ),
TIM7LP = bits_t(1, TIM7LP_POS ),
TIM12LP = bits_t(1, TIM12LP_POS ),
TIM13LP = bits_t(1, TIM13LP_POS ),
TIM14LP = bits_t(1, TIM14LP_POS ),
LPTIM1LP = bits_t(1, LPTIM1LP_POS),
RTCLP = bits_t(1, RTCLP_POS ),
WWDGLP = bits_t(1, WWDGLP_POS ),
CAN3LP = bits_t(1, CAN3LP_POS ),
SPI2LP = bits_t(1, SPI2LP_POS ),
SPI3LP = bits_t(1, SPI3LP_POS ),
SPDIFRXLP = bits_t(1, SPDIFRXLP_POS),
USART2LP = bits_t(1, USART2LP_POS),
USART3LP = bits_t(1, USART3LP_POS),
UART4LP = bits_t(1, UART4LP_POS ),
UART5LP = bits_t(1, UART5LP_POS ),
I2C1LP = bits_t(1, I2C1LP_POS ),
I2C2LP = bits_t(1, I2C2LP_POS ),
I2C3LP = bits_t(1, I2C3LP_POS ),
I2C4LP = bits_t(1, I2C4LP_POS ),
CAN1LP = bits_t(1, CAN1LP_POS ),
CAN2LP = bits_t(1, CAN2LP_POS ),
CECLP = bits_t(1, CECLP_POS ),
PWRLP = bits_t(1, PWRLP_POS ),
DACLP = bits_t(1, DACLP_POS ),
UART7LP = bits_t(1, UART7LP_POS ),
UART8LP = bits_t(1, UART8LP_POS );
}; // struct Apb1lpenr
using apb1lpenr_t = Reg<uint32_t, Apb1lpenr>;
apb1lpenr_t apb1lpenr;
struct Apb2lpenr {
using pos_t = Pos<uint32_t, Apb2lpenr>;
static constexpr pos_t TIM1LP_POS = pos_t( 0),
TIM8LP_POS = pos_t( 1),
USART1LP_POS = pos_t( 4),
USART6LP_POS = pos_t( 5),
SDMMC2LP_POS = pos_t( 7),
ADC1LP_POS = pos_t( 8),
ADC2LP_POS = pos_t( 9),
ADC3LP_POS = pos_t(10),
SDMMC1LP_POS = pos_t(11),
SPI1LP_POS = pos_t(12),
SPI4LP_POS = pos_t(13),
SYSCFGLP_POS = pos_t(14),
TIM9LP_POS = pos_t(16),
TIM10LP_POS = pos_t(17),
TIM11LP_POS = pos_t(18),
SPI5LP_POS = pos_t(20),
SPI6LP_POS = pos_t(21),
SAI1LP_POS = pos_t(22),
SAI2LP_POS = pos_t(23),
LTDCLP_POS = pos_t(26),
DFSDM1LP_POS = pos_t(29),
MDIOLP_POS = pos_t(30);
using bits_t = Bits<uint32_t, Apb2lpenr>;
static constexpr bits_t TIM1LP = bits_t(1, TIM1LP_POS ),
TIM8LP = bits_t(1, TIM8LP_POS ),
USART1LP = bits_t(1, USART1LP_POS),
USART6LP = bits_t(1, USART6LP_POS),
SDMMC2LP = bits_t(1, SDMMC2LP_POS),
ADC1LP = bits_t(1, ADC1LP_POS ),
ADC2LP = bits_t(1, ADC2LP_POS ),
ADC3LP = bits_t(1, ADC3LP_POS ),
SDMMC1LP = bits_t(1, SDMMC1LP_POS),
SPI1LP = bits_t(1, SPI1LP_POS ),
SPI4LP = bits_t(1, SPI4LP_POS ),
SYSCFGLP = bits_t(1, SYSCFGLP_POS),
TIM9LP = bits_t(1, TIM9LP_POS ),
TIM10LP = bits_t(1, TIM10LP_POS ),
TIM11LP = bits_t(1, TIM11LP_POS ),
SPI5LP = bits_t(1, SPI5LP_POS ),
SPI6LP = bits_t(1, SPI6LP_POS ),
SAI1LP = bits_t(1, SAI1LP_POS ),
SAI2LP = bits_t(1, SAI2LP_POS ),
LTDCLP = bits_t(1, LTDCLP_POS ),
DFSDM1LP = bits_t(1, DFSDM1LP_POS),
MDIOLP = bits_t(1, MDIOLP_POS );
}; // struct Apb2lpenr
using apb2lpenr_t = Reg<uint32_t, Apb2lpenr>;
apb2lpenr_t apb2lpenr;
private: uint32_t _reserved5[2]; public:
struct Bdcr {
using pos_t = Pos<uint32_t, Bdcr>;
static constexpr pos_t LSEON_POS = pos_t( 0),
LSERDY_POS = pos_t( 1),
LSEBYP_POS = pos_t( 2),
LSEDRV_POS = pos_t( 3),
RTCSEL_POS = pos_t( 8),
RTC_POS = pos_t(15),
BD_POS = pos_t(16);
using bits_t = Bits<uint32_t, Bdcr>;
static constexpr bits_t LSEON = bits_t(1, LSEON_POS ),
LSERDY = bits_t(1, LSERDY_POS ),
LSEBYP = bits_t(1, LSEBYP_POS ),
RTC = bits_t(1, RTC_POS ),
BD = bits_t(1, BD_POS );
static const uint32_t LSEDRV_MASK = 0b11,
RTCSEL_MASK = 0b11;
using mskd_t = Mskd<uint32_t, Bdcr>;
static constexpr mskd_t
LSEDRV_LOW = mskd_t(LSEDRV_MASK, 0b00, LSEDRV_POS),
LSEDRV_MEDHI = mskd_t(LSEDRV_MASK, 0b01, LSEDRV_POS),