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mypoke should not assume PHY capabilities struct to be 0xC long #4
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The machine powered off and on, had no effect. |
HOLY SHIT I'M SO LUCKY! Your code assumes PHY capabilities struct to be 0xC long, which does not hold true to my NIC(mine has 0xD), so only the first word is written to the right location. My NIC can power up and respond to ioctl after power cycle (lucky!), so I corrected wrong written values and re-applied the poke, this time it works. |
@feisuzhu I think you first who successfully unlocked 6.0 firmware. It will be nice, if you write here manual with changes (like [original](https://www.mail-archive.com/[email protected]/msg11459.html from @terpstra) or submit a patch if it necessary for covering work with newest firmware. |
does not work: 000068f0 + 00 => 000c 68fd, 690a, 6917 - the same srv# lspci | grep 710 srv# ethtool -i enp4s0f0 [ 78.911299] i40e 0000:04:00.3: Rx/Tx is disabled on this device because an unsupported SFP+ module type was detected. |
@feisuzhu Any insight you can share here? I got as far as above and got the PHY but I don't get how you fixed it finally by saying you used 0xd instead of 0xc? From what I found we use the same card, so any help would be appreciated! |
@hawaiik https://github.com/terpstra/xl710-unlocker/blob/master/mypoke.c#L60 |
So in line 60 of mypoke you just changed to ? |
@hawaiik Yes, and please don't follow my experience blindly, confirm yourself. |
@feisuzhu Alright, thank you for the headsup, I will take a look. |
It seems Intel changed some stuff again....I was not able to unlock the card so far..... |
@feisuzhu I can confirm that patching a card with nvram layout like you described in the ticked worked fine for me. Ie struct start position 0x68f6 and struct offset 0xD. |
Hello,
For reference,
Thanks for the awesome work and keep'em coming :D |
I seem to have a bit newer version of firmware 7.10. The target was at
|
@presslab-us |
Turned out offset 3 wasn't allowing LR4 modules. The unlock had already worked Changed from altering offset 0x8 to 0x3 and stuffed it with 0x0700 enabling 40GBASE-LR4, 40GBASE-SR4 & 40GBASE-CR4 |
I have the X710-DA4 with four SFP+ ports. I also have added all pertinent options to register 0x3. But even still, this card is very picky. If a module advertises in it's EEPROM "transceiver compliance codes" that it supports Fiber Channel (in addition to the normal Ethernet one) it won't work. I have edited the EEPROM to remove the Fiber Channel codes and then it is accepted. |
This seems like the most active thread here. Just wanted to update that I got this working on 8.4
My offset was 0x6947and instead of 0x8, the register with bit 11 was on 0x1. So I changed line 46 to this: int offset = 2*(phy0_offset + 0x1) My original value on 0x1 was 6b0c, which I set to 630c on line 63, to turn off bit 11. It took a while to figure this out, but once I did, the unsupported SFPs are working perfectly. |
Hello andrewohanian, On my machine, the firmware version of the XL710 drivers is 8.15 ethtool -i enp23s0f3 Can you elaborate what is the nature of the patch that needs to be made ? F. |
Alright, I now run: ./mytool 0 0x8000 |grep 000d 00000000 + 693a => 000d Then I do: ./mytool 0x693a I get: 0000693a + 00 => 000d That looks like a legit structure, with 0022, followed by 0083... the issue is at +08, the value is already at 630C ... yet DMESG says: [ 5434.690412] i40e 0000:17:00.3 enp23s0f3: NIC Link is Up, 10 Gbps Full Duplex, Flow Control: None So I do not see where is the Bit 11 to change ... since the value is already 630c at +08 What I am not getting here ? |
Hello @fmenard123 ! |
I have not. I since found a server with a built in switch that attaches to trace lines on a xeon—d built-in phy. I’ve successfully got something working. What kind of transceivers are you using ?
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Hello @fmenard123<https://github.com/fmenard123> !
I've ran into same issue, have you succeed to solve this?
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@fmenard123 D-Link DEM-CB300S DAC cable |
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