From e349f305d00e6222285fa4e285b183f14202bb40 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Fri, 31 May 2024 11:55:59 +0200 Subject: [PATCH 1/6] [rtl,sim] top: add new XBUS tag signal port --- rtl/core/neorv32_package.vhd | 3 ++- rtl/core/neorv32_top.vhd | 6 ++++-- sim/neorv32_tb.vhd | 1 + sim/simple/neorv32_tb.simple.vhd | 1 + 4 files changed, 8 insertions(+), 3 deletions(-) diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index 3319d5924..18db675cc 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -29,7 +29,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090905"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01090906"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width @@ -817,6 +817,7 @@ package neorv32_package is -- External bus interface (available if XBUS_EN = true) -- xbus_adr_o : out std_ulogic_vector(31 downto 0); xbus_dat_o : out std_ulogic_vector(31 downto 0); + xbus_tag_o : out std_ulogic_vector(2 downto 0); xbus_we_o : out std_ulogic; xbus_sel_o : out std_ulogic_vector(3 downto 0); xbus_stb_o : out std_ulogic; diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd index 2efb13b15..ba1e18d68 100644 --- a/rtl/core/neorv32_top.vhd +++ b/rtl/core/neorv32_top.vhd @@ -148,6 +148,7 @@ entity neorv32_top is -- External bus interface (available if XBUS_EN = true) -- xbus_adr_o : out std_ulogic_vector(31 downto 0); -- address xbus_dat_o : out std_ulogic_vector(31 downto 0); -- write data + xbus_tag_o : out std_ulogic_vector(2 downto 0); -- access tag xbus_we_o : out std_ulogic; -- read/write xbus_sel_o : out std_ulogic_vector(3 downto 0); -- byte enable xbus_stb_o : out std_ulogic; -- strobe @@ -643,7 +644,7 @@ begin port map ( clk_i => clk_i, rstn_i => rstn_sys, - a_lock_i => '0', -- no exclusive accesses for port A + a_lock_i => '0', -- no exclusive accesses for port A a_req_i => dcache_req, -- prioritized a_rsp_o => dcache_rsp, b_req_i => icache_req, @@ -686,7 +687,7 @@ begin port map ( clk_i => clk_i, rstn_i => rstn_sys, - a_lock_i => '0', -- no exclusive accesses for port A + a_lock_i => '0', -- no exclusive accesses for port A a_req_i => core_req, -- prioritized a_rsp_o => core_rsp, b_req_i => dma_req, @@ -948,6 +949,7 @@ begin xbus_adr_o => xbus_adr_o, xbus_dat_i => xbus_dat_i, xbus_dat_o => xbus_dat_o, + xbus_tag_o => xbus_tag_o, xbus_we_o => xbus_we_o, xbus_sel_o => xbus_sel_o, xbus_stb_o => xbus_stb_o, diff --git a/sim/neorv32_tb.vhd b/sim/neorv32_tb.vhd index 2ae37c837..4b94d9a73 100644 --- a/sim/neorv32_tb.vhd +++ b/sim/neorv32_tb.vhd @@ -295,6 +295,7 @@ begin -- External bus interface (available if XBUS_EN = true) -- xbus_adr_o => wb_cpu.addr, -- address xbus_dat_o => wb_cpu.wdata, -- write data + xbus_tag_o => open, -- access tag xbus_we_o => wb_cpu.we, -- read/write xbus_sel_o => wb_cpu.sel, -- byte enable xbus_stb_o => wb_cpu.stb, -- strobe diff --git a/sim/simple/neorv32_tb.simple.vhd b/sim/simple/neorv32_tb.simple.vhd index 9aa94d647..49b50b49f 100644 --- a/sim/simple/neorv32_tb.simple.vhd +++ b/sim/simple/neorv32_tb.simple.vhd @@ -271,6 +271,7 @@ begin -- External bus interface (available if XBUS_EN = true) -- xbus_adr_o => wb_cpu.addr, -- address xbus_dat_o => wb_cpu.wdata, -- write data + xbus_tag_o => open, -- access tag xbus_we_o => wb_cpu.we, -- read/write xbus_sel_o => wb_cpu.sel, -- byte enable xbus_stb_o => wb_cpu.stb, -- strobe From 6e12ba1353dda607dac63f40368a6be6a9b9311e Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Fri, 31 May 2024 12:43:08 +0200 Subject: [PATCH 2/6] [xbus] add AxPROT-compatible access status signal --- rtl/core/neorv32_xbus.vhd | 2 ++ 1 file changed, 2 insertions(+) diff --git a/rtl/core/neorv32_xbus.vhd b/rtl/core/neorv32_xbus.vhd index bf3d994e6..6e5d5de39 100644 --- a/rtl/core/neorv32_xbus.vhd +++ b/rtl/core/neorv32_xbus.vhd @@ -31,6 +31,7 @@ entity neorv32_xbus is xbus_adr_o : out std_ulogic_vector(31 downto 0); -- address xbus_dat_i : in std_ulogic_vector(31 downto 0); -- read data xbus_dat_o : out std_ulogic_vector(31 downto 0); -- write data + xbus_tag_o : out std_ulogic_vector(2 downto 0); -- access tag xbus_we_o : out std_ulogic; -- read/write xbus_sel_o : out std_ulogic_vector(3 downto 0); -- byte enable xbus_stb_o : out std_ulogic; -- strobe @@ -122,6 +123,7 @@ begin xbus_sel_o <= bus_req.ben; xbus_stb_o <= bus_req.stb; xbus_cyc_o <= bus_req.stb or pending; + xbus_tag_o <= bus_req.src & '0' & bus_req.priv; -- instr/data, secure, privileged/unprivileged -- response gating -- bus_rsp.data <= xbus_dat_i when (pending = '1') and (bus_rw = '0') else (others => '0'); -- no read-back if READ operation From 7baed67ac090d488c3cd1538da9b1728d6bbb257 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Fri, 31 May 2024 12:47:05 +0200 Subject: [PATCH 3/6] [changelog] add v1.9.9.6 --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index d64444d60..fbcd607de 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date | Version | Comment | Ticket | |:----:|:-------:|:--------|:------:| +| 31.05.2024 | 1.9.9.6 | add "tag" signal to XBUS to provide additional access information (compatible to the AXI4 _ARPROT_ and _AWPROT_ signals) | [#917](https://github.com/stnolting/neorv32/pull/917) | | 30.05.2024 | 1.9.9.5 | :bug: fix uncached-vs-cached memory accesses (do not interrupt cache bursts by direct/uncached memory accesses) | [#915](https://github.com/stnolting/neorv32/pull/915) | | 29.05.2024 | 1.9.9.4 | Vivado IP block: add resizing ports for GPIOs, XIRQs and PWM; split size configuration for GPIO inputs and outputs | [#913](https://github.com/stnolting/neorv32/pull/913) | | 27.05.2024 | 1.9.9.3 | removed `XIRQ_TRIGGER_*` generics; XIRQ trigger type is now _programmable_ by dedicated configuration registers | [#911](https://github.com/stnolting/neorv32/pull/911) | From 4b3fc47bd2968ad145e315653121ece702790c90 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Fri, 31 May 2024 12:47:14 +0200 Subject: [PATCH 4/6] [docs] add new top signal --- docs/datasheet/soc.adoc | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc index 5cfaae80a..b6afa953d 100644 --- a/docs/datasheet/soc.adoc +++ b/docs/datasheet/soc.adoc @@ -86,15 +86,16 @@ Some interfaces (like the TWI and the 1-Wire bus) require tri-state drivers in t | `jtag_tdo_o` | 1 | out | - | serial data output | `jtag_tms_i` | 1 | in | `'L'` | mode select 5+^| **<<_processor_external_bus_interface_xbus>>** -| `xbus_adr_o` | 32 | out | - | destination address -| `xbus_dat_o` | 32 | out | - | read data -| `xbus_we_o` | 1 | out | - | write enable ('0' = read transfer) -| `xbus_sel_o` | 4 | out | - | byte enable -| `xbus_stb_o` | 1 | out | - | strobe -| `xbus_cyc_o` | 1 | out | - | valid cycle -| `xbus_dat_i` | 32 | in | `'L'` | write data -| `xbus_ack_i` | 1 | in | `'L'` | transfer acknowledge -| `xbus_err_i` | 1 | in | `'L'` | transfer error +| `xbus_adr_o` | 32 | out | - | destination address +| `xbus_dat_o` | 32 | out | - | read data +| `xbus_tag_o` | 3 | out | - | access tag +| `xbus_we_o` | 1 | out | - | write enable ('0' = read transfer) +| `xbus_sel_o` | 4 | out | - | byte enable +| `xbus_stb_o` | 1 | out | - | strobe +| `xbus_cyc_o` | 1 | out | - | valid cycle +| `xbus_dat_i` | 32 | in | `'L'` | write data +| `xbus_ack_i` | 1 | in | `'L'` | transfer acknowledge +| `xbus_err_i` | 1 | in | `'L'` | transfer error 5+^| **<<_stream_link_interface_slink>>** | `slink_rx_dat_i` | 32 | in | `'L'` | RX data | `slink_rx_src_i` | 4 | in | `'L'` | RX source routing information From 5702eb0db3ad7703dcc9650cc6318bdb3c5b640b Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Fri, 31 May 2024 12:47:29 +0200 Subject: [PATCH 5/6] [docs] XBUS: add tag signal --- docs/datasheet/soc_xbus.adoc | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/docs/datasheet/soc_xbus.adoc b/docs/datasheet/soc_xbus.adoc index d87366356..545b6dcda 100644 --- a/docs/datasheet/soc_xbus.adoc +++ b/docs/datasheet/soc_xbus.adoc @@ -9,12 +9,13 @@ | | neorv32_cache.vhd | Generic cache module | Software driver files: | none | _implicitly used_ | Top entity ports: | `xbus_adr_o` | address output (32-bit) -| | `xbus_dat_i` | data input (32-bit) | | `xbus_dat_o` | data output (32-bit) +| | `xbus_tag_o` | access tag (3-bit) | | `xbus_we_o` | write enable (1-bit) | | `xbus_sel_o` | byte enable (4-bit) | | `xbus_stb_o` | bus strobe (1-bit) | | `xbus_cyc_o` | valid cycle (1-bit) +| | `xbus_dat_i` | data input (32-bit) | | `xbus_ack_i` | acknowledge (1-bit) | | `xbus_err_i` | bus error (1-bit) | Configuration generics: | `XBUS_EN` | enable external bus interface when `true` @@ -94,6 +95,16 @@ by two cycles. Furthermore, all outgoing signals (like the address) will be kept being initiated. +**Access Tag** + +The XBUS tag signal `xbus_tag_o(0)` provides additional information about the current access cycle. +It compatible to the the AXI4 `ARPROT` and `AWPROT` signals. + +* `xbus_tag_o(0)` **P**: access is performed from **privileged** mode (machine-mode) when set +* `xbus_tag_o(1)` **NS**: this bit is hardwired to `0` indicating a **secure** access +* `xbus_tag_o(2)` **I**: access is an **instruction** fetch when set; access is a data access when cleared + + **External Bus Cache (X-CACHE)** The XBUS interface provides an optional internal cache that can be used to buffer processor-external accesses. From 2243e397d75b10d5c227f73d29db70f675e1cdcc Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Fri, 31 May 2024 12:55:51 +0200 Subject: [PATCH 6/6] [Vivado IP] add support for AxPROT signals --- rtl/system_integration/neorv32_vivado_ip.vhd | 24 ++++++++------------ 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/rtl/system_integration/neorv32_vivado_ip.vhd b/rtl/system_integration/neorv32_vivado_ip.vhd index 3bf0f21d2..100c6b473 100644 --- a/rtl/system_integration/neorv32_vivado_ip.vhd +++ b/rtl/system_integration/neorv32_vivado_ip.vhd @@ -256,8 +256,9 @@ architecture neorv32_vivado_ip_rtl of neorv32_vivado_ip is adr : std_ulogic_vector(31 downto 0); di : std_ulogic_vector(31 downto 0); do : std_ulogic_vector(31 downto 0); + tag : std_ulogic_vector(2 downto 0); we : std_ulogic; - sel : std_ulogic_vector(03 downto 0); + sel : std_ulogic_vector(3 downto 0); cyc : std_ulogic; ack : std_ulogic; err : std_ulogic; @@ -382,12 +383,13 @@ begin jtag_tms_i => jtag_tms_i, -- External bus interface (available if XBUS_EN = true) -- xbus_adr_o => wb_core.adr, - xbus_dat_i => wb_core.di, xbus_dat_o => wb_core.do, + xbus_tag_o => wb_core.tag, xbus_we_o => wb_core.we, xbus_sel_o => wb_core.sel, xbus_stb_o => open, xbus_cyc_o => wb_core.cyc, + xbus_dat_i => wb_core.di, xbus_ack_i => wb_core.ack, xbus_err_i => wb_core.err, -- Stream Link Interface (available if IO_SLINK_EN = true) -- @@ -495,25 +497,19 @@ begin axi_wadr_received <= '0'; axi_wdat_received <= '0'; elsif rising_edge(clk) then - if (wb_core.cyc = '0') then -- idle + if (wb_core.cyc = '0') then axi_radr_received <= '0'; axi_wadr_received <= '0'; axi_wdat_received <= '0'; - else -- busy - -- "read address received" flag -- - if (wb_core.we = '0') then -- pending READ + else -- pending access + if (wb_core.we = '0') then -- read if (m_axi_arready = '1') then -- read address received by interconnect? axi_radr_received <= '1'; end if; - end if; - -- "write address received" flag -- - if (wb_core.we = '1') then -- pending WRITE + else -- write if (m_axi_awready = '1') then -- write address received by interconnect? axi_wadr_received <= '1'; end if; - end if; - -- "write data received" flag -- - if (wb_core.we = '1') then -- pending WRITE if (m_axi_wready = '1') then -- write data received by interconnect? axi_wdat_received <= '1'; end if; @@ -526,7 +522,7 @@ begin -- read address channel -- m_axi_araddr <= wb_core.adr; m_axi_arvalid <= wb_core.cyc and (not wb_core.we) and (not axi_radr_received); - m_axi_arprot <= "000"; + m_axi_arprot <= wb_core.tag; -- read data channel -- m_axi_rready <= wb_core.cyc and (not wb_core.we); @@ -535,7 +531,7 @@ begin -- write address channel -- m_axi_awaddr <= wb_core.adr; m_axi_awvalid <= wb_core.cyc and wb_core.we and (not axi_wadr_received); - m_axi_awprot <= "000"; + m_axi_awprot <= wb_core.tag; -- write data channel -- m_axi_wdata <= wb_core.do;