From 2d219a498c94773a5c1f118b505666ff591ec430 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Sat, 11 Feb 2023 19:07:13 +0100 Subject: [PATCH 1/7] :warning: [rtl] GPIO: change generic to allow fine-tuning of #IOs --- rtl/core/neorv32_gpio.vhd | 62 +++++++++++++++++------------- rtl/core/neorv32_package.vhd | 73 +++++++++++++++++++----------------- rtl/core/neorv32_sysinfo.vhd | 34 ++++++++--------- rtl/core/neorv32_top.vhd | 19 ++++++---- 4 files changed, 101 insertions(+), 87 deletions(-) diff --git a/rtl/core/neorv32_gpio.vhd b/rtl/core/neorv32_gpio.vhd index 63e9ea247..144124d05 100644 --- a/rtl/core/neorv32_gpio.vhd +++ b/rtl/core/neorv32_gpio.vhd @@ -1,12 +1,9 @@ -- ################################################################################################# -- # << NEORV32 - General Purpose Parallel Input/Output Port (GPIO) >> # -- # ********************************************************************************************* # --- # 64-bit general purpose parallel input & output port unit. Input/outputs are split into two # --- # 32-bit memory-mapped registers each. # --- # ********************************************************************************************* # -- # BSD 3-Clause License # -- # # --- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # +-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. # -- # # -- # Redistribution and use in source and binary forms, with or without modification, are # -- # permitted provided that the following conditions are met: # @@ -43,6 +40,9 @@ library neorv32; use neorv32.neorv32_package.all; entity neorv32_gpio is + generic ( + GPIO_NUM : natural -- number of GPIO input/output pairs (0..64) + ); port ( -- host access -- clk_i : in std_ulogic; -- global clock line @@ -53,7 +53,6 @@ entity neorv32_gpio is data_i : in std_ulogic_vector(31 downto 0); -- data in data_o : out std_ulogic_vector(31 downto 0); -- data out ack_o : out std_ulogic; -- transfer acknowledge - err_o : out std_ulogic; -- transfer error -- parallel io -- gpio_o : out std_ulogic_vector(63 downto 0); gpio_i : in std_ulogic_vector(63 downto 0) @@ -73,11 +72,16 @@ architecture neorv32_gpio_rtl of neorv32_gpio is signal rden : std_ulogic; -- read enable -- accessible regs -- - signal din_hi, din_lo : std_ulogic_vector(31 downto 0); -- r/-: parallel input hi/lo - signal dout_hi, dout_lo : std_ulogic_vector(31 downto 0); -- r/w: parallel output hi/lo + signal din, din_rd, dout, dout_rd : std_ulogic_vector(63 downto 0); begin + -- Sanity Checks -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + assert not ((GPIO_NUM < 0) or (GPIO_NUM > 64)) report + "NEORV32 PROCESSOR CONFIG ERROR! Invalid GPIO pin number configuration (0..64)." severity error; + + -- Access Control ------------------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = gpio_base_c(hi_abb_c downto lo_abb_c)) else '0'; @@ -91,23 +95,19 @@ begin write_access: process(rstn_i, clk_i) begin if (rstn_i = '0') then - dout_lo <= (others => '0'); - dout_hi <= (others => '0'); + dout <= (others => '0'); elsif rising_edge(clk_i) then if (wren = '1') then if (addr = gpio_out_lo_addr_c) then - dout_lo <= data_i; + dout(31 downto 00) <= data_i; end if; if (addr = gpio_out_hi_addr_c) then - dout_hi <= data_i; + dout(63 downto 32) <= data_i; end if; end if; end if; end process write_access; - -- GPIO output -- - gpio_o <= dout_hi & dout_lo; - -- Read Access ---------------------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- @@ -115,29 +115,37 @@ begin begin if rising_edge(clk_i) then -- bus handshake -- - ack_o <= (wren and addr(3)) or rden; - err_o <= wren and (not addr(3)); -- INPUT registers are read only! + ack_o <= wren or rden; -- read data -- data_o <= (others => '0'); if (rden = '1') then case addr(3 downto 2) is - when "00" => data_o <= din_lo; - when "01" => data_o <= din_hi; - when "10" => data_o <= dout_lo; - when others => data_o <= dout_hi; + when "00" => data_o <= din_rd(31 downto 00); + when "01" => data_o <= din_rd(63 downto 32); + when "10" => data_o <= dout_rd(31 downto 00); + when others => data_o <= dout_rd(63 downto 32); end case; end if; end if; end process read_access; - -- sample buffer to prevent metastability -- - input_buffer: process (clk_i) + + -- Physical Pin Mapping ------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + pin_mapping: process(din, dout) begin - if rising_edge(clk_i) then - din_lo <= gpio_i(31 downto 00); - din_hi <= gpio_i(63 downto 32); - end if; - end process input_buffer; + -- defaults -- + din_rd <= (others => '0'); + dout_rd <= (others => '0'); + for i in 0 to GPIO_NUM-1 loop + din_rd(i) <= din(i); + dout_rd(i) <= dout(i); + end loop; + end process pin_mapping; + + -- IO -- + gpio_o <= dout_rd; + din <= gpio_i when rising_edge(clk_i); -- sample buffer to prevent metastability end neorv32_gpio_rtl; diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index 4a8e8498f..6a0173543 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -65,7 +65,7 @@ package neorv32_package is -- Architecture Constants (do not modify!) ------------------------------------------------ -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080005"; -- NEORV32 version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080006"; -- NEORV32 version constant archid_c : natural := 19; -- official RISC-V architecture ID -- Check if we're inside the Matrix ------------------------------------------------------- @@ -764,17 +764,17 @@ package neorv32_package is alu_opb_mux : std_ulogic; -- operand B select (0=rs2, 1=IMM) alu_unsigned : std_ulogic; -- is unsigned ALU operation alu_frm : std_ulogic_vector(02 downto 0); -- FPU rounding mode - alu_cp_trig : std_ulogic_vector(05 downto 0); -- trigger CP (one-hot) + alu_cp_trig : std_ulogic_vector(05 downto 0); -- co-processor trigger (one-hot) -- bus interface -- bus_req : std_ulogic; -- trigger memory request bus_mo_we : std_ulogic; -- memory address and data output register write enable bus_fence : std_ulogic; -- fence operation bus_fencei : std_ulogic; -- fence.i operation bus_priv : std_ulogic; -- effective privilege level for load/store - -- instruction word bit fields -- - ir_funct3 : std_ulogic_vector(02 downto 0); -- funct3 bit-field - ir_funct12 : std_ulogic_vector(11 downto 0); -- funct12 bit-field - ir_opcode : std_ulogic_vector(06 downto 0); -- opcode bit-field + -- instruction word -- + ir_funct3 : std_ulogic_vector(02 downto 0); -- funct3 bit field + ir_funct12 : std_ulogic_vector(11 downto 0); -- funct12 bit field + ir_opcode : std_ulogic_vector(06 downto 0); -- opcode bit field -- cpu status -- cpu_priv : std_ulogic; -- effective privilege mode cpu_sleep : std_ulogic; -- set when CPU is in sleep mode @@ -782,32 +782,33 @@ package neorv32_package is cpu_debug : std_ulogic; -- set when CPU is in debug mode end record; + -- control bus reset initializer -- constant ctrl_bus_zero_c : ctrl_bus_t := ( - rf_wb_en => '0', - rf_rs1 => (others => '0'), - rf_rs2 => (others => '0'), - rf_rs3 => (others => '0'), - rf_rd => (others => '0'), - rf_mux => (others => '0'), - rf_zero_we => '0', - alu_op => (others => '0'), - alu_opa_mux => '0', - alu_opb_mux => '0', - alu_unsigned => '0', - alu_frm => (others => '0'), - alu_cp_trig => (others => '0'), - bus_req => '0', - bus_mo_we => '0', - bus_fence => '0', - bus_fencei => '0', - bus_priv => '0', - ir_funct3 => (others => '0'), - ir_funct12 => (others => '0'), - ir_opcode => (others => '0'), - cpu_priv => '0', - cpu_sleep => '0', - cpu_trap => '0', - cpu_debug => '0' + rf_wb_en => '0', + rf_rs1 => (others => '0'), + rf_rs2 => (others => '0'), + rf_rs3 => (others => '0'), + rf_rd => (others => '0'), + rf_mux => (others => '0'), + rf_zero_we => '0', + alu_op => (others => '0'), + alu_opa_mux => '0', + alu_opb_mux => '0', + alu_unsigned => '0', + alu_frm => (others => '0'), + alu_cp_trig => (others => '0'), + bus_req => '0', + bus_mo_we => '0', + bus_fence => '0', + bus_fencei => '0', + bus_priv => '0', + ir_funct3 => (others => '0'), + ir_funct12 => (others => '0'), + ir_opcode => (others => '0'), + cpu_priv => '0', + cpu_sleep => '0', + cpu_trap => '0', + cpu_debug => '0' ); -- Comparator Bus ------------------------------------------------------------------------- @@ -1027,7 +1028,7 @@ package neorv32_package is XIRQ_TRIGGER_TYPE : std_ulogic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger type: 0=level, 1=edge XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge -- Processor peripherals -- - IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM : natural := 0; -- number of GPIO input/output pairs (0..64) IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)? IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 @@ -1091,7 +1092,7 @@ package neorv32_package is slink_rx_val_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- valid input slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive slink_rx_lst_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- last data of packet - -- GPIO (available if IO_GPIO_EN = true) -- + -- GPIO (available if IO_GPIO_NUM > 0) -- gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input -- primary UART0 (available if IO_UART0_EN = true) -- @@ -1704,6 +1705,9 @@ package neorv32_package is -- Component: General Purpose Input/Output Port (GPIO) ------------------------------------ -- ------------------------------------------------------------------------------------------- component neorv32_gpio + generic ( + GPIO_NUM : natural -- number of GPIO input/output pairs (0..64) + ); port ( -- host access -- clk_i : in std_ulogic; -- global clock line @@ -1714,7 +1718,6 @@ package neorv32_package is data_i : in std_ulogic_vector(31 downto 0); -- data in data_o : out std_ulogic_vector(31 downto 0); -- data out ack_o : out std_ulogic; -- transfer acknowledge - err_o : out std_ulogic; -- transfer error -- parallel io -- gpio_o : out std_ulogic_vector(63 downto 0); gpio_i : in std_ulogic_vector(63 downto 0) @@ -2154,7 +2157,7 @@ package neorv32_package is -- On-Chip Debugger -- ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD? -- Processor peripherals -- - IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM : natural; -- number of GPIO input/output pairs (0..64) IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)? IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)? diff --git a/rtl/core/neorv32_sysinfo.vhd b/rtl/core/neorv32_sysinfo.vhd index 6250cc5e6..86fe7b161 100644 --- a/rtl/core/neorv32_sysinfo.vhd +++ b/rtl/core/neorv32_sysinfo.vhd @@ -6,7 +6,7 @@ -- # ********************************************************************************************* # -- # BSD 3-Clause License # -- # # --- # Copyright (c) 2022, Stephan Nolting. All rights reserved. # +-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. # -- # # -- # Redistribution and use in source and binary forms, with or without modification, are # -- # permitted provided that the following conditions are met: # @@ -67,7 +67,7 @@ entity neorv32_sysinfo is -- On-Chip Debugger -- ON_CHIP_DEBUGGER_EN : boolean; -- implement OCD? -- Processor peripherals -- - IO_GPIO_EN : boolean; -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM : natural; -- number of GPIO input/output pairs (0..64) IO_MTIME_EN : boolean; -- implement machine system timer (MTIME)? IO_UART0_EN : boolean; -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_UART1_EN : boolean; -- implement secondary universal asynchronous receiver/transmitter (UART1)? @@ -146,22 +146,22 @@ begin -- sysinfo_mem(2)(15) <= '0'; -- reserved -- IO -- - sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_EN); -- general purpose input/output port unit (GPIO) implemented? - sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_EN); -- machine system timer (MTIME) implemented? - sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART0_EN); -- primary universal asynchronous receiver/transmitter (UART0) implemented? - sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_EN); -- serial peripheral interface (SPI) implemented? - sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_EN); -- two-wire interface (TWI) implemented? - sysinfo_mem(2)(21) <= bool_to_ulogic_f(boolean(IO_PWM_NUM_CH > 0)); -- pulse-width modulation unit (PWM) implemented? - sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_EN); -- watch dog timer (WDT) implemented? - sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFS_EN); -- custom functions subsystem (CFS) implemented? - sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_EN); -- true random number generator (TRNG) implemented? - sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_SLINK_EN); -- stream links (SLINK) implemented? - sysinfo_mem(2)(26) <= bool_to_ulogic_f(IO_UART1_EN); -- secondary universal asynchronous receiver/transmitter (UART1) implemented? - sysinfo_mem(2)(27) <= bool_to_ulogic_f(IO_NEOLED_EN); -- NeoPixel-compatible smart LED interface (NEOLED) implemented? + sysinfo_mem(2)(16) <= bool_to_ulogic_f(boolean(IO_GPIO_NUM > 0)); -- general purpose input/output port unit (GPIO) implemented? + sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_EN); -- machine system timer (MTIME) implemented? + sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART0_EN); -- primary universal asynchronous receiver/transmitter (UART0) implemented? + sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_EN); -- serial peripheral interface (SPI) implemented? + sysinfo_mem(2)(20) <= bool_to_ulogic_f(IO_TWI_EN); -- two-wire interface (TWI) implemented? + sysinfo_mem(2)(21) <= bool_to_ulogic_f(boolean(IO_PWM_NUM_CH > 0)); -- pulse-width modulation unit (PWM) implemented? + sysinfo_mem(2)(22) <= bool_to_ulogic_f(IO_WDT_EN); -- watch dog timer (WDT) implemented? + sysinfo_mem(2)(23) <= bool_to_ulogic_f(IO_CFS_EN); -- custom functions subsystem (CFS) implemented? + sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_EN); -- true random number generator (TRNG) implemented? + sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_SLINK_EN); -- stream links (SLINK) implemented? + sysinfo_mem(2)(26) <= bool_to_ulogic_f(IO_UART1_EN); -- secondary universal asynchronous receiver/transmitter (UART1) implemented? + sysinfo_mem(2)(27) <= bool_to_ulogic_f(IO_NEOLED_EN); -- NeoPixel-compatible smart LED interface (NEOLED) implemented? sysinfo_mem(2)(28) <= bool_to_ulogic_f(boolean(IO_XIRQ_NUM_CH > 0)); -- external interrupt controller (XIRQ) implemented? - sysinfo_mem(2)(29) <= bool_to_ulogic_f(IO_GPTMR_EN); -- general purpose timer (GPTMR) implemented? - sysinfo_mem(2)(30) <= bool_to_ulogic_f(IO_XIP_EN); -- execute in place module (XIP) implemented? - sysinfo_mem(2)(31) <= bool_to_ulogic_f(IO_ONEWIRE_EN); -- 1-wire interface (ONEWIRE) implemented? + sysinfo_mem(2)(29) <= bool_to_ulogic_f(IO_GPTMR_EN); -- general purpose timer (GPTMR) implemented? + sysinfo_mem(2)(30) <= bool_to_ulogic_f(IO_XIP_EN); -- execute in place module (XIP) implemented? + sysinfo_mem(2)(31) <= bool_to_ulogic_f(IO_ONEWIRE_EN); -- 1-wire interface (ONEWIRE) implemented? -- SYSINFO(3): Cache configuration -- sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes) diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd index 061ac4ee8..70e7bf22a 100644 --- a/rtl/core/neorv32_top.vhd +++ b/rtl/core/neorv32_top.vhd @@ -116,7 +116,7 @@ entity neorv32_top is XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge -- Processor peripherals -- - IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM : natural := 0; -- number of GPIO input/output pairs (0..64) IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)? IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 @@ -187,7 +187,7 @@ entity neorv32_top is slink_rx_rdy_o : out std_ulogic_vector(7 downto 0); -- ready to receive slink_rx_lst_i : in std_ulogic_vector(7 downto 0) := (others => 'L'); -- last data of packet - -- GPIO (available if IO_GPIO_EN = true) -- + -- GPIO (available if IO_GPIO_NUM > 0) -- gpio_o : out std_ulogic_vector(63 downto 0); -- parallel output gpio_i : in std_ulogic_vector(63 downto 0) := (others => 'U'); -- parallel input @@ -246,7 +246,7 @@ architecture neorv32_top_rtl of neorv32_top is constant dmem_align_check_c : std_ulogic_vector(index_size_f(MEM_INT_DMEM_SIZE)-1 downto 0) := (others => '0'); -- helpers -- - constant io_slink_en_c : boolean := boolean(SLINK_NUM_RX > 0) or boolean(SLINK_NUM_TX > 0); -- implement slink at all? + constant io_slink_en_c : boolean := boolean(SLINK_NUM_RX > 0) or boolean(SLINK_NUM_TX > 0); -- implement SLINK at all?` -- reset generator -- signal rstn_ext_sreg : std_ulogic_vector(3 downto 0); @@ -394,7 +394,7 @@ begin -- ------------------------------------------------------------------------------------------- assert false report "NEORV32 PROCESSOR CONFIG NOTE: Peripherals = " & - cond_sel_string_f(IO_GPIO_EN, "GPIO ", "") & + cond_sel_string_f(boolean(IO_GPIO_NUM > 0), "GPIO ", "") & cond_sel_string_f(IO_MTIME_EN, "MTIME ", "") & cond_sel_string_f(IO_UART0_EN, "UART0 ", "") & cond_sel_string_f(IO_UART1_EN, "UART1 ", "") & @@ -1055,8 +1055,11 @@ begin -- General Purpose Input/Output Port (GPIO) ----------------------------------------------- -- ------------------------------------------------------------------------------------------- neorv32_gpio_inst_true: - if (IO_GPIO_EN = true) generate + if (IO_GPIO_NUM > 0) generate neorv32_gpio_inst: neorv32_gpio + generic map ( + GPIO_NUM => IO_GPIO_NUM -- number of GPIO input/output pairs (0..64) + ) port map ( -- host access -- clk_i => clk_i, -- global clock line @@ -1067,15 +1070,15 @@ begin data_i => p_bus.wdata, -- data in data_o => resp_bus(RESP_GPIO).rdata, -- data out ack_o => resp_bus(RESP_GPIO).ack, -- transfer acknowledge - err_o => resp_bus(RESP_GPIO).err, -- transfer error -- parallel io -- gpio_o => gpio_o, gpio_i => gpio_i ); + resp_bus(RESP_GPIO).err <= '0'; -- no access error possible end generate; neorv32_gpio_inst_false: - if (IO_GPIO_EN = false) generate + if (IO_GPIO_NUM = 0) generate resp_bus(RESP_GPIO) <= resp_bus_entry_terminate_c; -- gpio_o <= (others => '0'); @@ -1627,7 +1630,7 @@ begin -- On-Chip Debugger -- ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement OCD? -- Processor peripherals -- - IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM => IO_GPIO_NUM, -- number of GPIO input/output pairs (0..64) IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)? From 4dc1b166d45d80c7a3de59477784c883863ee419 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Sat, 11 Feb 2023 19:08:07 +0100 Subject: [PATCH 2/7] [rtl, sim] update GPIO generic --- .../neorv32_ProcessorTop_Minimal.vhd | 1 - .../neorv32_ProcessorTop_MinimalBoot.vhd | 4 ++-- .../neorv32_ProcessorTop_UP5KDemo.vhd | 8 ++++---- rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd | 10 +++++----- rtl/system_integration/neorv32_SystemTop_axi4lite.vhd | 6 +++--- sim/neorv32_tb.vhd | 4 ++-- sim/simple/neorv32_tb.simple.vhd | 4 ++-- 7 files changed, 18 insertions(+), 19 deletions(-) diff --git a/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd b/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd index 920629efa..1520217a5 100644 --- a/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd +++ b/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd @@ -158,7 +158,6 @@ begin IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..60); 0 = disabled IO_WDT_EN => IO_WDT_EN -- implement watch dog timer (WDT)? - ) port map ( -- Global control -- diff --git a/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd b/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd index 630fed37d..66658bcfe 100644 --- a/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd +++ b/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd @@ -171,7 +171,7 @@ begin ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 -- Processor peripherals -- - IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM => IO_GPIO_NUM, -- number of GPIO input/output pairs (0..64) IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..60); 0 = disabled @@ -182,7 +182,7 @@ begin clk_i => clk_i, -- global clock, rising edge rstn_i => rstn_i, -- global reset, low-active, async - -- GPIO (available if IO_GPIO_EN = true) -- + -- GPIO (available if IO_GPIO_NUM > 0) -- gpio_o => con_gpio_o, -- parallel output gpio_i => (others => '0'), -- parallel input diff --git a/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd b/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd index b0d9a5d35..c40c7eab5 100644 --- a/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd +++ b/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd @@ -82,7 +82,7 @@ entity neorv32_ProcessorTop_UP5KDemo is ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 -- Processor peripherals -- - IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM : natural := 64; -- number of GPIO input/output pairs (0..64) IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)? @@ -94,7 +94,7 @@ entity neorv32_ProcessorTop_UP5KDemo is clk_i : in std_logic; rstn_i : in std_logic; - -- GPIO (available if IO_GPIO_EN = true) -- + -- GPIO (available if IO_GPIO_NUM > 0) -- gpio_i : in std_ulogic_vector(3 downto 0); gpio_o : out std_ulogic_vector(3 downto 0); @@ -211,7 +211,7 @@ begin ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 -- Processor peripherals -- - IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM => IO_GPIO_NUM, -- number of GPIO input/output pairs (0..64) IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)? @@ -224,7 +224,7 @@ begin clk_i => clk_i, -- global clock, rising edge rstn_i => rstn_i, -- global reset, low-active, async - -- GPIO (available if IO_GPIO_EN = true) -- + -- GPIO (available if IO_GPIO_NUM > 0) -- gpio_o => con_gpio_o, -- parallel output gpio_i => con_gpio_i, -- parallel input diff --git a/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd b/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd index b56963756..1c971cdd3 100644 --- a/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd +++ b/rtl/system_integration/neorv32_SystemTop_AvalonMM.vhd @@ -1,7 +1,7 @@ -- ################################################################################################# -- # << NEORV32 - Processor Top Entity with AvalonMM Compatible Master Interface >> # -- # ********************************************************************************************* # --- # (c) "AvalonMM", "NIOS-2", "Qsys", "MegaWizard" and "Platform Designer" # +-- # (c) "AvalonMM", "NIOS-2", "Qsys", "MegaWizard" and "Platform Designer" # -- # are trademarks of Intel # -- # ********************************************************************************************* # -- # BSD 3-Clause License # @@ -106,7 +106,7 @@ entity neorv32_top_avalonmm is XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"ffffffff"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge -- Processor peripherals -- - IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM : natural := 0; -- number of GPIO input/output pairs (0..64) IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)? IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 @@ -311,7 +311,7 @@ begin XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY, -- Processor peripherals -- - IO_GPIO_EN => IO_GPIO_EN, + IO_GPIO_NUM => IO_GPIO_NUM, IO_MTIME_EN => IO_MTIME_EN, IO_UART0_EN => IO_UART0_EN, IO_UART0_RX_FIFO => IO_UART0_RX_FIFO, @@ -429,7 +429,7 @@ begin msw_irq_i => msw_irq_i, mext_irq_i => mext_irq_i ); - + -- Wishbone to AvalonMM bridge read_o <= '1' when (wb_stb_o = '1' and wb_we_o = '0') else '0'; write_o <= '1' when (wb_stb_o = '1' and wb_we_o = '1') else '0'; @@ -440,5 +440,5 @@ begin wb_dat_i <= std_ulogic_vector(readdata_i); wb_ack_i <= not(waitrequest_i); wb_err_i <= '0'; - + end neorv32_top_avalonmm_rtl; diff --git a/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd b/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd index b157cce2d..395a1027a 100644 --- a/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd +++ b/rtl/system_integration/neorv32_SystemTop_axi4lite.vhd @@ -92,7 +92,7 @@ entity neorv32_SystemTop_axi4lite is XIRQ_TRIGGER_TYPE : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger type: 0=level, 1=edge XIRQ_TRIGGER_POLARITY : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge -- Processor peripherals -- - IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM : natural := 0; -- number of GPIO input/output pairs (0..64) IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 @@ -339,7 +339,7 @@ begin XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE_INT, -- trigger type: 0=level, 1=edge XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY_INT, -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge -- Processor peripherals -- - IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM => IO_GPIO_NUM, -- number of GPIO input/output pairs (0..64) IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_UART0_RX_FIFO => IO_UART0_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1 @@ -393,7 +393,7 @@ begin xip_clk_o => xip_clk_o_int, -- serial clock xip_sdi_i => xip_sdi_i_int, -- device data input xip_sdo_o => xip_sdo_o_int, -- controller data output - -- GPIO (available if IO_GPIO_EN = true) -- + -- GPIO (available if IO_GPIO_NUM > 0) -- gpio_o => gpio_o_int, -- parallel output gpio_i => gpio_i_int, -- parallel input -- primary UART0 (available if IO_UART0_EN = true) -- diff --git a/sim/neorv32_tb.vhd b/sim/neorv32_tb.vhd index 8fc88db42..4d223cc74 100644 --- a/sim/neorv32_tb.vhd +++ b/sim/neorv32_tb.vhd @@ -336,7 +336,7 @@ begin XIRQ_TRIGGER_TYPE => (others => '1'), -- trigger type: 0=level, 1=edge XIRQ_TRIGGER_POLARITY => (others => '1'), -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge -- Processor peripherals -- - IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM => 64, -- number of GPIO input/output pairs (0..64) IO_MTIME_EN => true, -- implement machine system timer (MTIME)? IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_UART0_RX_FIFO => 32, -- RX fifo depth, has to be a power of two, min 1 @@ -400,7 +400,7 @@ begin slink_rx_val_i => slink_val, -- valid input slink_rx_rdy_o => slink_rdy, -- ready to receive slink_rx_lst_i => slink_lst, -- last data of package - -- GPIO (available if IO_GPIO_EN = true) -- + -- GPIO (available if IO_GPIO_NUM > 0) -- gpio_o => gpio, -- parallel output gpio_i => gpio, -- parallel input -- primary UART0 (available if IO_UART0_EN = true) -- diff --git a/sim/simple/neorv32_tb.simple.vhd b/sim/simple/neorv32_tb.simple.vhd index c392e055c..54fef561e 100644 --- a/sim/simple/neorv32_tb.simple.vhd +++ b/sim/simple/neorv32_tb.simple.vhd @@ -227,7 +227,7 @@ begin XIRQ_TRIGGER_TYPE => (others => '1'), -- trigger type: 0=level, 1=edge XIRQ_TRIGGER_POLARITY => (others => '1'), -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge -- Processor peripherals -- - IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM => 64, -- number of GPIO input/output pairs (0..64) IO_MTIME_EN => true, -- implement machine system timer (MTIME)? IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_UART0_RX_FIFO => 32, -- RX fifo depth, has to be a power of two, min 1 @@ -291,7 +291,7 @@ begin slink_rx_val_i => slink_val, -- valid input slink_rx_rdy_o => slink_rdy, -- ready to receive slink_rx_lst_i => slink_lst, -- last data of package - -- GPIO (available if IO_GPIO_EN = true) -- + -- GPIO (available if IO_GPIO_NUM > true) -- gpio_o => gpio, -- parallel output gpio_i => gpio, -- parallel input -- primary UART0 (available if IO_UART0_EN = true) -- From 74cc86ad3d510bc173c2f88553c4f8c27abe25b8 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Sat, 11 Feb 2023 19:08:20 +0100 Subject: [PATCH 3/7] [rtl] remove std_logic wrapper --- .../neorv32_ProcessorTop_stdlogic.vhd | 517 ------------------ 1 file changed, 517 deletions(-) delete mode 100644 rtl/system_integration/neorv32_ProcessorTop_stdlogic.vhd diff --git a/rtl/system_integration/neorv32_ProcessorTop_stdlogic.vhd b/rtl/system_integration/neorv32_ProcessorTop_stdlogic.vhd deleted file mode 100644 index 32d1744ce..000000000 --- a/rtl/system_integration/neorv32_ProcessorTop_stdlogic.vhd +++ /dev/null @@ -1,517 +0,0 @@ --- ################################################################################################# --- # << NEORV32 - Processor Top Entity with Resolved Port Signals (std_logic/std_logic_vector) >> # --- # ********************************************************************************************* # --- # BSD 3-Clause License # --- # # --- # Copyright (c) 2023, Stephan Nolting. All rights reserved. # --- # # --- # Redistribution and use in source and binary forms, with or without modification, are # --- # permitted provided that the following conditions are met: # --- # # --- # 1. Redistributions of source code must retain the above copyright notice, this list of # --- # conditions and the following disclaimer. # --- # # --- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # --- # conditions and the following disclaimer in the documentation and/or other materials # --- # provided with the distribution. # --- # # --- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # --- # endorse or promote products derived from this software without specific prior written # --- # permission. # --- # # --- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # --- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # --- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # --- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # --- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # --- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # --- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # --- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # --- # OF THE POSSIBILITY OF SUCH DAMAGE. # --- # ********************************************************************************************* # --- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # --- ################################################################################################# - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library neorv32; -use neorv32.neorv32_package.all; - -entity neorv32_ProcessorTop_stdlogic is - generic ( - -- General -- - CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz - INT_BOOTLOADER_EN : boolean := true; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM - CUSTOM_ID : std_logic_vector(31 downto 0) := x"00000000"; -- custom user-defined ID - HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) - -- On-Chip Debugger (OCD) -- - ON_CHIP_DEBUGGER_EN : boolean := false; -- implement on-chip debugger - -- RISC-V CPU Extensions -- - CPU_EXTENSION_RISCV_B : boolean := false; -- implement bit-manipulation extension? - CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? - CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? - CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension? - CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? - CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT reg!) - CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? - CPU_EXTENSION_RISCV_Zicntr : boolean := true; -- implement base counters? - CPU_EXTENSION_RISCV_Zihpm : boolean := false; -- implement hardware performance monitors? - CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? - CPU_EXTENSION_RISCV_Zmmul : boolean := false; -- implement multiply-only M sub-extension? - CPU_EXTENSION_RISCV_Zxcfu : boolean := false; -- implement custom (instr.) functions unit? - -- Extension Options -- - FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier - FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations - CPU_IPB_ENTRIES : natural := 1; -- entries in instruction prefetch buffer, has to be a power of 2, min 1 - -- Physical Memory Protection (PMP) -- - PMP_NUM_REGIONS : natural := 0; -- number of regions (0..16) - PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes - -- Hardware Performance Monitors (HPM) -- - HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) - HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) - -- Internal Instruction memory -- - MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory - MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes - -- Internal Data memory -- - MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory - MEM_INT_DMEM_SIZE : natural := 8*1024; -- size of processor-internal data memory in bytes - -- Internal Cache memory -- - ICACHE_EN : boolean := false; -- implement instruction cache - ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 - ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 - ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 - -- External memory interface -- - MEM_EXT_EN : boolean := false; -- implement external memory bus interface? - MEM_EXT_TIMEOUT : natural := 255; -- cycles after a pending bus access auto-terminates (0 = disabled) - MEM_EXT_PIPE_MODE : boolean := false; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode - MEM_EXT_BIG_ENDIAN : boolean := false; -- byte order: true=big-endian, false=little-endian - MEM_EXT_ASYNC_RX : boolean := false; -- use register buffer for RX data when false - MEM_EXT_ASYNC_TX : boolean := false; -- use register buffer for TX data when false - -- Stream link interface -- - SLINK_NUM_TX : natural := 0; -- number of TX links (0..8) - SLINK_NUM_RX : natural := 0; -- number of TX links (0..8) - SLINK_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two - SLINK_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two - -- External Interrupts Controller (XIRQ) -- - XIRQ_NUM_CH : natural := 0; -- number of external IRQ channels (0..32) - XIRQ_TRIGGER_TYPE : std_logic_vector(31 downto 0) := (others => '1'); -- trigger type: 0=level, 1=edge - XIRQ_TRIGGER_POLARITY : std_logic_vector(31 downto 0) := (others => '1'); -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge - -- Processor peripherals -- - IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? - IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? - IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? - IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 - IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 - IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)? - IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1 - IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1 - IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)? - IO_SPI_FIFO : natural := 0; -- SPI RTX fifo depth, has to be zero or a power of two - IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)? - IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement (0..60); 0 = disabled - IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)? - IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)? - IO_TRNG_FIFO : natural := 1; -- TRNG fifo depth, has to be a power of two, min 1 - IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)? - IO_CFS_CONFIG : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic - IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits - IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits - IO_NEOLED_EN : boolean := true; -- implement NeoPixel-compatible smart LED interface (NEOLED)? - IO_GPTMR_EN : boolean := false; -- implement general purpose timer (GPTMR)? - IO_XIP_EN : boolean := false; -- implement execute in place module (XIP)? - IO_ONEWIRE_EN : boolean := false -- implement 1-wire interface (ONEWIRE)? - ); - port ( - -- Global control -- - clk_i : in std_logic := '0'; -- global clock, rising edge - rstn_i : in std_logic := '0'; -- global reset, low-active, async - -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- - jtag_trst_i : in std_logic := '0'; -- low-active TAP reset (optional) - jtag_tck_i : in std_logic := '0'; -- serial clock - jtag_tdi_i : in std_logic := '0'; -- serial data input - jtag_tdo_o : out std_logic; -- serial data output - jtag_tms_i : in std_logic := '0'; -- mode select - -- Wishbone bus interface (available if MEM_EXT_EN = true) -- - wb_tag_o : out std_logic_vector(02 downto 0); -- tag - wb_adr_o : out std_logic_vector(31 downto 0); -- address - wb_dat_i : in std_logic_vector(31 downto 0) := (others => '0'); -- read data - wb_dat_o : out std_logic_vector(31 downto 0); -- write data - wb_we_o : out std_logic; -- read/write - wb_sel_o : out std_logic_vector(03 downto 0); -- byte enable - wb_stb_o : out std_logic; -- strobe - wb_cyc_o : out std_logic; -- valid cycle - wb_ack_i : in std_logic := '0'; -- transfer acknowledge - wb_err_i : in std_logic := '0'; -- transfer error - -- Advanced memory control signals (available if MEM_EXT_EN = true) -- - fence_o : out std_logic; -- indicates an executed FENCE operation - fencei_o : out std_logic; -- indicates an executed FENCEI operation - -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- - xip_csn_o : out std_logic; -- chip-select, low-active - xip_clk_o : out std_logic; -- serial clock - xip_sdi_i : in std_logic := '0'; -- device data input - xip_sdo_o : out std_logic; -- controller data output - -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- - slink_tx_dat_o : out sdata_8x32r_t; -- output data - slink_tx_val_o : out std_logic_vector(7 downto 0); -- valid output - slink_tx_rdy_i : in std_logic_vector(7 downto 0) := (others => '0'); -- ready to send - slink_tx_lst_o : out std_logic_vector(7 downto 0); -- last data of package - -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- - slink_rx_dat_i : in sdata_8x32r_t := (others => (others => '0')); -- input data - slink_rx_val_i : in std_logic_vector(7 downto 0) := (others => '0'); -- valid input - slink_rx_rdy_o : out std_logic_vector(7 downto 0); -- ready to receive - slink_rx_lst_i : in std_logic_vector(7 downto 0) := (others => '0'); -- last data of package - -- GPIO (available if IO_GPIO_EN = true) -- - gpio_o : out std_logic_vector(63 downto 0); -- parallel output - gpio_i : in std_logic_vector(63 downto 0) := (others => '0'); -- parallel input - -- primary UART0 (available if IO_UART0_EN = true) -- - uart0_txd_o : out std_logic; -- UART0 send data - uart0_rxd_i : in std_logic := '0'; -- UART0 receive data - uart0_rts_o : out std_logic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart0_cts_i : in std_logic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional - -- secondary UART1 (available if IO_UART1_EN = true) -- - uart1_txd_o : out std_logic; -- UART1 send data - uart1_rxd_i : in std_logic := '0'; -- UART1 receive data - uart1_rts_o : out std_logic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional - uart1_cts_i : in std_logic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional - -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o : out std_logic; -- SPI serial clock - spi_sdo_o : out std_logic; -- controller data out, peripheral data in - spi_sdi_i : in std_logic := '0'; -- controller data in, peripheral data out - spi_csn_o : out std_logic_vector(07 downto 0); -- SPI CS - -- TWI (available if IO_TWI_EN = true) -- - twi_sda_io : inout std_logic; -- twi serial data line - twi_scl_io : inout std_logic; -- twi serial clock line - -- 1-Wire Interface (available if IO_ONEWIRE_EN = true) -- - onewire_io : inout std_logic; -- 1-wire bus - -- PWM (available if IO_PWM_NUM_CH > 0) -- - pwm_o : out std_logic_vector(59 downto 0); -- pwm channels - -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- - cfs_in_i : in std_logic_vector(IO_CFS_IN_SIZE-1 downto 0); -- custom inputs - cfs_out_o : out std_logic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom outputs - -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- - neoled_o : out std_logic; -- async serial data line´ - -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- - xirq_i : in std_logic_vector(31 downto 0) := (others => '0'); -- IRQ channels - -- CPU Interrupts -- - mtime_irq_i : in std_logic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false - msw_irq_i : in std_logic := '0'; -- machine software interrupt - mext_irq_i : in std_logic := '0' -- machine external interrupt - ); -end entity; - -architecture neorv32_ProcessorTop_stdlogic_rtl of neorv32_ProcessorTop_stdlogic is - - -- type conversion -- - constant CUSTOM_ID_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(CUSTOM_ID); - constant IO_CFS_CONFIG_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(IO_CFS_CONFIG); - constant XIRQ_TRIGGER_TYPE_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_TYPE); - constant XIRQ_TRIGGER_POLARITY_INT : std_ulogic_vector(31 downto 0) := std_ulogic_vector(XIRQ_TRIGGER_POLARITY); - -- - signal clk_i_int : std_ulogic; - signal rstn_i_int : std_ulogic; - -- - signal jtag_trst_i_int :std_ulogic; - signal jtag_tck_i_int :std_ulogic; - signal jtag_tdi_i_int :std_ulogic; - signal jtag_tdo_o_int :std_ulogic; - signal jtag_tms_i_int :std_ulogic; - -- - signal wb_tag_o_int : std_ulogic_vector(02 downto 0); - signal wb_adr_o_int : std_ulogic_vector(31 downto 0); - signal wb_dat_i_int : std_ulogic_vector(31 downto 0); - signal wb_dat_o_int : std_ulogic_vector(31 downto 0); - signal wb_we_o_int : std_ulogic; - signal wb_sel_o_int : std_ulogic_vector(03 downto 0); - signal wb_stb_o_int : std_ulogic; - signal wb_cyc_o_int : std_ulogic; - signal wb_ack_i_int : std_ulogic; - signal wb_err_i_int : std_ulogic; - -- - signal fence_o_int : std_ulogic; - signal fencei_o_int : std_ulogic; - -- - signal xip_csn_o_int : std_ulogic; - signal xip_clk_o_int : std_ulogic; - signal xip_sdi_i_int : std_ulogic; - signal xip_sdo_o_int : std_ulogic; - -- - signal slink_tx_dat_o_int : sdata_8x32_t; - signal slink_tx_val_o_int : std_logic_vector(7 downto 0); - signal slink_tx_rdy_i_int : std_logic_vector(7 downto 0); - signal slink_tx_lst_o_int : std_logic_vector(7 downto 0); - signal slink_rx_dat_i_int : sdata_8x32_t; - signal slink_rx_val_i_int : std_logic_vector(7 downto 0); - signal slink_rx_rdy_o_int : std_logic_vector(7 downto 0); - signal slink_rx_lst_i_int : std_logic_vector(7 downto 0); - -- - signal gpio_o_int : std_ulogic_vector(63 downto 0); - signal gpio_i_int : std_ulogic_vector(63 downto 0); - -- - signal uart0_txd_o_int : std_ulogic; - signal uart0_rxd_i_int : std_ulogic; - signal uart0_rts_o_int : std_ulogic; - signal uart0_cts_i_int : std_ulogic; - -- - signal uart1_txd_o_int : std_ulogic; - signal uart1_rxd_i_int : std_ulogic; - signal uart1_rts_o_int : std_ulogic; - signal uart1_cts_i_int : std_ulogic; - -- - signal spi_sck_o_int : std_ulogic; - signal spi_sdo_o_int : std_ulogic; - signal spi_sdi_i_int : std_ulogic; - signal spi_csn_o_int : std_ulogic_vector(07 downto 0); - -- - signal pwm_o_int : std_ulogic_vector(59 downto 0); - -- - signal cfs_in_i_int : std_ulogic_vector(IO_CFS_IN_SIZE-1 downto 0); - signal cfs_out_o_int : std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); - -- - signal neoled_o_int : std_ulogic; - -- - signal xirq_i_int : std_ulogic_vector(31 downto 0); - -- - signal mtime_irq_i_int : std_ulogic; - signal msw_irq_i_int : std_ulogic; - signal mext_irq_i_int : std_ulogic; - -begin - - -- The Core Of The Problem ---------------------------------------------------------------- - -- ------------------------------------------------------------------------------------------- - neorv32_top_inst: neorv32_top - generic map ( - -- General -- - CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz - HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id (hartid) (32-bit) - CUSTOM_ID => CUSTOM_ID_INT, -- custom user-defined ID - INT_BOOTLOADER_EN => INT_BOOTLOADER_EN, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM - -- On-Chip Debugger (OCD) -- - ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, -- implement on-chip debugger - -- RISC-V CPU Extensions -- - CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit-manipulation extension? - CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? - CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? - CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension? - CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension? - CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT reg!) - CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? - CPU_EXTENSION_RISCV_Zicntr => CPU_EXTENSION_RISCV_Zicntr, -- implement base counters? - CPU_EXTENSION_RISCV_Zihpm => CPU_EXTENSION_RISCV_Zihpm, -- implement hardware performance monitors? - CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? - CPU_EXTENSION_RISCV_Zmmul => CPU_EXTENSION_RISCV_Zmmul, -- implement multiply-only M sub-extension? - CPU_EXTENSION_RISCV_Zxcfu => CPU_EXTENSION_RISCV_Zxcfu, -- implement custom (instr.) functions unit? - -- Extension Options -- - FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier - FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations - CPU_IPB_ENTRIES => CPU_IPB_ENTRIES, -- entries in instruction prefetch buffer, has to be a power of 2, min 1 - -- Physical Memory Protection (PMP) -- - PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..16) - PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes - -- Hardware Performance Monitors (HPM) -- - HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) - HPM_CNT_WIDTH => HPM_CNT_WIDTH, -- total size of HPM counters (0..64) - -- Internal Instruction memory -- - MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory - MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes - -- Internal Data memory -- - MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory - MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes - -- Internal Cache memory -- - ICACHE_EN => ICACHE_EN, -- implement instruction cache - ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 1), has to be a power of 2 - ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 - ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 - -- External memory interface -- - MEM_EXT_EN => MEM_EXT_EN, -- implement external memory bus interface? - MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT, -- cycles after a pending bus access auto-terminates (0 = disabled) - MEM_EXT_PIPE_MODE => MEM_EXT_PIPE_MODE, -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode - MEM_EXT_BIG_ENDIAN => MEM_EXT_BIG_ENDIAN, -- byte order: true=big-endian, false=little-endian - MEM_EXT_ASYNC_RX => MEM_EXT_ASYNC_RX, -- use register buffer for RX data when false - MEM_EXT_ASYNC_TX => MEM_EXT_ASYNC_TX, -- use register buffer for TX data when false - -- Stream link interface -- - SLINK_NUM_TX => SLINK_NUM_TX, -- number of TX links (0..8) - SLINK_NUM_RX => SLINK_NUM_RX, -- number of TX links (0..8) - SLINK_TX_FIFO => SLINK_TX_FIFO, -- TX fifo depth, has to be a power of two - SLINK_RX_FIFO => SLINK_RX_FIFO, -- RX fifo depth, has to be a power of two - -- External Interrupts Controller (XIRQ) -- - XIRQ_NUM_CH => XIRQ_NUM_CH, -- number of external IRQ channels (0..32) - XIRQ_TRIGGER_TYPE => XIRQ_TRIGGER_TYPE_INT, -- trigger type: 0=level, 1=edge - XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY_INT, -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge - -- Processor peripherals -- - IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? - IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? - IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? - IO_UART0_RX_FIFO => IO_UART0_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1 - IO_UART0_TX_FIFO => IO_UART0_TX_FIFO, -- TX fifo depth, has to be a power of two, min 1 - IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)? - IO_UART1_RX_FIFO => IO_UART1_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1 - IO_UART1_TX_FIFO => IO_UART1_TX_FIFO, -- TX fifo depth, has to be a power of two, min 1 - IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)? - IO_SPI_FIFO => IO_SPI_FIFO, -- SPI RTX fifo depth, has to be zero or a power of two - IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)? - IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..60); 0 = disabled - IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? - IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)? - IO_TRNG_FIFO => IO_TRNG_FIFO, -- TRNG fifo depth, has to be a power of two, min 1 - IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)? - IO_CFS_CONFIG => IO_CFS_CONFIG_INT, -- custom CFS configuration generic - IO_CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits - IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, -- size of CFS output conduit in bits - IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)? - IO_GPTMR_EN => IO_GPTMR_EN, -- implement general purpose timer (GPTMR)? - IO_XIP_EN => IO_XIP_EN, -- implement execute in place module (XIP)? - IO_ONEWIRE_EN => IO_ONEWIRE_EN -- implement 1-wire interface (ONEWIRE)? - ) - port map ( - -- Global control -- - clk_i => clk_i_int, -- global clock, rising edge - rstn_i => rstn_i_int, -- global reset, low-active, async - -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- - jtag_trst_i => jtag_trst_i_int, -- low-active TAP reset (optional) - jtag_tck_i => jtag_tck_i_int, -- serial clock - jtag_tdi_i => jtag_tdi_i_int, -- serial data input - jtag_tdo_o => jtag_tdo_o_int, -- serial data output - jtag_tms_i => jtag_tms_i_int, -- mode select - -- Wishbone bus interface (available if MEM_EXT_EN = true) -- - wb_tag_o => wb_tag_o_int, -- tag - wb_adr_o => wb_adr_o_int, -- address - wb_dat_i => wb_dat_i_int, -- read data - wb_dat_o => wb_dat_o_int, -- write data - wb_we_o => wb_we_o_int, -- read/write - wb_sel_o => wb_sel_o_int, -- byte enable - wb_stb_o => wb_stb_o_int, -- strobe - wb_cyc_o => wb_cyc_o_int, -- valid cycle - wb_ack_i => wb_ack_i_int, -- transfer acknowledge - wb_err_i => wb_err_i_int, -- transfer error - -- Advanced memory control signals (available if MEM_EXT_EN = true) -- - fence_o => fence_o_int, -- indicates an executed FENCE operation - fencei_o => fencei_o_int, -- indicates an executed FENCEI operation - -- XIP (execute in place via SPI) signals (available if IO_XIP_EN = true) -- - xip_csn_o => xip_csn_o_int, -- chip-select, low-active - xip_clk_o => xip_clk_o_int, -- serial clock - xip_sdi_i => xip_sdi_i_int, -- device data input - xip_sdo_o => xip_sdo_o_int, -- controller data output - -- TX stream interfaces (available if SLINK_NUM_TX > 0) -- - slink_tx_dat_o => slink_tx_dat_o_int, -- output data - slink_tx_val_o => slink_tx_val_o_int, -- valid output - slink_tx_rdy_i => slink_tx_rdy_i_int, -- ready to send - slink_tx_lst_o => slink_tx_lst_o_int, -- last data of package - -- RX stream interfaces (available if SLINK_NUM_RX > 0) -- - slink_rx_dat_i => slink_rx_dat_i_int, -- input data - slink_rx_val_i => slink_rx_val_i_int, -- valid input - slink_rx_rdy_o => slink_rx_rdy_o_int, -- ready to receive - slink_rx_lst_i => slink_rx_lst_i_int, -- last data of package - -- GPIO (available if IO_GPIO_EN = true) -- - gpio_o => gpio_o_int, -- parallel output - gpio_i => gpio_i_int, -- parallel input - -- primary UART0 (available if IO_UART0_EN = true) -- - uart0_txd_o => uart0_txd_o_int, -- UART0 send data - uart0_rxd_i => uart0_rxd_i_int, -- UART0 receive data - uart0_rts_o => uart0_rts_o_int, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional - uart0_cts_i => uart0_cts_i_int, -- hw flow control: UART0.TX allowed to transmit, low-active, optional - -- secondary UART1 (available if IO_UART1_EN = true) -- - uart1_txd_o => uart1_txd_o_int, -- UART1 send data - uart1_rxd_i => uart1_rxd_i_int, -- UART1 receive data - uart1_rts_o => uart1_rts_o_int, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional - uart1_cts_i => uart1_cts_i_int, -- hw flow control: UART1.TX allowed to transmit, low-active, optional - -- SPI (available if IO_SPI_EN = true) -- - spi_sck_o => spi_sck_o_int, -- SPI serial clock - spi_sdo_o => spi_sdo_o_int, -- controller data out, peripheral data in - spi_sdi_i => spi_sdi_i_int, -- controller data in, peripheral data out - spi_csn_o => spi_csn_o_int, -- SPI CS - -- TWI (available if IO_TWI_EN = true) -- - twi_sda_io => twi_sda_io, -- twi serial data line - twi_scl_io => twi_scl_io, -- twi serial clock line - -- 1-Wire Interface (available if IO_ONEWIRE_EN = true) -- - onewire_io => onewire_io, -- 1-wire bus - -- PWM (available if IO_PWM_NUM_CH > 0) -- - pwm_o => pwm_o_int, -- pwm channels - -- Custom Functions Subsystem IO (available if IO_CFS_EN = true) -- - cfs_in_i => cfs_in_i_int, -- custom inputs - cfs_out_o => cfs_out_o_int, -- custom outputs - -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- - neoled_o => neoled_o_int, -- async serial data line - -- External platform interrupts (available if XIRQ_NUM_CH > 0) -- - xirq_i => xirq_i_int, -- IRQ channels - -- CPU Interrupts -- - mtime_irq_i => mtime_irq_i_int, -- machine timer interrupt, available if IO_MTIME_EN = false - msw_irq_i => msw_irq_i_int, -- machine software interrupt - mext_irq_i => mext_irq_i_int -- machine external interrupt - ); - - -- type conversion -- - clk_i_int <= std_ulogic(clk_i); - rstn_i_int <= std_ulogic(rstn_i); - - jtag_trst_i_int <= std_ulogic(jtag_trst_i); - jtag_tck_i_int <= std_ulogic(jtag_tck_i); - jtag_tdi_i_int <= std_ulogic(jtag_tdi_i); - jtag_tdo_o <= std_logic(jtag_tdo_o_int); - jtag_tms_i_int <= std_ulogic(jtag_tms_i); - - wb_tag_o <= std_logic_vector(wb_tag_o_int); - wb_adr_o <= std_logic_vector(wb_adr_o_int); - wb_dat_i_int <= std_ulogic_vector(wb_dat_i); - wb_dat_o <= std_logic_vector(wb_dat_o_int); - wb_we_o <= std_logic(wb_we_o_int); - wb_sel_o <= std_logic_vector(wb_sel_o_int); - wb_stb_o <= std_logic(wb_stb_o_int); - wb_cyc_o <= std_logic(wb_cyc_o_int); - wb_ack_i_int <= std_ulogic(wb_ack_i); - wb_err_i_int <= std_ulogic(wb_err_i); - - fence_o <= std_logic(fence_o_int); - fencei_o <= std_logic(fencei_o_int); - - xip_csn_o <= std_logic(xip_csn_o_int); - xip_clk_o <= std_logic(xip_clk_o_int); - xip_sdi_i_int <= std_ulogic(xip_sdi_i); - xip_sdo_o <= std_logic(xip_sdo_o_int); - - slink_tx_val_o <= std_logic_vector(slink_tx_val_o_int); - slink_tx_rdy_i_int <= std_ulogic_vector(slink_tx_rdy_i); - slink_rx_lst_i_int <= std_ulogic_vector(slink_rx_lst_i); - slink_rx_val_i_int <= std_ulogic_vector(slink_rx_val_i); - slink_rx_rdy_o <= std_logic_vector(slink_rx_rdy_o_int); - slink_tx_lst_o <= std_logic_vector(slink_tx_lst_o_int); - - slink_conv: - for i in 0 to 7 generate - slink_tx_dat_o(i) <= std_logic_vector(slink_tx_dat_o_int(i)); - slink_rx_dat_i_int(i) <= std_ulogic_vector(slink_rx_dat_i(i)); - end generate; - - gpio_o <= std_logic_vector(gpio_o_int); - gpio_i_int <= std_ulogic_vector(gpio_i); - - uart0_txd_o <= std_logic(uart0_txd_o_int); - uart0_rxd_i_int <= std_ulogic(uart0_rxd_i); - uart0_rts_o <= std_logic(uart0_rts_o_int); - uart0_cts_i_int <= std_ulogic(uart0_cts_i); - uart1_txd_o <= std_logic(uart1_txd_o_int); - uart1_rxd_i_int <= std_ulogic(uart1_rxd_i); - uart1_rts_o <= std_logic(uart1_rts_o_int); - uart1_cts_i_int <= std_ulogic(uart1_cts_i); - - spi_sck_o <= std_logic(spi_sck_o_int); - spi_sdo_o <= std_logic(spi_sdo_o_int); - spi_sdi_i_int <= std_ulogic(spi_sdi_i); - spi_csn_o <= std_logic_vector(spi_csn_o_int); - - pwm_o <= std_logic_vector(pwm_o_int); - - cfs_in_i_int <= std_ulogic_vector(cfs_in_i); - cfs_out_o <= std_logic_vector(cfs_out_o_int); - - neoled_o <= std_logic(neoled_o_int); - - xirq_i_int <= std_ulogic_vector(xirq_i); - - msw_irq_i_int <= std_ulogic(msw_irq_i); - mext_irq_i_int <= std_ulogic(mext_irq_i); - - -end architecture; From 65199996f226820e3b9006d2c28fb66d2444483d Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Sat, 11 Feb 2023 19:12:24 +0100 Subject: [PATCH 4/7] [CHANGELOG] add v1.8.0.6 --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index b230285e7..934515510 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -31,6 +31,7 @@ mimpid = 0x01040312 => Version 01.04.03.12 => v1.4.3.12 | Date (*dd.mm.yyyy*) | Version | Comment | |:-------------------:|:-------:|:--------| +| 11.02.2023 | 1.8.0.6 | :warning: replaced boolean `IO_GPIO_EN` generic by natural `IO_GPIO_NUM` generic to fine-tune GPIO pin number; [#491](https://github.com/stnolting/neorv32/pull/491) | | 10.02.2023 | 1.8.0.5 | :test_tube: add CPU co-processor monitor (to auto-terminate operation if a co-processor operation takes too long); [#490](https://github.com/stnolting/neorv32/pull/490) | | 10.02.2023 | 1.8.0.4 | replace CPU-internal control bus by a VHDL `record` (much cleaner code); minor control optimizations; add 6ht CPU co-processor slot (yet unused); [#489](https://github.com/stnolting/neorv32/pull/489) | | 05.02.2023 | 1.8.0.3 | CPU control optimizations; [#487](https://github.com/stnolting/neorv32/pull/487) | From 35f7b8315fa53e51f82e8121366c712b0a951308 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Sat, 11 Feb 2023 19:31:37 +0100 Subject: [PATCH 5/7] [rtl] update test setups --- rtl/test_setups/neorv32_test_setup_approm.vhd | 4 ++-- rtl/test_setups/neorv32_test_setup_bootloader.vhd | 4 ++-- rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/rtl/test_setups/neorv32_test_setup_approm.vhd b/rtl/test_setups/neorv32_test_setup_approm.vhd index b07e5fd4e..a15cc0e4d 100644 --- a/rtl/test_setups/neorv32_test_setup_approm.vhd +++ b/rtl/test_setups/neorv32_test_setup_approm.vhd @@ -80,14 +80,14 @@ begin MEM_INT_DMEM_EN => true, -- implement processor-internal data memory MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes -- Processor peripherals -- - IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM => 8, -- number of GPIO input/output pairs (0..64) IO_MTIME_EN => true -- implement machine system timer (MTIME)? ) port map ( -- Global control -- clk_i => clk_i, -- global clock, rising edge rstn_i => rstn_i, -- global reset, low-active, async - -- GPIO (available if IO_GPIO_EN = true) -- + -- GPIO (available if IO_GPIO_NUM > 0) -- gpio_o => con_gpio_o -- parallel output ); diff --git a/rtl/test_setups/neorv32_test_setup_bootloader.vhd b/rtl/test_setups/neorv32_test_setup_bootloader.vhd index fd8477956..7a4206a11 100644 --- a/rtl/test_setups/neorv32_test_setup_bootloader.vhd +++ b/rtl/test_setups/neorv32_test_setup_bootloader.vhd @@ -83,7 +83,7 @@ begin MEM_INT_DMEM_EN => true, -- implement processor-internal data memory MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes -- Processor peripherals -- - IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM => 8, -- number of GPIO input/output pairs (0..64) IO_MTIME_EN => true, -- implement machine system timer (MTIME)? IO_UART0_EN => true -- implement primary universal asynchronous receiver/transmitter (UART0)? ) @@ -93,7 +93,7 @@ begin rstn_i => rstn_i, -- global reset, low-active, async -- GPIO (available if IO_GPIO_EN = true) -- gpio_o => con_gpio_o, -- parallel output - -- primary UART0 (available if IO_UART0_EN = true) -- + -- primary UART0 (available if IO_GPIO_NUM > 0) -- uart0_txd_o => uart0_txd_o, -- UART0 send data uart0_rxd_i => uart0_rxd_i -- UART0 receive data ); diff --git a/rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd b/rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd index 9663ae682..011c617d8 100644 --- a/rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd +++ b/rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd @@ -92,7 +92,7 @@ begin MEM_INT_DMEM_EN => true, -- implement processor-internal data memory MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes -- Processor peripherals -- - IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM => 8, -- number of GPIO input/output pairs (0..64) IO_MTIME_EN => true, -- implement machine system timer (MTIME)? IO_UART0_EN => true -- implement primary universal asynchronous receiver/transmitter (UART0)? ) @@ -106,7 +106,7 @@ begin jtag_tdi_i => jtag_tdi_i, -- serial data input jtag_tdo_o => jtag_tdo_o, -- serial data output jtag_tms_i => jtag_tms_i, -- mode select - -- GPIO (available if IO_GPIO_EN = true) -- + -- GPIO (available if IO_GPIO_NUM > 0) -- gpio_o => con_gpio_o, -- parallel output -- primary UART0 (available if IO_UART0_EN = true) -- uart0_txd_o => uart0_txd_o, -- UART0 send data From e89a9defde3ad386c6cba84abeba2df0f8616842 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Sat, 11 Feb 2023 19:41:41 +0100 Subject: [PATCH 6/7] [rtl] fix wrong generic --- rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd b/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd index 66658bcfe..71558ddad 100644 --- a/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd +++ b/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd @@ -80,7 +80,7 @@ entity neorv32_ProcessorTop_MinimalBoot is ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 -- Processor peripherals -- - IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? + IO_GPIO_NUM : natural := 0; -- number of GPIO input/output pairs (0..64) IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? IO_PWM_NUM_CH : natural := 3; -- number of PWM channels to implement (0..60); 0 = disabled From 5f24766547d2fce33a6a70223ad694271dd15d56 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Sat, 11 Feb 2023 19:47:35 +0100 Subject: [PATCH 7/7] [docs] update GPIO generics and description --- docs/datasheet/soc.adoc | 7 ++++--- docs/datasheet/soc_gpio.adoc | 17 +++++++---------- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc index 218b13ffd..afa640429 100644 --- a/docs/datasheet/soc.adoc +++ b/docs/datasheet/soc.adoc @@ -803,13 +803,14 @@ implemented reducing access latency by one cycle but eventually increasing the c ==== Processor Peripheral/IO Modules :sectnums!: -===== _IO_GPIO_EN_ +===== _IO_GPIO_NUM_ [cols="4,4,2"] [frame="all",grid="none"] |====== -| **IO_GPIO_EN** | _boolean_ | false -3+| Implement <<_general_purpose_input_and_output_port_gpio>> module when true. +| **IO_GPIO_NUM** | _natural_ | 0 +3+| Number of general purpose input/output pairs of the <<_general_purpose_input_and_output_port_gpio>>. If set to zero, +GPIO controller is not implemented at all. |====== diff --git a/docs/datasheet/soc_gpio.adoc b/docs/datasheet/soc_gpio.adoc index d277fea6e..2f328c3c4 100644 --- a/docs/datasheet/soc_gpio.adoc +++ b/docs/datasheet/soc_gpio.adoc @@ -10,14 +10,16 @@ | | neorv32_gpio.h | | Top entity port: | `gpio_o` | 64-bit parallel output port | | `gpio_i` | 64-bit parallel input port -| Configuration generics: | _IO_GPIO_EN_ | implement GPIO port when _true_ +| Configuration generics: | _IO_GPIO_NUM_ | number of input/output pairs (0..64) | CPU interrupts: | none | |======================= -The general purpose parallel IO port unit provides a simple 64-bit parallel input port and a 64-bit parallel -output port. These ports can be used chip-externally (for example to drive status LEDs, connect buttons, etc.) -or chip-internally to provide control signals for other IP modules. The component is disabled for -implementation when the _IO_GPIO_EN_ generic is set _false_. In this case the GPIO output port `gpio_o` is tied to all-zero. +The general purpose parallel IO unit provides a simple parallel input and output port. These ports can be used chip-externally +(for example to drive status LEDs, connect buttons, etc.) or chip-internally to provide control signals for other IP modules. +The actual number of input/output pairs is defined by the _IO_GPIO_NUM_ generic. When set to zero, the GPIO module is excluded +from synthesis and the output port `gpio_o` is tied to all-zero. If _IO_GPIO_NUM_ is less than the maximum value of 64 +only the LSB-aligned bits in `gpio_o` and `gpio_i` are actually connected while the remaining bits are unconnected or tied +to zero, respectively. .Access Atomicity [NOTE] @@ -25,11 +27,6 @@ The GPIO modules uses two memory-mapped registers (each 32-bit) each for accessi output signals. Since the CPU can only process 32-bit "at once" updating the entire output cannot be performed within a single clock cycle. -.INPUT is read-only -[NOTE] -Write accesses to the `NEORV32_GPIO.INPUT_LO` and `NEORV32_GPIO.INPUT_HI` registers will raise a store bus -error exception. The BUSKEEPER will indicate a "DEVICE_ERR" in this case. - **Register Map**