diff --git a/.github/workflows/Implementation.yml b/.github/workflows/Implementation.yml index 8f44f608f..20cbc367f 100644 --- a/.github/workflows/Implementation.yml +++ b/.github/workflows/Implementation.yml @@ -48,12 +48,12 @@ jobs: - name: '🚧 Generate ${{ matrix.board }} ${{ matrix.design }} bitstream' uses: docker://ghcr.io/stnolting/neorv32/impl with: - args: make -C setups/examples BOARD=${{ matrix.board }} ${{ matrix.design }} + args: make -C setups/osflow BOARD=${{ matrix.board }} ${{ matrix.design }} - name: '📤 Upload Artifact: ${{ matrix.board }} ${{ matrix.design }} bitstream and reports' uses: actions/upload-artifact@v2 with: name: ${{ matrix.board }}-${{ matrix.design }} path: | - setups/examples/${{ matrix.bitstream }} + setups/osflow/${{ matrix.bitstream }} setups/osflow/${{ matrix.board }}/*-report.txt diff --git a/setups/examples/README.md b/setups/examples/README.md deleted file mode 100644 index 889dbe2e1..000000000 --- a/setups/examples/README.md +++ /dev/null @@ -1,83 +0,0 @@ -# Examples - -### :construction: Under Construction :construction: - -## UPduino v3.0 - -* FPGA Board: :books: [tinyVision.ai Inc. UPduino v3 FPGA Board (GitHub)](https://github.com/tinyvision-ai-inc/UPduino-v3.0/), :credit_card: buy on [Tindie](https://www.tindie.com/products/tinyvision_ai/upduino-v30-low-cost-lattice-ice40-fpga-board/) -* FPGA: Lattice iCE40 UltraPlus 5k `iCE40UP5K-SG48I` - - -### [`neorv32_UPduino_v3_BoardTop_MinimalProcessor.vhd`](https://github.com/stnolting/neorv32/blob/master/examples/neorv32_UPduino_v3_BoardTop_MinimalProcessor.vhd) - -Minimal *blinky* example. - -### [`neorv32_UPduino_v3_BoardTop_SmallProcessor.vhd`](https://github.com/stnolting/neorv32/blob/master/examples/neorv32_UPduino_v3_BoardTop_SmallProcessor.vhd) - -This example setup turns the UPduino v3.0 into an RTOS capable NEORV32 *microcontroller*, along with a set of standard peripherals like UART, TWI and SPI. - -#### Processor Configuration - -* CPU: `rv32imac_Zicsr` (reduced CPU `[m]instret` & `[m]cycle` counter width!) -* Memory: 64 kB instruction memory (internal IMEM), 64 kB data memory (internal DMEM), 4 kB bootloader ROM -* Peripherals: `GPIO`, `MTIME`, `UART0`, `SPI`, `TWI`, `PWM`, `WDT` -* Clock: 18 MHz from on-chip HF oscillator (via PLL) -* Reset: via PLL "locked" signal; "external reset" via FPGA reconfiguration (`creset_n`) -* Tested with version [`1.5.5.5`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md) -* On-board FPGA bitstream flash storage can also be used to store/load NEORV32 application software (via the bootloader) - -#### Interface Signals - -:information_source: See [`upduino_v3.pcf`](https://github.com/stnolting/neorv32/blob/master/boards/osflow/UPduino_v3/upduino_v3.pcf) -for the FPGA pin mapping. - -| Top Entity Signal | FPGA Pin | Package Pin | Board Header Pin | -|:------------------------------|:----------:|:------------:|:-----------------| -| `flash_csn_o` (spi_cs[0]) | IOB_35B | 16 | J3-1 | -| `flash_sck_o` | IOB_34A | 15 | J3-2 | -| `flash_sdo_o` | IOB_32A | 14 | J3-3 | -| `flash_sdi_i` | IOB_33B | 17 | J3-4 | -| `gpio_i(0)` | IOB_3B_G6 | 44 | J3-9 | -| `gpio_i(1)` | IOB_8A | 4 | J3-10 | -| `gpio_i(2)` | IOB_9B | 3 | J3-11 | -| `gpio_i(3)` | IOB_4A | 48 | J3-12 | -| `gpio_o(0)` (status LED) | IOB_5B | 45 | J3-13 | -| `gpio_o(1)` | IOB_2A | 47 | J3-14 | -| `gpio_o(2)` | IOB_0A | 46 | J3-15 | -| `gpio_o(3)` | IOB_6A | 2 | J3-16 | -| - | - | - | - | -| **reconfigure FPGA** ("_reset_") | CRESET | 8 | J2-3 | -| `pwm_o(0)` (red) | RGB2 | 41 | J2-5 | -| `pwm_o(1)` (green) | RGB0 | 39 | J2-6 | -| `pwm_o(2)` (blue) | RGB1 | 40 | J2-7 | -| `twi_sda_io` | IOT_42B | 31 | J2-9 | -| `twi_scl_io` | IOT_45A_G1 | 37 | J2-10 | -| `spi_sdo_o` | IOT_44B | 34 | J2-11 | -| `spi_sck_o` | IOT_49A | 43 | J2-12 | -| `spi_csn_o` (spi_cs[1]) | IOT_48B | 36 | J2-13 | -| `spi_sdi_i` | IOT_51A | 42 | J2-14 | -| `uart_txd_o` (UART0) | IOT_50B | 38 | J2-15 | -| `uart_rxd_i` (UART0) | IOT_41A | 28 | J2-16 | - -:information_source: The TWI signals (`twi_sda_io` and `twi_scl_io`) and the reset input (`rstn_i`) require an external pull-up resistor. GPIO output 0 (`gpio_o(0)`) is used as output for a high-active status LED driven by the bootloader. - -#### FPGA Utilization - -``` -Device utilisation: - ICESTORM_LC: 5206/ 5280 98% - ICESTORM_RAM: 12/ 30 40% - SB_IO: 20/ 96 20% - SB_GB: 8/ 8 100% - ICESTORM_PLL: 1/ 1 100% - SB_WARMBOOT: 0/ 1 0% - ICESTORM_DSP: 0/ 8 0% - ICESTORM_HFOSC: 1/ 1 100% - ICESTORM_LFOSC: 0/ 1 0% - SB_I2C: 0/ 2 0% - SB_SPI: 0/ 2 0% - IO_I3C: 0/ 2 0% - SB_LEDDA_IP: 0/ 1 0% - SB_RGBA_DRV: 1/ 1 100% - ICESTORM_SPRAM: 4/ 4 100% -``` diff --git a/setups/examples/Makefile b/setups/osflow/Makefile similarity index 83% rename from setups/examples/Makefile rename to setups/osflow/Makefile index cb783af6e..d9d4cd9a0 100644 --- a/setups/examples/Makefile +++ b/setups/osflow/Makefile @@ -1,5 +1,3 @@ -OSFLOW := ../osflow -EXAMPLES := ../examples TEMPLATES := ../../rtl/templates MV := mv @@ -17,14 +15,14 @@ UPduino_REV ?= v3 run: $(eval TASK ?= clean $(BITSTREAM)) - $(MAKE) -C $(OSFLOW) -f common.mk \ - BOARD_SRC=$(EXAMPLES)/neorv32_$(BOARD)_BoardTop_$(DESIGN).vhd \ + $(MAKE) -f common.mk \ + BOARD_SRC=./board_tops/neorv32_$(BOARD)_BoardTop_$(DESIGN).vhd \ TOP=neorv32_$(BOARD)_BoardTop_$(DESIGN) \ ID=$(DESIGN) \ $(TASK) IMPL="$${BITSTREAM%%.*}"; for item in ".bit" ".svf"; do \ - if [ -f "$(OSFLOW)/$$IMPL$$item" ]; then \ - $(MV) "$(OSFLOW)/$$IMPL$$item" ./; \ + if [ -f "./$$IMPL$$item" ]; then \ + $(MV) "./$$IMPL$$item" ./; \ fi \ done @@ -81,7 +79,7 @@ MixedLanguage: $(MAKE) \ DESIGN=$@ \ DESIGN_SRC=$(TEMPLATES)/processor/neorv32_ProcessorTop_Minimal*.vhd \ - NEORV32_VERILOG_SRC='devices/ice40/sb_ice40_components.v ../examples/neorv32_Fomu_MixedLanguage_ClkGen.v' \ + NEORV32_VERILOG_SRC='devices/ice40/sb_ice40_components.v board_tops/neorv32_Fomu_MixedLanguage_ClkGen.v' \ $(BOARD) # Help diff --git a/setups/osflow/README.md b/setups/osflow/README.md index fe933eddd..db900c3d3 100644 --- a/setups/osflow/README.md +++ b/setups/osflow/README.md @@ -5,7 +5,9 @@ open source toolchains. Synthesis based on [ghdl-yosys](https://github.com/ghdl/ ## Folder Structure -* `boards`: board-specific makefiles for generating bitstreams +* `.`: Main makefile (main entry point) and partial-makefiles for synthesis, place & route and bitstream generation +* `boards`: board-specific _partial makefiles_ (used in by main makefile `Makefile`) for generating bitstreams +* `board_top`: board-specific top entities (board wrappers; may include FPGA-specific modules) * `constraints`: physical constraints (mainly pin mappings) * `devices`: FPGA-specific primitives and optimized processor modules (like memories) @@ -14,13 +16,30 @@ open source toolchains. Synthesis based on [ghdl-yosys](https://github.com/ghdl/ :construction: **TODO - Under Construction** :construction: +* local installation of the tools +* using containers + ## How To Run -:construction: **TODO - Under Construction** :construction: +The `Makefile` in this folder is the main entry point. To run the whole process of synthesis, place & route and bitstream +generation run: + +**Prototype:** +``` +make BOARD= +``` -```shell -make BOARD= +**Example:** ``` +make BOARD=Fomu Minimal +``` + +`` specifies the actual FPGA board and implicitly sets the FPGA type. The currently supported FPGA board +targets are listed in the `boards/` folder where each partial-makefile corresponds to a supported platform. + +`` is used to define the actual SoC top. Available SoCs are located in +[`rtl/templates/processor`](https://github.com/stnolting/neorv32/tree/master/rtl/templates/processor). + See https://github.com/stnolting/neorv32/blob/master/.github/workflows/Implementation.yml diff --git a/setups/examples/neorv32_Fomu_BoardTop_Minimal.vhd b/setups/osflow/board_tops/neorv32_Fomu_BoardTop_Minimal.vhd similarity index 100% rename from setups/examples/neorv32_Fomu_BoardTop_Minimal.vhd rename to setups/osflow/board_tops/neorv32_Fomu_BoardTop_Minimal.vhd diff --git a/setups/examples/neorv32_Fomu_BoardTop_MinimalBoot.vhd b/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MinimalBoot.vhd similarity index 100% rename from setups/examples/neorv32_Fomu_BoardTop_MinimalBoot.vhd rename to setups/osflow/board_tops/neorv32_Fomu_BoardTop_MinimalBoot.vhd diff --git a/setups/examples/neorv32_Fomu_BoardTop_MixedLanguage.vhd b/setups/osflow/board_tops/neorv32_Fomu_BoardTop_MixedLanguage.vhd similarity index 100% rename from setups/examples/neorv32_Fomu_BoardTop_MixedLanguage.vhd rename to setups/osflow/board_tops/neorv32_Fomu_BoardTop_MixedLanguage.vhd diff --git a/setups/examples/neorv32_Fomu_BoardTop_UP5KDemo.vhd b/setups/osflow/board_tops/neorv32_Fomu_BoardTop_UP5KDemo.vhd similarity index 100% rename from setups/examples/neorv32_Fomu_BoardTop_UP5KDemo.vhd rename to setups/osflow/board_tops/neorv32_Fomu_BoardTop_UP5KDemo.vhd diff --git a/setups/examples/neorv32_Fomu_MixedLanguage_ClkGen.v b/setups/osflow/board_tops/neorv32_Fomu_MixedLanguage_ClkGen.v similarity index 100% rename from setups/examples/neorv32_Fomu_MixedLanguage_ClkGen.v rename to setups/osflow/board_tops/neorv32_Fomu_MixedLanguage_ClkGen.v diff --git a/setups/examples/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd b/setups/osflow/board_tops/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd similarity index 100% rename from setups/examples/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd rename to setups/osflow/board_tops/neorv32_OrangeCrab_BoardTop_MinimalBoot.vhd diff --git a/setups/examples/neorv32_UPduino_BoardTop_MinimalBoot.vhd b/setups/osflow/board_tops/neorv32_UPduino_BoardTop_MinimalBoot.vhd similarity index 100% rename from setups/examples/neorv32_UPduino_BoardTop_MinimalBoot.vhd rename to setups/osflow/board_tops/neorv32_UPduino_BoardTop_MinimalBoot.vhd diff --git a/setups/examples/neorv32_UPduino_BoardTop_UP5KDemo.vhd b/setups/osflow/board_tops/neorv32_UPduino_BoardTop_UP5KDemo.vhd similarity index 100% rename from setups/examples/neorv32_UPduino_BoardTop_UP5KDemo.vhd rename to setups/osflow/board_tops/neorv32_UPduino_BoardTop_UP5KDemo.vhd diff --git a/setups/examples/neorv32_iCESugar_BoardTop_Minimal.vhd b/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_Minimal.vhd similarity index 100% rename from setups/examples/neorv32_iCESugar_BoardTop_Minimal.vhd rename to setups/osflow/board_tops/neorv32_iCESugar_BoardTop_Minimal.vhd diff --git a/setups/examples/neorv32_iCESugar_BoardTop_MinimalBoot.vhd b/setups/osflow/board_tops/neorv32_iCESugar_BoardTop_MinimalBoot.vhd similarity index 100% rename from setups/examples/neorv32_iCESugar_BoardTop_MinimalBoot.vhd rename to setups/osflow/board_tops/neorv32_iCESugar_BoardTop_MinimalBoot.vhd