diff --git a/CHANGELOG.md b/CHANGELOG.md index 1be54ab1e..fe86ac335 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date | Version | Comment | Ticket | |:----:|:-------:|:--------|:------:| +| 03.10.2024 | 1.10.5.2 | :warning: remove `A` ISA extensions; replaced by new `Zalrsc` ISA extension | [#1047](https://github.com/stnolting/neorv32/pull/1047) | | 02.10.2024 | 1.10.5.1 | :warning: rework CFU interface; reduce minimal latency of CFU instructions from 4 cycles to 3 cycles | [#1046](https://github.com/stnolting/neorv32/pull/1046) | | 01.10.2024 | [**:rocket:1.10.5**](https://github.com/stnolting/neorv32/releases/tag/v1.10.5) | **New release** | | | 30.09.2024 | 1.10.4.11 | :warning: split `B` ISA extensions into individual sub-extensions: `Zba`, `Zbb`, `Zbs` | [#1044](https://github.com/stnolting/neorv32/pull/1044) | diff --git a/README.md b/README.md index 2eee117e2..7660d8eb3 100644 --- a/README.md +++ b/README.md @@ -104,11 +104,11 @@ setup according to your needs. Note that all of the following SoC modules are en `RV32` [[`I`](https://stnolting.github.io/neorv32/#_i_isa_extension)/[`E`](https://stnolting.github.io/neorv32/#_e_isa_extension)] [[`M`](https://stnolting.github.io/neorv32/#_m_isa_extension)] -[[`A`](https://stnolting.github.io/neorv32/#_a_isa_extension)] [[`C`](https://stnolting.github.io/neorv32/#_c_isa_extension)] [[`B`](https://stnolting.github.io/neorv32/#_b_isa_extension)] [[`U`](https://stnolting.github.io/neorv32/#_u_isa_extension)] [[`X`](https://stnolting.github.io/neorv32/#_x_isa_extension)] +[[`Zalrsc`](https://stnolting.github.io/neorv32/#_zalrsc_isa_extension)] [[`Zba`](https://stnolting.github.io/neorv32/#_zba_isa_extension)] [[`Zbb`](https://stnolting.github.io/neorv32/#_zbb_isa_extension)] [[`Zbkb`](https://stnolting.github.io/neorv32/#_zbkb_isa_extension)] diff --git a/docs/datasheet/cpu.adoc b/docs/datasheet/cpu.adoc index e2bbb191b..800b671bc 100644 --- a/docs/datasheet/cpu.adoc +++ b/docs/datasheet/cpu.adoc @@ -49,13 +49,6 @@ will raise an exception to allow a _software-based_ emulation provided by the ap access can be **emulated** using the NEORV32 runtime environment. See section <<_application_context_handling>> for more information. -.No Atomic Read-Modify-Write Operations -[IMPORTANT] -The NEORV32 <<_a_isa_extension>> only supports the load-reservate (LR) and store-conditional (SR) instructions. -The remaining read-modify-write operations are not supported. However, these missing instructions can -be emulated. The NEORV32 <<_core_libraries>> provide an emulation wrapper for the missing AMO/read-modify-write -instructions that is based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`. - <<< // #################################################################################################################### @@ -335,7 +328,7 @@ is driven by the _accessed_ device or bus system (i.e. a processor-internal memo | `rw` | 1 | Access direction (`0` = read, `1` = write) | `src` | 1 | Access source (`0` = instruction fetch, `1` = load/store) | `priv` | 1 | Set if privileged (M-mode) access -| `rvso` | 1 | Set if current access is a reservation-set operation (atomic `lr` or `sc` instruction) +| `rvso` | 1 | Set if current access is a reservation-set operation (`lr` or `sc` instruction, <<_zalrsc_isa_extension>>) | `fence` | 1 | Data/instruction fence operation; valid without `stb` being set |======================= @@ -382,7 +375,7 @@ additional latency). However, _all_ bus signals (request and response) need to b :sectnums: ==== Atomic Accesses -The load-reservate (`lr.w`) and store-conditional (`sc.w`) instructions from the <<_a_isa_extension>> execute as standard +The load-reservate (`lr.w`) and store-conditional (`sc.w`) instructions from the <<_zalrsc_isa_extension>> execute as standard load/store bus transactions but with the `rvso` ("reservation set operation") signal being set. It is the task of the <<_reservation_set_controller>> to handle these LR/SC bus transactions accordingly. Note that these reservation set operations are intended for processor-internal usage only (i.e. the reservation state is not available for processor-external modules yet). @@ -391,12 +384,6 @@ are intended for processor-internal usage only (i.e. the reservation state is no [NOTE] See section <<_address_space>> / <<_reservation_set_controller>> for more information. -.Read-Modify-Write Operations -[IMPORTANT] -Read-modify-write operations (like an atomic swap / `amoswap.w`) are **not** supported yet. However, the NEORV32 -<<_core_libraries>> provide an emulation wrapper for those unsupported instructions that is -based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`. - The figure below shows three exemplary bus accesses (1 to 3 from left to right). The `req` signal record represents the CPU-side of the bus interface. For easier understanding the current state of the reservation set is added as `rvs_valid` signal. @@ -417,6 +404,11 @@ image::bus_interface_atomic.png[700] [NOTE] The "normal" load data mechanism is used to return success/failure of the `sc.w` instruction to the CPU (via the LSB of `rsp.data`). +.Cache Coherency +[IMPORTANT] +Atomic operations **always bypass** the CPU caches using direct/uncached accesses. Care must be taken +to maintain data cache coherency (e.g. by using the `fence` instruction). + <<< // #################################################################################################################### @@ -432,7 +424,6 @@ This chapter gives a brief overview of all available ISA extensions. [options="header",grid="rows"] |======================= | Name | Description | <<_processor_top_entity_generics, Enabled by Generic>> -| <<_a_isa_extension,`A`>> | Atomic memory access instructions | `RISCV_ISA_A` | <<_b_isa_extension,`B`>> | Bit manipulation instructions | _Implicitly_ enabled | <<_c_isa_extension,`C`>> | Compressed (16-bit) instructions | `RISCV_ISA_C` | <<_e_isa_extension,`E`>> | Embedded CPU extension (reduced register file size) | `RISCV_ISA_E` @@ -440,6 +431,7 @@ This chapter gives a brief overview of all available ISA extensions. | <<_m_isa_extension,`M`>> | Integer multiplication and division instructions | `RISCV_ISA_M` | <<_u_isa_extension,`U`>> | Less-privileged _user_ mode extension | `RISCV_ISA_U` | <<_x_isa_extension,`X`>> | Platform-specific / NEORV32-specific extension | Always enabled +| <<_zalrsc_isa_extension,`Zalrsc`>> | Atomic reservation-set instructions | `RISCV_ISA_Zalrsc` | <<_zba_isa_extension,`Zba`>> | Shifted-add bit manipulation instructions | `RISCV_ISA_Zba` | <<_zbb_isa_extension,`Zbb`>> | Basic bit manipulation instructions | `RISCV_ISA_Zbb` | <<_zbkb_isa_extension,`Zbkb`>> | Scalar cryptographic bit manipulation instructions | `RISCV_ISA_Zbkb` @@ -486,56 +478,6 @@ To benchmark a certain processor configuration for its setup-specific CPI value `sw/example/performance_tests` test programs. -==== `A` ISA Extension - -The `A` ISA extension adds instructions and mechanisms for atomic memory access operations. Note that the NEORV32 `A` -only includes the _load-reservate_ (`lr.w`) and _store-conditional_ (`sc.w`) instructions - the remaining read-modify-write -instructions (like `amoswap`) are **not supported**. However, these missing instructions can be emulated using the -LR and SC operations (quote from the RISC-V spec.: "_Any AMO can be emulated by an LR/SC pair._"). - -.AMO Emulation -[NOTE] -The NEORV32 <<_core_libraries>> provide an emulation wrapper for the missing AMO/read-modify-write instructions that is -based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`. - -Atomic instructions allow to notify an application if a certain memory location has been altered by another instance -(like another process running on the same CPU or a DMA access). Hence, they can be used to implement synchronization -mechanisms like mutexes and semaphores). - -The NEORV32 `A` extension is enabled via the `RISCV_ISA_A` generic (see <<_processor_top_entity_generics>>). -When enabled the following additional instructions are available. - -.Instructions and Timing -[cols="<2,<4,<3"] -[options="header", grid="rows"] -|======================= -| Class | Instructions | Execution cycles -| Load-reservate word | `lr.w` | 5 -| Store-conditional word | `sc.w` | 5 -|======================= - -The `lr.w` instructions stores one word to a word-aligned address and registers a _reservation set_. The `sc.w` -instruction stores a word to a word-aligned address only if the reservation set is still valid. Furthermore, the -`sc.w` operations returns the state of the reservation set (0 = reservation set still valid, data has been written; -1 = reservation set was broken, no data has been written). The reservation set is invalidated if another `lr.w` instruction -is executed or if any write access to the _reservated_ address takes place. Traps and/or CPU privilege level changes -do not modify current reservation sets. - -.`aq` and `rl` Bits -[NOTE] -The instruction word's `aq` and `lr` memory ordering bits are not evaluated by the hardware at all. - -.Atomic Memory Access on Hardware Level -[NOTE] -More information regarding the atomic memory accesses and the according reservation -sets can be found in section <<_reservation_set_controller>>. - -.Cache Coherency -[IMPORTANT] -Atomic operations **always bypass** the CPU caches using direct/uncached accesses. Care must be taken -to maintain data cache coherency (e.g. by using the `fence` instruction). - - ==== `B` ISA Extension The `B` ISA extension adds instructions for bit-manipulation operations. @@ -657,6 +599,38 @@ RISC-V specs. Also, custom trap codes for <<_mcause>> are implemented. * There are <<_neorv32_specific_csrs>>. +==== `Zalrsc` ISA Extension + +The `Zalrsc` ISA extension is a sub-extension of the RISC-V _atomic memory access_ (`A`) ISA extension and includes +instructions for reservation-set operations (load-reservate `lr` and store-conditional `sc`) only. +It is enabled by the top's `RISCV_ISA_Zalrsc` generic. + +.AMO / `A` Emulation +[NOTE] +The atomic memory access / read-modify-write operations of the `A` ISA extension can be emulated using the +LR and SC operations (quote from the RISC-V spec.: "_Any AMO can be emulated by an LR/SC pair._"). +The NEORV32 <<_core_libraries>> provide an emulation wrapper for emulating AMO/read-modify-write instructions that is +based on LR/SC pairs. A demo/program can be found in `sw/example/atomic_test`. + +.Instructions and Timing +[cols="<2,<4,<3"] +[options="header", grid="rows"] +|======================= +| Class | Instructions | Execution cycles +| Load-reservate word | `lr.w` | 5 +| Store-conditional word | `sc.w` | 5 +|======================= + +.`aq` and `rl` Bits +[NOTE] +The instruction word's `aq` and `lr` memory ordering bits are not evaluated by the hardware at all. + +.Atomic Memory Access on Hardware Level +[NOTE] +More information regarding the atomic memory accesses and the according reservation +sets can be found in section <<_reservation_set_controller>>. + + ==== `Zifencei` ISA Extension The `Zifencei` CPU extension allows manual synchronization of the instruction stream. This extension is always enabled. @@ -1054,8 +1028,8 @@ behave like regular C functions but that evaluate to a single custom instruction .CFU Execution Time [NOTE] The actual CFU execution time depends on the logic being implemented. The CPU architecture requires a minimal execution -time of 3 cycle and automatically terminates execution after 512 cycles if the CFU does not complete operation within -this time window. +time of 3 cycles (purely combinatorial CFU operation) and automatically terminates execution after 512 cycles if the CFU +does not complete operation within this time window. .Instructions and Timing [cols="<2,<5,<2"] diff --git a/docs/datasheet/cpu_csr.adoc b/docs/datasheet/cpu_csr.adoc index df479aa8a..931083b32 100644 --- a/docs/datasheet/cpu_csr.adoc +++ b/docs/datasheet/cpu_csr.adoc @@ -220,7 +220,6 @@ will _not_ cause an illegal instruction exception. [options="header",grid="rows"] |======================= | Bit | Name [C] | R/W | Function -| 0 | `CSR_MISA_A_EXT` | r/- | **A**: CPU extension (atomic memory access) available, set when <<_a_isa_extension>> enabled | 1 | `CSR_MISA_B_EXT` | r/- | **B**: CPU extension (bit-manipulation) available, set when <<_b_isa_extension>> enabled | 2 | `CSR_MISA_C_EXT` | r/- | **C**: CPU extension (compressed instruction) available, set when <<_c_isa_extension>> enabled | 4 | `CSR_MISA_E_EXT` | r/- | **E**: CPU extension (embedded) available, set when <<_e_isa_extension>> enabled @@ -972,7 +971,8 @@ discover ISA sub-extensions and CPU configuration options | 22 | `CSR_MXISA_ZBA` | r/- | <<_zba_isa_extension>> available | 23 | `CSR_MXISA_ZBB` | r/- | <<_zbb_isa_extension>> available | 24 | `CSR_MXISA_ZBS` | r/- | <<_zbs_isa_extension>> available -| 27:25 | - | r/- | _reserved_, hardwired to zero +| 25 | `CSR_MXISA_ZALRSC` | r/- | <<_zalrsc_isa_extension>> available +| 27:26 | - | r/- | _reserved_, hardwired to zero | 28 | `CSR_MXISA_RFHWRST` | r/- | full hardware reset of register file available when set (`REGFILE_HW_RST`) | 29 | `CSR_MXISA_FASTMUL` | r/- | fast multiplication available when set (`FAST_MUL_EN`) | 30 | `CSR_MXISA_FASTSHIFT` | r/- | fast shifts available when set (`FAST_SHIFT_EN`) diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc index f90879a4a..ac2c531a4 100644 --- a/docs/datasheet/soc.adoc +++ b/docs/datasheet/soc.adoc @@ -205,11 +205,11 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt | `ON_CHIP_DEBUGGER_EN` | boolean | false | Implement the on-chip debugger and the CPU debug mode. | `DM_LEGACY_MODE` | boolean | false | Debug module spec. version: `false` = v1.0, `true` = v0.13 (legacy mode). 4+^| **CPU <<_instruction_sets_and_extensions>>** -| `RISCV_ISA_A` | boolean | false | Enable <<_a_isa_extension>> (atomic memory accesses). | `RISCV_ISA_C` | boolean | false | Enable <<_c_isa_extension>> (compressed instructions). | `RISCV_ISA_E` | boolean | false | Enable <<_e_isa_extension>> (reduced register file size). | `RISCV_ISA_M` | boolean | false | Enable <<_m_isa_extension>> (hardware-based integer multiplication and division). | `RISCV_ISA_U` | boolean | false | Enable <<_u_isa_extension>> (less-privileged user mode). +| `RISCV_ISA_Zalrsc` | boolean | false | Enable <<_zalrsc_isa_extension>> (atomic reservation-set operations). | `RISCV_ISA_Zba` | boolean | false | Enable <<_zba_isa_extension>> (shifted-add bit-manipulation instructions). | `RISCV_ISA_Zbb` | boolean | false | Enable <<_zbb_isa_extension>> (basic bit-manipulation instructions). | `RISCV_ISA_Zbkb` | boolean | false | Enable <<_zbkb_isa_extension>> (scalar cryptography bit manipulation instructions). diff --git a/docs/figures/neorv32_processor.png b/docs/figures/neorv32_processor.png index 5d2faa5f9..c1c603ba5 100644 Binary files a/docs/figures/neorv32_processor.png and b/docs/figures/neorv32_processor.png differ diff --git a/rtl/core/neorv32_cpu.vhd b/rtl/core/neorv32_cpu.vhd index 247a72fef..861374611 100644 --- a/rtl/core/neorv32_cpu.vhd +++ b/rtl/core/neorv32_cpu.vhd @@ -28,11 +28,11 @@ entity neorv32_cpu is DEBUG_PARK_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode parking loop entry address DEBUG_EXC_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug mode exception entry address -- RISC-V ISA Extensions -- - RISCV_ISA_A : boolean; -- implement atomic memory operations extension RISCV_ISA_C : boolean; -- implement compressed extension RISCV_ISA_E : boolean; -- implement embedded RF extension RISCV_ISA_M : boolean; -- implement mul/div extension RISCV_ISA_U : boolean; -- implement user mode extension + RISCV_ISA_Zalrsc : boolean; -- implement atomic reservation-set extension RISCV_ISA_Zba : boolean; -- implement shifted-add bit-manipulation extension RISCV_ISA_Zbb : boolean; -- implement basic bit-manipulation extension RISCV_ISA_Zbkb : boolean; -- implement bit-manipulation instructions for cryptography @@ -135,12 +135,12 @@ begin -- CPU ISA configuration (in alphabetical order - not in canonical order!) -- assert false report "[NEORV32] CPU ISA: rv32" & cond_sel_string_f(RISCV_ISA_E, "e", "i") & - cond_sel_string_f(RISCV_ISA_A, "a", "" ) & cond_sel_string_f(riscv_b_c, "b", "" ) & cond_sel_string_f(RISCV_ISA_C, "c", "" ) & cond_sel_string_f(RISCV_ISA_M, "m", "" ) & cond_sel_string_f(RISCV_ISA_U, "u", "" ) & cond_sel_string_f(true, "x", "" ) & -- always enabled + cond_sel_string_f(RISCV_ISA_Zalrsc, "_zalrsc", "" ) & cond_sel_string_f(RISCV_ISA_Zba, "_zba", "" ) & cond_sel_string_f(RISCV_ISA_Zbb, "_zbb", "" ) & cond_sel_string_f(RISCV_ISA_Zbkb, "_zbkb", "" ) & @@ -190,12 +190,12 @@ begin DEBUG_PARK_ADDR => DEBUG_PARK_ADDR, -- cpu debug mode parking loop entry address DEBUG_EXC_ADDR => DEBUG_EXC_ADDR, -- cpu debug mode exception entry address -- RISC-V ISA Extensions -- - RISCV_ISA_A => RISCV_ISA_A, -- implement atomic memory operations extension RISCV_ISA_B => riscv_b_c, -- implement bit-manipulation extension RISCV_ISA_C => RISCV_ISA_C, -- implement compressed extension RISCV_ISA_E => RISCV_ISA_E, -- implement embedded RF extension RISCV_ISA_M => RISCV_ISA_M, -- implement mul/div extension RISCV_ISA_U => RISCV_ISA_U, -- implement user mode extension + RISCV_ISA_Zalrsc => RISCV_ISA_Zalrsc, -- implement atomic reservation-set extension RISCV_ISA_Zba => RISCV_ISA_Zba, -- implement shifted-add bit-manipulation extension RISCV_ISA_Zbb => RISCV_ISA_Zbb, -- implement basic bit-manipulation extension RISCV_ISA_Zbkb => RISCV_ISA_Zbkb, -- implement bit-manipulation instructions for cryptography @@ -351,7 +351,7 @@ begin -- ------------------------------------------------------------------------------------------- neorv32_cpu_lsu_inst: entity neorv32.neorv32_cpu_lsu generic map ( - AMO_LRSC_ENABLE => RISCV_ISA_A -- enable atomic LR/SC operations + AMO_LRSC_ENABLE => RISCV_ISA_Zalrsc -- enable atomic LR/SC operations ) port map ( -- global control -- diff --git a/rtl/core/neorv32_cpu_control.vhd b/rtl/core/neorv32_cpu_control.vhd index 3f4e0adf4..36a5d7186 100644 --- a/rtl/core/neorv32_cpu_control.vhd +++ b/rtl/core/neorv32_cpu_control.vhd @@ -35,17 +35,17 @@ entity neorv32_cpu_control is DEBUG_PARK_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug-mode parking loop entry address, 4-byte aligned DEBUG_EXC_ADDR : std_ulogic_vector(31 downto 0); -- cpu debug-mode exception entry address, 4-byte aligned -- RISC-V ISA Extensions -- - RISCV_ISA_A : boolean; -- implement atomic memory operations extension RISCV_ISA_B : boolean; -- implement bit-manipulation extension RISCV_ISA_C : boolean; -- implement compressed extension RISCV_ISA_E : boolean; -- implement embedded-class register file extension RISCV_ISA_M : boolean; -- implement mul/div extension RISCV_ISA_U : boolean; -- implement user mode extension + RISCV_ISA_Zalrsc : boolean; -- implement atomic reservation-set extension RISCV_ISA_Zba : boolean; -- implement shifted-add bit-manipulation extension RISCV_ISA_Zbb : boolean; -- implement basic bit-manipulation extension RISCV_ISA_Zbkb : boolean; -- implement bit-manipulation instructions for cryptography RISCV_ISA_Zbkc : boolean; -- implement carry-less multiplication instructions - RISCV_ISA_Zbkx : boolean; -- implement cryptography crossbar permutation extension? + RISCV_ISA_Zbkx : boolean; -- implement cryptography crossbar permutation extension RISCV_ISA_Zbs : boolean; -- implement single-bit bit-manipulation extension RISCV_ISA_Zfinx : boolean; -- implement 32-bit floating-point extension RISCV_ISA_Zicntr : boolean; -- implement base counters @@ -525,7 +525,7 @@ begin when opcode_jal_c => -- J-immediate alu_imm_o <= replicate_f(execute_engine.ir(31), 12) & execute_engine.ir(19 downto 12) & execute_engine.ir(20) & execute_engine.ir(30 downto 21) & '0'; when opcode_amo_c => -- atomic memory access - if RISCV_ISA_A then alu_imm_o <= (others => '0'); end if; + if RISCV_ISA_Zalrsc then alu_imm_o <= (others => '0'); end if; when others => NULL; -- use default end case; @@ -684,7 +684,7 @@ begin end case; -- memory read/write access -- - if RISCV_ISA_A and (opcode(2) = opcode_amo_c(2)) then -- atomic lr/sc + if RISCV_ISA_Zalrsc and (opcode(2) = opcode_amo_c(2)) then -- atomic lr/sc ctrl_nxt.lsu_rw <= execute_engine.ir(instr_funct7_lsb_c+2); else -- normal load/store ctrl_nxt.lsu_rw <= execute_engine.ir(5); @@ -850,7 +850,7 @@ begin (trap_ctrl.exc_buf(exc_saccess_c) = '1') or (trap_ctrl.exc_buf(exc_laccess_c) = '1') or -- access exception (trap_ctrl.exc_buf(exc_salign_c) = '1') or (trap_ctrl.exc_buf(exc_lalign_c) = '1') or -- alignment exception (trap_ctrl.exc_buf(exc_illegal_c) = '1') then -- illegal instruction exception - if (RISCV_ISA_A and (opcode(2) = opcode_amo_c(2))) or (opcode(5) = '0') then -- atomic operation / normal load + if (RISCV_ISA_Zalrsc and (opcode(2) = opcode_amo_c(2))) or (opcode(5) = '0') then -- atomic operation / normal load ctrl_nxt.rf_wb_en <= '1'; -- allow write-back to register file (won't happen in case of exception) end if; execute_engine.state_nxt <= DISPATCH; @@ -1077,8 +1077,8 @@ begin end case; when opcode_amo_c => -- atomic memory operation (LR/SC) - if RISCV_ISA_A and (execute_engine.ir(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") and - (execute_engine.ir(instr_funct7_lsb_c+6 downto instr_funct7_lsb_c+3) = "0001") then -- LR.W/SC.W + if RISCV_ISA_Zalrsc and (execute_engine.ir(instr_funct3_msb_c downto instr_funct3_lsb_c) = "010") and + (execute_engine.ir(instr_funct7_lsb_c+6 downto instr_funct7_lsb_c+3) = "0001") then -- LR.W/SC.W illegal_cmd <= '0'; else illegal_cmd <= '1'; @@ -1722,7 +1722,6 @@ begin -- when csr_mstatush_c => csr.rdata <= (others => '0'); -- machine status register, high word - hardwired to zero when csr_misa_c => -- ISA and extensions - csr.rdata(0) <= bool_to_ulogic_f(RISCV_ISA_A); -- A CPU extension csr.rdata(1) <= bool_to_ulogic_f(RISCV_ISA_B); -- B CPU extension csr.rdata(2) <= bool_to_ulogic_f(RISCV_ISA_C); -- C CPU extension csr.rdata(4) <= bool_to_ulogic_f(RISCV_ISA_E); -- E CPU extension @@ -1911,8 +1910,8 @@ begin csr.rdata(22) <= bool_to_ulogic_f(RISCV_ISA_Zba); -- Zba: shifted-add bit-manipulation csr.rdata(23) <= bool_to_ulogic_f(RISCV_ISA_Zbb); -- Zbb: basic bit-manipulation extension csr.rdata(24) <= bool_to_ulogic_f(RISCV_ISA_Zbs); -- Zbs: single-bit bit-manipulation extension + csr.rdata(25) <= bool_to_ulogic_f(RISCV_ISA_Zalrsc); -- Zalrsc: reservation set extension -- reserved -- - csr.rdata(25) <= '0'; csr.rdata(26) <= '0'; csr.rdata(27) <= '0'; -- tuning options -- diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index 99b2cda1d..0ffd3cdab 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -29,7 +29,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100501"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100502"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width @@ -677,11 +677,11 @@ package neorv32_package is ON_CHIP_DEBUGGER_EN : boolean := false; DM_LEGACY_MODE : boolean := false; -- RISC-V CPU Extensions -- - RISCV_ISA_A : boolean := false; RISCV_ISA_C : boolean := false; RISCV_ISA_E : boolean := false; RISCV_ISA_M : boolean := false; RISCV_ISA_U : boolean := false; + RISCV_ISA_Zalrsc : boolean := false; RISCV_ISA_Zba : boolean := false; RISCV_ISA_Zbb : boolean := false; RISCV_ISA_Zbkb : boolean := false; diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd index fa246e095..fc86aa405 100644 --- a/rtl/core/neorv32_top.vhd +++ b/rtl/core/neorv32_top.vhd @@ -33,11 +33,11 @@ entity neorv32_top is DM_LEGACY_MODE : boolean := false; -- debug module spec version: false = v1.0, true = v0.13 -- RISC-V CPU Extensions -- - RISCV_ISA_A : boolean := false; -- implement atomic memory operations extension RISCV_ISA_C : boolean := false; -- implement compressed extension RISCV_ISA_E : boolean := false; -- implement embedded RF extension RISCV_ISA_M : boolean := false; -- implement mul/div extension RISCV_ISA_U : boolean := false; -- implement user mode extension + RISCV_ISA_Zalrsc : boolean := false; -- implement atomic reservation-set extension RISCV_ISA_Zba : boolean := false; -- implement shifted-add bit-manipulation extension RISCV_ISA_Zbb : boolean := false; -- implement basic bit-manipulation extension RISCV_ISA_Zbkb : boolean := false; -- implement bit-manipulation instructions for cryptography @@ -453,11 +453,11 @@ begin DEBUG_PARK_ADDR => dm_park_entry_c, DEBUG_EXC_ADDR => dm_exc_entry_c, -- RISC-V ISA Extensions -- - RISCV_ISA_A => RISCV_ISA_A, RISCV_ISA_C => RISCV_ISA_C, RISCV_ISA_E => RISCV_ISA_E, RISCV_ISA_M => RISCV_ISA_M, RISCV_ISA_U => RISCV_ISA_U, + RISCV_ISA_Zalrsc => RISCV_ISA_Zalrsc, RISCV_ISA_Zba => RISCV_ISA_Zba, RISCV_ISA_Zbb => RISCV_ISA_Zbb, RISCV_ISA_Zbkb => RISCV_ISA_Zbkb, @@ -666,7 +666,7 @@ begin -- Reservation Set Controller (for atomic LR/SC accesses) -- ************************************************************************************************************************** neorv32_bus_reservation_set_true: - if RISCV_ISA_A generate + if RISCV_ISA_Zalrsc generate neorv32_bus_reservation_set_inst: entity neorv32.neorv32_bus_reservation_set port map ( clk_i => clk_i, @@ -682,7 +682,7 @@ begin end generate; neorv32_bus_reservation_set_false: - if not RISCV_ISA_A generate + if not RISCV_ISA_Zalrsc generate main2_req <= main_req; main_rsp <= main2_rsp; end generate; diff --git a/rtl/system_integration/neorv32_vivado_ip.tcl b/rtl/system_integration/neorv32_vivado_ip.tcl index 468e79942..065cba873 100644 --- a/rtl/system_integration/neorv32_vivado_ip.tcl +++ b/rtl/system_integration/neorv32_vivado_ip.tcl @@ -130,8 +130,6 @@ ipgui::move_param -component [ipx::current_core] -order 10 [ipgui::get_guiparams # ************************************************************** # Configuration GUI: CPU # ************************************************************** -set_property display_name {RISC-V A ISA extension} [ipgui::get_guiparamspec -name "RISCV_ISA_A" -component [ipx::current_core]] -set_property tooltip {Atomic memory operations} [ipgui::get_guiparamspec -name "RISCV_ISA_A" -component [ipx::current_core]] set_property display_name {RISC-V C ISA extension} [ipgui::get_guiparamspec -name "RISCV_ISA_C" -component [ipx::current_core]] set_property tooltip {Compressed instructions} [ipgui::get_guiparamspec -name "RISCV_ISA_C" -component [ipx::current_core]] set_property display_name {RISC-V E ISA extension} [ipgui::get_guiparamspec -name "RISCV_ISA_E" -component [ipx::current_core]] @@ -140,6 +138,8 @@ set_property display_name {RISC-V M ISA extension} [ipgu set_property tooltip {Integer multiplication and division hardware} [ipgui::get_guiparamspec -name "RISCV_ISA_M" -component [ipx::current_core]] set_property display_name {RISC-V U ISA extension} [ipgui::get_guiparamspec -name "RISCV_ISA_U" -component [ipx::current_core]] set_property tooltip {Less-privileged user-mode} [ipgui::get_guiparamspec -name "RISCV_ISA_U" -component [ipx::current_core]] +set_property display_name {RISC-V Zalrsc ISA extension} [ipgui::get_guiparamspec -name "RISCV_ISA_Zalrsc" -component [ipx::current_core]] +set_property tooltip {Atomic reservation-set instructions} [ipgui::get_guiparamspec -name "RISCV_ISA_Zalrsc" -component [ipx::current_core]] set_property display_name {RISC-V Zba ISA extension} [ipgui::get_guiparamspec -name "RISCV_ISA_Zba" -component [ipx::current_core]] set_property tooltip {Shifted-add bit-manipulation instructions} [ipgui::get_guiparamspec -name "RISCV_ISA_Zba" -component [ipx::current_core]] set_property display_name {RISC-V Zbb ISA extension} [ipgui::get_guiparamspec -name "RISCV_ISA_Zbb" -component [ipx::current_core]] @@ -191,12 +191,12 @@ set_property display_name {Enable PMP NA2 and NAPOT modes} [ipgu set_property tooltip {Naturally-aligned-power-of-two} [ipgui::get_guiparamspec -name "PMP_NAP_MODE_EN" -component [ipx::current_core]] ipgui::add_group -name {CPU Configuration} -component [ipx::current_core] -parent [ipgui::get_pagespec -name "Page 0" -component [ipx::current_core]] -display_name {CPU Configuration} -ipgui::move_group -component [ipx::current_core] -order 1 [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] -parent [ipgui::get_pagespec -name "Page 0" -component [ipx::current_core]] -ipgui::move_param -component [ipx::current_core] -order 0 [ipgui::get_guiparamspec -name "RISCV_ISA_A" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] -ipgui::move_param -component [ipx::current_core] -order 1 [ipgui::get_guiparamspec -name "RISCV_ISA_C" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] -ipgui::move_param -component [ipx::current_core] -order 2 [ipgui::get_guiparamspec -name "RISCV_ISA_E" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] -ipgui::move_param -component [ipx::current_core] -order 3 [ipgui::get_guiparamspec -name "RISCV_ISA_M" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] -ipgui::move_param -component [ipx::current_core] -order 4 [ipgui::get_guiparamspec -name "RISCV_ISA_U" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] +ipgui::move_group -component [ipx::current_core] -order 1 [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] -parent [ipgui::get_pagespec -name "Page 0" -component [ipx::current_core]] +ipgui::move_param -component [ipx::current_core] -order 0 [ipgui::get_guiparamspec -name "RISCV_ISA_C" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] +ipgui::move_param -component [ipx::current_core] -order 1 [ipgui::get_guiparamspec -name "RISCV_ISA_E" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] +ipgui::move_param -component [ipx::current_core] -order 2 [ipgui::get_guiparamspec -name "RISCV_ISA_M" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] +ipgui::move_param -component [ipx::current_core] -order 3 [ipgui::get_guiparamspec -name "RISCV_ISA_U" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] +ipgui::move_param -component [ipx::current_core] -order 4 [ipgui::get_guiparamspec -name "RISCV_ISA_Zalrsc" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] ipgui::move_param -component [ipx::current_core] -order 5 [ipgui::get_guiparamspec -name "RISCV_ISA_Zba" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] ipgui::move_param -component [ipx::current_core] -order 6 [ipgui::get_guiparamspec -name "RISCV_ISA_Zbb" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] ipgui::move_param -component [ipx::current_core] -order 7 [ipgui::get_guiparamspec -name "RISCV_ISA_Zfinx" -component [ipx::current_core]] -parent [ipgui::get_groupspec -name "CPU Configuration" -component [ipx::current_core]] @@ -376,8 +376,4 @@ ipx::save_core [ipx::current_core] set_property ip_repo_paths $cur_dir/$outputdir/packaged_ip [current_project] update_ip_catalog - -# ************************************************************** -# Close IP-packaging project -# ************************************************************** close_project diff --git a/rtl/system_integration/neorv32_vivado_ip.vhd b/rtl/system_integration/neorv32_vivado_ip.vhd index 584b4b6a2..4eb77e716 100644 --- a/rtl/system_integration/neorv32_vivado_ip.vhd +++ b/rtl/system_integration/neorv32_vivado_ip.vhd @@ -35,11 +35,11 @@ entity neorv32_vivado_ip is -- On-Chip Debugger (OCD) -- ON_CHIP_DEBUGGER_EN : boolean := false; -- RISC-V CPU Extensions -- - RISCV_ISA_A : boolean := false; RISCV_ISA_C : boolean := false; RISCV_ISA_E : boolean := false; RISCV_ISA_M : boolean := false; RISCV_ISA_U : boolean := false; + RISCV_ISA_Zalrsc : boolean := false; RISCV_ISA_Zba : boolean := false; RISCV_ISA_Zbb : boolean := false; RISCV_ISA_Zbkb : boolean := false; @@ -310,11 +310,11 @@ begin ON_CHIP_DEBUGGER_EN => ON_CHIP_DEBUGGER_EN, DM_LEGACY_MODE => false, -- RISC-V CPU Extensions -- - RISCV_ISA_A => RISCV_ISA_A, RISCV_ISA_C => RISCV_ISA_C, RISCV_ISA_E => RISCV_ISA_E, RISCV_ISA_M => RISCV_ISA_M, RISCV_ISA_U => RISCV_ISA_U, + RISCV_ISA_Zalrsc => RISCV_ISA_Zalrsc, RISCV_ISA_Zba => RISCV_ISA_Zba, RISCV_ISA_Zbb => RISCV_ISA_Zbb, RISCV_ISA_Zbkb => RISCV_ISA_Zbkb, diff --git a/sim/neorv32_tb.vhd b/sim/neorv32_tb.vhd index ba25d6137..b2a824aa9 100644 --- a/sim/neorv32_tb.vhd +++ b/sim/neorv32_tb.vhd @@ -200,11 +200,11 @@ begin -- On-Chip Debugger (OCD) -- ON_CHIP_DEBUGGER_EN => true, -- implement on-chip debugger -- RISC-V CPU Extensions -- - RISCV_ISA_A => true, -- implement atomic memory operations extension? RISCV_ISA_C => true, -- implement compressed extension? RISCV_ISA_E => false, -- implement embedded RF extension? RISCV_ISA_M => true, -- implement mul/div extension? RISCV_ISA_U => true, -- implement user mode extension? + RISCV_ISA_Zalrsc => true, -- implement atomic reservation-set extension RISCV_ISA_Zba => true, -- implement shifted-add bit-manipulation extension RISCV_ISA_Zbb => true, -- implement basic bit-manipulation extension RISCV_ISA_Zbkb => true, -- implement bit-manipulation instructions for cryptography diff --git a/sim/simple/neorv32_tb.simple.vhd b/sim/simple/neorv32_tb.simple.vhd index f4026fa66..7c98aaa84 100644 --- a/sim/simple/neorv32_tb.simple.vhd +++ b/sim/simple/neorv32_tb.simple.vhd @@ -172,11 +172,11 @@ begin -- On-Chip Debugger (OCD) -- ON_CHIP_DEBUGGER_EN => true, -- implement on-chip debugger -- RISC-V CPU Extensions -- - RISCV_ISA_A => true, -- implement atomic memory operations extension? RISCV_ISA_C => false, -- implement compressed extension? RISCV_ISA_E => false, -- implement embedded RF extension? RISCV_ISA_M => true, -- implement mul/div extension? RISCV_ISA_U => true, -- implement user mode extension? + RISCV_ISA_Zalrsc => true, -- implement atomic reservation-set extension RISCV_ISA_Zba => true, -- implement shifted-add bit-manipulation extension RISCV_ISA_Zbb => true, -- implement basic bit-manipulation extension RISCV_ISA_Zbkb => true, -- implement bit-manipulation instructions for cryptography diff --git a/sw/example/atomic_test/main.c b/sw/example/atomic_test/main.c index 7fb4fa6b2..de87c4f68 100644 --- a/sw/example/atomic_test/main.c +++ b/sw/example/atomic_test/main.c @@ -121,7 +121,7 @@ int main() { neorv32_uart0_printf("<<< NEORV32 AMO Operations (atomic read-modify-write) Emulation Test >>>\n\n"); // check if A extension is implemented at all - if ((neorv32_cpu_csr_read(CSR_MISA) & (1<