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input/output/inout (Verilog) in signal names causes issues #13

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stiggy87 opened this issue Nov 29, 2012 · 1 comment

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stiggy87 commented Nov 29, 2012

If a user has input/output/inout in names of signals, the current regexp causes it to be grabbed and parsed improperly.

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stiggy87 commented Dec 19, 2012

To Do:

Add Regex exception to determine this and then ignore. This may need variable transfers between regex lines.

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