From 294d32ca802d1a72f8f5b4913f27c3e023c9a738 Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Wed, 19 Feb 2025 18:22:06 +0200 Subject: [PATCH 1/2] build: enable debug mode Rust builds with verilator --- README.md | 2 ++ examples/hello_rt/Makefile | 6 +++++- examples/periodic_tasks/Makefile | 6 +++++- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 1b40391..8b831b1 100644 --- a/README.md +++ b/README.md @@ -27,6 +27,8 @@ Verilator simulations can be invoked from the repository root with make verilate simv TEST= # Rust make verilate simv RUST=1 TEST_DIR=examples/hello_rt TEST= +# Rust (debug mode with software assertions) +make verilate simv RUST=1 DEBUG=1 TEST_DIR=examples/hello_rt TEST= ``` This will clean and compile the design and the software test, then invoke the simulation. diff --git a/examples/hello_rt/Makefile b/examples/hello_rt/Makefile index d6e040d..6c199b1 100644 --- a/examples/hello_rt/Makefile +++ b/examples/hello_rt/Makefile @@ -1,4 +1,8 @@ +ifndef DEBUG +MAYBE_RELEASE = --release +endif + # Build the entire program .PHONY: $(TEST) $(TEST): - cargo build --release -Frtl-tb --example $(TEST) $(CARGO_FLAGS) + cargo build $(MAYBE_RELEASE) -Frtl-tb --example $(TEST) $(CARGO_FLAGS) diff --git a/examples/periodic_tasks/Makefile b/examples/periodic_tasks/Makefile index 677657c..abc5fbb 100644 --- a/examples/periodic_tasks/Makefile +++ b/examples/periodic_tasks/Makefile @@ -1,4 +1,8 @@ +ifndef DEBUG +MAYBE_RELEASE = --release +endif + # Build the entire program .PHONY: $(TEST) $(TEST): - cargo build --release -Frtl-tb --bin $(TEST) $(CARGO_FLAGS) + cargo build $(MAYBE_RELEASE) -Frtl-tb --bin $(TEST) $(CARGO_FLAGS) From cf480a11b814147235bc0ea1228eb64dc15e40f3 Mon Sep 17 00:00:00 2001 From: Henri Lunnikivi Date: Wed, 19 Feb 2025 18:22:26 +0200 Subject: [PATCH 2/2] bsp(timer_group): debug assert cnt <= cmp --- examples/atalanta_bsp/src/timer_group.rs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/examples/atalanta_bsp/src/timer_group.rs b/examples/atalanta_bsp/src/timer_group.rs index ccf9100..1eb8ada 100644 --- a/examples/atalanta_bsp/src/timer_group.rs +++ b/examples/atalanta_bsp/src/timer_group.rs @@ -63,6 +63,12 @@ impl Timer { /// Set current timer counter value #[inline] pub fn set_counter(&mut self, cnt: u32) { + #[cfg(debug_assertions)] + { + // Counter must not be set to a value higher than compare + let cmp = read_u32p(unsafe { &mut (*self.0).cmp as *mut u32 }); + debug_assert!(cnt <= cmp); + } write_u32p(unsafe { &mut (*self.0).cnt as *mut u32 }, cnt) }