All notable changes to this project will be documented in this file.
The format is based on Keep a Changelog and this project adheres to Semantic Versioning.
- 4 * 32-bit timer group
- QSPI APB peripheral (umapped in FPGA)
- Wake from sleep with IRQ
- Mtimer X values
- Mtimer with new implementation
- rt-ibex to version with functional hardware stacking
- Peripherals frequency to be runtime-configurable
- Make Mtimer writable
- Verilator support after long stale period
- Erronious hard-coded program entry address
- PCS instance to default design configuration
- Readmem-program loading for Verilator
- C++ port of elfloader for Verilator
- "wfi" to timer_test to accommodate for rt-ibex's sleep mode
- Support for UART receiver in Atalanta and its TB environment
- UART_RX test case and updated UART baudrate
- OBI Bender dependency to vendor package to avoid problematic syntax in
obi_cut.sv - Core fully-connected crossbar to partially-connected pseudo-crossbar
- Refactor smoke_tests and handling of crt0.s in SW flow
- NanoDMA instance with interrupt-based test
- GPIO output sanity test to examples,
vip_rt_top
- interconnect address map width
OtherRulesbad initialization- DMA undriven ports
- DMA
read_mgr.addrandwrite_mgr.addrlatches - DMA
rd_reqandwr_reqcombo loops - uart.sv duplicated newline behavior
- Peripheral memory map to fit SPI
- AXI address mapping end address
- RT-Ibex initial fetch address to BASE+0x100 (was 0x80) to accommodate 64 entry vector table
- FPGA flow timing error handling
- OpenTitan SPI host IP due to internal undriven port
- Changelog