From f36227bf9c0e3057f130d115df7db9eb73e02188 Mon Sep 17 00:00:00 2001 From: Julian Mendez Date: Tue, 8 Aug 2023 14:58:48 -0700 Subject: [PATCH 1/7] fix idelaye3 issues - busy signal and placement --- xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd | 2 +- xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd b/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd index 3f7f95b18c..e63f22b401 100644 --- a/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd +++ b/xilinx/UltraScale/general/rtl/Delaye3PatchFsm.vhd @@ -134,7 +134,7 @@ begin -- Outputs patchLoad <= r.Load; patchCntValue <= r.dlyValue; - if (v.dlyTarget /= CNTVALUEOUT) or (r.state /= IDLE_S) then + if (r.state /= IDLE_S) then busy <= '1'; else busy <= '0'; diff --git a/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd b/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd index f8304daa25..06e93d2fec 100644 --- a/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd +++ b/xilinx/UltraScale/general/rtl/Idelaye3Wrapper.vhd @@ -37,7 +37,8 @@ entity Idelaye3Wrapper is IS_RST_INVERTED : bit := '0'; -- Optional inversion for RST REFCLK_FREQUENCY : real := 300.0; -- IDELAYCTRL clock input frequency in MHz (200.0-2667.0) SIM_DEVICE : string := "ULTRASCALE"; -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS) - UPDATE_MODE : string := "ASYNC"); -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC) + UPDATE_MODE : string := "ASYNC"; + IODELAY_GROUP_G : string := "DLYGRP_C"); -- Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC) port ( BUSY : out sl; -- 1-bit output: Patch module is busy CASC_OUT : out sl; -- 1-bit output: Cascade delay output to ODELAY input cascade @@ -62,6 +63,9 @@ architecture rtl of Idelaye3Wrapper is signal patchCntValue : slv(8 downto 0); signal patchLoad : sl; + attribute IODELAY_GROUP : string; + attribute IODELAY_GROUP of U_IDELAYE3 : label is IODELAY_GROUP_G; + begin CNTVALUEOUT <= currentCntValue; From 854aa0b04967357f5dbff13112e2c5e4e0dd174a Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 20 Sep 2023 14:55:51 -0700 Subject: [PATCH 2/7] Update Pgp4TxLiteWrapper.vhd ### Description - Cadence Genus will give an error if the port has a default value on the entity definition but not connected at the component instantiation. - This PR resolves this error --- protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd index 780e19d25b..a7dee767d5 100644 --- a/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd +++ b/protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd @@ -83,6 +83,11 @@ begin pgpTxActive => '1', pgpTxMasters(0) => pgpTxMaster, pgpTxSlaves(0) => pgpTxSlave, + -- Status of receive and remote FIFOs (Asynchronous) + locRxFifoCtrl(0)=> AXI_STREAM_CTRL_UNUSED_C, + locRxLinkReady => '1', + remRxFifoCtrl(0)=> AXI_STREAM_CTRL_UNUSED_C, + remRxLinkReady => '1', -- PHY interface phyTxActive => '1', phyTxReady => phyTxReady, From ee47639c5832a030b3e01ac5221a0ff4b2cb7afd Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 22 Sep 2023 13:49:41 -0700 Subject: [PATCH 3/7] .sh whitespace removal --- ghdl-build.sh | 2 +- scripts/generateDocumentationAndDeploy.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/ghdl-build.sh b/ghdl-build.sh index 3915889e6e..035036d0c4 100755 --- a/ghdl-build.sh +++ b/ghdl-build.sh @@ -9,7 +9,7 @@ # the terms contained in the LICENSE.txt file. #----------------------------------------------------------------------------- -# Note: The manually installing of ghdl v3.0.0 until supported in Github Action's Ubuntu LTS +# Note: The manually installing of ghdl v3.0.0 until supported in Github Action's Ubuntu LTS echo 'Installing GHDL ...' sudo apt update diff --git a/scripts/generateDocumentationAndDeploy.sh b/scripts/generateDocumentationAndDeploy.sh index db81602698..7a2698fde8 100644 --- a/scripts/generateDocumentationAndDeploy.sh +++ b/scripts/generateDocumentationAndDeploy.sh @@ -88,7 +88,7 @@ echo "" > .nojekyll echo 'Generating Doxygen code documentation...' doxygen -v -# Update the INPUT configuration +# Update the INPUT configuration echo "INPUT = $TRAVIS_BUILD_DIR" >> $DOXYFILE # Update the EXCLUDE configuration From d8199967b8de2979012d691d38ff32e7fe3f2844 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 22 Sep 2023 13:50:30 -0700 Subject: [PATCH 4/7] .vh whitespace removal --- .../Micron/ddr3/tb/1024Mb_ddr3_parameters.vh | 58 +++++++++---------- .../Micron/ddr3/tb/2048Mb_ddr3_parameters.vh | 58 +++++++++---------- .../Micron/ddr3/tb/4096Mb_ddr3_parameters.vh | 58 +++++++++---------- .../Micron/ddr3/tb/8192Mb_ddr3_parameters.vh | 50 ++++++++-------- 4 files changed, 112 insertions(+), 112 deletions(-) diff --git a/devices/Micron/ddr3/tb/1024Mb_ddr3_parameters.vh b/devices/Micron/ddr3/tb/1024Mb_ddr3_parameters.vh index d42ba3fc94..934a37cdd8 100644 --- a/devices/Micron/ddr3/tb/1024Mb_ddr3_parameters.vh +++ b/devices/Micron/ddr3/tb/1024Mb_ddr3_parameters.vh @@ -1,24 +1,24 @@ /**************************************************************************************** * -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the * above limitation may not apply to you. * * Copyright 2003 Micron Technology, Inc. All rights reserved. @@ -54,7 +54,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width parameter TIS = 35; // tIS ps Input Setup Time parameter TIH = 75; // tIH ps Input Hold Time parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time @@ -94,7 +94,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width parameter TIS = 50; // tIS ps Input Setup Time parameter TIH = 100; // tIH ps Input Hold Time parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time @@ -134,7 +134,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width parameter TIS = 170; // tIS ps Input Setup Time parameter TIH = 120; // tIH ps Input Hold Time parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time @@ -174,7 +174,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -214,7 +214,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -254,7 +254,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -294,7 +294,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -334,7 +334,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width parameter TIS = 350; // tIS ps Input Setup Time parameter TIH = 275; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -375,7 +375,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width parameter TIS = 350; // tIS ps Input Setup Time parameter TIH = 275; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -478,7 +478,7 @@ parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - + // Data OUT parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# // Data Strobe OUT diff --git a/devices/Micron/ddr3/tb/2048Mb_ddr3_parameters.vh b/devices/Micron/ddr3/tb/2048Mb_ddr3_parameters.vh index 6fcfffb5d7..eaaa813ab8 100644 --- a/devices/Micron/ddr3/tb/2048Mb_ddr3_parameters.vh +++ b/devices/Micron/ddr3/tb/2048Mb_ddr3_parameters.vh @@ -1,24 +1,24 @@ /**************************************************************************************** * -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the * above limitation may not apply to you. * * Copyright 2003 Micron Technology, Inc. All rights reserved. @@ -54,7 +54,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width parameter TIS = 35; // tIS ps Input Setup Time parameter TIH = 75; // tIH ps Input Hold Time parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time @@ -94,7 +94,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width parameter TIS = 50; // tIS ps Input Setup Time parameter TIH = 100; // tIH ps Input Hold Time parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time @@ -134,7 +134,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width parameter TIS = 170; // tIS ps Input Setup Time parameter TIH = 120; // tIH ps Input Hold Time parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time @@ -174,7 +174,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -214,7 +214,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -254,7 +254,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -294,7 +294,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -334,7 +334,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width parameter TIS = 350; // tIS ps Input Setup Time parameter TIH = 275; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -375,7 +375,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width parameter TIS = 350; // tIS ps Input Setup Time parameter TIH = 275; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -466,7 +466,7 @@ parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - + // Data OUT parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# // Data Strobe OUT diff --git a/devices/Micron/ddr3/tb/4096Mb_ddr3_parameters.vh b/devices/Micron/ddr3/tb/4096Mb_ddr3_parameters.vh index e9e7e93136..a5fe950670 100644 --- a/devices/Micron/ddr3/tb/4096Mb_ddr3_parameters.vh +++ b/devices/Micron/ddr3/tb/4096Mb_ddr3_parameters.vh @@ -1,24 +1,24 @@ /**************************************************************************************** * -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the * above limitation may not apply to you. * * Copyright 2003 Micron Technology, Inc. All rights reserved. @@ -54,7 +54,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width parameter TIS = 35; // tIS ps Input Setup Time parameter TIH = 75; // tIH ps Input Hold Time parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time @@ -94,7 +94,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width parameter TIS = 50; // tIS ps Input Setup Time parameter TIH = 100; // tIH ps Input Hold Time parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time @@ -134,7 +134,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width parameter TIS = 170; // tIS ps Input Setup Time parameter TIH = 120; // tIH ps Input Hold Time parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time @@ -174,7 +174,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -214,7 +214,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -254,7 +254,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -294,7 +294,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -334,7 +334,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width parameter TIS = 350; // tIS ps Input Setup Time parameter TIH = 275; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -375,7 +375,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width parameter TIS = 350; // tIS ps Input Setup Time parameter TIH = 275; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -466,7 +466,7 @@ parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - + // Data OUT parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# // Data Strobe OUT diff --git a/devices/Micron/ddr3/tb/8192Mb_ddr3_parameters.vh b/devices/Micron/ddr3/tb/8192Mb_ddr3_parameters.vh index c6848ad0d2..9a99186149 100644 --- a/devices/Micron/ddr3/tb/8192Mb_ddr3_parameters.vh +++ b/devices/Micron/ddr3/tb/8192Mb_ddr3_parameters.vh @@ -1,24 +1,24 @@ /**************************************************************************************** * -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the * above limitation may not apply to you. * * Copyright 2003 Micron Technology, Inc. All rights reserved. @@ -54,7 +54,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width parameter TIS = 35; // tIS ps Input Setup Time parameter TIH = 75; // tIH ps Input Hold Time parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time @@ -94,7 +94,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width parameter TIS = 50; // tIS ps Input Setup Time parameter TIH = 100; // tIH ps Input Hold Time parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time @@ -134,7 +134,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width parameter TIS = 170; // tIS ps Input Setup Time parameter TIH = 120; // tIH ps Input Hold Time parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time @@ -174,7 +174,7 @@ parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width parameter TIS = 190; // tIS ps Input Setup Time parameter TIH = 140; // tIH ps Input Hold Time parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time @@ -215,7 +215,7 @@ parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width parameter TIS = 275; // tIS ps Input Setup Time parameter TIH = 200; // tIH ps Input Hold Time parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time @@ -306,7 +306,7 @@ parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - + // Data OUT parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# // Data Strobe OUT From 24dd43cab0168b4158f8554164cf9500f9d5fa4d Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Fri, 22 Sep 2023 13:52:22 -0700 Subject: [PATCH 5/7] .c/.h whitespace removal --- axi/simlink/src/RogueSideBand.c | 24 +- axi/simlink/src/RogueSideBand.h | 18 +- axi/simlink/src/RogueTcpMemory.c | 36 +- axi/simlink/src/RogueTcpMemory.h | 18 +- axi/simlink/src/RogueTcpStream.c | 32 +- axi/simlink/src/RogueTcpStream.h | 14 +- axi/simlink/src/VhpiGeneric.c | 30 +- axi/simlink/src/VhpiGeneric.h | 16 +- base/general/simlink/src/VhpiGeneric.c | 24 +- base/general/simlink/src/VhpiGeneric.h | 16 +- protocols/jtag/xvcSrv/src/mmioHelper.h | 12 +- protocols/jtag/xvcSrv/src/xvcConn.h | 12 +- protocols/jtag/xvcSrv/src/xvcDriver.h | 12 +- protocols/jtag/xvcSrv/src/xvcDrvAxisFifo.h | 12 +- protocols/jtag/xvcSrv/src/xvcDrvLoopBack.h | 12 +- protocols/jtag/xvcSrv/src/xvcDrvUdp.h | 12 +- protocols/jtag/xvcSrv/src/xvcSrv.h | 12 +- xilinx/general/sdk/common/printf.c | 490 ++++++++++----------- xilinx/general/sdk/common/printf.h | 248 +++++------ xilinx/general/sdk/common/ssi_printf.c | 18 +- xilinx/general/sdk/common/ssi_printf.h | 10 +- 21 files changed, 539 insertions(+), 539 deletions(-) diff --git a/axi/simlink/src/RogueSideBand.c b/axi/simlink/src/RogueSideBand.c index b1bc374661..43e6b54e34 100755 --- a/axi/simlink/src/RogueSideBand.c +++ b/axi/simlink/src/RogueSideBand.c @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -27,17 +27,17 @@ void RogueSideBandRestart(RogueSideBandData *data, portDataT *portData) { char buffer[100]; - if ( data->zmqPush != NULL ) zmq_close(data->zmqPush ); + if ( data->zmqPush != NULL ) zmq_close(data->zmqPush ); if ( data->zmqPull != NULL ) zmq_close(data->zmqPull); if ( data->zmqCtx != NULL ) zmq_term(data->zmqCtx); data->zmqCtx = NULL; data->zmqPush = NULL; data->zmqPull = NULL; - + data->zmqCtx = zmq_ctx_new(); data->zmqPull = zmq_socket(data->zmqCtx,ZMQ_PULL); - data->zmqPush = zmq_socket(data->zmqCtx,ZMQ_PUSH); + data->zmqPush = zmq_socket(data->zmqCtx,ZMQ_PUSH); vhpi_printf("RogueSideBand: Listening on ports %i & %i\n",data->port, data->port+1); @@ -52,7 +52,7 @@ void RogueSideBandRestart(RogueSideBandData *data, portDataT *portData) { vhpi_assert("RogueSideBand: Failed to bind push port",vhpiFatal); return; } - + } // Send a message @@ -61,7 +61,7 @@ void RogueSideBandSend ( RogueSideBandData *data, portDataT *portData ) { uint8_t ba[4]; char buffer[200]; - if ( (zmq_msg_init_size(&msg,4) < 0) ) { + if ( (zmq_msg_init_size(&msg,4) < 0) ) { vhpi_assert("RogueSideBand: Failed to init message",vhpiFatal); return; } @@ -119,7 +119,7 @@ int RogueSideBandRecv ( RogueSideBandData *data, portDataT *portData ) { } // Init function -void RogueSideBandInit(vhpiHandleT compInst) { +void RogueSideBandInit(vhpiHandleT compInst) { // Create new port data structure portDataT *portData = (portDataT *) malloc(sizeof(portDataT)); @@ -188,7 +188,7 @@ void RogueSideBandUpdate ( void *userPtr ) { data->rxOpCode = 0x00; data->rxOpCodeEn = 0; data->txRemData = 0x00; - data->txRemDataChanged = 0x00; + data->txRemDataChanged = 0x00; data->txOpCode = 0x00; data->txOpCodeEn = 0; setInt(s_rxOpCodeEn,0); diff --git a/axi/simlink/src/RogueSideBand.h b/axi/simlink/src/RogueSideBand.h index 1df1779393..c82bf01ea1 100755 --- a/axi/simlink/src/RogueSideBand.h +++ b/axi/simlink/src/RogueSideBand.h @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -35,20 +35,20 @@ typedef struct { uint32_t currClk; uint16_t port; - + uint8_t rxRemData; uint8_t rxOpCode; uint8_t rxOpCodeEn; uint8_t txRemData; - uint8_t txRemDataChanged; + uint8_t txRemDataChanged; uint8_t txOpCode; uint8_t txOpCodeEn; void * zmqCtx; void * zmqPull; - void * zmqPush; - + void * zmqPush; + } RogueSideBandData; // Init function diff --git a/axi/simlink/src/RogueTcpMemory.c b/axi/simlink/src/RogueTcpMemory.c index 53d4b3fa68..a08fc0e3da 100755 --- a/axi/simlink/src/RogueTcpMemory.c +++ b/axi/simlink/src/RogueTcpMemory.c @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -34,7 +34,7 @@ void RogueTcpMemoryRestart(RogueTcpMemoryData *data, portDataT *portData) { data->zmqCtx = NULL; data->zmqPull = NULL; data->zmqPush = NULL; - + data->zmqCtx = zmq_ctx_new(); data->zmqPull = zmq_socket(data->zmqCtx,ZMQ_PULL); data->zmqPush = zmq_socket(data->zmqCtx,ZMQ_PUSH); @@ -61,9 +61,9 @@ void RogueTcpMemorySend ( RogueTcpMemoryData *data, portDataT *portData ) { zmq_msg_t msg[6]; if ( (zmq_msg_init_size(&(msg[0]),4) < 0) || // ID - (zmq_msg_init_size(&(msg[1]),8) < 0) || // Addr - (zmq_msg_init_size(&(msg[2]),4) < 0) || // Size - (zmq_msg_init_size(&(msg[3]),4) < 0) || // type + (zmq_msg_init_size(&(msg[1]),8) < 0) || // Addr + (zmq_msg_init_size(&(msg[2]),4) < 0) || // Size + (zmq_msg_init_size(&(msg[3]),4) < 0) || // type (zmq_msg_init_size(&(msg[5]),4) < 0) ) { // result vhpi_assert("RogueTcpMemory: Failed to init message header",vhpiFatal); return; @@ -82,7 +82,7 @@ void RogueTcpMemorySend ( RogueTcpMemoryData *data, portDataT *portData ) { // Copy data memcpy(zmq_msg_data(&(msg[4])),data->data,data->size); - + // Send data for (x=0; x < 6; x++) { if ( zmq_sendmsg(data->zmqPush,&(msg[x]),(x==5)?0:ZMQ_SNDMORE) < 0 ) @@ -162,7 +162,7 @@ int RogueTcpMemoryRecv ( RogueTcpMemoryData *data, portDataT *portData ) { } // Init function -void RogueTcpMemoryInit(vhpiHandleT compInst) { +void RogueTcpMemoryInit(vhpiHandleT compInst) { // Create new port data structure portDataT *portData = (portDataT *) malloc(sizeof(portDataT)); @@ -172,9 +172,9 @@ void RogueTcpMemoryInit(vhpiHandleT compInst) { portData->portCount = PORT_COUNT; // Set port directions - portData->portDir[s_clock] = vhpiIn; - portData->portDir[s_reset] = vhpiIn; - portData->portDir[s_port] = vhpiIn; + portData->portDir[s_clock] = vhpiIn; + portData->portDir[s_reset] = vhpiIn; + portData->portDir[s_port] = vhpiIn; portData->portDir[s_araddr] = vhpiOut; portData->portDir[s_arprot] = vhpiOut; @@ -200,9 +200,9 @@ void RogueTcpMemoryInit(vhpiHandleT compInst) { portData->portDir[s_bvalid] = vhpiIn; // Set port widths - portData->portWidth[s_clock] = 1; - portData->portWidth[s_reset] = 1; - portData->portWidth[s_port] = 16; + portData->portWidth[s_clock] = 1; + portData->portWidth[s_reset] = 1; + portData->portWidth[s_port] = 16; portData->portWidth[s_araddr] = 32; portData->portWidth[s_arprot] = 3; @@ -262,7 +262,7 @@ void RogueTcpMemoryUpdate ( void *userPtr ) { setInt(s_rready,1); setInt(s_awvalid,0); setInt(s_bready,1); - } + } // Data movement else { diff --git a/axi/simlink/src/RogueTcpMemory.h b/axi/simlink/src/RogueTcpMemory.h index 97bafa48a0..a081fdb03d 100755 --- a/axi/simlink/src/RogueTcpMemory.h +++ b/axi/simlink/src/RogueTcpMemory.h @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -66,12 +66,12 @@ typedef struct { uint8_t arprot; uint8_t arvalid; uint8_t rready; - + uint8_t arready; uint32_t rdata; uint8_t rresp; uint8_t rvalid; - + uint32_t awaddr; uint8_t awprot; uint8_t awvalid; @@ -79,7 +79,7 @@ typedef struct { uint8_t wstrb; uint8_t wvalid; uint8_t bready; - + uint8_t awready; uint8_t wready; uint8_t bresp; @@ -100,7 +100,7 @@ typedef struct { void * zmqCtx; void * zmqPull; void * zmqPush; - + } RogueTcpMemoryData; // Init function diff --git a/axi/simlink/src/RogueTcpStream.c b/axi/simlink/src/RogueTcpStream.c index c67dd1db77..e7f77a0faf 100755 --- a/axi/simlink/src/RogueTcpStream.c +++ b/axi/simlink/src/RogueTcpStream.c @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -35,7 +35,7 @@ void RogueTcpStreamRestart(RogueTcpStreamData *data, portDataT *portData) { data->zmqCtx = NULL; data->zmqPush = NULL; data->zmqPull = NULL; - + data->zmqCtx = zmq_ctx_new(); data->zmqPull = zmq_socket(data->zmqCtx,ZMQ_PULL); data->zmqPush = zmq_socket(data->zmqCtx,ZMQ_PUSH); @@ -93,7 +93,7 @@ void RogueTcpStreamSend ( RogueTcpStreamData *data, portDataT *portData ) { // Copy data memcpy(zmq_msg_data(&(msg[3])),data->ibData,data->ibSize); - + // Send data for (x=0; x < 4; x++) { if ( zmq_msg_send(&(msg[x]), data->zmqPush, (x==3)?0:ZMQ_SNDMORE) < 0 ) { @@ -180,7 +180,7 @@ int RogueTcpStreamRecv ( RogueTcpStreamData *data, portDataT *portData ) { // Init function -void RogueTcpStreamInit(vhpiHandleT compInst) { +void RogueTcpStreamInit(vhpiHandleT compInst) { // Create new port data structure portDataT *portData = (portDataT *) malloc(sizeof(portDataT)); @@ -190,10 +190,10 @@ void RogueTcpStreamInit(vhpiHandleT compInst) { portData->portCount = PORT_COUNT; // Set port directions - portData->portDir[s_clock] = vhpiIn; - portData->portDir[s_reset] = vhpiIn; - portData->portDir[s_port] = vhpiIn; - portData->portDir[s_ssi] = vhpiIn; + portData->portDir[s_clock] = vhpiIn; + portData->portDir[s_reset] = vhpiIn; + portData->portDir[s_port] = vhpiIn; + portData->portDir[s_ssi] = vhpiIn; portData->portDir[s_obValid] = vhpiOut; portData->portDir[s_obReady] = vhpiIn; @@ -204,7 +204,7 @@ void RogueTcpStreamInit(vhpiHandleT compInst) { portData->portDir[s_obKeep] = vhpiOut; portData->portDir[s_obLast] = vhpiOut; - portData->portDir[s_ibValid] = vhpiIn; + portData->portDir[s_ibValid] = vhpiIn; portData->portDir[s_ibReady] = vhpiOut; portData->portDir[s_ibDataLow] = vhpiIn; portData->portDir[s_ibDataHigh] = vhpiIn; @@ -285,7 +285,7 @@ void RogueTcpStreamUpdate ( void *userPtr ) { setInt(s_obUserHigh,0); setInt(s_obKeep,0); setInt(s_obLast,0); - } + } // Data movement else { @@ -341,7 +341,7 @@ void RogueTcpStreamUpdate ( void *userPtr ) { if ( data->obCount == 0 ) setInt(s_obUserLow,data->obFuser); else setInt(s_obUserLow,0); setInt(s_obUserHigh,0); - + // Get data dHigh = 0; dLow = 0; @@ -362,7 +362,7 @@ void RogueTcpStreamUpdate ( void *userPtr ) { } else { dHigh |= (data->obData[data->obCount] << ((x-4)*8)); - if ( (data->obCount+1) == data->obSize ) + if ( (data->obCount+1) == data->obSize ) setInt(s_obUserHigh,(data->obLuser << ((x-4)*8))); } diff --git a/axi/simlink/src/RogueTcpStream.h b/axi/simlink/src/RogueTcpStream.h index 95382d650c..e4091ad73e 100755 --- a/axi/simlink/src/RogueTcpStream.h +++ b/axi/simlink/src/RogueTcpStream.h @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -62,11 +62,11 @@ typedef struct { uint16_t port; uint8_t ssi; time_t ltime; - + void * zmqCtx; void * zmqPush; void * zmqPull; - + } RogueTcpStreamData; // Init function diff --git a/axi/simlink/src/VhpiGeneric.c b/axi/simlink/src/VhpiGeneric.c index 89e89f7e92..22d6984323 100755 --- a/axi/simlink/src/VhpiGeneric.c +++ b/axi/simlink/src/VhpiGeneric.c @@ -12,11 +12,11 @@ // and only has to set the width and the in/out types for each port. //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- // Modification history: @@ -48,7 +48,7 @@ void VhpiGenericConvertIn( portDataT *portData ) { for (x=0; x < portData->portCount; x++) { if ( portData->portDir[x] != vhpiOut ) { if ( portData->portWidth[x] == 1 ) { - if ( portData->portValue[x]->value.enumval == 3 ) + if ( portData->portValue[x]->value.enumval == 3 ) portData->intValue[x] = 1; else portData->intValue[x] = 0; @@ -57,7 +57,7 @@ void VhpiGenericConvertIn( portDataT *portData ) { portData->intValue[x] = 0; for (y=0; y < portData->portWidth[x]; y++) { bit = (portData->portWidth[x] - 1) - y; - if ( portData->portValue[x]->value.enums[y] == 3 ) + if ( portData->portValue[x]->value.enums[y] == 3 ) portData->intValue[x] += 1<portValue[x]->value.enums[y] = 2; } } - else + else for (y=0; y < portData->portWidth[x]; y++) { portData->portValue[x]->value.enums[y] = 4; // Tri-state } @@ -136,7 +136,7 @@ void VhpiGenericCallBack(vhpiCbDataT *cbData ) { // Set output values for (x=0; x < portData->portCount; x++) { - if ( portData->portDir[x] != vhpiIn ) + if ( portData->portDir[x] != vhpiIn ) if ( (ret = vhpi_put_value(portData->portHandle[x],portData->portValue[x], vhpiForcePropagate))) vhpi_printf("vhpi_put_value status error %i for port %i\n",ret,x); } @@ -152,7 +152,7 @@ void VhpiGenericErrors ( vhpiCbDataT *cb ) { // Function that is called as the module is elaborated. -// Here we will simply register an error handling callback function. +// Here we will simply register an error handling callback function. void VhpiGenericElab(vhpiHandleT compInst) { // Create callback structure, setup callback function @@ -160,16 +160,16 @@ void VhpiGenericElab(vhpiHandleT compInst) { pCbData->cbf = VhpiGenericErrors; pCbData->time = (vhpiTimeT*) malloc(sizeof(vhpiTimeT)); pCbData->reason = vhpiCbPLIError; - + #if (VCS_VERSION >= 2016) vhpi_register_cb(pCbData,vhpiReturnCb); #else vhpi_register_cb(pCbData); -#endif +#endif } -// Function that is called as the module is initialized. +// Function that is called as the module is initialized. // Check ports and setup functions to handle clock changes void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ) { @@ -208,7 +208,7 @@ void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ) { width = vhpi_value_size(portData->portHandle[x],vhpiEnumVecVal); portData->portValue[x]->value.enums = (vhpiEnumT*)malloc(width); portData->portValue[x]->bufSize = width; - for (y=0; y < portData->portWidth[x]; y++ ) + for (y=0; y < portData->portWidth[x]; y++ ) portData->portValue[x]->value.enums[y] = 2; } @@ -244,6 +244,6 @@ void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ) { vhpi_register_cb(cbData,vhpiReturnCb); #else vhpi_register_cb(cbData); - #endif + #endif } } diff --git a/axi/simlink/src/VhpiGeneric.h b/axi/simlink/src/VhpiGeneric.h index 8921bb44cb..0d18c2946d 100755 --- a/axi/simlink/src/VhpiGeneric.h +++ b/axi/simlink/src/VhpiGeneric.h @@ -8,14 +8,14 @@ //----------------------------------------------------------------------------- // Description: // This is a generic block of code to handle the low level interface to the -// VHDL simulator. +// VHDL simulator. //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- // Modification history: @@ -59,7 +59,7 @@ typedef struct portDataS { // Current simulation time vhpiTimeT simTime; - + // Name of block char *blockName; @@ -72,7 +72,7 @@ typedef struct portDataS { } portDataT; -// Function that is called as the module is initialized. +// Function that is called as the module is initialized. // Check ports and setup functions to handle clock changes void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ); diff --git a/base/general/simlink/src/VhpiGeneric.c b/base/general/simlink/src/VhpiGeneric.c index 8891a5798c..769cd3430f 100755 --- a/base/general/simlink/src/VhpiGeneric.c +++ b/base/general/simlink/src/VhpiGeneric.c @@ -12,11 +12,11 @@ // and only has to set the width and the in/out types for each port. //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- // Modification history: @@ -49,7 +49,7 @@ void VhpiGenericConvertIn( portDataT *portData ) { for (x=0; x < portData->portCount; x++) { if ( portData->portDir[x] != vhpiOut ) { if ( portData->portWidth[x] == 1 ) { - if ( portData->portValue[x]->value.enumval == 3 ) + if ( portData->portValue[x]->value.enumval == 3 ) portData->intValue[x] = 1; else portData->intValue[x] = 0; @@ -58,7 +58,7 @@ void VhpiGenericConvertIn( portDataT *portData ) { portData->intValue[x] = 0; for (y=0; y < portData->portWidth[x]; y++) { bit = (portData->portWidth[x] - 1) - y; - if ( portData->portValue[x]->value.enums[y] == 3 ) + if ( portData->portValue[x]->value.enums[y] == 3 ) portData->intValue[x] += 1<portValue[x]->value.enums[y] = 2; } } - else + else for (y=0; y < portData->portWidth[x]; y++) { portData->portValue[x]->value.enums[y] = 4; // Tri-state } @@ -135,7 +135,7 @@ void VhpiGenericCallBack(vhpiCbDataT *cbData ) { // Set output values for (x=0; x < portData->portCount; x++) { - if ( portData->portDir[x] != vhpiIn ) + if ( portData->portDir[x] != vhpiIn ) vhpi_put_value(portData->portHandle[x],portData->portValue[x], vhpiForcePropagate); } } @@ -150,7 +150,7 @@ void VhpiGenericErrors ( vhpiCbDataT *cb ) { // Function that is called as the module is elaborated. -// Here we will simply register an error handling callback function. +// Here we will simply register an error handling callback function. void VhpiGenericElab(vhpiHandleT compInst) { // Create callback structure, setup callback function @@ -162,7 +162,7 @@ void VhpiGenericElab(vhpiHandleT compInst) { } -// Function that is called as the module is initialized. +// Function that is called as the module is initialized. // Check ports and setup functions to handle clock changes void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ) { @@ -198,7 +198,7 @@ void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ) { portData->portValue[x]->format = vhpiEnumVecVal; width = vhpi_value_size(portData->portHandle[x],vhpiEnumVecVal); portData->portValue[x]->value.enums = (vhpiEnumT*)malloc(width); - for (y=0; y < portData->portWidth[x]; y++ ) + for (y=0; y < portData->portWidth[x]; y++ ) portData->portValue[x]->value.enums[y] = 2; } diff --git a/base/general/simlink/src/VhpiGeneric.h b/base/general/simlink/src/VhpiGeneric.h index 8921bb44cb..0d18c2946d 100755 --- a/base/general/simlink/src/VhpiGeneric.h +++ b/base/general/simlink/src/VhpiGeneric.h @@ -8,14 +8,14 @@ //----------------------------------------------------------------------------- // Description: // This is a generic block of code to handle the low level interface to the -// VHDL simulator. +// VHDL simulator. //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- // Modification history: @@ -59,7 +59,7 @@ typedef struct portDataS { // Current simulation time vhpiTimeT simTime; - + // Name of block char *blockName; @@ -72,7 +72,7 @@ typedef struct portDataS { } portDataT; -// Function that is called as the module is initialized. +// Function that is called as the module is initialized. // Check ports and setup functions to handle clock changes void VhpiGenericInit(vhpiHandleT compInst, portDataT *portData ); diff --git a/protocols/jtag/xvcSrv/src/mmioHelper.h b/protocols/jtag/xvcSrv/src/mmioHelper.h index ff72ecac2c..9a82723002 100644 --- a/protocols/jtag/xvcSrv/src/mmioHelper.h +++ b/protocols/jtag/xvcSrv/src/mmioHelper.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/protocols/jtag/xvcSrv/src/xvcConn.h b/protocols/jtag/xvcSrv/src/xvcConn.h index 18c937fc24..da38543b15 100644 --- a/protocols/jtag/xvcSrv/src/xvcConn.h +++ b/protocols/jtag/xvcSrv/src/xvcConn.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/protocols/jtag/xvcSrv/src/xvcDriver.h b/protocols/jtag/xvcSrv/src/xvcDriver.h index aeadbc9374..8951be3b10 100644 --- a/protocols/jtag/xvcSrv/src/xvcDriver.h +++ b/protocols/jtag/xvcSrv/src/xvcDriver.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/protocols/jtag/xvcSrv/src/xvcDrvAxisFifo.h b/protocols/jtag/xvcSrv/src/xvcDrvAxisFifo.h index e394bf9e65..d1d9bdf7fb 100644 --- a/protocols/jtag/xvcSrv/src/xvcDrvAxisFifo.h +++ b/protocols/jtag/xvcSrv/src/xvcDrvAxisFifo.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/protocols/jtag/xvcSrv/src/xvcDrvLoopBack.h b/protocols/jtag/xvcSrv/src/xvcDrvLoopBack.h index d841a04419..277e6a6c88 100644 --- a/protocols/jtag/xvcSrv/src/xvcDrvLoopBack.h +++ b/protocols/jtag/xvcSrv/src/xvcDrvLoopBack.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/protocols/jtag/xvcSrv/src/xvcDrvUdp.h b/protocols/jtag/xvcSrv/src/xvcDrvUdp.h index d1649542e9..d0dc69e699 100644 --- a/protocols/jtag/xvcSrv/src/xvcDrvUdp.h +++ b/protocols/jtag/xvcSrv/src/xvcDrvUdp.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/protocols/jtag/xvcSrv/src/xvcSrv.h b/protocols/jtag/xvcSrv/src/xvcSrv.h index 28a357e38a..a361b91d77 100644 --- a/protocols/jtag/xvcSrv/src/xvcSrv.h +++ b/protocols/jtag/xvcSrv/src/xvcSrv.h @@ -3,14 +3,14 @@ //----------------------------------------------------------------------------- // Company : SLAC National Accelerator Laboratory //----------------------------------------------------------------------------- -// Description: +// Description: //----------------------------------------------------------------------------- // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. //----------------------------------------------------------------------------- diff --git a/xilinx/general/sdk/common/printf.c b/xilinx/general/sdk/common/printf.c index ebcb5f3b7e..5c3d85679b 100755 --- a/xilinx/general/sdk/common/printf.c +++ b/xilinx/general/sdk/common/printf.c @@ -1,245 +1,245 @@ -/* - * Copyright (c) 2004,2012 Kustaa Nyholm / SpareTimeLabs - * - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or other - * materials provided with the distribution. - * - * Neither the name of the Kustaa Nyholm or SpareTimeLabs nor the names of its - * contributors may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, - * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - */ - -#include "printf.h" - -typedef void (*putcf) (void*,char); -static putcf stdout_putf; -static void* stdout_putp; - - -#ifdef PRINTF_LONG_SUPPORT - -static void uli2a(unsigned long int num, unsigned int base, int uc,char * bf) - { - int n=0; - unsigned int d=1; - while (num/d >= base) - d*=base; - while (d!=0) { - int dgt = num / d; - num%=d; - d/=base; - if (n || dgt>0|| d==0) { - *bf++ = dgt+(dgt<10 ? '0' : (uc ? 'A' : 'a')-10); - ++n; - } - } - *bf=0; - } - -static void li2a (long num, char * bf) - { - if (num<0) { - num=-num; - *bf++ = '-'; - } - uli2a(num,10,0,bf); - } - -#endif - -static void ui2a(unsigned int num, unsigned int base, int uc,char * bf) - { - int n=0; - unsigned int d=1; - while (num/d >= base) - d*=base; - while (d!=0) { - int dgt = num / d; - num%= d; - d/=base; - if (n || dgt>0 || d==0) { - *bf++ = dgt+(dgt<10 ? '0' : (uc ? 'A' : 'a')-10); - ++n; - } - } - *bf=0; - } - -static void i2a (int num, char * bf) - { - if (num<0) { - num=-num; - *bf++ = '-'; - } - ui2a(num,10,0,bf); - } - -static int a2d(char ch) - { - if (ch>='0' && ch<='9') - return ch-'0'; - else if (ch>='a' && ch<='f') - return ch-'a'+10; - else if (ch>='A' && ch<='F') - return ch-'A'+10; - else return -1; - } - -static char a2i(char ch, const char** src,int base,int* nump) - { - const char* p= *src; - int num=0; - int digit; - while ((digit=a2d(ch))>=0) { - if (digit>base) break; - num=num*base+digit; - ch=*p++; - } - *src=p; - *nump=num; - return ch; - } - -static void putchw(void* putp,putcf putf,int n, char z, char* bf) - { - char fc=z? '0' : ' '; - char ch; - char* p=bf; - while (*p++ && n > 0) - n--; - while (n-- > 0) - putf(putp,fc); - while ((ch= *bf++)) - putf(putp,ch); - } - -void tfp_format(void* putp,putcf putf,const char *fmt, va_list va) - { - char bf[12]; - - char ch; - - - while ((ch=*(fmt++))) { - if (ch!='%') - putf(putp,ch); - else { - char lz=0; -#ifdef PRINTF_LONG_SUPPORT - char lng=0; -#endif - int w=0; - ch=*(fmt++); - if (ch=='0') { - ch=*(fmt++); - lz=1; - } - if (ch>='0' && ch<='9') { - ch=a2i(ch,&fmt,10,&w); - } -#ifdef PRINTF_LONG_SUPPORT - if (ch=='l') { - ch=*(fmt++); - lng=1; - } -#endif - switch (ch) { - case 0: - goto abort; - case 'u' : { -#ifdef PRINTF_LONG_SUPPORT - if (lng) - uli2a(va_arg(va, unsigned long int),10,0,bf); - else -#endif - ui2a(va_arg(va, unsigned int),10,0,bf); - putchw(putp,putf,w,lz,bf); - break; - } - case 'd' : { -#ifdef PRINTF_LONG_SUPPORT - if (lng) - li2a(va_arg(va, unsigned long int),bf); - else -#endif - i2a(va_arg(va, int),bf); - putchw(putp,putf,w,lz,bf); - break; - } - case 'x': case 'X' : -#ifdef PRINTF_LONG_SUPPORT - if (lng) - uli2a(va_arg(va, unsigned long int),16,(ch=='X'),bf); - else -#endif - ui2a(va_arg(va, unsigned int),16,(ch=='X'),bf); - putchw(putp,putf,w,lz,bf); - break; - case 'c' : - putf(putp,(char)(va_arg(va, int))); - break; - case 's' : - putchw(putp,putf,w,0,va_arg(va, char*)); - break; - case '%' : - putf(putp,ch); - default: - break; - } - } - } - abort:; - } - - -void init_printf(void* putp,void (*putf) (void*,char)) - { - stdout_putf=putf; - stdout_putp=putp; - } - -void tfp_printf(const char *fmt, ...) - { - va_list va; - va_start(va,fmt); - tfp_format(stdout_putp,stdout_putf,fmt,va); - va_end(va); - } - -static void putcp(void* p,char c) - { - *(*((char**)p))++ = c; - } - - - -void tfp_sprintf(char* s,const char *fmt, ...) - { - va_list va; - va_start(va,fmt); - tfp_format(&s,putcp,fmt,va); - putcp(&s,0); - va_end(va); - } - - +/* + * Copyright (c) 2004,2012 Kustaa Nyholm / SpareTimeLabs + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * Neither the name of the Kustaa Nyholm or SpareTimeLabs nor the names of its + * contributors may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + */ + +#include "printf.h" + +typedef void (*putcf) (void*,char); +static putcf stdout_putf; +static void* stdout_putp; + + +#ifdef PRINTF_LONG_SUPPORT + +static void uli2a(unsigned long int num, unsigned int base, int uc,char * bf) + { + int n=0; + unsigned int d=1; + while (num/d >= base) + d*=base; + while (d!=0) { + int dgt = num / d; + num%=d; + d/=base; + if (n || dgt>0|| d==0) { + *bf++ = dgt+(dgt<10 ? '0' : (uc ? 'A' : 'a')-10); + ++n; + } + } + *bf=0; + } + +static void li2a (long num, char * bf) + { + if (num<0) { + num=-num; + *bf++ = '-'; + } + uli2a(num,10,0,bf); + } + +#endif + +static void ui2a(unsigned int num, unsigned int base, int uc,char * bf) + { + int n=0; + unsigned int d=1; + while (num/d >= base) + d*=base; + while (d!=0) { + int dgt = num / d; + num%= d; + d/=base; + if (n || dgt>0 || d==0) { + *bf++ = dgt+(dgt<10 ? '0' : (uc ? 'A' : 'a')-10); + ++n; + } + } + *bf=0; + } + +static void i2a (int num, char * bf) + { + if (num<0) { + num=-num; + *bf++ = '-'; + } + ui2a(num,10,0,bf); + } + +static int a2d(char ch) + { + if (ch>='0' && ch<='9') + return ch-'0'; + else if (ch>='a' && ch<='f') + return ch-'a'+10; + else if (ch>='A' && ch<='F') + return ch-'A'+10; + else return -1; + } + +static char a2i(char ch, const char** src,int base,int* nump) + { + const char* p= *src; + int num=0; + int digit; + while ((digit=a2d(ch))>=0) { + if (digit>base) break; + num=num*base+digit; + ch=*p++; + } + *src=p; + *nump=num; + return ch; + } + +static void putchw(void* putp,putcf putf,int n, char z, char* bf) + { + char fc=z? '0' : ' '; + char ch; + char* p=bf; + while (*p++ && n > 0) + n--; + while (n-- > 0) + putf(putp,fc); + while ((ch= *bf++)) + putf(putp,ch); + } + +void tfp_format(void* putp,putcf putf,const char *fmt, va_list va) + { + char bf[12]; + + char ch; + + + while ((ch=*(fmt++))) { + if (ch!='%') + putf(putp,ch); + else { + char lz=0; +#ifdef PRINTF_LONG_SUPPORT + char lng=0; +#endif + int w=0; + ch=*(fmt++); + if (ch=='0') { + ch=*(fmt++); + lz=1; + } + if (ch>='0' && ch<='9') { + ch=a2i(ch,&fmt,10,&w); + } +#ifdef PRINTF_LONG_SUPPORT + if (ch=='l') { + ch=*(fmt++); + lng=1; + } +#endif + switch (ch) { + case 0: + goto abort; + case 'u' : { +#ifdef PRINTF_LONG_SUPPORT + if (lng) + uli2a(va_arg(va, unsigned long int),10,0,bf); + else +#endif + ui2a(va_arg(va, unsigned int),10,0,bf); + putchw(putp,putf,w,lz,bf); + break; + } + case 'd' : { +#ifdef PRINTF_LONG_SUPPORT + if (lng) + li2a(va_arg(va, unsigned long int),bf); + else +#endif + i2a(va_arg(va, int),bf); + putchw(putp,putf,w,lz,bf); + break; + } + case 'x': case 'X' : +#ifdef PRINTF_LONG_SUPPORT + if (lng) + uli2a(va_arg(va, unsigned long int),16,(ch=='X'),bf); + else +#endif + ui2a(va_arg(va, unsigned int),16,(ch=='X'),bf); + putchw(putp,putf,w,lz,bf); + break; + case 'c' : + putf(putp,(char)(va_arg(va, int))); + break; + case 's' : + putchw(putp,putf,w,0,va_arg(va, char*)); + break; + case '%' : + putf(putp,ch); + default: + break; + } + } + } + abort:; + } + + +void init_printf(void* putp,void (*putf) (void*,char)) + { + stdout_putf=putf; + stdout_putp=putp; + } + +void tfp_printf(const char *fmt, ...) + { + va_list va; + va_start(va,fmt); + tfp_format(stdout_putp,stdout_putf,fmt,va); + va_end(va); + } + +static void putcp(void* p,char c) + { + *(*((char**)p))++ = c; + } + + + +void tfp_sprintf(char* s,const char *fmt, ...) + { + va_list va; + va_start(va,fmt); + tfp_format(&s,putcp,fmt,va); + putcp(&s,0); + va_end(va); + } + + diff --git a/xilinx/general/sdk/common/printf.h b/xilinx/general/sdk/common/printf.h index 536f987de7..a04ed7fac5 100755 --- a/xilinx/general/sdk/common/printf.h +++ b/xilinx/general/sdk/common/printf.h @@ -1,124 +1,124 @@ -/* -File: printf.h - -Copyright (c) 2004,2012 Kustaa Nyholm / SpareTimeLabs - -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -Redistributions of source code must retain the above copyright notice, this list -of conditions and the following disclaimer. - -Redistributions in binary form must reproduce the above copyright notice, this -list of conditions and the following disclaimer in the documentation and/or other -materials provided with the distribution. - -Neither the name of the Kustaa Nyholm or SpareTimeLabs nor the names of its -contributors may be used to endorse or promote products derived from this software -without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. - ----------------------------------------------------------------------- - -This library is realy just two files: 'printf.h' and 'printf.c'. - -They provide a simple and small (+200 loc) printf functionality to -be used in embedded systems. - -I've found them so usefull in debugging that I do not bother with a -debugger at all. - -They are distributed in source form, so to use them, just compile them -into your project. - -Two printf variants are provided: printf and sprintf. - -The formats supported by this implementation are: 'd' 'u' 'c' 's' 'x' 'X'. - -Zero padding and field width are also supported. - -If the library is compiled with 'PRINTF_SUPPORT_LONG' defined then the -long specifier is also -supported. Note that this will pull in some long math routines (pun intended!) -and thus make your executable noticably longer. - -The memory foot print of course depends on the target cpu, compiler and -compiler options, but a rough guestimate (based on a H8S target) is about -1.4 kB for code and some twenty 'int's and 'char's, say 60 bytes of stack space. -Not too bad. Your milage may vary. By hacking the source code you can -get rid of some hunred bytes, I'm sure, but personally I feel the balance of -functionality and flexibility versus code size is close to optimal for -many embedded systems. - -To use the printf you need to supply your own character output function, -something like : - -void putc ( void* p, char c) - { - while (!SERIAL_PORT_EMPTY) ; - SERIAL_PORT_TX_REGISTER = c; - } - -Before you can call printf you need to initialize it to use your -character output function with something like: - -init_printf(NULL,putc); - -Notice the 'NULL' in 'init_printf' and the parameter 'void* p' in 'putc', -the NULL (or any pointer) you pass into the 'init_printf' will eventually be -passed to your 'putc' routine. This allows you to pass some storage space (or -anything realy) to the character output function, if necessary. -This is not often needed but it was implemented like that because it made -implementing the sprintf function so neat (look at the source code). - -The code is re-entrant, except for the 'init_printf' function, so it -is safe to call it from interupts too, although this may result in mixed output. -If you rely on re-entrancy, take care that your 'putc' function is re-entrant! - -The printf and sprintf functions are actually macros that translate to -'tfp_printf' and 'tfp_sprintf'. This makes it possible -to use them along with 'stdio.h' printf's in a single source file. -You just need to undef the names before you include the 'stdio.h'. -Note that these are not function like macros, so if you have variables -or struct members with these names, things will explode in your face. -Without variadic macros this is the best we can do to wrap these -fucnction. If it is a problem just give up the macros and use the -functions directly or rename them. - -For further details see source code. - -regs Kusti, 23.10.2004 -*/ - - -#ifndef __TFP_PRINTF__ -#define __TFP_PRINTF__ - -#include - -void init_printf(void* putp,void (*putf) (void*,char)); - -void tfp_printf(const char *fmt, ...); -void tfp_sprintf(char* s,const char *fmt, ...); - -void tfp_format(void* putp,void (*putf) (void*,char),const char *fmt, va_list va); - -#define printf tfp_printf -#define sprintf tfp_sprintf - -#endif - - - +/* +File: printf.h + +Copyright (c) 2004,2012 Kustaa Nyholm / SpareTimeLabs + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +Redistributions of source code must retain the above copyright notice, this list +of conditions and the following disclaimer. + +Redistributions in binary form must reproduce the above copyright notice, this +list of conditions and the following disclaimer in the documentation and/or other +materials provided with the distribution. + +Neither the name of the Kustaa Nyholm or SpareTimeLabs nor the names of its +contributors may be used to endorse or promote products derived from this software +without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +---------------------------------------------------------------------- + +This library is realy just two files: 'printf.h' and 'printf.c'. + +They provide a simple and small (+200 loc) printf functionality to +be used in embedded systems. + +I've found them so usefull in debugging that I do not bother with a +debugger at all. + +They are distributed in source form, so to use them, just compile them +into your project. + +Two printf variants are provided: printf and sprintf. + +The formats supported by this implementation are: 'd' 'u' 'c' 's' 'x' 'X'. + +Zero padding and field width are also supported. + +If the library is compiled with 'PRINTF_SUPPORT_LONG' defined then the +long specifier is also +supported. Note that this will pull in some long math routines (pun intended!) +and thus make your executable noticably longer. + +The memory foot print of course depends on the target cpu, compiler and +compiler options, but a rough guestimate (based on a H8S target) is about +1.4 kB for code and some twenty 'int's and 'char's, say 60 bytes of stack space. +Not too bad. Your milage may vary. By hacking the source code you can +get rid of some hunred bytes, I'm sure, but personally I feel the balance of +functionality and flexibility versus code size is close to optimal for +many embedded systems. + +To use the printf you need to supply your own character output function, +something like : + +void putc ( void* p, char c) + { + while (!SERIAL_PORT_EMPTY) ; + SERIAL_PORT_TX_REGISTER = c; + } + +Before you can call printf you need to initialize it to use your +character output function with something like: + +init_printf(NULL,putc); + +Notice the 'NULL' in 'init_printf' and the parameter 'void* p' in 'putc', +the NULL (or any pointer) you pass into the 'init_printf' will eventually be +passed to your 'putc' routine. This allows you to pass some storage space (or +anything realy) to the character output function, if necessary. +This is not often needed but it was implemented like that because it made +implementing the sprintf function so neat (look at the source code). + +The code is re-entrant, except for the 'init_printf' function, so it +is safe to call it from interupts too, although this may result in mixed output. +If you rely on re-entrancy, take care that your 'putc' function is re-entrant! + +The printf and sprintf functions are actually macros that translate to +'tfp_printf' and 'tfp_sprintf'. This makes it possible +to use them along with 'stdio.h' printf's in a single source file. +You just need to undef the names before you include the 'stdio.h'. +Note that these are not function like macros, so if you have variables +or struct members with these names, things will explode in your face. +Without variadic macros this is the best we can do to wrap these +fucnction. If it is a problem just give up the macros and use the +functions directly or rename them. + +For further details see source code. + +regs Kusti, 23.10.2004 +*/ + + +#ifndef __TFP_PRINTF__ +#define __TFP_PRINTF__ + +#include + +void init_printf(void* putp,void (*putf) (void*,char)); + +void tfp_printf(const char *fmt, ...); +void tfp_sprintf(char* s,const char *fmt, ...); + +void tfp_format(void* putp,void (*putf) (void*,char),const char *fmt, va_list va); + +#define printf tfp_printf +#define sprintf tfp_sprintf + +#endif + + + diff --git a/xilinx/general/sdk/common/ssi_printf.c b/xilinx/general/sdk/common/ssi_printf.c index f95471c7b8..4b63686d1b 100644 --- a/xilinx/general/sdk/common/ssi_printf.c +++ b/xilinx/general/sdk/common/ssi_printf.c @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// @@ -32,7 +32,7 @@ void ssi_putc ( void* p, char c) { pp->tmp = 0; pp->tmpCnt = 0; } - + // Dual port ram buffer if enabled if ( pp->buffSize > 0 ) { //Xil_Out8(pp->buffBase+4+pp->buffPtr, c); @@ -44,17 +44,17 @@ void ssi_putc ( void* p, char c) { // Adjust pointer pp->buffPtr++; - if ( pp->buffPtr == (pp->buffSize-4) ) + if ( pp->buffPtr == (pp->buffSize-4) ) pp->buffPtr = 0; // Adjust total - if ( pp->buffTot < (pp->buffSize-4) ) + if ( pp->buffTot < (pp->buffSize-4) ) pp->buffTot++; // Update tracking Xil_Out32(pp->buffBase, pp->buffTot << 16 | pp->buffPtr); } - + } void ssi_printf_init(uint32_t buffBase, uint16_t buffSize) { diff --git a/xilinx/general/sdk/common/ssi_printf.h b/xilinx/general/sdk/common/ssi_printf.h index c28aa6402d..3ee37d6c1a 100644 --- a/xilinx/general/sdk/common/ssi_printf.h +++ b/xilinx/general/sdk/common/ssi_printf.h @@ -1,10 +1,10 @@ ////////////////////////////////////////////////////////////////////////////// // This file is part of 'SLAC Firmware Standard Library'. -// It is subject to the license terms in the LICENSE.txt file found in the -// top-level directory of this distribution and at: -// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. -// No part of 'SLAC Firmware Standard Library', including this file, -// may be copied, modified, propagated, or distributed except according to +// It is subject to the license terms in the LICENSE.txt file found in the +// top-level directory of this distribution and at: +// https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. +// No part of 'SLAC Firmware Standard Library', including this file, +// may be copied, modified, propagated, or distributed except according to // the terms contained in the LICENSE.txt file. ////////////////////////////////////////////////////////////////////////////// From 832c9502fa05d46f97e0a3541c3507583c4b08d3 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Mon, 25 Sep 2023 14:01:09 -0700 Subject: [PATCH 6/7] exposing JUMBO_G generic to high level ETH wrapper level --- ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd | 2 ++ ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd | 2 ++ ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd | 2 ++ .../GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd | 2 ++ ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd | 2 ++ ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd | 2 ++ ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd | 2 ++ ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd | 2 ++ ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd | 2 ++ ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd | 2 ++ ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd | 2 ++ .../TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd | 2 ++ .../gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd | 2 ++ .../TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd | 2 ++ .../gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd | 2 ++ ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd | 2 ++ ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd | 2 ++ .../TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd | 2 ++ .../gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd | 2 ++ ethernet/XauiCore/gth7/rtl/XauiGth7.vhd | 2 ++ ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd | 2 ++ ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd | 2 ++ .../XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd | 2 ++ ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd | 2 ++ .../XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd | 2 ++ ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd | 2 ++ ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd | 2 ++ ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd | 2 ++ .../XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd | 2 ++ 29 files changed, 58 insertions(+) diff --git a/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd b/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd index c3bd67f0ea..1236b18b45 100644 --- a/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd +++ b/ethernet/GigEthCore/gth7/rtl/GigEthGth7.vhd @@ -26,6 +26,7 @@ use surf.GigEthPkg.all; entity GigEthGth7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -170,6 +171,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, PHY_TYPE_G => "GMII", diff --git a/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd b/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd index 94061d5503..b46cb01d4f 100644 --- a/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd +++ b/ethernet/GigEthCore/gth7/rtl/GigEthGth7Wrapper.vhd @@ -31,6 +31,7 @@ entity GigEthGth7Wrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -166,6 +167,7 @@ begin U_GigEthGth7 : entity surf.GigEthGth7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd index 0312243ba9..1d1e2f86cd 100644 --- a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd +++ b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScale.vhd @@ -26,6 +26,7 @@ use surf.GigEthPkg.all; entity GigEthGthUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -182,6 +183,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, PHY_TYPE_G => "GMII", diff --git a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd index 9d0620f54c..9b5b31138c 100644 --- a/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd +++ b/ethernet/GigEthCore/gthUltraScale/rtl/GigEthGthUltraScaleWrapper.vhd @@ -31,6 +31,7 @@ entity GigEthGthUltraScaleWrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- Clocking Configurations EXT_PLL_G : boolean := false; @@ -193,6 +194,7 @@ begin U_GigEthGthUltraScale : entity surf.GigEthGthUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd index 8442c148f4..ad5168567e 100644 --- a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd +++ b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7.vhd @@ -26,6 +26,7 @@ use surf.GigEthPkg.all; entity GigEthGtp7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -224,6 +225,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, PHY_TYPE_G => "GMII", diff --git a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd index 6cff4cf26e..bfab8912fd 100644 --- a/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd +++ b/ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd @@ -31,6 +31,7 @@ entity GigEthGtp7Wrapper is TPD_G : time := 1 ns; SIMULATION_G : boolean := false; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; @@ -221,6 +222,7 @@ begin U_GigEthGtp7 : entity surf.GigEthGtp7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd index 5d28d3a8c5..59378c1ec8 100644 --- a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd +++ b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7.vhd @@ -27,6 +27,7 @@ use surf.GigEthPkg.all; entity GigEthGtx7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; SYNTH_MODE_G : string := "inferred"; -- AXI-Lite Configurations @@ -235,6 +236,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, PHY_TYPE_G => "GMII", diff --git a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd index 84639c0a2d..e593e34331 100644 --- a/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd +++ b/ethernet/GigEthCore/gtx7/rtl/GigEthGtx7Wrapper.vhd @@ -31,6 +31,7 @@ entity GigEthGtx7Wrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- Clocking Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -166,6 +167,7 @@ begin U_GigEthGtx7 : entity surf.GigEthGtx7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd b/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd index 397551aeb8..b09e32ac1c 100644 --- a/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd +++ b/ethernet/GigEthCore/lvdsUltraScale/rtl/GigEthLvdsUltraScale.vhd @@ -25,6 +25,7 @@ use surf.GigEthPkg.all; entity GigEthLvdsUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXIL_REG_G : boolean := false; @@ -156,6 +157,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PAUSE_512BITS_G => PAUSE_512BITS_C, PHY_TYPE_G => "GMII", diff --git a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd index dc484dc008..3b3b2ebb1e 100644 --- a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd +++ b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7.vhd @@ -26,6 +26,7 @@ use surf.EthMacPkg.all; entity TenGigEthGth7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -208,6 +209,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) diff --git a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd index f9392605a5..6e00f4454d 100644 --- a/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd +++ b/ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Wrapper.vhd @@ -28,6 +28,7 @@ entity TenGigEthGth7Wrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -126,6 +127,7 @@ begin TenGigEthGth7_Inst : entity surf.TenGigEthGth7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd index dc5850a151..4a5e2b891d 100644 --- a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScale.vhd @@ -25,6 +25,7 @@ use surf.EthMacPkg.all; entity TenGigEthGthUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -234,6 +235,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, FIFO_ADDR_WIDTH_G => 12, -- single 4K UltraRAM SYNTH_MODE_G => "xpm", diff --git a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd index fcb7ec41c4..33945f6105 100644 --- a/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd @@ -28,6 +28,7 @@ entity TenGigEthGthUltraScaleWrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations EXT_REF_G : boolean := false; @@ -143,6 +144,7 @@ begin TenGigEthGthUltraScale_Inst : entity surf.TenGigEthGthUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd index 9d740f47fe..3eab811909 100644 --- a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScale.vhd @@ -26,6 +26,7 @@ use surf.EthMacPkg.all; entity TenGigEthGthUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -254,6 +255,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) diff --git a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd index 69d69f5274..3c1f7f72f5 100644 --- a/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd +++ b/ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd @@ -28,6 +28,7 @@ entity TenGigEthGthUltraScaleWrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations EXT_REF_G : boolean := false; @@ -146,6 +147,7 @@ begin TenGigEthGthUltraScale_Inst : entity surf.TenGigEthGthUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd index 57dd3a9ca5..d21ee53c66 100644 --- a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd +++ b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7.vhd @@ -26,6 +26,7 @@ use surf.EthMacPkg.all; entity TenGigEthGtx7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -234,6 +235,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) diff --git a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd index d4b9894021..afe0f8903b 100644 --- a/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd +++ b/ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Wrapper.vhd @@ -28,6 +28,7 @@ entity TenGigEthGtx7Wrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -134,6 +135,7 @@ begin TenGigEthGtx7_Inst : entity surf.TenGigEthGtx7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd index f4dc127e38..dc8ebe3697 100644 --- a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd +++ b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScale.vhd @@ -25,6 +25,7 @@ use surf.EthMacPkg.all; entity TenGigEthGtyUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -234,6 +235,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, FIFO_ADDR_WIDTH_G => 12, -- single 4K UltraRAM SYNTH_MODE_G => "xpm", diff --git a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd index 48aaab8cf4..948d3e528d 100644 --- a/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd +++ b/ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd @@ -29,6 +29,7 @@ entity TenGigEthGtyUltraScaleWrapper is generic ( TPD_G : time := 1 ns; NUM_LANE_G : natural range 1 to 4 := 1; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations QPLL_REFCLK_SEL_G : slv(2 downto 0) := "001"; @@ -140,6 +141,7 @@ begin TenGigEthGtyUltraScale_Inst : entity surf.TenGigEthGtyUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd b/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd index 41e2cf60be..13e17834c0 100644 --- a/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd +++ b/ethernet/XauiCore/gth7/rtl/XauiGth7.vhd @@ -26,6 +26,7 @@ use surf.EthMacPkg.all; entity XauiGth7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -92,6 +93,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) diff --git a/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd b/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd index a248e2e78a..53fd5fc385 100644 --- a/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd +++ b/ethernet/XauiCore/gth7/rtl/XauiGth7Wrapper.vhd @@ -29,6 +29,7 @@ use unisim.vcomponents.all; entity XauiGth7Wrapper is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -95,6 +96,7 @@ begin XauiGth7_Inst : entity surf.XauiGth7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd index a03a032408..a5ea828b06 100644 --- a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd +++ b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScale.vhd @@ -28,6 +28,7 @@ use unisim.vcomponents.all; entity XauiGthUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- XAUI Configurations REF_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz @@ -202,6 +203,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, FIFO_ADDR_WIDTH_G => 12, -- single 4K UltraRAM SYNTH_MODE_G => "xpm", diff --git a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd index fe0d60bf73..8e984b8284 100644 --- a/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd +++ b/ethernet/XauiCore/gthUltraScale+/rtl/XauiGthUltraScaleWrapper.vhd @@ -29,6 +29,7 @@ use unisim.vcomponents.all; entity XauiGthUltraScaleWrapper is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; EN_WDT_G : boolean := false; EXT_REF_G : boolean := false; @@ -139,6 +140,7 @@ begin XauiGthUltraScale_Inst : entity surf.XauiGthUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd index d30a8d8fc4..7e1e90cdec 100644 --- a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd +++ b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScale.vhd @@ -29,6 +29,7 @@ use unisim.vcomponents.all; entity XauiGthUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -195,6 +196,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) diff --git a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd index e199d11fb3..a560bdf56c 100644 --- a/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd +++ b/ethernet/XauiCore/gthUltraScale/rtl/XauiGthUltraScaleWrapper.vhd @@ -29,6 +29,7 @@ use unisim.vcomponents.all; entity XauiGthUltraScaleWrapper is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; EN_WDT_G : boolean := false; EXT_REF_G : boolean := false; @@ -139,6 +140,7 @@ begin XauiGthUltraScale_Inst : entity surf.XauiGthUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd b/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd index 90972f89f7..0ff5e63c0e 100644 --- a/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd +++ b/ethernet/XauiCore/gtx7/rtl/XauiGtx7.vhd @@ -26,6 +26,7 @@ use surf.EthMacPkg.all; entity XauiGtx7 is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -92,6 +93,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, PHY_TYPE_G => "XGMII", PRIM_CONFIG_G => AXIS_CONFIG_G) diff --git a/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd b/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd index dcaa5c867e..f7ffdd41cf 100644 --- a/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd +++ b/ethernet/XauiCore/gtx7/rtl/XauiGtx7Wrapper.vhd @@ -29,6 +29,7 @@ use unisim.vcomponents.all; entity XauiGtx7Wrapper is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- QUAD PLL Configurations USE_GTREFCLK_G : boolean := false; -- FALSE: gtClkP/N, TRUE: gtRefClk @@ -95,6 +96,7 @@ begin XauiGtx7_Inst : entity surf.XauiGtx7 generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, diff --git a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd index 7480e5092e..aa62e3f26e 100644 --- a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd +++ b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScale.vhd @@ -28,6 +28,7 @@ use unisim.vcomponents.all; entity XauiGtyUltraScale is generic ( TPD_G : time := 1 ns; + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- XAUI Configurations REF_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz @@ -202,6 +203,7 @@ begin U_MAC : entity surf.EthMacTop generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, FIFO_ADDR_WIDTH_G => 12, -- single 4K UltraRAM SYNTH_MODE_G => "xpm", diff --git a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd index 9f9edac47e..4100ce704d 100644 --- a/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd +++ b/ethernet/XauiCore/gtyUltraScale+/rtl/XauiGtyUltraScaleWrapper.vhd @@ -31,6 +31,7 @@ entity XauiGtyUltraScaleWrapper is TPD_G : time := 1 ns; EN_WDT_G : boolean := false; STABLE_CLK_FREQ_G : real := 156.25E+6; -- Support 156.25MHz or 312.5MHz + JUMBO_G : boolean := true; PAUSE_EN_G : boolean := true; -- AXI-Lite Configurations EN_AXI_REG_G : boolean := false; @@ -134,6 +135,7 @@ begin XauiGtyUltraScale_Inst : entity surf.XauiGtyUltraScale generic map ( TPD_G => TPD_G, + JUMBO_G => JUMBO_G, PAUSE_EN_G => PAUSE_EN_G, -- AXI-Lite Configurations EN_AXI_REG_G => EN_AXI_REG_G, From f85aebb9b9f5058f41033107ad19d5ac0b019356 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 27 Sep 2023 10:13:47 -0700 Subject: [PATCH 7/7] Updating AxiStreamRingBuffer.vhd adding support for COMMON_CLK_G when (dataClk=axilClk) case --- axi/axi-stream/rtl/AxiStreamRingBuffer.vhd | 3 +++ 1 file changed, 3 insertions(+) diff --git a/axi/axi-stream/rtl/AxiStreamRingBuffer.vhd b/axi/axi-stream/rtl/AxiStreamRingBuffer.vhd index 07747931dd..85857fa4ef 100644 --- a/axi/axi-stream/rtl/AxiStreamRingBuffer.vhd +++ b/axi/axi-stream/rtl/AxiStreamRingBuffer.vhd @@ -29,6 +29,7 @@ entity AxiStreamRingBuffer is RST_ASYNC_G : boolean := false; SYNTH_MODE_G : string := "inferred"; MEMORY_TYPE_G : string := "block"; + COMMON_CLK_G : boolean := false; -- true if dataClk=axilClk DATA_BYTES_G : positive := 16; RAM_ADDR_WIDTH_G : positive := 9; -- AXI Stream Configurations @@ -172,6 +173,7 @@ begin U_Ram : entity surf.SimpleDualPortRamXpm generic map ( TPD_G => TPD_G, + COMMON_CLK_G => COMMON_CLK_G, MEMORY_TYPE_G => MEMORY_TYPE_G, READ_LATENCY_G => 2, DATA_WIDTH_G => 8*DATA_BYTES_G, @@ -193,6 +195,7 @@ begin U_Ram : entity surf.SimpleDualPortRamAlteraMf generic map ( TPD_G => TPD_G, + COMMON_CLK_G => COMMON_CLK_G, MEMORY_TYPE_G => MEMORY_TYPE_G, READ_LATENCY_G => 2, DATA_WIDTH_G => 8*DATA_BYTES_G,