Merge pull request #1208 from slaclab/pre-release

Release Candidate v2.52.0

.github/workflows/surf_ci.yml

@@ -49,9 +49,9 @@ jobs:
           python -m compileall -f python/ scripts/ tests/
           flake8 --count python/ scripts/ tests/
 
-      - name: C/C++ Linter
-        run: |
-          find . -name '*.h' -o -name '*.cpp' -o -name '*.c' | xargs cpplint
+#      - name: C/C++ Linter
+#        run: |
+#          find . -name '*.h' -o -name '*.cpp' -o -name '*.c' | xargs cpplint
 
       - name: VHDL Regression Testing
         run: |

axi/axi-stream/rtl/AxiStreamFrameRateLimiter.vhd

@@ -40,6 +40,7 @@ entity AxiStreamFrameRateLimiter is
       sAxisSlave      : out AxiStreamSlaveType;
       mAxisMaster     : out AxiStreamMasterType;
       mAxisSlave      : in  AxiStreamSlaveType;
+      mAxisCtrl       : in  AxiStreamCtrlType      := AXI_STREAM_CTRL_UNUSED_C;
       -- Optional: AXI Lite Interface (axilClk domain)
       axilClk         : in  sl                     := '0';
       axilRst         : in  sl                     := '0';
@@ -135,7 +136,8 @@ begin
          dataIn  => writeReg(1)(0),
          dataOut => backpressure);
 
-   comb : process (axisRst, backpressure, r, rateLimit, sAxisMaster, txSlave) is
+   comb : process (axisRst, backpressure, mAxisCtrl, r, rateLimit, sAxisMaster,
+                   txSlave) is
       variable v : RegType;
       variable i : natural;
    begin
@@ -157,8 +159,16 @@ begin
          when IDLE_S =>
             -- Update the variable
             if (r.rateLimit = 0) or (r.rateLimit /= r.frameCnt) then
-               v.tValid := '1';
+               -- Check if back pressure mode
+               if (backpressure = '0') then
+                  -- Accept data if not paused downstream
+                  v.tValid := not(mAxisCtrl.pause);
+               else
+                  -- Accept data
+                  v.tValid := '1';
+               end if;
             else
+               -- Blow off data
                v.tValid := '0';
             end if;
 

axi/axi-stream/rtl/AxiStreamGearbox.vhd

@@ -27,6 +27,7 @@ entity AxiStreamGearbox is
    generic (
       -- General Configurations
       TPD_G               : time     := 1 ns;
+      RST_POLARITY_G      : sl       := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
       RST_ASYNC_G         : boolean  := false;
       READY_EN_G          : boolean  := true;
       PIPE_STAGES_G       : natural  := 0;
@@ -131,6 +132,7 @@ begin
          generic map (
             -- General Configurations
             TPD_G               => TPD_G,
+            RST_POLARITY_G      => RST_POLARITY_G,
             RST_ASYNC_G         => RST_ASYNC_G,
             READY_EN_G          => READY_EN_G,
             PIPE_STAGES_G       => PIPE_STAGES_G,
@@ -156,7 +158,10 @@ begin
    GEN_GEARBOX : if (WORD_MULTIPLE_C = false) generate
 
       comb : process (axisRst, pipeAxisSlave, r, sAxisMaster, sSideBand) is
-         variable v : RegType;
+
+         variable tKeepTmp : slv(AXI_STREAM_MAX_TKEEP_WIDTH_C-1 downto 0);
+         variable v        : RegType;
+
       begin
          -- Latch the current value
          v := r;
@@ -231,21 +236,32 @@ begin
             -- Assign incoming sideband
             v.sideBand := sSideBand;
 
+            -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+            -- bit-by-bit assignment to appease ASIC synthesis flow tools
+            -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
             -- Assign incoming TDATA
-            v.tData(8*v.writeIndex+8*SLV_BYTES_C-1 downto 8*v.writeIndex) := sAxisMaster.tData(8*SLV_BYTES_C-1 downto 0);
+            for i in (SLV_BYTES_C*8)-1 downto 0 loop
+               v.tData((8*v.writeIndex)+i) := sAxisMaster.tData(i);
+            end loop;
 
             -- Check if TSTRB enabled
-            if(TSTRB_EN_C) then
-               -- Assign incoming TSTRB
-               v.tStrb(1*v.writeIndex+1*SLV_BYTES_C-1 downto 1*v.writeIndex) := sAxisMaster.tStrb(1*SLV_BYTES_C-1 downto 0);
+            if TSTRB_EN_C then
+               for i in (SLV_BYTES_C)-1 downto 0 loop
+                  v.tStrb(v.writeIndex+i) := sAxisMaster.tStrb(i);
+               end loop;
             end if;
 
+            -- temporary variable
+            tKeepTmp := genTKeep(conv_integer(sAxisMaster.tKeep(bitSize(SLV_BYTES_C)-1 downto 0)));
             -- Assign incoming TKEEP
-            if (SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C) then
-               v.tKeep(1*v.writeIndex+1*SLV_BYTES_C-1 downto 1*v.writeIndex) := genTKeep(conv_integer(sAxisMaster.tKeep(bitSize(SLV_BYTES_C)-1 downto 0)));
-            else
-               v.tKeep(1*v.writeIndex+1*SLV_BYTES_C-1 downto 1*v.writeIndex) := sAxisMaster.tKeep(1*SLV_BYTES_C-1 downto 0);
-            end if;
+            for i in (SLV_BYTES_C)-1 downto 0 loop
+               if SLAVE_AXI_CONFIG_G.TKEEP_MODE_C = TKEEP_COUNT_C then
+                  v.tKeep(v.writeIndex+i) := tKeepTmp(i);
+               else
+                  v.tKeep(v.writeIndex+i) := sAxisMaster.tKeep(i);
+               end if;
+            end loop;
+            -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
             -- Check if TDEST enabled
             if(TDEST_EN_C) then
@@ -332,7 +348,7 @@ begin
          end if;
 
          -- Synchronous Reset
-         if (RST_ASYNC_G = false and axisRst = '1') then
+         if (RST_ASYNC_G = false and axisRst = RST_POLARITY_G) then
             v := REG_INIT_C;
          end if;
 
@@ -343,7 +359,7 @@ begin
 
       seq : process (axisClk, axisRst) is
       begin
-         if (RST_ASYNC_G) and (axisRst = '1') then
+         if (RST_ASYNC_G) and (axisRst = RST_POLARITY_G) then
             r <= REG_INIT_C after TPD_G;
          elsif rising_edge(axisClk) then
             r <= rin after TPD_G;
@@ -356,6 +372,7 @@ begin
       U_Pipeline : entity surf.AxiStreamPipeline
          generic map (
             TPD_G             => TPD_G,
+            RST_POLARITY_G    => RST_POLARITY_G,
             RST_ASYNC_G       => RST_ASYNC_G,
             SIDE_BAND_WIDTH_G => SIDE_BAND_WIDTH_G,
             PIPE_STAGES_G     => PIPE_STAGES_G)

axi/axi-stream/rtl/AxiStreamResize.vhd

@@ -27,6 +27,7 @@ entity AxiStreamResize is
    generic (
       -- General Configurations
       TPD_G             : time     := 1 ns;
+      RST_POLARITY_G    : sl       := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
       RST_ASYNC_G       : boolean  := false;
       READY_EN_G        : boolean  := true;
       PIPE_STAGES_G     : natural  := 0;
@@ -266,10 +267,10 @@ begin
 
    seq : process (axisClk, axisRst) is
    begin
-      if (RST_ASYNC_G) and (axisRst = '1' or (SLV_BYTES_C = MST_BYTES_C)) then
+      if (RST_ASYNC_G) and (axisRst = RST_POLARITY_G or (SLV_BYTES_C = MST_BYTES_C)) then
          r <= REG_INIT_C after TPD_G;
       elsif (rising_edge(axisClk)) then
-         if (RST_ASYNC_G = false) and (axisRst = '1' or (SLV_BYTES_C = MST_BYTES_C)) then
+         if (RST_ASYNC_G = false) and (axisRst = RST_POLARITY_G or (SLV_BYTES_C = MST_BYTES_C)) then
             r <= REG_INIT_C after TPD_G;
          else
             r <= rin after TPD_G;
@@ -281,6 +282,7 @@ begin
    AxiStreamPipeline_1 : entity surf.AxiStreamPipeline
       generic map (
          TPD_G             => TPD_G,
+         RST_POLARITY_G    => RST_POLARITY_G,
          RST_ASYNC_G       => RST_ASYNC_G,
          SIDE_BAND_WIDTH_G => SIDE_BAND_WIDTH_G,
          PIPE_STAGES_G     => PIPE_STAGES_G)

base/general/rtl/TextUtilPkg.vhd

@@ -119,7 +119,10 @@ package TextUtilPkg is
    procedure print(file out_file :    text;
                    char          : in character);
 
-
+   -- appends contents of a string to a file until line feed occurs
+   -- (LF is considered to be the end of the string)
+   procedure strWrite(file out_file :    text;
+                      new_string    : in string);
 
 end TextUtilPkg;
 

devices/AnalogDevices/ruckus.tcl

@@ -2,6 +2,7 @@
 source $::env(RUCKUS_PROC_TCL)
 
 # Load ruckus files
+loadRuckusTcl "$::DIR_PATH/ad5541"
 loadRuckusTcl "$::DIR_PATH/ad5780"
 loadRuckusTcl "$::DIR_PATH/general"
 

devices/Marvell/Sgmii88E1111/lvdsUltraScale/Sgmii88E1111LvdsUltraScale.vhd

@@ -27,6 +27,7 @@ entity Sgmii88E1111LvdsUltraScale is
       TPD_G             : time                  := 1 ns;
       STABLE_CLK_FREQ_G : real                  := 156.25E+6;
       PAUSE_EN_G        : boolean               := true;
+      JUMBO_G           : boolean               := true;
       EN_AXIL_REG_G     : boolean               := false;
       PHY_G             : natural range 0 to 31 := 7;
       AXIS_CONFIG_G     : AxiStreamConfigType   := EMAC_AXIS_CONFIG_C);
@@ -191,6 +192,7 @@ begin
       generic map (
          TPD_G         => TPD_G,
          PAUSE_EN_G    => PAUSE_EN_G,
+         JUMBO_G       => JUMBO_G,
          EN_AXIL_REG_G => EN_AXIL_REG_G,
          AXIS_CONFIG_G => AXIS_CONFIG_G)
       port map (

devices/Ti/dp83867/core/SgmiiDp83867Mdio.vhd

@@ -38,6 +38,7 @@ entity SgmiiDp83867Mdio is
       linkIsUp        : out sl;
       -- MDIO interface
       mdc             : out sl;
+      mdTri           : out sl;
       mdo             : out sl;
       mdi             : in  sl;
       -- link status change interrupt
@@ -47,25 +48,24 @@ end entity SgmiiDp83867Mdio;
 architecture rtl of SgmiiDp83867Mdio is
 
    constant P_INIT_C : MdioProgramArray := (
-      mdioWriteInst(PHY_G, 16#0D#, x"001F", false),  -- Address 0x000D: Setup for extended address
-      mdioWriteInst(PHY_G, 16#0E#, x"00D3", false),  -- Address 0x000E: Set extended address = 0x00D3
-      mdioWriteInst(PHY_G, 16#0D#, x"401F", false),  -- Address 0x000D: Setup for extended data write
-      mdioWriteInst(PHY_G, 16#0E#, x"4000", false),  -- Address 0x000E: Enable SGMII clock
-
-      mdioWriteInst(PHY_G, 16#0D#, x"001F", false),  -- Address 0x000D: Setup for extended address
-      mdioWriteInst(PHY_G, 16#0E#, x"0032", false),  -- Address 0x000E: Set extended address = 0x0032
-      mdioWriteInst(PHY_G, 16#0D#, x"401F", false),  -- Address 0x000D: Setup for extended data write
-      mdioWriteInst(PHY_G, 16#0E#, x"0000", false),  -- Address 0x000E: RGMII must be disabled
-
-      mdioWriteInst(PHY_G, 16#1E#, x"0082", false),  -- Address 0x001E: INTN/PWDNN Pad is an Interrupt Output.
-      mdioWriteInst(PHY_G, 16#14#, x"29C7", false),  -- Address 0x0014: Configure interrupt polarity, enable auto negotiation, Enable Speed Optimization
-      mdioWriteInst(PHY_G, 16#12#, X"0c00", false),  -- Address 0x0012: Interrupt of link and autoneg changes
-      mdioWriteInst(PHY_G, 16#10#, x"5868", false),  -- Address 0x0010: Enable SGMII
-      -- mdioWriteInst(PHY_G, 16#09#, X"0200", false),  -- Address 0x0009: Advertise 1000   FD only
-      -- mdioWriteInst(PHY_G, 16#04#, X"0140", false),  -- Address 0x0004: Advertise 10/100 FD only
-      mdioWriteInst(PHY_G, 16#00#, x"1140", false),  -- Address 0x0000: Enable autoneg and full duplex
-
-      mdioWriteInst(PHY_G, 16#1F#, x"4000", true));  -- Address 0x001F: Initiate the soft restart.
+      mdioWriteInst(PHY_G, 16#0D#, x"001F", false),  -- Address 0x0D: Setup for extended address
+      mdioWriteInst(PHY_G, 16#0E#, x"00D3", false),  -- Address 0x0E: Set extended address = 0xD3 (more than 5-bit address)
+      mdioWriteInst(PHY_G, 16#0D#, x"401F", false),  -- Address 0x0D: Setup for extended data write
+      mdioWriteInst(PHY_G, 16#0E#, x"4000", false),  -- Address 0x0E: Enable SGMII clock
+
+      mdioWriteInst(PHY_G, 16#0D#, x"001F", false),  -- Address 0x0D: Setup for extended address
+      mdioWriteInst(PHY_G, 16#0E#, x"0032", false),  -- Address 0x0E: Set extended address = 0x32 (more than 5-bit address)
+      mdioWriteInst(PHY_G, 16#0D#, x"401F", false),  -- Address 0x0D: Setup for extended data write
+      mdioWriteInst(PHY_G, 16#0E#, x"0000", false),  -- Address 0x0E: RGMII must be disabled
+
+      mdioWriteInst(PHY_G, 16#00#, x"1140", false),  -- Address 0x00: enable autoneg on copper side
+      mdioWriteInst(PHY_G, 16#10#, x"5848", false),  -- Address 0x10: Enable SGMII
+      mdioWriteInst(PHY_G, 16#14#, x"2907", false),  -- Address 0x14: disable ANEG on SMII side
+
+      mdioWriteInst(PHY_G, 16#09#, X"0200", false),  -- Address 0x09: Advertise 1000   FD only
+      mdioWriteInst(PHY_G, 16#04#, X"0001", false),  -- Address 0x04: Don't advertise 10/100
+
+      mdioWriteInst(PHY_G, 16#1F#, x"4000", true));  -- Address 0x1F: Initiate the soft restart.
 
    constant REG0x13_IDX_C : natural := 0;
    constant REG0x11_IDX_C : natural := 1;
@@ -118,8 +118,10 @@ begin
          hdlrDone => hdlrDone,
          args     => args,
          mdc      => mdc,
+         mdTri    => mdTri,
          mdi      => mdi,
-         mdo      => mdo, phyIrq => linkIrq);
+         mdo      => mdo,
+         phyIrq   => linkIrq);
 
    COMB : process(args, hdlrDone, r)
       variable v       : RegType;