diff --git a/base/crc/rtl/Crc32.vhd b/base/crc/rtl/Crc32.vhd index 8d1a44c838..1b3582de6a 100644 --- a/base/crc/rtl/Crc32.vhd +++ b/base/crc/rtl/Crc32.vhd @@ -34,16 +34,16 @@ use surf.CrcPkg.all; entity Crc32 is generic ( TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; BYTE_WIDTH_G : positive := 4; INPUT_REGISTER_G : boolean := true; CRC_INIT_G : slv(31 downto 0) := x"FFFFFFFF"; CRC_POLY_G : slv(31 downto 0) := x"04C11DB7"); port ( - crcPwrOnRst : in sl := not RST_POLARITY_G; - crcOut : out slv(31 downto 0); -- CRC output - crcRem : out slv(31 downto 0); -- CRC interim remainder + crcPwrOnRst : in sl := not RST_POLARITY_G; + crcOut : out slv(31 downto 0); -- CRC output + crcRem : out slv(31 downto 0); -- CRC interim remainder crcClk : in sl; -- system clock crcDataValid : in sl; -- indicate that new data arrived and CRC can be computed crcDataWidth : in slv(2 downto 0); -- indicate width in bytes minus 1, 0 - 1 byte, 1 - 2 bytes ... , 7 - 8 bytes @@ -149,7 +149,7 @@ begin begin if (RST_ASYNC_G and crcPwrOnRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; - elsif (rising_edge(crcClk)) then + elsif (rising_edge(crcClk)) then if (RST_ASYNC_G = false and crcPwrOnRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; else diff --git a/base/crc/rtl/Crc32Parallel.vhd b/base/crc/rtl/Crc32Parallel.vhd old mode 100755 new mode 100644 index 59cbb06a46..aee2bededa --- a/base/crc/rtl/Crc32Parallel.vhd +++ b/base/crc/rtl/Crc32Parallel.vhd @@ -40,21 +40,21 @@ use surf.CrcPkg.all; entity Crc32Parallel is generic ( TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; BYTE_WIDTH_G : positive := 4; INPUT_REGISTER_G : boolean := true; CRC_INIT_G : slv(31 downto 0) := x"FFFFFFFF"); port ( - crcPwrOnRst : in sl := not RST_POLARITY_G; - crcOut : out slv(31 downto 0); -- CRC output - crcRem : out slv(31 downto 0); -- CRC interim remainder + crcPwrOnRst : in sl := not RST_POLARITY_G; + crcOut : out slv(31 downto 0); -- CRC output + crcRem : out slv(31 downto 0); -- CRC interim remainder crcClk : in sl; -- system clock crcDataValid : in sl; -- indicate that new data arrived and CRC can be computed crcDataWidth : in slv(2 downto 0); -- indicate width in bytes minus 1, 0 - 1 byte, 1 - 2 bytes ... , 7 - 8 bytes crcIn : in slv((BYTE_WIDTH_G*8-1) downto 0); -- input data for CRC calculation crcInit : in slv(31 downto 0) := CRC_INIT_G; -- optional override of CRC_INIT_G - crcReset : in sl); -- initializes CRC logic to crcInit + crcReset : in sl); -- initializes CRC logic to crcInit end Crc32Parallel; architecture rtl of Crc32Parallel is @@ -191,7 +191,7 @@ begin begin if (RST_ASYNC_G and crcPwrOnRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; - elsif (rising_edge(crcClk)) then + elsif (rising_edge(crcClk)) then if (RST_ASYNC_G = false and crcPwrOnRst = RST_POLARITY_G) then r <= REG_INIT_C after TPD_G; else diff --git a/base/sync/rtl/RstSync.vhd b/base/sync/rtl/RstSync.vhd index f4d11e2b71..cca8ab948b 100644 --- a/base/sync/rtl/RstSync.vhd +++ b/base/sync/rtl/RstSync.vhd @@ -24,7 +24,7 @@ use surf.StdRtlPkg.all; entity RstSync is generic ( - TPD_G : time := 1 ns; -- Simulation FF output delay + TPD_G : time := 1 ns; -- Simulation FF output delay IN_POLARITY_G : std_logic := '1'; -- 0 for active low rst, 1 for high OUT_POLARITY_G : std_logic := '1'; BYPASS_SYNC_G : boolean := false; -- Bypass Synchronizer module for synchronous data configuration @@ -60,7 +60,7 @@ begin dataOut => syncInt); -- Final stage does not have async constraints applied, can be duplicated to ease timing - OUT_REG : process (clk, asyncRst) is + OUT_REG : process (asyncRst, clk) is begin if (asyncRst = IN_POLARITY_G and OUT_REG_RST_G) then syncRst <= OUT_POLARITY_G after TPD_G; diff --git a/base/sync/rtl/SynchronizerFifo.vhd b/base/sync/rtl/SynchronizerFifo.vhd index 5ce2dc1d58..4233d12fd6 100644 --- a/base/sync/rtl/SynchronizerFifo.vhd +++ b/base/sync/rtl/SynchronizerFifo.vhd @@ -23,7 +23,7 @@ use surf.StdRtlPkg.all; entity SynchronizerFifo is generic ( TPD_G : time := 1 ns; - RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset + RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset RST_ASYNC_G : boolean := false; COMMON_CLK_G : boolean := false; -- Bypass FifoAsync module for synchronous data configuration MEMORY_TYPE_G : string := "distributed"; @@ -34,7 +34,7 @@ entity SynchronizerFifo is INIT_G : slv := "0"); port ( -- Asynchronous Reset - rst : in sl := not RST_POLARITY_G; + rst : in sl := not RST_POLARITY_G; -- Write Ports (wr_clk domain) wr_clk : in sl; wr_en : in sl := '1';