Fix bugs found in simulation

slaclab · Sep 19, 2023 · 442c0aa · 442c0aa
1 parent 1c351f6
commit 442c0aa
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Showing 2 changed files with 8 additions and 4 deletions.
diff --git a/protocols/i2c/rtl/I2cRegMaster.vhd b/protocols/i2c/rtl/I2cRegMaster.vhd
@@ -166,7 +166,7 @@ begin
             v.i2cMasterIn.wrData  := regIn.regAddr(addrIndexVar+7 downto addrIndexVar);
             v.i2cMasterIn.wrValid := '1';
             -- Must drop txnReq as last byte is sent if reading
-            v.i2cMasterIn.txnReq  := not toSl(slv(r.byteCount) = regIn.regAddrSize and regIn.regOp = '0');
+            v.i2cMasterIn.txnReq  := not toSl(slv(r.byteCount) = regIn.regAddrSize and regIn.regOp = '0' and regIn.wrDataOnRd = '0');
 
             if (i2cMasterOut.wrAck = '1') then
                v.byteCount           := r.byteCount + 1;
@@ -197,7 +197,7 @@ begin
                      v.state := REG_ACK_S;
                   else
                      -- Handle wrDataOnRead case
-                     v.state := READ_TXN_S;
+                     v.state     := READ_TXN_S;
                   end if;
 
                end if;
@@ -209,6 +209,7 @@ begin
             v.i2cMasterIn.txnReq := '1';
             v.i2cMasterIn.op     := '0';
             v.i2cMasterIn.stop   := '1';  -- i2c stop after all bytes are read
+            v.byteCount := (others => '0');                        
             v.state              := READ_S;
 
          when READ_S =>

diff --git a/protocols/i2c/rtl/I2cRegSlave.vhd b/protocols/i2c/rtl/I2cRegSlave.vhd
@@ -34,6 +34,7 @@ entity I2cRegSlave is
       -- RAM generics
       ADDR_SIZE_G          : natural                 := 2;   -- in bytes
       DATA_SIZE_G          : positive                := 1;   -- in bytes
+      ADDR_AUTO_INC_G      : boolean                 := true;
       ENDIANNESS_G         : integer range 0 to 1    := 0);  -- 0=LE, 1=BE
    port (
       sRst   : in  sl := '0';
@@ -137,8 +138,10 @@ begin
 
       -- Auto increment the address after each read or write
       -- This enables bursts.
-      if (r.wrEn = '1' or r.rdEn = '1') then
-         v.addr := r.addr + 1;
+      if (ADDR_AUTO_INC_G) then
+         if (r.wrEn = '1' or r.rdEn = '1') then
+            v.addr := r.addr + 1;
+         end if;
       end if;
 
       -- Tx Data always valid, assigned based on byte cnt