diff --git a/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/FetchSubTuple.maxja b/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/FetchSubTuple.maxja deleted file mode 100644 index b5ef31f..0000000 --- a/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/FetchSubTuple.maxja +++ /dev/null @@ -1,205 +0,0 @@ - LUTs FFs BRAMs DSPs : FetchSubTuple.maxj - 1898 109 1 0 : resources used by this file - 0.36% 0.01% 0.04% 0.00% : % of available - 19.24% 0.44% 0.70% 0.00% : % of total used - 69.07% 0.73% 100.00% 0.00% : % of user resources - - : //package com.custom_computing_ic.dfe_snippets.utils; - : - : import com.maxeler.maxcompiler.v2.kernelcompiler.KernelLib; - : import com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar; - : import com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEType; - : import com.maxeler.maxcompiler.v2.kernelcompiler.types.composite.DFEVector; - : import com.maxeler.maxcompiler.v2.kernelcompiler.types.composite.DFEVectorType; - : import com.maxeler.maxcompiler.v2.kernelcompiler.stdlib.KernelMath; - : import com.maxeler.maxcompiler.v2.utils.*; - : - : - : /*** - : This implements a FIFO buffer which enables pushing fixed number of items - : and fetching arbitrary number of items per cycle. - : - : The number of entries to fetch is a run time parameter which varies from 0 - : to tupleSize. The maximum number of entries fetchable per cycle and the - : input width is a compile time parameter (tupleSize). - : - : Inputs and outputs are DFEVector of tupleSize, where output vector carries - : requested number of entries popped from FIFO, and rest of that vector filled - : with zeroes. - : - : The buffer occasionally issues stall signal (nextPushEnable() == 0) - : to avoid overflow of internal FIFOs and help orchestrating outer - : code. In case of underflow (requesting more entries than internally stored) - : it returns stored entries and zeroes. - : - : Assumed use case: multi-pipe processing of input stream of length - : not divisible to number of pipes p. At the end of the stream the number - : of values to be read is less then p; this buffer helps not to go - : across the boundary and not to loose/discard values happen to be - : beyond the boundary. - : - : */ - : - : public class FetchSubTuple extends KernelLib - : { - : private static final int bufferDepth = 8; - : - : private DFEVectorType m_tupleType; - : private DFEVectorType m_boolTupleType; - : private DFEType m_contentType; - : - : private int m_tupleSize; - : private int m_tupleBitWidth; - : private boolean m_align; - : - : private DFEVector> m_buffer; - : // current depth (fill level) at each FIFO component - : private DFEVector m_depth; - : private DFEVar m_nextPushEnable; - : - : /*** - : @param tupleSize The maximum number of entries to be processed per cycle. - : @param dataBitWidth The bitwidth of dataType: necessary for correct initialisation of internal FIFOs. - : @param dataType The type of the content stored. - : @param align Whether to align the content of sub-tuple to 0-th index at the output (default=false) - : */ - : public FetchSubTuple(KernelLib owner, String name, int tupleSize, int dataBitWidth, - : DFEType dataType, boolean align) - : { - : super(owner); - : - : m_align = align; - : m_tupleBitWidth = MathUtils.bitsToAddress(tupleSize); - : int depthBitWidth = MathUtils.bitsToAddress(bufferDepth); - : m_contentType = dataType; - : m_tupleSize = tupleSize; - : m_tupleType = - : new DFEVectorType (m_contentType, m_tupleSize); - : m_boolTupleType = - : new DFEVectorType (dfeBool(), m_tupleSize); - : - : m_nextPushEnable = dfeBool().newInstance(this); - : m_depth = new DFEVectorType (dfeUInt(depthBitWidth), m_tupleSize).newInstance(this); - : - : // 2 dim array: first dim = 1..tupleSise, 2nd dim = 1..bufferDepth - : DFEVectorType fifo_type = new DFEVectorType(m_contentType, bufferDepth); - : m_buffer = new DFEVectorType>(fifo_type, tupleSize).newInstance(this); - : } - : - : public DFEVar nextPushEnable() { return m_nextPushEnable; } - : - : - : /*** - : @param subTupleSize Number of elements to retrieve. Must be between 0 and tupleSize. - : @param enable Boolean: indicates whether inputTuple is requested to be pushed into the buffer. - : @param inputTuple Vector of input data. All its tupleSize entries are pushed to the buffer, if return is 1. - : @return Vector of tupleSize, with only subTupleSize entries retrieved from the buffer. - : */ - : public DFEVector popPush(DFEVar subTupleSize, DFEVar pushEnable, DFEVector inputTuple) - : { - : DFEType tupleIndexType = null; - : if (m_tupleBitWidth == 0) - : { - : tupleIndexType = dfeUInt(1); - : } - : else - : { - : tupleIndexType = dfeUInt(m_tupleBitWidth); - : } - : - : // ---------------------------------------------------------------------- - : // Manage state - : // ---------------------------------------------------------------------- - : - : // in case subTupleSize has incompatible bit width - : DFEVar numElements = subTupleSize.cast(tupleIndexType); - : - : DFEVector readEnable = m_boolTupleType.newInstance(this); - : DFEVector mask = m_boolTupleType.newInstance(this); - : DFEVar shiftLoop = tupleIndexType.newInstance(this); - : - : optimization.pushPipeliningFactor(0.0); - 4 2 0 0 : DFEVar shift = control.count.pulse(1)? 0 : stream.offset(shiftLoop,-1); - 10 10 0 0 : shiftLoop <== KernelMath.modulo(shift.cast(dfeUInt(m_tupleBitWidth+1)) + - 6 0 0 0 : numElements.cast(dfeUInt(m_tupleBitWidth+1)), m_tupleSize) - : .cast(tupleIndexType); - : optimization.popPipeliningFactor(); - : - : for (int i = 0; i < m_tupleSize; i++) - : { - 23 28 0 0 : mask[i] <== (i < numElements); - : } - : readEnable = null; - : if (m_tupleBitWidth == 0) - : { - : readEnable = mask; - : } - : else - : { - 99 64 1 0 : readEnable = mask.rotateElementsLeft(shift); - : } - : optimization.pushPipeliningFactor(0.0); - : // all FIFOs have same depth +/-1 - just watching an arbitrary FIFO - 1 1 0 0 : DFEVar pastDepth0 = control.count.pulse(1)? 0 : stream.offset(m_depth[0],-1); - : m_nextPushEnable = pastDepth0 < bufferDepth-3; - : - : for (int i = 0; i < m_tupleSize; i++) - : { - 3 4 0 0 : DFEVar pastDepth = control.count.pulse(1)? 0 : stream.offset(m_depth[i],-1); - 72 0 0 0 : m_depth[i] <== pushEnable? - : (readEnable[i]? pastDepth : (pastDepth+1)) - : :(readEnable[i]? (pastDepth-1) : pastDepth); - : } - : - : optimization.popPipeliningFactor(); - : - : // ---------------------------------------------------------------------- - : // Data storage update - : // ---------------------------------------------------------------------- - : - : DFEVector tuple = m_tupleType.newInstance(this); - : - : optimization.pushPipeliningFactor(0.0); - : for (int i = 0; i < m_tupleSize; i++) - : { - : - 48 0 0 0 : DFEVar pastDepth = control.count.pulse(1)? 0 : stream.offset(m_depth[i],-1); - : - 48 0 0 0 : DFEVar asIfReadEnable = (pushEnable & pastDepth.eq(0))? - : inputTuple[i] - : : stream.offset(m_buffer[i][0],-1); - 1536 0 0 0 : tuple[i] <== readEnable[i]? asIfReadEnable - : : constant.var(m_contentType, 0); - : // shifting those FIFOs that are being read + inserting new entries - : for (int j = 0; j < bufferDepth; j++) - : { - : if (j == bufferDepth-1) - : { - : m_buffer[i][j] <== (pushEnable & pastDepth.eq(j))? inputTuple[i] : 0; - : } - : else - : { - 48 0 0 0 : DFEVar asIfReadDisabled = (pushEnable & pastDepth.eq(j))? - : inputTuple[i] - : : stream.offset(m_buffer[i][j],-1); - : DFEVar asIfReadEnabled = (pushEnable & pastDepth.eq(j+1))? - : inputTuple[i] - : : stream.offset(m_buffer[i][j+1],-1); - : m_buffer[i][j] <== readEnable[i]? asIfReadEnabled - : : asIfReadDisabled; - : } - : } - : } - : optimization.popPipeliningFactor(); - : - : // align tuple values so that they start from index 0 - : if (m_align) - : { - : return tuple.rotateElementsRight(shift); - : } - : else - : { - : return tuple; - : } - : } - : } diff --git a/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/FetchSubTupleKernel.maxja b/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/FetchSubTupleKernel.maxja index bdbe852..29218d5 100644 --- a/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/FetchSubTupleKernel.maxja +++ b/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/FetchSubTupleKernel.maxja @@ -1,8 +1,8 @@ LUTs FFs BRAMs DSPs : FetchSubTupleKernel.maxj - 1996 239 1 0 : resources used by this file - 0.38% 0.02% 0.04% 0.00% : % of available - 20.23% 0.97% 0.70% 0.00% : % of total used - 72.63% 1.60% 100.00% 0.00% : % of user resources + 11446 428 2 0 : resources used by this file + 2.18% 0.04% 0.08% 0.00% : % of available + 57.24% 1.21% 0.74% 0.00% : % of total used + 95.74% 1.96% 100.00% 0.00% : % of user resources : /*** : Here we provide an example use case of irregular fetch buffer. @@ -23,7 +23,7 @@ : import com.maxeler.maxcompiler.v2.kernelcompiler.types.composite.DFEVector; : import com.maxeler.maxcompiler.v2.kernelcompiler.types.composite.DFEVectorType; : - : //import com.custom_computing_ic.dfe_snippets.utils.FetchSubTuple; + : import com.custom_computing_ic.dfe_snippets.utils.FetchSubTuple; : : class FetchSubTupleKernel extends Kernel : { @@ -37,10 +37,10 @@ : DFEVectorType tupleType = : new DFEVectorType (floatType, tupleSize); : - 70 101 0 0 : DFEVar cycleCounter = control.count.simpleCounter(32); + 70 102 0 0 : DFEVar cycleCounter = control.count.simpleCounter(32); 1 1 0 0 : DFEVar prefetchEnable = cycleCounter < 1; 5 4 0 0 : DFEVar pushEnable = ~prefetchEnable & ( (cycleCounter < 27) | (cycleCounter > 30) ); - 12 4 0 0 : DFEVar popEnable = ~prefetchEnable & ( (cycleCounter < 10) | (cycleCounter > 11) ); + 11 4 0 0 : DFEVar popEnable = ~prefetchEnable & ( (cycleCounter < 10) | (cycleCounter > 11) ); : : : @@ -53,12 +53,12 @@ : //debug.simPrintf("\ncycle=%d, pushEnable2=%d | ", cycleCounter, pushEnable2); : 1 1 0 0 : DFEVector input = io.input("input", tupleType, dataRequestEnable); - 1 6 0 0 : DFEVar size = io.input("sizes", scalarType, popEnable); + 1 7 0 0 : DFEVar size = io.input("sizes", scalarType, popEnable); : : boolean alignOutput = false; : FetchSubTuple buffer = new FetchSubTuple(this, "test", tupleSize, 64, floatType, alignOutput); - 5 9 0 0 : DFEVar subTupleSize = (popEnable)? size: 0; - 1898 109 1 0 : DFEVector outTuple = buffer.popPush(subTupleSize, pushEnable2, input); + 6 6 0 0 : DFEVar subTupleSize = (popEnable)? size: 0; + 11348 299 2 0 : DFEVector outTuple = buffer.popPush(subTupleSize, pushEnable2, input); : : dataRequestEnableLoop <== buffer.nextPushEnable(); : diff --git a/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/FetchSubTupleManager.maxja b/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/FetchSubTupleManager.maxja index 57f8026..8273159 100644 --- a/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/FetchSubTupleManager.maxja +++ b/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/FetchSubTupleManager.maxja @@ -1,8 +1,8 @@ LUTs FFs BRAMs DSPs : FetchSubTupleManager.maxj - 2560 13008 1 0 : resources used by this file - 0.49% 1.24% 0.04% 0.00% : % of available - 25.95% 52.73% 0.70% 0.00% : % of total used - 93.16% 87.28% 100.00% 0.00% : % of user resources + 11888 17409 2 0 : resources used by this file + 2.27% 1.66% 0.08% 0.00% : % of available + 59.45% 49.42% 0.74% 0.00% : % of total used + 99.44% 79.61% 100.00% 0.00% : % of user resources : import com.maxeler.maxcompiler.v2.managers.engine_interfaces.CPUTypes; : import com.maxeler.maxcompiler.v2.managers.engine_interfaces.EngineInterface; @@ -14,7 +14,7 @@ : public class FetchSubTupleManager extends CustomManager{ : : private static final String s_kernelName = "FetchSubTupleKernel"; - : private static final int tupleSize = 24; + : private static final int tupleSize = 64; : : FetchSubTupleManager(EngineParameters ep) : { @@ -23,7 +23,7 @@ : config.setDefaultStreamClockFrequency(200); : : - 2224 595 1 0 : KernelBlock k = addKernel(new FetchSubTupleKernel(makeKernelParameters(s_kernelName), tupleSize)); + 11674 793 2 0 : KernelBlock k = addKernel(new FetchSubTupleKernel(makeKernelParameters(s_kernelName), tupleSize)); : : k.getInput("input") <== addStreamFromCPU("input"); : k.getInput("sizes") <== addStreamFromCPU("sizes"); @@ -52,9 +52,9 @@ : : : public static void main(String[] args) { - 2224 595 1 0 : FetchSubTupleManager manager = new FetchSubTupleManager(new EngineParameters(args)); + 11674 793 2 0 : FetchSubTupleManager manager = new FetchSubTupleManager(new EngineParameters(args)); : manager.createSLiCinterface(interfaceDefault()); : manager.addMaxFileConstant("tupleSize", tupleSize); - 336 12413 0 0 : manager.build(); + 214 16616 0 0 : manager.build(); : } : } diff --git a/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/_build.log b/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/_build.log index f2ae002..7a4b947 100644 --- a/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/_build.log +++ b/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/_build.log @@ -1,4721 +1,4852 @@ -Tue 01:03: PROGRESS: MaxCompiler version: 2014.1 -Tue 01:03: PROGRESS: Build "FetchSubTuple" start time: Tue Aug 25 01:03:53 BST 2015 -Tue 01:03: PROGRESS: Main build process running as user pburovsk on host cccad3.doc.ic.ac.uk -Tue 01:03: INFO : Loading build properties from bundled MaxCompiler_build.conf... -Tue 01:03: INFO : No default external build property file has been specified. -Tue 01:03: INFO : (Set environment variable MAXCOMPILER_DEFAULT_CONF_FILE to assign one) -Tue 01:03: INFO : Loading user build properties from: /mnt/ccnas/pburovsk/.MaxCompiler_build_user.conf -Tue 01:03: INFO : No user-specified external build property file has been specified. -Tue 01:03: INFO : (Set environment variable MAXCOMPILER_BUILD_CONF_FILE to assign one) -Tue 01:03: PROGRESS: Build location: /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/./FetchSubTuple_MAIA_DFE -Tue 01:03: PROGRESS: Detailed build log available in "_build.log" -Tue 01:03: INFO : Created build manager FetchSubTuple (FetchSubTuple_MAIA_DFE Tue Aug 25 01:03:53 BST 2015). (01:03:53 25/08/15) -Tue 01:03: INFO : Working in dir: /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/./FetchSubTuple_MAIA_DFE -Tue 01:03: INFO : Java class path (2 paths): -Tue 01:03: INFO : /vol/cc/opt/maxeler/maxcompiler-2014.1/lib/MaxCompiler.jar -Tue 01:03: INFO : . -Tue 01:03: INFO : Java process started by 'main' method in class 'FetchSubTupleManager'. -Tue 01:03: INFO : build.arbitrated_core_cache parameter is blank, not using core-cache -Tue 01:03: INFO : Checking license files in directory: /vol/cc/opt/maxeler/maxcompiler-2014.1/licenses -Tue 01:03: INFO : All license signatures valid. -Tue 01:03: INFO : Backing-up source-files (old source files in build directory will be removed first)... -Tue 01:03: INFO : Source directories: ../src -Tue 01:03: INFO : Not deleting directory (does not exist): src -Tue 01:03: INFO : Copying source-files took 6.94691 ms -Tue 01:03: USER : -Tue 01:03: USER : ENGINE BUILD PARAMETERS -Tue 01:03: USER : Build name: FetchSubTuple_MAIA_DFE -Tue 01:03: USER : DFEModel: MAIA -Tue 01:03: USER : maxFileName: FetchSubTuple -Tue 01:03: USER : target: DFE -Tue 01:03: USER : enableMPCX: true -Tue 01:03: PROGRESS: Instantiating kernel "FetchSubTupleKernel" -Tue 01:03: INFO : Manager Configuration: -Tue 01:03: INFO : ManagerConfiguration.allowNonMultipleTransitions = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.board = MAX4848A [Init: null, init: MAX4848A] -Tue 01:03: INFO : ManagerConfiguration.build.buildEffort = MEDIUM [Init: MEDIUM] -Tue 01:03: INFO : ManagerConfiguration.build.enableChipScopeInserter = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.build.enableTimingAnalysis = true [Init: true] -Tue 01:03: INFO : ManagerConfiguration.build.level = FULL_BUILD [Init: FULL_BUILD] -Tue 01:03: INFO : ManagerConfiguration.build.mpprContinueAfterMeetingTiming = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.build.mpprCtMax = 1 [Init: 1] -Tue 01:03: INFO : ManagerConfiguration.build.mpprCtMin = 1 [Init: 1] -Tue 01:03: INFO : ManagerConfiguration.build.mpprParallelism = 1 [Init: 1] -Tue 01:03: INFO : ManagerConfiguration.build.mpprRetryMissesThrshld = 0 [Init: 0] -Tue 01:03: INFO : ManagerConfiguration.build.optGoal = AREA [Init: AREA] -Tue 01:03: INFO : ManagerConfiguration.build.physSynthAsyncPipelining = AUTO [Init: AUTO] -Tue 01:03: INFO : ManagerConfiguration.build.physSynthCombLogic = AUTO [Init: AUTO] -Tue 01:03: INFO : ManagerConfiguration.build.physSynthCombLogicForArea = AUTO [Init: AUTO] -Tue 01:03: INFO : ManagerConfiguration.build.physSynthEffort = AUTO [Init: AUTO] -Tue 01:03: INFO : ManagerConfiguration.build.physSynthRegDuplication = AUTO [Init: AUTO] -Tue 01:03: INFO : ManagerConfiguration.build.physSynthRetiming = AUTO [Init: AUTO] -Tue 01:03: INFO : ManagerConfiguration.build.physicalSynthesis = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.buildTarget = DFE [Init: null, init: DFE] -Tue 01:03: INFO : ManagerConfiguration.debug.chipscopeCaptureDepth = 4096 [Init: 4096] -Tue 01:03: INFO : ManagerConfiguration.debug.fifoUnderOverFlowRegs = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.debug.memCtlDebugRegs = true [Init: true] -Tue 01:03: INFO : ManagerConfiguration.debug.memCtlExtraDebugRegs = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.debug.memMarginingSupport = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.debug.memPhyDebugRegister = NONE [Init: NONE] -Tue 01:03: INFO : ManagerConfiguration.debug.memPllLockDebugRegs = true [Init: true] -Tue 01:03: INFO : ManagerConfiguration.debug.streamStatus = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.debug.streamStatusChecksums = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.addressGeneratorsInSlowClock = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.arbitrationMode = ROUND_ROBIN [Init: ROUND_ROBIN] -Tue 01:03: INFO : ManagerConfiguration.dram.burstSize = 8 [Init: 8] -Tue 01:03: INFO : ManagerConfiguration.dram.cmdFifoInReg = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.cmdFifoLutRam = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.cmdFifoRegInRam = true [Init: true] -Tue 01:03: INFO : ManagerConfiguration.dram.cmdFifoSize = 31 [Init: 31] -Tue 01:03: INFO : ManagerConfiguration.dram.commandEchoModeEnabled = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.commandEchoModeFifoDepth = 512 [Init: 512] -Tue 01:03: INFO : ManagerConfiguration.dram.commandEchoModeStreamAlmostEmptyLatency = 792 [Init: 792] -Tue 01:03: INFO : ManagerConfiguration.dram.commandEchoModeStreamAlmostEmptyLatency = 8 [Init: 8] -Tue 01:03: INFO : ManagerConfiguration.dram.commandEchoModeStreamStallLatency = 8 [Init: 8] -Tue 01:03: INFO : ManagerConfiguration.dram.dataFifoDepth = 512 [Init: 512] -Tue 01:03: INFO : ManagerConfiguration.dram.dataFifoLutRam = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.dataFifoWidth = 792 [Init: 792] -Tue 01:03: INFO : ManagerConfiguration.dram.eccMode = true [Init: false, change: true] -Tue 01:03: INFO : ManagerConfiguration.dram.fabricDataFifoReg = true [Init: true] -Tue 01:03: INFO : ManagerConfiguration.dram.fabricRdDataFifoReg = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.flagSupport = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.highPrioStream = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.max2CompatMode = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.max4m_MAIA_MCP_UseRefClk = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.max4qrateMode = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.memCmdIncSize = 8 [Init: 8] -Tue 01:03: INFO : ManagerConfiguration.dram.memCmdStartAddrSize = 32 [Init: 32] -Tue 01:03: INFO : ManagerConfiguration.dram.onCardMemFreq = 400.0 [Init: 0.0, change: 400.0] -Tue 01:03: INFO : ManagerConfiguration.dram.parEccDebugStream = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.parityEccWidth = 72 [Init: 0, change: 72] -Tue 01:03: INFO : ManagerConfiguration.dram.parityMode = true [Init: false, change: true] -Tue 01:03: INFO : ManagerConfiguration.dram.perdqsPhaseDetect = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.dram.performanceMode = true [Init: true] -Tue 01:03: INFO : ManagerConfiguration.enableMPCX = true [Init: false, init: true] -Tue 01:03: INFO : ManagerConfiguration.maxring.maxringConnections = [] [Init: []] -Tue 01:03: INFO : ManagerConfiguration.maxring.maxringNumLanes = {} [Init: {}] -Tue 01:03: INFO : ManagerConfiguration.multiCycleMappedMemoryBus = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.network.qsfpBotMode = QSFP_OFF [Init: QSFP_OFF] -Tue 01:03: INFO : ManagerConfiguration.network.qsfpMidMode = QSFP_OFF [Init: QSFP_OFF] -Tue 01:03: INFO : ManagerConfiguration.network.qsfpTopMode = QSFP_OFF [Init: QSFP_OFF] -Tue 01:03: INFO : ManagerConfiguration.pcie.numPCIeLanes = 8 [Init: 0, change: 8] -Tue 01:03: INFO : ManagerConfiguration.pcie.pcieFastClock = true [Init: false, change: true] -Tue 01:03: INFO : ManagerConfiguration.pcie.streamFromHostMaxNum = 0 [Init: 0] -Tue 01:03: INFO : ManagerConfiguration.pcie.streamToHostMaxNum = 0 [Init: 0] -Tue 01:03: INFO : ManagerConfiguration.persona.boardModel = MAX4848A [Init: null, change: MAX4848A] -Tue 01:03: INFO : ManagerConfiguration.persona.ddr3Enable = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.persona.ddr3Frq = 400.0 [Init: 400.0] -Tue 01:03: INFO : ManagerConfiguration.persona.ddr3Qmode = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.persona.disableMultiplePersona = true [Init: true] -Tue 01:03: INFO : ManagerConfiguration.persona.dynamic_scaling = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.persona.maxRingLocal = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.persona.maxRingOptical = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.persona.maxringDataRate = 2500.0 [Init: 2500.0] -Tue 01:03: INFO : ManagerConfiguration.persona.maxringOpticalDataRate = 10000.0 [Init: 10000.0] -Tue 01:03: INFO : ManagerConfiguration.persona.mode = InitMode [Init: InitMode] -Tue 01:03: INFO : ManagerConfiguration.persona.networkPTP = OFF [Init: OFF] -Tue 01:03: INFO : ManagerConfiguration.persona.networkQSFP_BOT = QSFP_OFF [Init: QSFP_OFF] -Tue 01:03: INFO : ManagerConfiguration.persona.networkQSFP_MID = QSFP_OFF [Init: QSFP_OFF] -Tue 01:03: INFO : ManagerConfiguration.persona.networkQSFP_TOP = QSFP_OFF [Init: QSFP_OFF] -Tue 01:03: INFO : ManagerConfiguration.persona.panMaxRingA = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.persona.panMaxRingB = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.persona.personaInterfaceVersion = 1 [Init: 1] -Tue 01:03: INFO : ManagerConfiguration.persona.qdr2Enable = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.persona.qdr2Frq = 550.0 [Init: 550.0] -Tue 01:03: INFO : ManagerConfiguration.persona.streamClks = 1 [Init: 1] -Tue 01:03: INFO : ManagerConfiguration.persona.streamFrq = [200.0] [Init: [150.0], change: [200.0]] -Tue 01:03: INFO : ManagerConfiguration.persona.streamPs = [0] [Init: [0]] -Tue 01:03: INFO : ManagerConfiguration.persona.usePCIeGen1 = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.simulation.nativeFloatingPoint = false [Init: false] -Tue 01:03: INFO : ManagerConfiguration.streamClockFrq = 200 [Init: 100, change: 200] -Tue 01:03: INFO : ManagerConfiguration.useLegacyStreamFIFOs = false [Init: false] -Tue 01:03: INFO : -Tue 01:03: INFO : -- -Tue 01:03: INFO : Running manager compiler graph-pass: GenerateMXGInfo -Tue 01:03: INFO : Running manager compiler graph-pass: CalculateBandwidthForward -Tue 01:03: INFO : Running manager compiler graph-pass: CalculateBandwidthBackward -Tue 01:03: INFO : Running manager compiler graph-pass: ScheduleStallLatency -Tue 01:03: INFO : Running manager compiler graph-pass: ClockWidthAssignment -Tue 01:03: INFO : Running manager compiler graph-pass: InsertDualAspectLogic -Tue 01:03: INFO : Running manager compiler graph-pass: ClockWidthAssignment -Tue 01:03: INFO : Running manager compiler graph-pass: InsertPullPushAdapter -Tue 01:03: INFO : Running manager compiler graph-pass: ClockWidthAssignment -Tue 01:03: INFO : Running manager compiler graph-pass: InsertStreamFifos -Tue 01:03: INFO : Running manager compiler graph-pass: ClockWidthAssignment -Tue 01:03: INFO : Running manager compiler graph-pass: InsertStreamStatus -Tue 01:03: INFO : Running manager compiler graph-pass: InsertChipscope -Tue 01:03: INFO : Inserted 0 chipscope manager nodes. -Tue 01:03: INFO : Running manager compiler graph-pass: ClockWidthAssignment -Tue 01:03: PROGRESS: -Tue 01:03: PROGRESS: Compiling kernel "FetchSubTupleKernel" -Tue 01:03: INFO : Configuration: -Tue 01:03: INFO : KernelConfiguration.additionalInputPipelining = 64 [Init: 64] -Tue 01:03: INFO : KernelConfiguration.allowDSPCascading = true [Init: true] -Tue 01:03: INFO : KernelConfiguration.allowInputsOutputsBeforeFlushNode = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.allowZeroLatencyNodeHold = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.board = MAX4848A [Init: MAX2116B, change: MAX4848A] -Tue 01:03: INFO : KernelConfiguration.bramBitsThreshold = 2080 [Init: 2080] -Tue 01:03: INFO : KernelConfiguration.buildTarget = HARDWARE [Init: NONE, change: HARDWARE] -Tue 01:03: INFO : KernelConfiguration.cePipelining = 2 [Init: 2] -Tue 01:03: INFO : KernelConfiguration.clockPhaseBalanceThreshold = 0.1 [Init: 0.1] -Tue 01:03: INFO : KernelConfiguration.clockPhasingRetries = 50 [Init: 50] -Tue 01:03: INFO : KernelConfiguration.dumpNeighboursString = [Init: ] -Tue 01:03: INFO : KernelConfiguration.enableCeReplication = true [Init: true] -Tue 01:03: INFO : KernelConfiguration.enableClockPhasePartitioning = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.enableDebugIOControlRegs = true [Init: true] -Tue 01:03: INFO : KernelConfiguration.enableDummyBuild = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.enableKernelProfiler = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.enablePipelinedComputeController = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.enableShadowRegister = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.enableSmartKernelControl = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.fifoSrlRegisterStages = 1 [Init: 1] -Tue 01:03: INFO : KernelConfiguration.flushOnInputDataCongtiguous = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.hardwareDebugDepth = 512 [Init: 512] -Tue 01:03: INFO : KernelConfiguration.hwHierarchyMode = UNSET [Init: UNSET] -Tue 01:03: INFO : KernelConfiguration.latencyAnnotation = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.latencyAnnotationIOs = [Init: null] -Tue 01:03: INFO : KernelConfiguration.maxCoalescedFifoWidth = 2147483647 [Init: 2147483647] -Tue 01:03: INFO : KernelConfiguration.maxPreAdderFanOut = 1 [Init: 1] -Tue 01:03: INFO : KernelConfiguration.netlistMode = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.numPhotonStateMachines = 1 [Init: 1] -Tue 01:03: INFO : KernelConfiguration.optimizations.ceCounterRegisterDuplication = 1 [Init: 1] -Tue 01:03: INFO : KernelConfiguration.optimizations.conditionalArithmetic = true [Init: true] -Tue 01:03: INFO : KernelConfiguration.optimizations.counterChainWrapPipelining = 0 [Init: 0] -Tue 01:03: INFO : KernelConfiguration.optimizations.dspAddChain = OPTIMISE [Init: null, Init after BuildTarget change: OPTIMISE] -Tue 01:03: INFO : KernelConfiguration.optimizations.enableActiveFanoutReduction = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.optimizations.enableBUFGCE = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.optimizations.enableBetterInputRegistering = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.optimizations.enableBetterRegistering = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.optimizations.enableFIFOCoalescingAcrossPlacementConstraints = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.optimizations.enableFifoCoalescing = true [Init: true] -Tue 01:03: INFO : KernelConfiguration.optimizations.enableFullPrecisionBinaryOpConstants = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.optimizations.enableIntegratedRounding = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.optimizations.enableMappedMemoryHostReadBack = true [Init: true] -Tue 01:03: INFO : KernelConfiguration.optimizations.enableMultiCycleReset = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.optimizations.enablePowerTwoFloatMult = true [Init: true] -Tue 01:03: INFO : KernelConfiguration.optimizations.enableRedundantNodeDeletion = true [Init: true] -Tue 01:03: INFO : KernelConfiguration.optimizations.enableStateMachineRegisterMerging = true [Init: true] -Tue 01:03: INFO : KernelConfiguration.optimizations.inputFlushDistanceFactor = 0 [Init: 0] -Tue 01:03: INFO : KernelConfiguration.optimizations.minimumStaticFIFOSplitDepth = 1 [Init: 1] -Tue 01:03: INFO : KernelConfiguration.optimizations.optimizationTechnique = DEFAULT [Init: DEFAULT] -Tue 01:03: INFO : KernelConfiguration.optimizations.triAdd = true [Init: true] -Tue 01:03: INFO : KernelConfiguration.partialReconfBlockName = [Init: ] -Tue 01:03: INFO : KernelConfiguration.partialReconfMode = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.partialReconfTemplate = false [Init: false] -Tue 01:03: INFO : KernelConfiguration.replicateNodeCeLog2NumPartitions = 0 [Init: 0] -Tue 01:03: INFO : KernelConfiguration.romBRAMBitsThreshold = 2080 [Init: 2080] -Tue 01:03: INFO : KernelConfiguration.simulation.ramAddressCollisionBehaviour = EXCEPTION [Init: EXCEPTION] -Tue 01:03: INFO : KernelConfiguration.simulation.ramOutOfBoundsAccessBehaviour = EXCEPTION [Init: EXCEPTION] -Tue 01:03: INFO : KernelConfiguration.simulation.simProgressMessageFrequency = 0 [Init: 0] -Tue 01:03: INFO : -Tue 01:03: INFO : -- -Tue 01:03: WARNING : Warning (UNCONNECTED_DESIGN_ELEMENT): -Tue 01:03: WARNING : Unconnected elements in design 'FetchSubTupleKernel' -Tue 01:03: WARNING : details in : /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/FetchSubTupleKernel_graph_warnings.txt -Tue 01:03: INFO : Writing current graph to: FetchSubTuple-FetchSubTupleKernel-original.pxg -Tue 01:03: INFO : Running kernel graph-pass 'GeneratePXG'. -Tue 01:03: INFO : Graph-pass 'GeneratePXG' took 1.84720 s (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'MarkConstantPass'. -Tue 01:03: INFO : Graph-pass 'MarkConstantPass' took 9.79854 ms (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'ReachabilityPass'. -Tue 01:03: INFO : Graph-pass 'ReachabilityPass' took 59.9342 ms (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'FindInputsLeadingToFlush'. -Tue 01:03: INFO : Graph-pass 'FindInputsLeadingToFlush' took 483.910 µs (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'CheckForStatefulToFlushViolations'. -Tue 01:03: INFO : Graph-pass 'CheckForStatefulToFlushViolations' took 801.507 µs (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'CheckForInputToFlushViolations'. -Tue 01:03: INFO : Graph-pass 'CheckForInputToFlushViolations' took 3.18501 ms (1 iterations) -Tue 01:03: INFO : Not deleting directory (does not exist): neighbours -Tue 01:03: INFO : Running Photon pre-schedule graph optimisations -Tue 01:03: INFO : Running kernel graph-pass 'AlignOrEradicatePrintfs'. -Tue 01:03: INFO : Graph-pass 'AlignOrEradicatePrintfs' took 4.93850 ms (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'FoldConstantsPass'. -Tue 01:03: INFO : Graph-pass 'FoldConstantsPass' took 11.4848 ms (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'OptimiseNodesPass'. -Tue 01:03: INFO : Graph-pass 'OptimiseNodesPass' took 104.544 ms (2 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'DeleteRedundantNodes'. -Tue 01:03: INFO : Graph-pass 'DeleteRedundantNodes' took 1.57575 ms (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'AlteraDSPExtractionGraphPass'. -Tue 01:03: INFO : Optimized 0 sub-graphs into DSP multiply/add chains -Tue 01:03: INFO : Graph-pass 'AlteraDSPExtractionGraphPass' took 100.597 ms (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'TriAddExtractionPass'. -Tue 01:03: INFO : Graph-pass 'TriAddExtractionPass' took 3.17958 ms (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'ConditionalAddExtractionPass'. -Tue 01:03: INFO : Optimized 0 sub-graphs into conditional adds/subs/triadds. -Tue 01:03: INFO : Graph-pass 'ConditionalAddExtractionPass' took 4.22764 ms (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'PO2FPMultOptimiser'. -Tue 01:03: INFO : Graph-pass 'PO2FPMultOptimiser' took 1.88451 ms (1 iterations) -Tue 01:03: INFO : Logging Photon stats to: FetchSubTupleKernel_photon_stats.csv -Tue 01:03: INFO : Running kernel graph-pass 'StatsPass'. -Tue 01:03: INFO : Graph-pass 'StatsPass' took 7.85259 ms (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'CollectNumericExceptions'. -Tue 01:03: INFO : Graph-pass 'CollectNumericExceptions' took 455.233 µs (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'StreamOffsetDivExpand'. -Tue 01:03: INFO : Graph-pass 'StreamOffsetDivExpand' took 1.35797 ms (1 iterations) -Tue 01:03: INFO : Running kernel graph-pass 'FindIllegalLoops'. -Tue 01:04: INFO : Graph-pass 'FindIllegalLoops' took 4.65351 s (1 iterations) -Tue 01:04: INFO : Scheduling Photon graph (pass 1) -Tue 01:04: INFO : Running kernel graph-pass 'MarkConstantPass'. -Tue 01:04: INFO : Graph-pass 'MarkConstantPass' took 2.22208 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'MIPScheduler'. -Tue 01:04: INFO : Running command: "/vol/cc/opt/maxeler/maxcompiler-2014.1/bin/glpsol" --intopt --model "scheduler.mod" --data "FetchSubTupleKernel_scheduler_1_C.dat" --display "FetchSubTupleKernel_scheduler_1_C.out" --log "FetchSubTupleKernel_scheduler_1_C.log" -Tue 01:04: INFO : GLPSOL: GLPK LP/MIP Solver (modified by Maxeler Technologies Inc., October 2013), v4.52 -Tue 01:04: INFO : Parameter(s) specified in the command line: -Tue 01:04: INFO : --intopt --model scheduler.mod --data FetchSubTupleKernel_scheduler_1_C.dat -Tue 01:04: INFO : --display FetchSubTupleKernel_scheduler_1_C.out --log FetchSubTupleKernel_scheduler_1_C.log -Tue 01:04: INFO : Reading model section from scheduler.mod... -Tue 01:04: INFO : 95 lines were read -Tue 01:04: INFO : Reading data section from FetchSubTupleKernel_scheduler_1_C.dat... -Tue 01:04: INFO : 14548 lines were read -Tue 01:04: INFO : Generating schedulingEquation... -Tue 01:04: INFO : Generating bufferingEquation... -Tue 01:04: INFO : Generating afterFlushNode... -Tue 01:04: INFO : Generating forcePairConstraints... -Tue 01:04: INFO : Generating forceAtEnd... -Tue 01:04: INFO : Generating autoVarLatencyUserMin... -Tue 01:04: INFO : Generating autoVarLatencyUserMax... -Tue 01:04: INFO : Generating fifos... -Tue 01:04: INFO : Model has been successfully generated -Tue 01:04: INFO : GLPK Integer Optimizer, v4.52 -Tue 01:04: INFO : 7817 rows, 4447 columns, 21762 non-zeros -Tue 01:04: INFO : 4447 integer variables, none of which are binary -Tue 01:04: INFO : Preprocessing... -Tue 01:04: INFO : 7816 rows, 4443 columns, 19538 non-zeros -Tue 01:04: INFO : 4443 integer variables, none of which are binary -Tue 01:04: INFO : Scaling... -Tue 01:04: INFO : A: min|aij| = 1.000e+00 max|aij| = 1.000e+00 ratio = 1.000e+00 -Tue 01:04: INFO : Problem data seem to be well scaled -Tue 01:04: INFO : Constructing initial basis... -Tue 01:04: INFO : Size of triangular part is 7816 -Tue 01:04: INFO : Solving LP relaxation... -Tue 01:04: INFO : GLPK Simplex Optimizer, v4.52 -Tue 01:04: INFO : 7816 rows, 4443 columns, 19538 non-zeros -Tue 01:04: INFO : 0: obj = 0.000000000e+00 infeas = 1.069e+03 (0) -Tue 01:04: INFO : 500: obj = 5.000000000e+00 infeas = 5.270e+02 (0) -Tue 01:04: INFO : 1000: obj = 5.453000000e+03 infeas = 2.460e+02 (0) -Tue 01:04: INFO : 1500: obj = 8.130000000e+03 infeas = 1.410e+02 (0) -Tue 01:04: INFO : 2000: obj = 1.241900000e+04 infeas = 4.000e+00 (0) -Tue 01:04: INFO : * 2011: obj = 1.253900000e+04 infeas = 0.000e+00 (0) -Tue 01:04: INFO : * 2500: obj = 1.250900000e+04 infeas = 0.000e+00 (0) -Tue 01:04: INFO : * 2858: obj = 1.249200000e+04 infeas = 0.000e+00 (0) -Tue 01:04: INFO : OPTIMAL LP SOLUTION FOUND -Tue 01:04: INFO : Integer optimization begins... -Tue 01:04: INFO : + 2858: mip = not found yet >= -inf (1; 0) -Tue 01:04: INFO : + 2858: >>>>> 1.249200000e+04 >= 1.249200000e+04 0.0% (1; 0) -Tue 01:04: INFO : + 2858: mip = 1.249200000e+04 >= tree is empty 0.0% (0; 1) -Tue 01:04: INFO : INTEGER OPTIMAL SOLUTION FOUND -Tue 01:04: INFO : Time used: 0.7 secs -Tue 01:04: INFO : Memory used: 17.9 Mb (18748772 bytes) -Tue 01:04: INFO : Model has been successfully processed -Tue 01:04: INFO : Graph-pass 'MIPScheduler' took 1.22003 s (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'SubstituteEqPlaceholders'. -Tue 01:04: INFO : Graph-pass 'SubstituteEqPlaceholders' took 560.954 µs (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'ScheduleApplier'. -Tue 01:04: INFO : Graph-pass 'ScheduleApplier' took 10.9334 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'StatsPass'. -Tue 01:04: INFO : Graph-pass 'StatsPass' took 7.16104 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'ReachabilityPass'. -Tue 01:04: INFO : Graph-pass 'ReachabilityPass' took 6.75130 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'CheckForInputToFlushViolations'. -Tue 01:04: INFO : Graph-pass 'CheckForInputToFlushViolations' took 1.75265 ms (1 iterations) -Tue 01:04: INFO : Running Photon post-schedule graph optimisations (pass 1) -Tue 01:04: INFO : Running kernel graph-pass 'TapFIFOsPass'. -Tue 01:04: INFO : Graph-pass 'TapFIFOsPass' took 4.58358 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'FoldFIFOsPass'. -Tue 01:04: INFO : Graph-pass 'FoldFIFOsPass' took 1.54563 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'ValidateFIFOs'. -Tue 01:04: INFO : Graph-pass 'ValidateFIFOs' took 606.655 µs (1 iterations) -Tue 01:04: INFO : Scheduling Photon graph (pass 2) -Tue 01:04: INFO : Running kernel graph-pass 'MarkConstantPass'. -Tue 01:04: INFO : Graph-pass 'MarkConstantPass' took 981.262 µs (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'RemoveDistMeasurementNodes'. -Tue 01:04: INFO : Graph-pass 'RemoveDistMeasurementNodes' took 22.1990 µs (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'SubstituteEqPlaceholders'. -Tue 01:04: INFO : Graph-pass 'SubstituteEqPlaceholders' took 716.428 µs (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'ScheduleApplier'. -Tue 01:04: INFO : Graph-pass 'ScheduleApplier' took 297.107 ms (1 iterations) -Tue 01:04: INFO : Maximum stream latency for kernel 'FetchSubTupleKernel': 19 -Tue 01:04: INFO : Using user logic for flush. -Tue 01:04: INFO : Running kernel graph-pass 'StatsPass'. -Tue 01:04: INFO : Graph-pass 'StatsPass' took 10.4894 ms (1 iterations) -Tue 01:04: INFO : Running Photon post-schedule graph optimisations (pass 2) -Tue 01:04: INFO : Running kernel graph-pass 'TapFIFOsPass'. -Tue 01:04: INFO : Graph-pass 'TapFIFOsPass' took 111.174 ms (2 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'FoldFIFOsPass'. -Tue 01:04: INFO : Graph-pass 'FoldFIFOsPass' took 1.36224 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'MarkConstantPass'. -Tue 01:04: INFO : Graph-pass 'MarkConstantPass' took 1.06417 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'ScheduleAsserter'. -Tue 01:04: INFO : Graph-pass 'ScheduleAsserter' took 6.84977 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'ReplaceEvalStreamOffsetNodes'. -Tue 01:04: INFO : Graph-pass 'ReplaceEvalStreamOffsetNodes' took 367.553 µs (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'FIFOCoalesceRespectingPlacementPass'. -Tue 01:04: INFO : Graph-pass 'FIFOCoalesceRespectingPlacementPass' took 6.29677 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'FIFOReport'. -Tue 01:04: INFO : Graph-pass 'FIFOReport' took 7.67674 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'StatsPass'. -Tue 01:04: INFO : Graph-pass 'StatsPass' took 7.92091 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'RemoveUntypedConstants'. -Tue 01:04: INFO : Graph-pass 'RemoveUntypedConstants' took 191.430 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'VariableSizeMappedRegInserter'. -Tue 01:04: INFO : Graph-pass 'VariableSizeMappedRegInserter' took 457.617 µs (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'MarkConstantPass'. -Tue 01:04: INFO : Graph-pass 'MarkConstantPass' took 299.338 µs (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'MakeMaxFileNodeData'. -Tue 01:04: INFO : Graph-pass 'MakeMaxFileNodeData' took 109.520 ms (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'MoveFanoutRegsForwards'. -Tue 01:04: INFO : Graph-pass 'MoveFanoutRegsForwards' took 647.921 µs (1 iterations) -Tue 01:04: INFO : Optimization report for Kernel 'FetchSubTupleKernel'. -Tue 01:04: INFO : Enabled optimizations: -Tue 01:04: INFO : DSP-MultAdd -Tue 01:04: INFO : Tri-Adder -Tue 01:04: INFO : Conditional (Tri)Adds/Subs/AddSubs -Tue 01:04: INFO : Power-of-2 Floating Point -Tue 01:04: INFO : Fifo Coalescing -Tue 01:04: INFO : Creating a preliminary MaxCompilerDesignData.dat. (@ CoreCompile FetchSubTupleKernel) -Tue 01:04: INFO : Running kernel graph-pass 'WeightBasedCEPartitioner'. -Tue 01:04: INFO : Partitioning design into 1 CE domain(s) to minimize global signal fanout. -Tue 01:04: INFO : Graph-pass 'WeightBasedCEPartitioner' took 101.713 µs (1 iterations) -Tue 01:04: INFO : Using maximum counter CE delay chain length 5 -Tue 01:04: INFO : CE Partition 0 Clock Phase 0 : Nodes=3097 (use fill=59, use flush=4) Fill counters=2 (+12 delay regs) Flush counters=1 (+6 delay regs) -Tue 01:04: INFO : Running kernel graph-pass 'FindWriteableMappedMemories'. -Tue 01:04: INFO : Graph-pass 'FindWriteableMappedMemories' took 449.430 µs (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'MarkConstantPass'. -Tue 01:04: INFO : Graph-pass 'MarkConstantPass' took 859.170 µs (1 iterations) -Tue 01:04: INFO : Running kernel graph-pass 'MaxConstantLatency'. -Tue 01:04: INFO : Graph-pass 'MaxConstantLatency' took 1.13526 ms (1 iterations) -Tue 01:04: INFO : Maximum constant latency: 0 -Tue 01:04: INFO : Running kernel graph-pass 'PhotonMaxDCTopEntity'. -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 5 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 5 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (5 bits wide), cost 0 RAMB18-equivalents, and 5 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 9 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 9 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 4 (3 bits wide), cost 0 RAMB18-equivalents, and 3 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 -Tue 01:04: INFO : Graph-pass 'PhotonMaxDCTopEntity' took 6.72873 s (1 iterations) -Tue 01:04: INFO : Writing current graph to: FetchSubTuple-FetchSubTupleKernel-final-hardware.pxg -Tue 01:04: INFO : Running kernel graph-pass 'GeneratePXG'. -Tue 01:04: INFO : Graph-pass 'GeneratePXG' took 1.68826 s (1 iterations) -Tue 01:04: INFO : Running manager compiler graph-pass: GenerateMXGInfo -Tue 01:04: INFO : Running manager compiler graph-pass: GenerateSlicHostCode -Tue 01:04: INFO : Generating SLIC interface information -Tue 01:04: INFO : Generating SLIC code for interface 'default' -Tue 01:04: INFO : Skipping blacklisted scalar parameter 'FetchSubTupleKernel.current_run_cycle_count' -Tue 01:04: INFO : Interface 'default' depends on parameter 'numCycles' -Tue 01:04: INFO : Interface 'default' depends on parameter 'numInputs' -Tue 01:04: INFO : Generating XML description for Maxfile -Tue 01:04: INFO : Generating XML description for mode 'default' -Tue 01:04: INFO : Skipping blacklisted scalar parameter 'FetchSubTupleKernel.current_run_cycle_count' -Tue 01:04: INFO : Interface 'default' depends on parameter 'numCycles' -Tue 01:04: INFO : Interface 'default' depends on parameter 'numInputs' -Tue 01:04: INFO : Adding SLIC sections to the maxfile -Tue 01:04: INFO : Adding user files to the maxfile -Tue 01:04: INFO : Generating SLIC include file -Tue 01:04: INFO : Done generating SLIC interface information -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Control Streams: Connecting block MappedElementsSwitchPCIeEA with select value: 1 -Tue 01:04: INFO : Running command: quartus_fit --version 2>&1 > quartus_version_test -Tue 01:04: INFO : ERROR: ld.so: object '/vol/cc/opt/maxeler/maxcompiler-2014.1/lib/maxeleros-sim/lib/libmaxeleros.so' from LD_PRELOAD cannot be preloaded: ignored. -Tue 01:04: INFO : Detected Quartus II version 13.1 -Tue 01:04: INFO : Running ' lmutil lmdiag -n quartus' -Tue 01:04: INFO : Successfully checked out license for Quartus (quartus) -Tue 01:04: INFO : Updating the preliminary MaxCompilerDesignData.dat. (@ Main build) -Tue 01:04: INFO : Deleting /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxCompilerDesignData.dat -Tue 01:04: PROGRESS: Generating input files (VHDL, netlists, MegaWizard/CoreGen) -Tue 01:04: INFO : Not deleting directory (does not exist): tmp -Tue 01:04: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; qmegawiz --64bit -silent module=altclkctrl -f:MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1.txt MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1.vhd > qmegawiz.log -Tue 01:04: INFO : Not deleting directory (does not exist): tmp -Tue 01:04: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; qmegawiz --64bit -silent module=altclkctrl -f:MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena.txt MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena.vhd > qmegawiz.log -Tue 01:04: INFO : Mapped register report: -Tue 01:04: INFO : 0 SFA_FORWARD_EN 4bytes -Tue 01:04: INFO : 4 dbg_stall_vector 1bytes -Tue 01:04: INFO : 5 io_output_force_disabled 1bytes -Tue 01:04: INFO : 6 io_sizes_force_disabled 1bytes -Tue 01:04: INFO : 7 io_input_force_disabled 1bytes -Tue 01:04: INFO : 8 run_cycle_count 6bytes -Tue 01:04: INFO : e current_run_cycle_count 6bytes -Tue 01:04: INFO : 14 dbg_ctld_empty 1bytes -Tue 01:04: INFO : 15 dbg_ctld_almost_empty 1bytes -Tue 01:04: INFO : 16 dbg_ctld_done 1bytes -Tue 01:04: INFO : 17 dbg_ctld_read 1bytes -Tue 01:04: INFO : 18 dbg_ctld_request 1bytes -Tue 01:04: INFO : 19 dbg_flush_start 1bytes -Tue 01:04: INFO : 1a dbg_full_level 1bytes -Tue 01:04: INFO : 1b dbg_flush_start_level 1bytes -Tue 01:04: INFO : 1c dbg_done_out 1bytes -Tue 01:04: INFO : 1d dbg_flushing 1bytes -Tue 01:04: INFO : 1e dbg_fill_level 1bytes -Tue 01:04: INFO : 1f dbg_flush_level 1bytes -Tue 01:04: INFO : 20 dbg_ctld_read_pipe_dbg 1bytes -Tue 01:04: INFO : 21 dbg_out_valid 1bytes -Tue 01:04: INFO : 22 dbg_out_stall 1bytes -Tue 01:04: INFO : 23 dynpcie_sth0_sth_compl_fifo_flags 1bytes -Tue 01:04: INFO : 24 clock_counters_base_clock_cclk 2bytes -Tue 01:04: INFO : 26 clock_counters_STREAM 2bytes -Tue 01:04: INFO : 28 clock_counters_clk_pcie 2bytes -Tue 01:04: INFO : 2a seen_reset_reset_n 1bytes -Tue 01:04: INFO : 2b seen_reset_STREAM_rst 1bytes -Tue 01:04: INFO : 2c seen_reset_STREAM_rst_delay 1bytes -Tue 01:04: INFO : 2d seen_reset_PCIE_rst 1bytes -Tue 01:04: INFO : 2e seen_reset_PCIE_rst_delay 1bytes -Tue 01:04: INFO : 2f seen_toggle_crash_input 1bytes -Tue 01:04: INFO : Mapped register chain length = 48 -Tue 01:04: INFO : Mapped memory report: -Tue 01:04: INFO : Memory 'MappedClockControl.STREAM_CLKPRIM' @ 4063232 -Tue 01:04: INFO : Memory 'MappedDRP.CHECKSUM' @ 3932160 -Tue 01:04: INFO : Memory 'Monitoring.PERFMONITOR' @ 3866624 -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... -Tue 01:04: INFO : All asynchronous jobs are now completed. -Tue 01:04: PROGRESS: Running back-end build (16 phases) -Tue 01:04: PROGRESS: (1/16) - Prepare MaxFile Data (GenerateMaxFileDataFile) -Tue 01:04: INFO : Build pass 'GenerateMaxFileDataFile' took 26.7383 ms. -Tue 01:04: PROGRESS: (2/16) - Prepare for Placement (QuartusMap) -Tue 01:04: INFO : Starting quartus_map. (01:04:59 25/08/15) -Tue 01:04: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_map MAX4MAIAPeripheryTop --64bit --parallel=1 -Tue 01:05: INFO : Info: ******************************************************************* -Tue 01:05: INFO : Info: Running Quartus II 64-Bit Analysis & Synthesis -Tue 01:05: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version -Tue 01:05: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. -Tue 01:05: INFO : Info: Your use of Altera Corporation's design tools, logic functions -Tue 01:05: INFO : Info: and other software and tools, and its AMPP partner logic -Tue 01:05: INFO : Info: functions, and any output files from any of the foregoing -Tue 01:05: INFO : Info: (including device programming or simulation files), and any -Tue 01:05: INFO : Info: associated documentation or information are expressly subject -Tue 01:05: INFO : Info: to the terms and conditions of the Altera Program License -Tue 01:05: INFO : Info: Subscription Agreement, Altera MegaCore Function License -Tue 01:05: INFO : Info: Agreement, or other applicable license agreement, including, -Tue 01:05: INFO : Info: without limitation, that your use is for the sole purpose of -Tue 01:05: INFO : Info: programming logic devices manufactured by Altera and sold by -Tue 01:05: INFO : Info: Altera or its authorized distributors. Please refer to the -Tue 01:05: INFO : Info: applicable agreement for further details. -Tue 01:05: INFO : Info: Processing started: Tue Aug 25 01:05:04 2015 -Tue 01:05: INFO : Info: Command: quartus_map MAX4MAIAPeripheryTop --parallel=1 -Tue 01:05: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/map/altera_quartus/quartus.ini -Tue 01:05: INFO : Critical Warning (12473): User specified to use only one processors but 16 processors were detected which could be used to decrease run time. -Tue 01:05: INFO : Info (12021): Found 6 design units, including 3 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_primitives.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: dff_ce_asyncsr-altera -Tue 01:05: INFO : Info (12022): Found design unit 2: dff_ce_syncsr-altera -Tue 01:05: INFO : Info (12022): Found design unit 3: dff_ce_syncsr_ne-altera -Tue 01:05: INFO : Info (12023): Found entity 1: dff_ce_asyncsr -Tue 01:05: INFO : Info (12023): Found entity 2: dff_ce_syncsr -Tue 01:05: INFO : Info (12023): Found entity 3: dff_ce_syncsr_ne -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PhotonDesignControl.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PhotonDesignControl-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: PhotonDesignControl -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/rg_buffer_sfh.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: rg_buffer_sfh-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: rg_buffer_sfh -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/rg_buffer_info.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: rg_buffer_info-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: rg_buffer_info -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/posted_credits_fifo.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: posted_credits_fifo-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: posted_credits_fifo -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_2_16_2_aclr_fwft.vhdl(101) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_2_16_2_aclr_fwft.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_2_16_2_aclr_fwft-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_2_16_2_aclr_fwft -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/rg_buffer_sth.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: rg_buffer_sth-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: rg_buffer_sth -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/rg_buffer_info_sth.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: rg_buffer_info_sth-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: rg_buffer_info_sth -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/sth_compl_fifo_debug.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: sth_compl_fifo_debug-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: sth_compl_fifo_debug -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of.vhdl(106) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../compl_fifo.vhdl(104) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/compl_fifo.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: compl_fifo-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: compl_fifo -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../pcie_tx_fifo.vhdl(104) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_tx_fifo.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: pcie_tx_fifo-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: pcie_tx_fifo -Tue 01:05: INFO : Info (12021): Found 2 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/cross_clock_pkg.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: cross_clock_pkg -Tue 01:05: INFO : Info (12022): Found design unit 2: cross_clock_pkg-body -Tue 01:05: INFO : Info (12021): Found 4 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/strobe_to_strobe.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: strobe_to_strobe_prim-altera -Tue 01:05: INFO : Info (12022): Found design unit 2: strobe_to_strobe-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: strobe_to_strobe_prim -Tue 01:05: INFO : Info (12023): Found entity 2: strobe_to_strobe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/max4_cpld_flash_if/max4_cpld_flash_if.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: max4_cpld_flash_if-struct -Tue 01:05: INFO : Info (12023): Found entity 1: max4_cpld_flash_if -Tue 01:05: INFO : Info (12021): Found 4 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/basic_synchroniser/basic_synchroniser.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: basic_synchroniser_prim-altera -Tue 01:05: INFO : Info (12022): Found design unit 2: basic_synchroniser-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: basic_synchroniser_prim -Tue 01:05: INFO : Info (12023): Found entity 2: basic_synchroniser -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/max_events/max_events.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: max_events-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: max_events -Tue 01:05: INFO : Info (12021): Found 4 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/level_synchroniser/level_synchroniser.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: level_synchroniser_prim-altera -Tue 01:05: INFO : Info (12022): Found design unit 2: level_synchroniser-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: level_synchroniser_prim -Tue 01:05: INFO : Info (12023): Found entity 2: level_synchroniser -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/max4_cpld_ioexpand/max4_cpld_ioexpand.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: max4_cpld_ioexpand-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: max4_cpld_ioexpand -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_xcvr_reconfig_SV.v -Tue 01:05: INFO : Info (12023): Found entity 1: pcie_xcvr_reconfig_SV -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV.v -Tue 01:05: INFO : Info (12023): Found entity 1: pcie_reconfig_SV -Tue 01:05: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_xcvr_functions.sv -Tue 01:05: INFO : Info (12022): Found design unit 1: altera_xcvr_functions (SystemVerilog) (pcie_reconfig_SV) -Tue 01:05: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_h.sv -Tue 01:05: INFO : Info (12022): Found design unit 1: sv_xcvr_h (SystemVerilog) (pcie_reconfig_SV) -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_resync.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_resync -Tue 01:05: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_h.sv -Tue 01:05: INFO : Info (12022): Found design unit 1: alt_xcvr_reconfig_h (SystemVerilog) (pcie_reconfig_SV) -Tue 01:05: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_dfe_cal_sweep_h.sv -Tue 01:05: INFO : Info (12022): Found design unit 1: sv_xcvr_dfe_cal_sweep_h (SystemVerilog) (pcie_reconfig_SV) -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cal_seq.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cal_seq -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xreconf_cif.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xreconf_cif -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xreconf_uif.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xreconf_uif -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xreconf_basic_acq.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xreconf_basic_acq -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_analog.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_analog -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_analog_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_analog_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xreconf_analog_datactrl.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xreconf_analog_datactrl -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xreconf_analog_rmw.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xreconf_analog_rmw -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xreconf_analog_ctrlsm.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xreconf_analog_ctrlsm -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_offset_cancellation.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_offset_cancellation -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_offset_cancellation_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_offset_cancellation_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_eyemon.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_eyemon -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_eyemon_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_eyemon_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_eyemon_ctrl_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_eyemon_ctrl_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_eyemon_ber_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_eyemon_ber_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/ber_reader_dcfifo.v -Tue 01:05: INFO : Info (12023): Found entity 1: ber_reader_dcfifo -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/step_to_mon_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: step_to_mon_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/mon_to_step_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: mon_to_step_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_reg_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_reg_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_cal_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_cal_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_cal_sweep_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_cal_sweep_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_cal_sweep_datapath_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_cal_sweep_datapath_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_oc_cal_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_oc_cal_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_pi_phase_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_pi_phase_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_step_to_mon_en_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_step_to_mon_en_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_adapt_tap_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_adapt_tap_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_ctrl_mux_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_ctrl_mux_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_local_reset_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_local_reset_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_cal_sim_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_cal_sim_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_adapt_tap_sim_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_adapt_tap_sim_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_adce.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_adce -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_adce_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_adce_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_adce_datactrl_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_adce_datactrl_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_sv.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_cal.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_cal -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_control.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_control -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_datapath.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_datapath -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_pll_reset.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_pll_reset -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_eye_width.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_eye_width -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_align_clk.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_align_clk -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_get_sum.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_get_sum -Tue 01:05: INFO : Info (12021): Found 0 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_cal_sim_model.sv -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_mif.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_mif -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_reconfig_mif.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_reconfig_mif -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_reconfig_mif_ctrl.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_reconfig_mif_ctrl -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_reconfig_mif_avmm.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_reconfig_mif_avmm -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_pll.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_pll -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_reconfig_pll.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_reconfig_pll -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_reconfig_pll_ctrl.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_reconfig_pll_ctrl -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_soc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_soc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_ram.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_ram -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_direct.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_direct -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xrbasic_l2p_addr.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xrbasic_l2p_addr -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xrbasic_l2p_ch.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xrbasic_l2p_ch -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xrbasic_l2p_rom.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xrbasic_l2p_rom -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xrbasic_lif_csr.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xrbasic_lif_csr -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xrbasic_lif.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xrbasic_lif -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_reconfig_basic.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_reconfig_basic -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_arbiter_acq.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_arbiter_acq -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_basic.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_basic -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_arbiter.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_arbiter -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_m2s.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_m2s -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_wait_generate.v -Tue 01:05: INFO : Info (12023): Found entity 1: altera_wait_generate -Tue 01:05: INFO : Info (12021): Found 3 design units, including 3 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_csr_selector.sv -Tue 01:05: INFO : Info (12023): Found entity 1: csr_mux -Tue 01:05: INFO : Info (12023): Found entity 2: csr_indexed_write_mux -Tue 01:05: INFO : Info (12023): Found entity 3: csr_indexed_read_only_reg -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_reconfig_bundle_to_basic.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_reconfig_bundle_to_basic -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu.v -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu -Tue 01:05: INFO : Info (12021): Found 3 design units, including 3 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_reconfig_cpu.v -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module -Tue 01:05: INFO : Info (12023): Found entity 2: alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module -Tue 01:05: INFO : Info (12023): Found entity 3: alt_xcvr_reconfig_cpu_reconfig_cpu -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench.v -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0.v -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0 -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_irq_mapper.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_irq_mapper -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_reset_controller.v -Tue 01:05: INFO : Info (12023): Found entity 1: altera_reset_controller -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_reset_synchronizer.v -Tue 01:05: INFO : Info (12023): Found entity 1: altera_reset_synchronizer -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_merlin_master_translator.sv -Tue 01:05: INFO : Info (12023): Found entity 1: altera_merlin_master_translator -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_merlin_slave_translator.sv -Tue 01:05: INFO : Info (12023): Found entity 1: altera_merlin_slave_translator -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_merlin_master_agent.sv -Tue 01:05: INFO : Info (12023): Found entity 1: altera_merlin_master_agent -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_merlin_slave_agent.sv -Tue 01:05: INFO : Info (12023): Found entity 1: altera_merlin_slave_agent -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_merlin_burst_uncompressor.sv -Tue 01:05: INFO : Info (12023): Found entity 1: altera_merlin_burst_uncompressor -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_avalon_sc_fifo.v -Tue 01:05: INFO : Info (12023): Found entity 1: altera_avalon_sc_fifo -Tue 01:05: INFO : Info (12021): Found 2 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_default_decode -Tue 01:05: INFO : Info (12023): Found entity 2: alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router -Tue 01:05: INFO : Info (12021): Found 2 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001_default_decode -Tue 01:05: INFO : Info (12023): Found entity 2: alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_default_decode -Tue 01:05: INFO : Info (12023): Found entity 2: alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router -Tue 01:05: INFO : Info (12021): Found 2 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001_default_decode -Tue 01:05: INFO : Info (12023): Found entity 2: alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001 -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux_001.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux_001 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_merlin_arbitrator.sv -Tue 01:05: INFO : Info (12023): Found entity 1: altera_merlin_arbitrator -Tue 01:05: INFO : Info (12023): Found entity 2: altera_merlin_arb_adder -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux_001.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux_001 -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux_001.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux_001 -Tue 01:05: INFO : Info (12021): Found 4 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1/MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1_altclkctrl_blh-RTL -Tue 01:05: INFO : Info (12022): Found design unit 2: mwaltclkctrl_quartusv13_1_0_gclk_numclk_1-RTL -Tue 01:05: INFO : Info (12023): Found entity 1: MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1_altclkctrl_blh -Tue 01:05: INFO : Info (12023): Found entity 2: MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: pcie_SV_hard_ip-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: pcie_SV_hard_ip -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/altpcie_sv_hip_ast_hwtcl.v -Tue 01:05: INFO : Info (12023): Found entity 1: altpcie_sv_hip_ast_hwtcl -Tue 01:05: INFO : Warning (10229): Verilog HDL Expression warning at altpcie_hip_256_pipen1b.v(1142): truncated literal to match 128 bits -Tue 01:05: INFO : Info (12021): Found 7 design units, including 7 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/altpcie_hip_256_pipen1b.v -Tue 01:05: INFO : Info (12023): Found entity 1: altpcie_hip_256_pipen1b -Tue 01:05: INFO : Info (12023): Found entity 2: altpcie_hip_bitsync2 -Tue 01:05: INFO : Info (12023): Found entity 3: altpcie_hip_bitsync -Tue 01:05: INFO : Info (12023): Found entity 4: altpcie_hip_vecsync2 -Tue 01:05: INFO : Info (12023): Found entity 5: altpcie_hip_vecsync -Tue 01:05: INFO : Info (12023): Found entity 6: hd_altpe3_hip_eq_bypass_ph3 -Tue 01:05: INFO : Info (12023): Found entity 7: hip_eq_dprio -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/altpcie_rs_serdes.v -Tue 01:05: INFO : Info (12023): Found entity 1: altpcie_rs_serdes -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/altpcie_rs_hip.v -Tue 01:05: INFO : Info (12023): Found entity 1: altpcie_rs_hip -Tue 01:05: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/altera_xcvr_functions.sv -Tue 01:05: INFO : Info (12022): Found design unit 1: altera_xcvr_functions (SystemVerilog) (pcie_SV_hard_ip) -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_pcs.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_pcs -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_pcs_ch.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_pcs_ch -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_pma.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_pma -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_reconfig_bundle_to_xcvr.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_reconfig_bundle_to_xcvr -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_reconfig_bundle_to_ip.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_reconfig_bundle_to_ip -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_reconfig_bundle_merger.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_reconfig_bundle_merger -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_rx_pma.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_rx_pma -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_tx_pma.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_tx_pma -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_tx_pma_ch.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_tx_pma_ch -Tue 01:05: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_h.sv -Tue 01:05: INFO : Info (12022): Found design unit 1: sv_xcvr_h (SystemVerilog) (pcie_SV_hard_ip) -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_avmm_csr.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_avmm_csr -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_avmm_dcd.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_avmm_dcd -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_avmm.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_avmm -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_data_adapter.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_data_adapter -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_native.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_native -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_plls.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_plls -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/alt_xcvr_resync.sv -Tue 01:05: INFO : Info (12023): Found entity 1: alt_xcvr_resync -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_10g_rx_pcs_rbc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_hssi_10g_rx_pcs_rbc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_10g_tx_pcs_rbc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_hssi_10g_tx_pcs_rbc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_8g_rx_pcs_rbc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_hssi_8g_rx_pcs_rbc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_8g_tx_pcs_rbc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_hssi_8g_tx_pcs_rbc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_8g_pcs_aggregate_rbc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_hssi_8g_pcs_aggregate_rbc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_common_pcs_pma_interface_rbc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_hssi_common_pcs_pma_interface_rbc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_common_pld_pcs_interface_rbc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_hssi_common_pld_pcs_interface_rbc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_pipe_gen1_2_rbc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_hssi_pipe_gen1_2_rbc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_pipe_gen3_rbc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_hssi_pipe_gen3_rbc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_rx_pcs_pma_interface_rbc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_hssi_rx_pcs_pma_interface_rbc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_rx_pld_pcs_interface_rbc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_hssi_rx_pld_pcs_interface_rbc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_tx_pcs_pma_interface_rbc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_hssi_tx_pcs_pma_interface_rbc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_tx_pld_pcs_interface_rbc.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_hssi_tx_pld_pcs_interface_rbc -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_emsip_adapter.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_emsip_adapter -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_pipe_native.sv -Tue 01:05: INFO : Info (12023): Found entity 1: sv_xcvr_pipe_native -Tue 01:05: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/alt_xcvr_reconfig_h.sv -Tue 01:05: INFO : Info (12022): Found design unit 1: alt_xcvr_reconfig_h (SystemVerilog) (pcie_SV_hard_ip) -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/altpcie_reconfig_driver.sv -Tue 01:05: INFO : Info (12023): Found entity 1: altpcie_reconfig_driver -Tue 01:05: INFO : Info (12021): Found 4 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena/MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena_altclkctrl_tmg-RTL -Tue 01:05: INFO : Info (12022): Found design unit 2: mwaltclkctrl_quartusv13_1_0_auto_numclk_1_ena-RTL -Tue 01:05: INFO : Info (12023): Found entity 1: MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena_altclkctrl_tmg -Tue 01:05: INFO : Info (12023): Found entity 2: MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena -Tue 01:05: INFO : Info (12021): Found 6 design units, including 6 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_pll_reconfig_top/altera_pll_reconfig_top.v -Tue 01:05: INFO : Info (12023): Found entity 1: altera_pll_reconfig_top -Tue 01:05: INFO : Info (12023): Found entity 2: self_reset -Tue 01:05: INFO : Info (12023): Found entity 3: dprio_mux -Tue 01:05: INFO : Info (12023): Found entity 4: fpll_dprio_init -Tue 01:05: INFO : Info (12023): Found entity 5: dyn_phase_shift -Tue 01:05: INFO : Info (12023): Found entity 6: generic_lcell_comb -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "shreg_extract" at ../../../reset_control/reset_control.vhd(35) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/reset_control/reset_control.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: reset_control-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: reset_control -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../max_SV_pcie_rx/max_SV_pcie_rx.vhd(157) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/max_SV_pcie_rx/max_SV_pcie_rx.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: max_SV_pcie_rx-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: max_SV_pcie_rx -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../max_SV_pcie_tx/max_SV_pcie_tx.vhd(170) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/max_SV_pcie_tx/max_SV_pcie_tx.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: max_SV_pcie_tx-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: max_SV_pcie_tx -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../max_pcie_slave_req_dispatcher/max_pcie_slave_req_dispatcher.vhd(65) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/max_pcie_slave_req_dispatcher/max_pcie_slave_req_dispatcher.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: max_pcie_slave_req_dispatcher-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: max_pcie_slave_req_dispatcher -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../max_SV_pcie_slave/max_SV_pcie_slave.vhd(322) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/max_SV_pcie_slave/max_SV_pcie_slave.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: max_SV_pcie_slave-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: max_SV_pcie_slave -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/start_of_day_reset/start_of_day_reset.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: start_of_day_reset-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: start_of_day_reset -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/perf_monitor/perf_monitor.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: perf_monitor-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: perf_monitor -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_posted_credits_writer/pcie_posted_credits_writer.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: pcie_posted_credits_writer-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: pcie_posted_credits_writer -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_slave_streaming_sfh_ring/pcie_slave_streaming_sfh_ring.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: pcie_slave_streaming_sfh_ring-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: pcie_slave_streaming_sfh_ring -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/pcie_slave_streaming_sth_ring/pcie_slave_streaming_sth_ring.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: pcie_slave_streaming_sth_ring-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: pcie_slave_streaming_sth_ring -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/fast_request_arbiter/fast_request_arbiter.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: fast_request_arbiter-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: fast_request_arbiter -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/priority_encoder/priority_encoder.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: priority_encoder-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: priority_encoder -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/write_request_encoder/write_request_encoder.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: write_request_encoder-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: write_request_encoder -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/mapped_register_readable/mapped_register_readable.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: mapped_register_readable-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: mapped_register_readable -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../dualaspectmuxpipe_mux4/dualaspectmuxpipe_mux4.vhd(40) -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "max_fanout" at ../../../dualaspectmuxpipe_mux4/dualaspectmuxpipe_mux4.vhd(43) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/dualaspectmuxpipe_mux4/dualaspectmuxpipe_mux4.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: dualaspectmuxpipe_mux4-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: dualaspectmuxpipe_mux4 -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../dualaspectmuxpipe_counter/dualaspectmuxpipe_counter.vhd(55) -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "max_fanout" at ../../../dualaspectmuxpipe_counter/dualaspectmuxpipe_counter.vhd(64) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/dualaspectmuxpipe_counter/dualaspectmuxpipe_counter.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: dualaspectmuxpipe_counter-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: dualaspectmuxpipe_counter -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../dualaspectreg_int/dualaspectreg_int.vhd(27) -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "max_fanout" at ../../../dualaspectreg_int/dualaspectreg_int.vhd(37) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/dualaspectreg_int/dualaspectreg_int.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: dualaspectreg_int-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: dualaspectreg_int -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "max_fanout" at ../../../mapped_register/mapped_register.vhd(27) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/mapped_register/mapped_register.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: mapped_register-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: mapped_register -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49/FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49-StateMachine -Tue 01:05: INFO : Info (12023): Found entity 1: FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SimpleSR/SimpleSR.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SimpleSR-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SimpleSR -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/ConditionalAddSubtract/ConditionalAddSubtract.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: ConditionalAddSubtract-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: ConditionalAddSubtract -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33/FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33-StateMachine -Tue 01:05: INFO : Info (12023): Found entity 1: FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/signal_forwarding_adapter/signal_forwarding_adapter.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: signal_forwarding_adapter-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: signal_forwarding_adapter -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/common_packet_parser/common_packet_parser.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: common_packet_parser-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: common_packet_parser -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/mapped_memories_adapter/mapped_memories_adapter.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: mapped_memories_adapter-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: mapped_memories_adapter -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/mapped_memories_controller_core/mapped_memories_controller_core.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: mapped_memories_controller_core-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: mapped_memories_controller_core -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/mapped_registers_controller/mapped_registers_controller.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: mapped_registers_controller-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: mapped_registers_controller -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/mec_switch_arbiter/mec_switch_arbiter.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: mec_switch_arbiter-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: mec_switch_arbiter -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/mapped_clock_control/mapped_clock_control.vhd -Tue 01:05: INFO : Info (12022): Found design unit 1: mapped_clock_control-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: mapped_clock_control -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/mec_switch_arbiter_i.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: mec_switch_arbiter_i-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: mec_switch_arbiter_i -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MappedClockControl_id_3e.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MappedClockControl_id_3e-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MappedClockControl_id_3e -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/stream_clkprim_lock_count_32.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: stream_clkprim_lock_count_32-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: stream_clkprim_lock_count_32 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SanityBlock_cclk_STREAM_clk_pcie.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SanityBlock_cclk_STREAM_clk_pcie-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SanityBlock_cclk_STREAM_clk_pcie -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/mapped_element_switch/mapped_element_switch.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: mapped_element_switch-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: mapped_element_switch -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/mapped_element_switch/src_to_dst_control.quartus.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: src_to_dst_control-rtl -Tue 01:05: INFO : Info (12023): Found entity 1: src_to_dst_control -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MAX4MAIAPeripheryTop.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MAX4MAIAPeripheryTop-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MAX4MAIAPeripheryTop -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MAX4CPLDInterface.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MAX4CPLDInterface-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MAX4CPLDInterface -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MAXEvents.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MAXEvents-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MAXEvents -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/StratixPCIeBase.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: StratixPCIeBase-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: StratixPCIeBase -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/TransceiverReconfig.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: TransceiverReconfig-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: TransceiverReconfig -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../StratixVHardIPPCIe.vhdl(503) -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../StratixVHardIPPCIe.vhdl(510) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/StratixVHardIPPCIe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: StratixVHardIPPCIe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: StratixVHardIPPCIe -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraClockGenerator_250_200_STREAM.vhdl(107) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraClockGenerator_250_200_STREAM.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraClockGenerator_250_200_STREAM-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraClockGenerator_250_200_STREAM -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../StratixVClockManager_in250_out_f200p0dc50_f200p180dc50.vhdl(276) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/StratixVClockManager_in250_out_f200p0dc50_f200p180dc50.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: StratixVClockManager_in250_out_f200p0dc50_f200p180dc50-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: StratixVClockManager_in250_out_f200p0dc50_f200p180dc50 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MAX4FPGATop.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MAX4FPGATop-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MAX4FPGATop -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv496.vhdl(113) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv496.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv496-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv496 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126.vhdl(115) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PCIeEA.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PCIeEA-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PCIeEA -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384.vhdl(113) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384 -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_34_512_34_dualclock_aclr.vhdl(110) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_34_512_34_dualclock_aclr.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_34_512_34_dualclock_aclr-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_34_512_34_dualclock_aclr -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/StratixPCIeInterface.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: StratixPCIeInterface-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: StratixPCIeInterface -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MAX4PCIeSlaveInterface.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MAX4PCIeSlaveInterface-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MAX4PCIeSlaveInterface -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/FPGAWrapperEntity_Manager_FetchSubTuple.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: FPGAWrapperEntity_Manager_FetchSubTuple-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: FPGAWrapperEntity_Manager_FetchSubTuple -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PerfMonitor.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PerfMonitor-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PerfMonitor -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MappedElementAdapterForwarder.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MappedElementAdapterForwarder-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MappedElementAdapterForwarder -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PCIeStreaming_2_3.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PCIeStreaming_2_3-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PCIeStreaming_2_3 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PCIeSlaveStreamFromHost.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PCIeSlaveStreamFromHost-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PCIeSlaveStreamFromHost -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PCIeSlaveStreamToHost.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PCIeSlaveStreamToHost-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PCIeSlaveStreamToHost -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SlaveStreamingCreditsBarParser.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SlaveStreamingCreditsBarParser-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SlaveStreamingCreditsBarParser -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SlaveStreamingRingConfigBarParser.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SlaveStreamingRingConfigBarParser-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SlaveStreamingRingConfigBarParser -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MemWriteRequestArbiter.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MemWriteRequestArbiter-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MemWriteRequestArbiter -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/FastRequestArbiter_req4.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: FastRequestArbiter_req4-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: FastRequestArbiter_req4 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/TagGenerator.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: TagGenerator-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: TagGenerator -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/RequestEncoder.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: RequestEncoder-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: RequestEncoder -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_128_512_128_aclr_afv448.vhdl(104) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_128_512_128_aclr_afv448.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_128_512_128_aclr_afv448-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_128_512_128_aclr_afv448 -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_115_512_115_aclr_fwft.vhdl(101) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_115_512_115_aclr_fwft.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_115_512_115_aclr_fwft-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_115_512_115_aclr_fwft -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/ReadComplRequestArbiter.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: ReadComplRequestArbiter-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: ReadComplRequestArbiter -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/FastRequestArbiter_req1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: FastRequestArbiter_req1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: FastRequestArbiter_req1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MappedRegBlock_921618fecb8cf8badc2cf71cbe32b185.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MappedRegBlock_921618fecb8cf8badc2cf71cbe32b185-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MappedRegBlock_921618fecb8cf8badc2cf71cbe32b185 -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../Manager_FetchSubTuple.vhdl(407) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_21.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_21-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_21 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477.vhdl(115) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_19.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_19-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_19 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/StreamFifo_altera_1536_1536_512_pushin_sl5_pullout_el1_singleclock_errflgs.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: StreamFifo_altera_1536_1536_512_pushin_sl5_pullout_el1_singleclock_errflgs-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: StreamFifo_altera_1536_1536_512_pushin_sl5_pullout_el1_singleclock_errflgs -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_1536_512_1536_aclr_afv474_of_uf.vhdl(106) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_1536_512_1536_aclr_afv474_of_uf.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_1536_512_1536_aclr_afv474_of_uf-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_1536_512_1536_aclr_afv474_of_uf -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_17.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_17-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_17 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7.vhdl(117) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_13.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_13-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_13 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_1536_512_1536_aclr_afv510_aev8_of_uf.vhdl(109) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_1536_512_1536_aclr_afv510_aev8_of_uf.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_1536_512_1536_aclr_afv510_aev8_of_uf-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_1536_512_1536_aclr_afv510_aev8_of_uf -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_15.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_15-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_15 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_128_512_128_aclr_afv477_of_uf.vhdl(106) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_128_512_128_aclr_afv477_of_uf.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_128_512_128_aclr_afv477_of_uf-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_128_512_128_aclr_afv477_of_uf -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_11.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_11-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_11 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_8.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_8-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_8 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/DualAspectMux_1536_128_COUNTER_PIPELINED_LIMITED.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: DualAspectMux_1536_128_COUNTER_PIPELINED_LIMITED-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: DualAspectMux_1536_128_COUNTER_PIPELINED_LIMITED -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/DualAspectCounterPipelined_128_1536.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: DualAspectCounterPipelined_128_1536-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: DualAspectCounterPipelined_128_1536 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_4.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_4-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_4 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/DualAspectMux_128_32_COUNTER_PIPELINED.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: DualAspectMux_128_32_COUNTER_PIPELINED-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: DualAspectMux_128_32_COUNTER_PIPELINED -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/DualAspectCounterPipelined_32_128.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: DualAspectCounterPipelined_32_128-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: DualAspectCounterPipelined_32_128 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/DualAspectReg_128_1536.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: DualAspectReg_128_1536-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: DualAspectReg_128_1536 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/WrapperNodeIO_output.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: WrapperNodeIO_output-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: WrapperNodeIO_output -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/WrapperNodeIO_sizes.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: WrapperNodeIO_sizes-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: WrapperNodeIO_sizes -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/WrapperNodeIO_input.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: WrapperNodeIO_input-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: WrapperNodeIO_input -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "buffer_type" at ../../../FetchSubTupleKernel_streamwrapper.vhdl(367) -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "buffer_type" at ../../../FetchSubTupleKernel_streamwrapper.vhdl(368) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/FetchSubTupleKernel_streamwrapper.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: FetchSubTupleKernel_streamwrapper-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: FetchSubTupleKernel_streamwrapper -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/FlushLevelCounter_2.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: FlushLevelCounter_2-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: FlushLevelCounter_2 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/FillLevelCounter_1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: FillLevelCounter_1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: FillLevelCounter_1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/FillLevelCounter_0.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: FillLevelCounter_0-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: FillLevelCounter_0 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MappedRegBlock_b5497fa47497f5c6632937a587d5df01.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MappedRegBlock_b5497fa47497f5c6632937a587d5df01-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MappedRegBlock_b5497fa47497f5c6632937a587d5df01 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/FetchSubTupleKernel.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: FetchSubTupleKernel-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: FetchSubTupleKernel -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_EQ_48_0_UNSIGNED_48_0_UNSIGNED_growbits_pipe1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCFixed_EQ_48_0_UNSIGNED_48_0_UNSIGNED_growbits_pipe1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCFixed_EQ_48_0_UNSIGNED_48_0_UNSIGNED_growbits_pipe1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/StateMachineEntity_FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: StateMachineEntity_FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: StateMachineEntity_FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/OutputRegisterEntity_48with_reset.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: OutputRegisterEntity_48with_reset-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: OutputRegisterEntity_48with_reset -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PhotonMUX_1_2_64_nopipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PhotonMUX_1_2_64_nopipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PhotonMUX_1_2_64_nopipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_64x1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MultiStageDelay_64x1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MultiStageDelay_64x1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_64x1_reg1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SRLDelay_64x1_reg1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SRLDelay_64x1_reg1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PhotonBitwiseOp_1_Andnopipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PhotonBitwiseOp_1_Andnopipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PhotonBitwiseOp_1_Andnopipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_EQ_3_0_UNSIGNED_3_0_UNSIGNED_growbits_nopipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCFixed_EQ_3_0_UNSIGNED_3_0_UNSIGNED_growbits_nopipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCFixed_EQ_3_0_UNSIGNED_3_0_UNSIGNED_growbits_nopipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PhotonMUX_1_2_3_nopipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PhotonMUX_1_2_3_nopipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PhotonMUX_1_2_3_nopipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_3x4.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MultiStageDelay_3x4-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MultiStageDelay_3x4 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_3x4_reg1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SRLDelay_3x4_reg1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SRLDelay_3x4_reg1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/Pulse_cycles1_initT.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: Pulse_cycles1_initT-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: Pulse_cycles1_initT -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_1x4.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MultiStageDelay_1x4-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MultiStageDelay_1x4 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_1x4_reg1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SRLDelay_1x4_reg1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SRLDelay_1x4_reg1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_3x1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MultiStageDelay_3x1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MultiStageDelay_3x1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_3x1_reg1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SRLDelay_3x1_reg1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SRLDelay_3x1_reg1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_ADD_3_0_UNSIGNED_3_0_UNSIGNED_nogrowbits_nopipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCFixed_ADD_3_0_UNSIGNED_3_0_UNSIGNED_nogrowbits_nopipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCFixed_ADD_3_0_UNSIGNED_3_0_UNSIGNED_nogrowbits_nopipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_SUB_3_0_UNSIGNED_3_0_UNSIGNED_nogrowbits_nopipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCFixed_SUB_3_0_UNSIGNED_3_0_UNSIGNED_nogrowbits_nopipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCFixed_SUB_3_0_UNSIGNED_3_0_UNSIGNED_nogrowbits_nopipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/InputRegisterEntity2013_1536.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: InputRegisterEntity2013_1536-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: InputRegisterEntity2013_1536 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_1x4_reg2.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SRLDelay_1x4_reg2-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SRLDelay_1x4_reg2 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PhotonBitwiseNot_1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PhotonBitwiseNot_1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PhotonBitwiseNot_1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PhotonBitwiseOp_1_Andpipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PhotonBitwiseOp_1_Andpipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PhotonBitwiseOp_1_Andpipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_1x9.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MultiStageDelay_1x9-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MultiStageDelay_1x9 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_1x9_reg1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SRLDelay_1x9_reg1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SRLDelay_1x9_reg1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PhotonBitwiseOp_1_Orpipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PhotonBitwiseOp_1_Orpipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PhotonBitwiseOp_1_Orpipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_GT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCFixed_GT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCFixed_GT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_LT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCFixed_LT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCFixed_LT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PhotonMUX_1_2_1_pipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PhotonMUX_1_2_1_pipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PhotonMUX_1_2_1_pipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_LT_3_0_UNSIGNED_3_0_UNSIGNED_growbits_nopipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCFixed_LT_3_0_UNSIGNED_3_0_UNSIGNED_growbits_nopipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCFixed_LT_3_0_UNSIGNED_3_0_UNSIGNED_growbits_nopipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/WordLevelShifter_Left_Circular_1_24_5.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: WordLevelShifter_Left_Circular_1_24_5-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: WordLevelShifter_Left_Circular_1_24_5 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCSingleLUTConstDiv_n3_d3_quotient_remainder_lat0.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCSingleLUTConstDiv_n3_d3_quotient_remainder_lat0-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCSingleLUTConstDiv_n3_d3_quotient_remainder_lat0 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCSingleLUTConstDiv_n4_d3_quotient_remainder_lat0.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCSingleLUTConstDiv_n4_d3_quotient_remainder_lat0-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCSingleLUTConstDiv_n4_d3_quotient_remainder_lat0 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCSingleLUTConstDiv_n5_d3_quotient_remainder_lat0.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCSingleLUTConstDiv_n5_d3_quotient_remainder_lat0-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCSingleLUTConstDiv_n5_d3_quotient_remainder_lat0 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PhotonMUX_1_2_5_nopipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PhotonMUX_1_2_5_nopipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PhotonMUX_1_2_5_nopipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCDivMod_A6_B5_R6_Pipe1_Squash3ff0000000000000.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCDivMod_A6_B5_R6_Pipe1_Squash3ff0000000000000-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCDivMod_A6_B5_R6_Pipe1_Squash3ff0000000000000 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCIntegerDiv_Num6_Denom5_Skip0_Frac0_Rem_Pipe1_Squash3ff0000000000000.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCIntegerDiv_Num6_Denom5_Skip0_Frac0_Rem_Pipe1_Squash3ff0000000000000-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCIntegerDiv_Num6_Denom5_Skip0_Frac0_Rem_Pipe1_Squash3ff0000000000000 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_ADD_6_0_UNSIGNED_6_0_UNSIGNED_nogrowbits_nopipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCFixed_ADD_6_0_UNSIGNED_6_0_UNSIGNED_nogrowbits_nopipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCFixed_ADD_6_0_UNSIGNED_6_0_UNSIGNED_nogrowbits_nopipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixedCast_5_0_UNSIGNED_6_0_UNSIGNED_TONEAR_nopipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCFixedCast_5_0_UNSIGNED_6_0_UNSIGNED_TONEAR_nopipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCFixedCast_5_0_UNSIGNED_6_0_UNSIGNED_TONEAR_nopipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_5x1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MultiStageDelay_5x1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MultiStageDelay_5x1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_5x1_reg1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SRLDelay_5x1_reg1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SRLDelay_5x1_reg1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_LT_5_0_UNSIGNED_5_0_UNSIGNED_growbits_pipe1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCFixed_LT_5_0_UNSIGNED_5_0_UNSIGNED_growbits_pipe1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCFixed_LT_5_0_UNSIGNED_5_0_UNSIGNED_growbits_pipe1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixedCast_32_0_UNSIGNED_5_0_UNSIGNED_TONEAR_pipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MaxDCFixedCast_32_0_UNSIGNED_5_0_UNSIGNED_TONEAR_pipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MaxDCFixedCast_32_0_UNSIGNED_5_0_UNSIGNED_TONEAR_pipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/PhotonMUX_1_2_32_pipe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: PhotonMUX_1_2_32_pipe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: PhotonMUX_1_2_32_pipe -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/InputRegisterEntity2013_32.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: InputRegisterEntity2013_32-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: InputRegisterEntity2013_32 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_1x5.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MultiStageDelay_1x5-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MultiStageDelay_1x5 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_1x5_reg1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SRLDelay_1x5_reg1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SRLDelay_1x5_reg1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_1x1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MultiStageDelay_1x1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MultiStageDelay_1x1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_1x1_reg1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SRLDelay_1x1_reg1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SRLDelay_1x1_reg1 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/StateMachineEntity_FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: StateMachineEntity_FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: StateMachineEntity_FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MappedDRP_Addr_3c0000_ChecksumMappedDRP.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MappedDRP_Addr_3c0000_ChecksumMappedDRP-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MappedDRP_Addr_3c0000_ChecksumMappedDRP -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/ChecksumMappedDRP_RAM.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: ChecksumMappedDRP_RAM-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: ChecksumMappedDRP_RAM -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_1x2_reg1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SRLDelay_1x2_reg1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SRLDelay_1x2_reg1 -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0.vhdl(219) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/SignalForwardingEA.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: SignalForwardingEA-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: SignalForwardingEA -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/CommonPacketParser_SignalForwarding.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: CommonPacketParser_SignalForwarding-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: CommonPacketParser_SignalForwarding -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/ControlMux.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: ControlMux-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: ControlMux -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1.vhdl(328) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1 -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_36_512_36_dualclock_aclr.vhdl(110) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_36_512_36_dualclock_aclr.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_36_512_36_dualclock_aclr-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_36_512_36_dualclock_aclr -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_71_512_71_dualclock_aclr.vhdl(110) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_71_512_71_dualclock_aclr.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_71_512_71_dualclock_aclr-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: AlteraFifoEntity_71_512_71_dualclock_aclr -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MappedMemoriesEA.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MappedMemoriesEA-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MappedMemoriesEA -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/CommonPacketParser_MappedMemories.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: CommonPacketParser_MappedMemories-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: CommonPacketParser_MappedMemories -Tue 01:05: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../MappedRegistersController_48.vhdl(193) -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MappedRegistersController_48.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MappedRegistersController_48-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MappedRegistersController_48 -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MappedRegistersEA.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MappedRegistersEA-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MappedRegistersEA -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/CommonPacketParser_MappedRegisters.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: CommonPacketParser_MappedRegisters-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: CommonPacketParser_MappedRegisters -Tue 01:05: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe.vhdl -Tue 01:05: INFO : Info (12022): Found design unit 1: MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe-MaxDC -Tue 01:05: INFO : Info (12023): Found entity 1: MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe -Tue 01:05: INFO : Info (12127): Elaborating entity "MAX4MAIAPeripheryTop" for the top level hierarchy -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(541): object "pciebase_i_sim_pipe_rate" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(542): object "pciebase_i_sim_ltssmstate" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(543): object "pciebase_i_eidleinfersel0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(544): object "pciebase_i_eidleinfersel1" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(545): object "pciebase_i_eidleinfersel2" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(546): object "pciebase_i_eidleinfersel3" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(547): object "pciebase_i_eidleinfersel4" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(548): object "pciebase_i_eidleinfersel5" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(549): object "pciebase_i_eidleinfersel6" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(550): object "pciebase_i_eidleinfersel7" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(551): object "pciebase_i_powerdown0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(552): object "pciebase_i_powerdown1" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(553): object "pciebase_i_powerdown2" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(554): object "pciebase_i_powerdown3" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(555): object "pciebase_i_powerdown4" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(556): object "pciebase_i_powerdown5" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(557): object "pciebase_i_powerdown6" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(558): object "pciebase_i_powerdown7" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(559): object "pciebase_i_rxpolarity0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(560): object "pciebase_i_rxpolarity1" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(561): object "pciebase_i_rxpolarity2" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(562): object "pciebase_i_rxpolarity3" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(563): object "pciebase_i_rxpolarity4" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(564): object "pciebase_i_rxpolarity5" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(565): object "pciebase_i_rxpolarity6" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(566): object "pciebase_i_rxpolarity7" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(567): object "pciebase_i_txcompl0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(568): object "pciebase_i_txcompl1" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(569): object "pciebase_i_txcompl2" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(570): object "pciebase_i_txcompl3" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(571): object "pciebase_i_txcompl4" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(572): object "pciebase_i_txcompl5" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(573): object "pciebase_i_txcompl6" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(574): object "pciebase_i_txcompl7" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(575): object "pciebase_i_txdata0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(576): object "pciebase_i_txdata1" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(577): object "pciebase_i_txdata2" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(578): object "pciebase_i_txdata3" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(579): object "pciebase_i_txdata4" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(580): object "pciebase_i_txdata5" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(581): object "pciebase_i_txdata6" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(582): object "pciebase_i_txdata7" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(583): object "pciebase_i_txdatak0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(584): object "pciebase_i_txdatak1" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(585): object "pciebase_i_txdatak2" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(586): object "pciebase_i_txdatak3" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(587): object "pciebase_i_txdatak4" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(588): object "pciebase_i_txdatak5" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(589): object "pciebase_i_txdatak6" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(590): object "pciebase_i_txdatak7" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(591): object "pciebase_i_txdetectrx0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(592): object "pciebase_i_txdetectrx1" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(593): object "pciebase_i_txdetectrx2" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(594): object "pciebase_i_txdetectrx3" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(595): object "pciebase_i_txdetectrx4" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(596): object "pciebase_i_txdetectrx5" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(597): object "pciebase_i_txdetectrx6" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(598): object "pciebase_i_txdetectrx7" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(599): object "pciebase_i_txelecidle0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(600): object "pciebase_i_txelecidle1" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(601): object "pciebase_i_txelecidle2" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(602): object "pciebase_i_txelecidle3" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(603): object "pciebase_i_txelecidle4" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(604): object "pciebase_i_txelecidle5" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(605): object "pciebase_i_txelecidle6" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(606): object "pciebase_i_txelecidle7" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(607): object "pciebase_i_txdeemph0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(608): object "pciebase_i_txdeemph1" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(609): object "pciebase_i_txdeemph2" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(610): object "pciebase_i_txdeemph3" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(611): object "pciebase_i_txdeemph4" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(612): object "pciebase_i_txdeemph5" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(613): object "pciebase_i_txdeemph6" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(614): object "pciebase_i_txdeemph7" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(615): object "pciebase_i_txswing0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(616): object "pciebase_i_txswing1" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(617): object "pciebase_i_txswing2" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(618): object "pciebase_i_txswing3" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(619): object "pciebase_i_txswing4" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(620): object "pciebase_i_txswing5" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(621): object "pciebase_i_txswing6" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(622): object "pciebase_i_txswing7" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(623): object "pciebase_i_txmargin0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(624): object "pciebase_i_txmargin1" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(625): object "pciebase_i_txmargin2" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(626): object "pciebase_i_txmargin3" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(627): object "pciebase_i_txmargin4" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(628): object "pciebase_i_txmargin5" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(629): object "pciebase_i_txmargin6" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(630): object "pciebase_i_txmargin7" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(643): object "max4_cpld_top_level_qsfp_top_i2c_scl_fb" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(644): object "max4_cpld_top_level_qsfp_top_i2c_sda_fb" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(645): object "max4_cpld_top_level_qsfp_top_i2c_alert" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(646): object "max4_cpld_top_level_qsfp_top_i2c_modprsl" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(647): object "max4_cpld_top_level_qsfp_mid_i2c_scl_fb" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(648): object "max4_cpld_top_level_qsfp_mid_i2c_sda_fb" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(649): object "max4_cpld_top_level_qsfp_mid_i2c_alert" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(650): object "max4_cpld_top_level_qsfp_mid_i2c_modprsl" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(651): object "max4_cpld_top_level_qsfp_bot_i2c_scl_fb" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(652): object "max4_cpld_top_level_qsfp_bot_i2c_sda_fb" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(653): object "max4_cpld_top_level_qsfp_bot_i2c_alert" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(654): object "max4_cpld_top_level_qsfp_bot_i2c_modprsl" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "MAX4FPGATop" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(724): object "wrapper_pcie_pcie_control_sfh_done" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(726): object "wrapper_pcie_pcie_control_sth_stall" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(743): object "max4pcieslaveinterface_i_flush" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(745): object "max4pcieslaveinterface_i_soft_reset" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(746): object "max4pcieslaveinterface_i_throttle_limit" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(773): object "max4pcieslaveinterface_i_maxring_s_fh" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(774): object "max4pcieslaveinterface_i_maxring_s_set_highz_n" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(775): object "max4pcieslaveinterface_i_maxring_id_fh" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(776): object "max4pcieslaveinterface_i_maxring_id_set_highz_n" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(790): object "max4pcieslaveinterface_i_ptp_phy_sresetn" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(791): object "max4pcieslaveinterface_i_compl_fifo_flags" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(794): object "max4pcieslaveinterface_i_compute_reset_n" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(801): object "max4pcieslaveinterface_i_local_ifpga_session_key" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(907): object "ftb_archange_mappedelementsswitchpcieea_dbg_empty" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(908): object "ftb_archange_mappedelementsswitchpcieea_dbg_stall" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(911): object "ftb_archange_mappedelementsswitchpcieea_outputstream_push_done" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(914): object "ftb_mappedelementsswitchpcieea_full" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(916): object "ftb_mappedelementsswitchpcieea_wr_data_count" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "FPGAWrapperEntity_Manager_FetchSubTuple" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(631): object "inst_ln11_synchroniser_level_dst" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(632): object "inst_ln11_synchroniser1_level_dst" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(633): object "inst_ln11_synchroniser2_level_dst" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(645): object "inst_ln32_mappedclockcontrol_clkbuf_clksel0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(708): object "signalforwardingadapter_i_port_out_sysmon_reset" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(709): object "signalforwardingadapter_i_port_out_pcc_switch_regs" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(710): object "signalforwardingadapter_i_port_out_pcc_start" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(711): object "signalforwardingadapter_i_port_out_pcc_reset" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "basic_synchroniser" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|basic_synchroniser:inst_ln11_synchroniser" -Tue 01:05: INFO : Info (12128): Elaborating entity "basic_synchroniser_prim" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|basic_synchroniser:inst_ln11_synchroniser|basic_synchroniser_prim:\g_wide:0:g_width1:sync_level_src" -Tue 01:05: INFO : Warning (10542): VHDL Variable Declaration warning at basic_synchroniser.vhd(67): used initial value expression for variable "n" because variable was never assigned a value -Tue 01:05: INFO : Info (12128): Elaborating entity "dff_ce_asyncsr" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|basic_synchroniser:inst_ln11_synchroniser|basic_synchroniser_prim:\g_wide:0:g_width1:sync_level_src|dff_ce_asyncsr:\g_slice_packing:0:i_sync0" -Tue 01:05: INFO : Info (12128): Elaborating entity "LPM_FF" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|basic_synchroniser:inst_ln11_synchroniser|basic_synchroniser_prim:\g_wide:0:g_width1:sync_level_src|dff_ce_asyncsr:\g_slice_packing:0:i_sync0|LPM_FF:dff" -Tue 01:05: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|basic_synchroniser:inst_ln11_synchroniser|basic_synchroniser_prim:\g_wide:0:g_width1:sync_level_src|dff_ce_asyncsr:\g_slice_packing:0:i_sync0|LPM_FF:dff" -Tue 01:05: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|basic_synchroniser:inst_ln11_synchroniser|basic_synchroniser_prim:\g_wide:0:g_width1:sync_level_src|dff_ce_asyncsr:\g_slice_packing:0:i_sync0|LPM_FF:dff" with the following parameter: -Tue 01:05: INFO : Info (12134): Parameter "LPM_WIDTH" = "1" -Tue 01:05: INFO : Info (12134): Parameter "LPM_AVALUE" = "UNUSED" -Tue 01:05: INFO : Info (12134): Parameter "LPM_SVALUE" = "UNUSED" -Tue 01:05: INFO : Info (12134): Parameter "LPM_PVALUE" = "UNUSED" -Tue 01:05: INFO : Info (12134): Parameter "LPM_FFTYPE" = "DFF" -Tue 01:05: INFO : Info (12134): Parameter "LPM_TYPE" = "DFF" -Tue 01:05: INFO : Info (12134): Parameter "LPM_HINT" = "UNUSED" -Tue 01:05: INFO : Info (12128): Elaborating entity "SanityBlock_cclk_STREAM_clk_pcie" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SanityBlock_cclk_STREAM_clk_pcie:SanityBlock_i" -Tue 01:05: INFO : Info (12128): Elaborating entity "MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SanityBlock_cclk_STREAM_clk_pcie:SanityBlock_i|MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c:MappedRegBlock_i" -Tue 01:05: INFO : Info (12128): Elaborating entity "mapped_register_readable" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SanityBlock_cclk_STREAM_clk_pcie:SanityBlock_i|MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c:MappedRegBlock_i|mapped_register_readable:inst_ln484_mappedregblock" -Tue 01:05: INFO : Info (12128): Elaborating entity "mapped_register_readable" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SanityBlock_cclk_STREAM_clk_pcie:SanityBlock_i|MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c:MappedRegBlock_i|mapped_register_readable:inst_ln484_mappedregblock3" -Tue 01:05: INFO : Warning (10445): VHDL Subtype or Type Declaration warning at mapped_register_readable.vhd(74): subtype or type has null range -Tue 01:05: INFO : Info (12128): Elaborating entity "MappedClockControl_id_3e" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedClockControl_id_3e:inst_ln32_mappedclockcontrol" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedClockControl_id_3e.vhdl(145): object "inst_ln200_mappedclockcontrol_cc_reg_pll_ce" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "stream_clkprim_lock_count_32" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedClockControl_id_3e:inst_ln32_mappedclockcontrol|stream_clkprim_lock_count_32:inst_ln16_plllockinstrumentation" -Tue 01:05: INFO : Info (12128): Elaborating entity "mapped_clock_control" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedClockControl_id_3e:inst_ln32_mappedclockcontrol|mapped_clock_control:inst_ln200_mappedclockcontrol" -Tue 01:05: INFO : Info (12128): Elaborating entity "reset_control" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|reset_control:inst_ln21_resetcontrol" -Tue 01:05: INFO : Info (12128): Elaborating entity "MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe:MappedElementSwitch_i" -Tue 01:05: INFO : Info (12128): Elaborating entity "mapped_element_switch" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe:MappedElementSwitch_i|mapped_element_switch:MappedElementSwitchExternal_i" -Tue 01:05: INFO : Info (12128): Elaborating entity "mec_switch_arbiter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe:MappedElementSwitch_i|mapped_element_switch:MappedElementSwitchExternal_i|mec_switch_arbiter:request_source_arbiter" -Tue 01:05: INFO : Info (12128): Elaborating entity "src_to_dst_control" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe:MappedElementSwitch_i|mapped_element_switch:MappedElementSwitchExternal_i|src_to_dst_control:request_source_control" -Tue 01:05: INFO : Info (12128): Elaborating entity "MappedRegistersController_48" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedRegistersController_48:MappedRegistersController_i" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedRegistersController_48.vhdl(168): object "mappedregistersea_i_reserved_0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedRegistersController_48.vhdl(170): object "mappedregistersea_i_is_response_header" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedRegistersController_48.vhdl(172): object "mappedregistersea_i_reserved_1" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "MappedRegistersEA" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedRegistersController_48:MappedRegistersController_i|MappedRegistersEA:MappedRegistersEA_i" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedRegistersEA.vhdl(148): object "commonpacketparser_i_ea_manual_rdy" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "CommonPacketParser_MappedRegisters" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedRegistersController_48:MappedRegistersController_i|MappedRegistersEA:MappedRegistersEA_i|CommonPacketParser_MappedRegisters:CommonPacketParser_i" -Tue 01:05: INFO : Info (12128): Elaborating entity "common_packet_parser" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedRegistersController_48:MappedRegistersController_i|MappedRegistersEA:MappedRegistersEA_i|CommonPacketParser_MappedRegisters:CommonPacketParser_i|common_packet_parser:CommonPacketParserExternal_MappedRegisters" -Tue 01:05: INFO : Info (12128): Elaborating entity "ControlMux" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedRegistersController_48:MappedRegistersController_i|MappedRegistersEA:MappedRegistersEA_i|CommonPacketParser_MappedRegisters:CommonPacketParser_i|ControlMux:control_mux" -Tue 01:05: INFO : Info (12128): Elaborating entity "mapped_registers_controller" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedRegistersController_48:MappedRegistersController_i|mapped_registers_controller:MappedRegistersControllerExternal_i" -Tue 01:05: INFO : Info (12128): Elaborating entity "MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1.vhdl(261): object "mappedmemoriesea_i_reserved_0" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1.vhdl(264): object "mappedmemoriesea_i_is_response_header" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "mapped_memories_controller_core" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|mapped_memories_controller_core:MappedMemoriesControllerCoreExternal_i" -Tue 01:05: INFO : Info (12128): Elaborating entity "MappedMemoriesEA" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|MappedMemoriesEA:MappedmemoriesEA_i" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedMemoriesEA.vhdl(150): object "commonpacketparser_i_ea_manual_rdy" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "CommonPacketParser_MappedMemories" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|MappedMemoriesEA:MappedmemoriesEA_i|CommonPacketParser_MappedMemories:CommonPacketParser_i" -Tue 01:05: INFO : Info (12128): Elaborating entity "mapped_memories_adapter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|mapped_memories_adapter:mapped_memories_domain_adapter_drp" -Tue 01:05: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_71_512_71_dualclock_aclr" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp" -Tue 01:05: INFO : Info (12128): Elaborating entity "dcfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo" -Tue 01:05: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo" -Tue 01:05: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo" with the following parameter: -Tue 01:05: INFO : Info (12134): Parameter "lpm_width" = "71" -Tue 01:05: INFO : Info (12134): Parameter "lpm_widthu" = "9" -Tue 01:05: INFO : Info (12134): Parameter "lpm_numwords" = "512" -Tue 01:05: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:05: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" -Tue 01:05: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:05: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:05: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:05: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:05: INFO : Info (12134): Parameter "delay_rdusedw" = "1" -Tue 01:05: INFO : Info (12134): Parameter "delay_wrusedw" = "1" -Tue 01:05: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" -Tue 01:05: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" -Tue 01:05: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" -Tue 01:05: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" -Tue 01:05: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_cu42.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: dcfifo_cu42 -Tue 01:05: INFO : Info (12128): Elaborating entity "dcfifo_cu42" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_p07.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: a_graycounter_p07 -Tue 01:05: INFO : Info (12128): Elaborating entity "a_graycounter_p07" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|a_graycounter_p07:rdptr_g1p" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_lec.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: a_graycounter_lec -Tue 01:05: INFO : Info (12128): Elaborating entity "a_graycounter_lec" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|a_graycounter_lec:wrptr_g1p" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_88e1.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: altsyncram_88e1 -Tue 01:05: INFO : Info (12128): Elaborating entity "altsyncram_88e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_qld.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: alt_synch_pipe_qld -Tue 01:05: INFO : Info (12128): Elaborating entity "alt_synch_pipe_qld" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|alt_synch_pipe_qld:rs_dgwp" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: dffpipe_pe9 -Tue 01:05: INFO : Info (12128): Elaborating entity "dffpipe_pe9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe12" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: alt_synch_pipe_rld -Tue 01:05: INFO : Info (12128): Elaborating entity "alt_synch_pipe_rld" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|alt_synch_pipe_rld:ws_dgrp" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: dffpipe_qe9 -Tue 01:05: INFO : Info (12128): Elaborating entity "dffpipe_qe9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe15" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_b16.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: cmpr_b16 -Tue 01:05: INFO : Info (12128): Elaborating entity "cmpr_b16" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|cmpr_b16:rdempty_eq_comp" -Tue 01:05: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_36_512_36_dualclock_aclr" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp" -Tue 01:05: INFO : Info (12128): Elaborating entity "dcfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo" -Tue 01:05: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo" -Tue 01:05: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo" with the following parameter: -Tue 01:05: INFO : Info (12134): Parameter "lpm_width" = "36" -Tue 01:05: INFO : Info (12134): Parameter "lpm_widthu" = "9" -Tue 01:05: INFO : Info (12134): Parameter "lpm_numwords" = "512" -Tue 01:05: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:05: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" -Tue 01:05: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:05: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:05: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:05: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:05: INFO : Info (12134): Parameter "delay_rdusedw" = "1" -Tue 01:05: INFO : Info (12134): Parameter "delay_wrusedw" = "1" -Tue 01:05: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" -Tue 01:05: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" -Tue 01:05: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" -Tue 01:05: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" -Tue 01:05: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_eu42.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: dcfifo_eu42 -Tue 01:05: INFO : Info (12128): Elaborating entity "dcfifo_eu42" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_eu42:auto_generated" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_a8e1.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: altsyncram_a8e1 -Tue 01:05: INFO : Info (12128): Elaborating entity "altsyncram_a8e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_eu42:auto_generated|altsyncram_a8e1:fifo_ram" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_sld.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: alt_synch_pipe_sld -Tue 01:05: INFO : Info (12128): Elaborating entity "alt_synch_pipe_sld" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_eu42:auto_generated|alt_synch_pipe_sld:rs_dgwp" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_re9.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: dffpipe_re9 -Tue 01:05: INFO : Info (12128): Elaborating entity "dffpipe_re9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_eu42:auto_generated|alt_synch_pipe_sld:rs_dgwp|dffpipe_re9:dffpipe6" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_tld.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: alt_synch_pipe_tld -Tue 01:05: INFO : Info (12128): Elaborating entity "alt_synch_pipe_tld" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_eu42:auto_generated|alt_synch_pipe_tld:ws_dgrp" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_se9.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: dffpipe_se9 -Tue 01:05: INFO : Info (12128): Elaborating entity "dffpipe_se9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_eu42:auto_generated|alt_synch_pipe_tld:ws_dgrp|dffpipe_se9:dffpipe9" -Tue 01:05: INFO : Info (12128): Elaborating entity "SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0.vhdl(194): object "signalforwardingea_i_is_response_header" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "SignalForwardingEA" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|SignalForwardingEA:SignalForwardingEA_i" -Tue 01:05: INFO : Info (12128): Elaborating entity "CommonPacketParser_SignalForwarding" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|SignalForwardingEA:SignalForwardingEA_i|CommonPacketParser_SignalForwarding:CommonPacketParser_i" -Tue 01:05: INFO : Info (12128): Elaborating entity "common_packet_parser" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|SignalForwardingEA:SignalForwardingEA_i|CommonPacketParser_SignalForwarding:CommonPacketParser_i|common_packet_parser:CommonPacketParserExternal_SignalForwarding" -Tue 01:05: INFO : Info (12128): Elaborating entity "MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830:inst_ln130_mappedregblock" -Tue 01:05: INFO : Info (12128): Elaborating entity "mapped_register" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830:inst_ln130_mappedregblock|mapped_register:inst_ln504_mappedregblock" -Tue 01:05: INFO : Info (12128): Elaborating entity "signal_forwarding_adapter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|signal_forwarding_adapter:SignalForwardingAdapterExternal_i" -Tue 01:05: INFO : Info (12128): Elaborating entity "MappedDRP_Addr_3c0000_ChecksumMappedDRP" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp" -Tue 01:05: INFO : Info (12128): Elaborating entity "ChecksumMappedDRP_RAM" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i" -Tue 01:05: INFO : Info (12128): Elaborating entity "SRLDelay_1x2_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i|SRLDelay_1x2_reg1:rd_delay" -Tue 01:05: INFO : Info (12128): Elaborating entity "SimpleSR" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i|SRLDelay_1x2_reg1:rd_delay|SimpleSR:inst_ln25_alterasrldelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i|altsyncram:checksum_mem" -Tue 01:05: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i|altsyncram:checksum_mem" -Tue 01:05: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i|altsyncram:checksum_mem" with the following parameter: -Tue 01:05: INFO : Info (12134): Parameter "address_aclr_a" = "UNUSED" -Tue 01:05: INFO : Info (12134): Parameter "address_aclr_b" = "NONE" -Tue 01:05: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" -Tue 01:05: INFO : Info (12134): Parameter "byte_size" = "8" -Tue 01:05: INFO : Info (12134): Parameter "byteena_aclr_a" = "UNUSED" -Tue 01:05: INFO : Info (12134): Parameter "byteena_aclr_b" = "NONE" -Tue 01:05: INFO : Info (12134): Parameter "byteena_reg_b" = "CLOCK1" -Tue 01:05: INFO : Info (12134): Parameter "clock_enable_core_a" = "USE_INPUT_CLKEN" -Tue 01:05: INFO : Info (12134): Parameter "clock_enable_core_b" = "USE_INPUT_CLKEN" -Tue 01:05: INFO : Info (12134): Parameter "clock_enable_input_a" = "BYPASS" -Tue 01:05: INFO : Info (12134): Parameter "clock_enable_input_b" = "BYPASS" -Tue 01:05: INFO : Info (12134): Parameter "clock_enable_output_a" = "BYPASS" -Tue 01:05: INFO : Info (12134): Parameter "clock_enable_output_b" = "BYPASS" -Tue 01:05: INFO : Info (12134): Parameter "intended_device_family" = "stratixv" -Tue 01:05: INFO : Info (12134): Parameter "ecc_pipeline_stage_enabled" = "FALSE" -Tue 01:05: INFO : Info (12134): Parameter "enable_ecc" = "FALSE" -Tue 01:05: INFO : Info (12134): Parameter "implement_in_les" = "OFF" -Tue 01:05: INFO : Info (12134): Parameter "indata_aclr_a" = "UNUSED" -Tue 01:05: INFO : Info (12134): Parameter "indata_aclr_b" = "NONE" -Tue 01:05: INFO : Info (12134): Parameter "indata_reg_b" = "CLOCK0" -Tue 01:05: INFO : Info (12134): Parameter "init_file" = "32x512_ROM_SINGLE_PORT_ireg_checksum.mif" -Tue 01:05: INFO : Info (12134): Parameter "init_file_layout" = "PORT_A" -Tue 01:05: INFO : Info (12134): Parameter "maximum_depth" = "0" -Tue 01:05: INFO : Info (12134): Parameter "numwords_a" = "512" -Tue 01:05: INFO : Info (12134): Parameter "numwords_b" = "0" -Tue 01:05: INFO : Info (12134): Parameter "operation_mode" = "ROM" -Tue 01:05: INFO : Info (12134): Parameter "outdata_aclr_a" = "NONE" -Tue 01:05: INFO : Info (12134): Parameter "outdata_aclr_b" = "NONE" -Tue 01:05: INFO : Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" -Tue 01:05: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" -Tue 01:05: INFO : Info (12134): Parameter "power_up_uninitialized" = "FALSE" -Tue 01:05: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" -Tue 01:05: INFO : Info (12134): Parameter "rdcontrol_aclr_b" = "NONE" -Tue 01:05: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK1" -Tue 01:05: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" -Tue 01:05: INFO : Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" -Tue 01:05: INFO : Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" -Tue 01:05: INFO : Info (12134): Parameter "stratixiv_m144k_allow_dual_clocks" = "ON" -Tue 01:05: INFO : Info (12134): Parameter "width_a" = "32" -Tue 01:05: INFO : Info (12134): Parameter "width_b" = "1" -Tue 01:05: INFO : Info (12134): Parameter "width_byteena_a" = "1" -Tue 01:05: INFO : Info (12134): Parameter "width_byteena_b" = "1" -Tue 01:05: INFO : Info (12134): Parameter "width_eccstatus" = "3" -Tue 01:05: INFO : Info (12134): Parameter "widthad_a" = "9" -Tue 01:05: INFO : Info (12134): Parameter "widthad_b" = "1" -Tue 01:05: INFO : Info (12134): Parameter "wrcontrol_aclr_a" = "UNUSED" -Tue 01:05: INFO : Info (12134): Parameter "wrcontrol_aclr_b" = "NONE" -Tue 01:05: INFO : Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" -Tue 01:05: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" -Tue 01:05: INFO : Info (12134): Parameter "lpm_type" = "altsyncram" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_8754.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: altsyncram_8754 -Tue 01:05: INFO : Info (12128): Elaborating entity "altsyncram_8754" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i|altsyncram:checksum_mem|altsyncram_8754:auto_generated" -Tue 01:05: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity" -Tue 01:05: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel" -Tue 01:05: INFO : Info (12128): Elaborating entity "FetchSubTupleKernel_streamwrapper" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_streamwrapper.vhdl(277): object "fetchsubtuplekernel_core_output_output_control" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_streamwrapper.vhdl(289): object "control_sm_pcc_finished" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_streamwrapper.vhdl(301): object "control_sm_next_flush_level" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "FetchSubTupleKernel" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel.vhdl(449): object "node_id2_nodecounterv1_wrap" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel.vhdl(538): object "node_id93_nodedivmod_quotient" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel.vhdl(3535): object "node_id2844_nodecounterv1_wrap" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel.vhdl(3542): object "node_id2850_nodecounterv1_wrap" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "PhotonBitwiseNot_1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonBitwiseNot_1:node_id2792_nodenot" -Tue 01:05: INFO : Info (12128): Elaborating entity "StateMachineEntity_FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|StateMachineEntity_FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33:node_id2_nodecounterv1" -Tue 01:05: INFO : Info (12128): Elaborating entity "FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|StateMachineEntity_FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33:node_id2_nodecounterv1|FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33:inst_ln165_statemachineentitycore" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33.vhdl(258): object "dummy_sensitivity_signal_output_function" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33.vhdl(259): object "dummy_sensitivity_signal_nextstate_function" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "dff_ce_syncsr" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|dff_ce_syncsr:node_id2_nodecounterv1_ce_pipereg_inst_0" -Tue 01:05: INFO : Info (12128): Elaborating entity "LPM_FF" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|dff_ce_syncsr:node_id2_nodecounterv1_ce_pipereg_inst_0|LPM_FF:dff" -Tue 01:05: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|dff_ce_syncsr:node_id2_nodecounterv1_ce_pipereg_inst_0|LPM_FF:dff" -Tue 01:05: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|dff_ce_syncsr:node_id2_nodecounterv1_ce_pipereg_inst_0|LPM_FF:dff" with the following parameter: -Tue 01:05: INFO : Info (12134): Parameter "LPM_WIDTH" = "1" -Tue 01:05: INFO : Info (12134): Parameter "LPM_AVALUE" = "UNUSED" -Tue 01:05: INFO : Info (12134): Parameter "LPM_SVALUE" = "UNUSED" -Tue 01:05: INFO : Info (12134): Parameter "LPM_PVALUE" = "UNUSED" -Tue 01:05: INFO : Info (12134): Parameter "LPM_FFTYPE" = "DFF" -Tue 01:05: INFO : Info (12134): Parameter "LPM_TYPE" = "LPM_FF" -Tue 01:05: INFO : Info (12134): Parameter "LPM_HINT" = "UNUSED" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCFixed_LT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_LT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1:node_id4_nodelt" -Tue 01:05: INFO : Info (12128): Elaborating entity "MultiStageDelay_1x1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x1:node_id2854_nodefifo" -Tue 01:05: INFO : Info (12128): Elaborating entity "SRLDelay_1x1_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x1:node_id2854_nodefifo|SRLDelay_1x1_reg1:SRLDelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCFixed_GT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_GT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1:node_id16_nodegt" -Tue 01:05: INFO : Info (12128): Elaborating entity "PhotonBitwiseOp_1_Orpipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonBitwiseOp_1_Orpipe:node_id17_nodeor" -Tue 01:05: INFO : Info (12128): Elaborating entity "PhotonBitwiseOp_1_Andpipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonBitwiseOp_1_Andpipe:node_id18_nodeand" -Tue 01:05: INFO : Info (12128): Elaborating entity "MultiStageDelay_1x5" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x5:node_id2855_nodefifo" -Tue 01:05: INFO : Info (12128): Elaborating entity "SRLDelay_1x5_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x5:node_id2855_nodefifo|SRLDelay_1x5_reg1:SRLDelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "SimpleSR" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x5:node_id2855_nodefifo|SRLDelay_1x5_reg1:SRLDelay|SimpleSR:inst_ln25_alterasrldelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "PhotonBitwiseOp_1_Andnopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonBitwiseOp_1_Andnopipe:node_id79_nodeand" -Tue 01:05: INFO : Info (12128): Elaborating entity "SRLDelay_1x4_reg2" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|SRLDelay_1x4_reg2:inst_ln49_alterasrldelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "SimpleSR" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|SRLDelay_1x4_reg2:inst_ln49_alterasrldelay|SimpleSR:inst_ln25_alterasrldelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "InputRegisterEntity2013_32" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|InputRegisterEntity2013_32:node_id80_nodeinput_sizessizes_data0_reg" -Tue 01:05: INFO : Info (12128): Elaborating entity "PhotonMUX_1_2_32_pipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonMUX_1_2_32_pipe:node_id82_nodemux" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCFixedCast_32_0_UNSIGNED_5_0_UNSIGNED_TONEAR_pipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixedCast_32_0_UNSIGNED_5_0_UNSIGNED_TONEAR_pipe:node_id83_nodecast" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCFixed_LT_5_0_UNSIGNED_5_0_UNSIGNED_growbits_pipe1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_LT_5_0_UNSIGNED_5_0_UNSIGNED_growbits_pipe1:node_id142_nodelt" -Tue 01:05: INFO : Info (12128): Elaborating entity "Pulse_cycles1_initT" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|Pulse_cycles1_initT:node_id85_nodepulse" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCFixedCast_5_0_UNSIGNED_6_0_UNSIGNED_TONEAR_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixedCast_5_0_UNSIGNED_6_0_UNSIGNED_TONEAR_nopipe:node_id89_nodecast" -Tue 01:05: INFO : Info (12128): Elaborating entity "MultiStageDelay_5x1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_5x1:node_id2856_nodefifo" -Tue 01:05: INFO : Info (12128): Elaborating entity "SRLDelay_5x1_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_5x1:node_id2856_nodefifo|SRLDelay_5x1_reg1:SRLDelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCFixed_ADD_6_0_UNSIGNED_6_0_UNSIGNED_nogrowbits_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_ADD_6_0_UNSIGNED_6_0_UNSIGNED_nogrowbits_nopipe:node_id91_nodeadd" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCDivMod_A6_B5_R6_Pipe1_Squash3ff0000000000000" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCDivMod_A6_B5_R6_Pipe1_Squash3ff0000000000000:node_id93_nodedivmod" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCIntegerDiv_Num6_Denom5_Skip0_Frac0_Rem_Pipe1_Squash3ff0000000000000" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCDivMod_A6_B5_R6_Pipe1_Squash3ff0000000000000:node_id93_nodedivmod|MaxDCIntegerDiv_Num6_Denom5_Skip0_Frac0_Rem_Pipe1_Squash3ff0000000000000:inst_ln49_maxdcintegerdiv" -Tue 01:05: INFO : Info (12128): Elaborating entity "ConditionalAddSubtract" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCDivMod_A6_B5_R6_Pipe1_Squash3ff0000000000000:node_id93_nodedivmod|MaxDCIntegerDiv_Num6_Denom5_Skip0_Frac0_Rem_Pipe1_Squash3ff0000000000000:inst_ln49_maxdcintegerdiv|ConditionalAddSubtract:inst_ln20_condaddsub" -Tue 01:05: INFO : Info (12128): Elaborating entity "ConditionalAddSubtract" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCDivMod_A6_B5_R6_Pipe1_Squash3ff0000000000000:node_id93_nodedivmod|MaxDCIntegerDiv_Num6_Denom5_Skip0_Frac0_Rem_Pipe1_Squash3ff0000000000000:inst_ln49_maxdcintegerdiv|ConditionalAddSubtract:inst_ln20_condaddsub5" -Tue 01:05: INFO : Info (12128): Elaborating entity "PhotonMUX_1_2_5_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonMUX_1_2_5_nopipe:node_id88_nodemux" -Tue 01:05: INFO : Info (12128): Elaborating entity "WordLevelShifter_Left_Circular_1_24_5" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_24_5:node_id143_nodewordlevelshift" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at WordLevelShifter_Left_Circular_1_24_5.vhdl(101): object "inst_ln23_maxdcsinglelutconstdiv2_quotient" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCSingleLUTConstDiv_n5_d3_quotient_remainder_lat0" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_24_5:node_id143_nodewordlevelshift|MaxDCSingleLUTConstDiv_n5_d3_quotient_remainder_lat0:inst_ln23_maxdcsinglelutconstdiv" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCSingleLUTConstDiv_n4_d3_quotient_remainder_lat0" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_24_5:node_id143_nodewordlevelshift|MaxDCSingleLUTConstDiv_n4_d3_quotient_remainder_lat0:inst_ln23_maxdcsinglelutconstdiv1" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCSingleLUTConstDiv_n3_d3_quotient_remainder_lat0" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_24_5:node_id143_nodewordlevelshift|MaxDCSingleLUTConstDiv_n3_d3_quotient_remainder_lat0:inst_ln23_maxdcsinglelutconstdiv2" -Tue 01:05: INFO : Info (12128): Elaborating entity "MultiStageDelay_1x4" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x4:node_id2857_nodefifo" -Tue 01:05: INFO : Info (12128): Elaborating entity "SRLDelay_1x4_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x4:node_id2857_nodefifo|SRLDelay_1x4_reg1:SRLDelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "MultiStageDelay_3x1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_3x1:node_id2858_nodefifo" -Tue 01:05: INFO : Info (12128): Elaborating entity "SRLDelay_3x1_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_3x1:node_id2858_nodefifo|SRLDelay_3x1_reg1:SRLDelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "PhotonMUX_1_2_3_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonMUX_1_2_3_nopipe:node_id250_nodemux" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCFixed_SUB_3_0_UNSIGNED_3_0_UNSIGNED_nogrowbits_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_SUB_3_0_UNSIGNED_3_0_UNSIGNED_nogrowbits_nopipe:node_id255_nodesub" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCFixed_ADD_3_0_UNSIGNED_3_0_UNSIGNED_nogrowbits_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_ADD_3_0_UNSIGNED_3_0_UNSIGNED_nogrowbits_nopipe:node_id252_nodeadd" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCFixed_LT_3_0_UNSIGNED_3_0_UNSIGNED_growbits_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_LT_3_0_UNSIGNED_3_0_UNSIGNED_growbits_nopipe:node_id245_nodelt" -Tue 01:05: INFO : Info (12128): Elaborating entity "PhotonMUX_1_2_1_pipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonMUX_1_2_1_pipe:node_id23_nodemux" -Tue 01:05: INFO : Info (12128): Elaborating entity "MultiStageDelay_1x9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x9:node_id2860_nodefifo" -Tue 01:05: INFO : Info (12128): Elaborating entity "SRLDelay_1x9_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x9:node_id2860_nodefifo|SRLDelay_1x9_reg1:SRLDelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "SimpleSR" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x9:node_id2860_nodefifo|SRLDelay_1x9_reg1:SRLDelay|SimpleSR:inst_ln25_alterasrldelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCFixed_EQ_3_0_UNSIGNED_3_0_UNSIGNED_growbits_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_EQ_3_0_UNSIGNED_3_0_UNSIGNED_growbits_nopipe:node_id2702_nodeeq" -Tue 01:05: INFO : Info (12128): Elaborating entity "InputRegisterEntity2013_1536" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|InputRegisterEntity2013_1536:node_id28_nodeinput_inputinput_data0_reg" -Tue 01:05: INFO : Info (12128): Elaborating entity "PhotonMUX_1_2_64_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonMUX_1_2_64_nopipe:node_id2712_nodemux" -Tue 01:05: INFO : Info (12128): Elaborating entity "MultiStageDelay_64x1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_64x1:node_id2887_nodefifo" -Tue 01:05: INFO : Info (12128): Elaborating entity "SRLDelay_64x1_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_64x1:node_id2887_nodefifo|SRLDelay_64x1_reg1:SRLDelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "MultiStageDelay_3x4" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_3x4:node_id3714_nodefifo" -Tue 01:05: INFO : Info (12128): Elaborating entity "SRLDelay_3x4_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_3x4:node_id3714_nodefifo|SRLDelay_3x4_reg1:SRLDelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "SimpleSR" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_3x4:node_id3714_nodefifo|SRLDelay_3x4_reg1:SRLDelay|SimpleSR:inst_ln25_alterasrldelay" -Tue 01:05: INFO : Info (12128): Elaborating entity "StateMachineEntity_FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|StateMachineEntity_FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49:node_id2844_nodecounterv1" -Tue 01:05: INFO : Info (12128): Elaborating entity "FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|StateMachineEntity_FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49:node_id2844_nodecounterv1|FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49:inst_ln165_statemachineentitycore" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49.vhdl(258): object "dummy_sensitivity_signal_output_function" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49.vhdl(259): object "dummy_sensitivity_signal_nextstate_function" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "OutputRegisterEntity_48with_reset" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|OutputRegisterEntity_48with_reset:node_id2847current_run_cycle_count_reg" -Tue 01:05: INFO : Info (12128): Elaborating entity "MaxDCFixed_EQ_48_0_UNSIGNED_48_0_UNSIGNED_growbits_pipe1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_EQ_48_0_UNSIGNED_48_0_UNSIGNED_growbits_pipe1:node_id2853_nodeeq" -Tue 01:05: INFO : Info (12128): Elaborating entity "MappedRegBlock_b5497fa47497f5c6632937a587d5df01" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|MappedRegBlock_b5497fa47497f5c6632937a587d5df01:mapped_reg_block" -Tue 01:05: INFO : Info (12128): Elaborating entity "mapped_register" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|MappedRegBlock_b5497fa47497f5c6632937a587d5df01:mapped_reg_block|mapped_register:inst_ln504_mappedregblock" -Tue 01:05: INFO : Warning (10445): VHDL Subtype or Type Declaration warning at mapped_register.vhd(56): subtype or type has null range -Tue 01:05: INFO : Info (12128): Elaborating entity "mapped_register" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|MappedRegBlock_b5497fa47497f5c6632937a587d5df01:mapped_reg_block|mapped_register:inst_ln504_mappedregblock3" -Tue 01:05: INFO : Info (12128): Elaborating entity "mapped_register_readable" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|MappedRegBlock_b5497fa47497f5c6632937a587d5df01:mapped_reg_block|mapped_register_readable:inst_ln484_mappedregblock1" -Tue 01:05: INFO : Info (12128): Elaborating entity "dff_ce_syncsr_ne" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|dff_ce_syncsr_ne:inst_ln44_alteraflipflops" -Tue 01:05: INFO : Info (12128): Elaborating entity "PhotonDesignControl" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|PhotonDesignControl:control_sm" -Tue 01:05: INFO : Info (12128): Elaborating entity "FillLevelCounter_0" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FillLevelCounter_0:ce_fill_0_0_pdc0" -Tue 01:05: INFO : Info (12128): Elaborating entity "FillLevelCounter_1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FillLevelCounter_1:ce_fill_0_1_pdc0" -Tue 01:05: INFO : Info (12128): Elaborating entity "FlushLevelCounter_2" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FlushLevelCounter_2:ce_flush_0_2_pdc0" -Tue 01:05: INFO : Info (12128): Elaborating entity "level_synchroniser" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|level_synchroniser:inst_ln11_synchroniser" -Tue 01:05: INFO : Info (12128): Elaborating entity "level_synchroniser_prim" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|level_synchroniser:inst_ln11_synchroniser|level_synchroniser_prim:\g_wide:0:g_width1:sync_level_src" -Tue 01:05: INFO : Warning (10542): VHDL Variable Declaration warning at level_synchroniser.vhd(71): used initial value expression for variable "n" because variable was never assigned a value -Tue 01:05: INFO : Info (12128): Elaborating entity "WrapperNodeIO_input" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|WrapperNodeIO_input:input" -Tue 01:05: INFO : Info (12128): Elaborating entity "WrapperNodeIO_sizes" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|WrapperNodeIO_sizes:sizes" -Tue 01:05: INFO : Info (12128): Elaborating entity "WrapperNodeIO_output" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|WrapperNodeIO_output:output" -Tue 01:05: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_1:Stream_1" -Tue 01:05: INFO : Info (12128): Elaborating entity "DualAspectReg_128_1536" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_1:Stream_1|DualAspectReg_128_1536:inst_ln31_streamingblock" -Tue 01:05: INFO : Info (12128): Elaborating entity "dualaspectreg_int" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_1:Stream_1|DualAspectReg_128_1536:inst_ln31_streamingblock|dualaspectreg_int:inst_ln126_dualaspectreg" -Tue 01:05: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_4" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_4:Stream_4" -Tue 01:05: INFO : Info (12128): Elaborating entity "DualAspectMux_128_32_COUNTER_PIPELINED" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_4:Stream_4|DualAspectMux_128_32_COUNTER_PIPELINED:inst_ln31_streamingblock" -Tue 01:05: INFO : Info (12128): Elaborating entity "DualAspectCounterPipelined_32_128" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_4:Stream_4|DualAspectMux_128_32_COUNTER_PIPELINED:inst_ln31_streamingblock|DualAspectCounterPipelined_32_128:inst_ln31_dualaspectcounterpipelined" -Tue 01:05: INFO : Info (12128): Elaborating entity "dualaspectmuxpipe_counter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_4:Stream_4|DualAspectMux_128_32_COUNTER_PIPELINED:inst_ln31_streamingblock|DualAspectCounterPipelined_32_128:inst_ln31_dualaspectcounterpipelined|dualaspectmuxpipe_counter:inst_ln228_dualaspectcounterpipelined" -Tue 01:05: INFO : Info (12128): Elaborating entity "dualaspectmuxpipe_mux4" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_4:Stream_4|DualAspectMux_128_32_COUNTER_PIPELINED:inst_ln31_streamingblock|DualAspectCounterPipelined_32_128:inst_ln31_dualaspectcounterpipelined|dualaspectmuxpipe_mux4:inst_ln196_dualaspectcounterpipelined" -Tue 01:05: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_8" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_8:Stream_8" -Tue 01:05: INFO : Info (12128): Elaborating entity "DualAspectMux_1536_128_COUNTER_PIPELINED_LIMITED" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_8:Stream_8|DualAspectMux_1536_128_COUNTER_PIPELINED_LIMITED:inst_ln31_streamingblock" -Tue 01:05: INFO : Info (12128): Elaborating entity "DualAspectCounterPipelined_128_1536" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_8:Stream_8|DualAspectMux_1536_128_COUNTER_PIPELINED_LIMITED:inst_ln31_streamingblock|DualAspectCounterPipelined_128_1536:inst_ln31_dualaspectcounterpipelined" -Tue 01:05: INFO : Info (12128): Elaborating entity "dualaspectmuxpipe_counter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_8:Stream_8|DualAspectMux_1536_128_COUNTER_PIPELINED_LIMITED:inst_ln31_streamingblock|DualAspectCounterPipelined_128_1536:inst_ln31_dualaspectcounterpipelined|dualaspectmuxpipe_counter:inst_ln228_dualaspectcounterpipelined" -Tue 01:05: INFO : Info (12128): Elaborating entity "dualaspectmuxpipe_mux4" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_8:Stream_8|DualAspectMux_1536_128_COUNTER_PIPELINED_LIMITED:inst_ln31_streamingblock|DualAspectCounterPipelined_128_1536:inst_ln31_dualaspectcounterpipelined|dualaspectmuxpipe_mux4:inst_ln196_dualaspectcounterpipelined" -Tue 01:05: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_11" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_11.vhdl(108): object "inst_ln31_streamingblock_underflow" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_11.vhdl(109): object "inst_ln31_streamingblock_overflow" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_11.vhdl(110): object "inst_ln31_streamingblock_dbg_empty" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_11.vhdl(111): object "inst_ln31_streamingblock_dbg_stall" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs.vhdl(107): object "inst_ln47_alterafifo_full" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs.vhdl(111): object "inst_ln47_alterafifo_wr_data_count" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo" -Tue 01:05: INFO : Info (12128): Elaborating entity "dcfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo" -Tue 01:05: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo" -Tue 01:05: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo" with the following parameter: -Tue 01:05: INFO : Info (12134): Parameter "lpm_width" = "128" -Tue 01:05: INFO : Info (12134): Parameter "lpm_widthu" = "9" -Tue 01:05: INFO : Info (12134): Parameter "lpm_numwords" = "512" -Tue 01:05: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:05: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" -Tue 01:05: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:05: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:05: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:05: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:05: INFO : Info (12134): Parameter "delay_rdusedw" = "1" -Tue 01:05: INFO : Info (12134): Parameter "delay_wrusedw" = "1" -Tue 01:05: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" -Tue 01:05: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" -Tue 01:05: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" -Tue 01:05: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" -Tue 01:05: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_3r52.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: dcfifo_3r52 -Tue 01:05: INFO : Info (12128): Elaborating entity "dcfifo_3r52" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_qbb.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: a_gray2bin_qbb -Tue 01:05: INFO : Info (12128): Elaborating entity "a_gray2bin_qbb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|a_gray2bin_qbb:wrptr_g_gray2bin" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ebe1.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: altsyncram_ebe1 -Tue 01:05: INFO : Info (12128): Elaborating entity "altsyncram_ebe1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|altsyncram_ebe1:fifo_ram" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_uld.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: alt_synch_pipe_uld -Tue 01:05: INFO : Info (12128): Elaborating entity "alt_synch_pipe_uld" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|alt_synch_pipe_uld:rs_dgwp" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_te9.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: dffpipe_te9 -Tue 01:05: INFO : Info (12128): Elaborating entity "dffpipe_te9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|alt_synch_pipe_uld:rs_dgwp|dffpipe_te9:dffpipe6" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: dffpipe_oe9 -Tue 01:05: INFO : Info (12128): Elaborating entity "dffpipe_oe9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|dffpipe_oe9:ws_brp" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_vld.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: alt_synch_pipe_vld -Tue 01:05: INFO : Info (12128): Elaborating entity "alt_synch_pipe_vld" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|alt_synch_pipe_vld:ws_dgrp" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_ue9.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: dffpipe_ue9 -Tue 01:05: INFO : Info (12128): Elaborating entity "dffpipe_ue9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|alt_synch_pipe_vld:ws_dgrp|dffpipe_ue9:dffpipe10" -Tue 01:05: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_15" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_15.vhdl(107): object "inst_ln31_streamingblock_underflow" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_15.vhdl(108): object "inst_ln31_streamingblock_overflow" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_15.vhdl(109): object "inst_ln31_streamingblock_dbg_empty" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_15.vhdl(110): object "inst_ln31_streamingblock_dbg_stall" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs.vhdl(104): object "inst_ln47_alterafifo_full" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_128_512_128_aclr_afv477_of_uf" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo" -Tue 01:05: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" -Tue 01:05: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" -Tue 01:05: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" with the following parameter: -Tue 01:05: INFO : Info (12134): Parameter "lpm_width" = "128" -Tue 01:05: INFO : Info (12134): Parameter "lpm_widthu" = "9" -Tue 01:05: INFO : Info (12134): Parameter "lpm_numwords" = "512" -Tue 01:05: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:05: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" -Tue 01:05: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:05: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:05: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:05: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:05: INFO : Info (12134): Parameter "almost_full_value" = "477" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_9ee1.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: scfifo_9ee1 -Tue 01:05: INFO : Info (12128): Elaborating entity "scfifo_9ee1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_pvb1.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: a_dpfifo_pvb1 -Tue 01:05: INFO : Info (12128): Elaborating entity "a_dpfifo_pvb1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_s7f.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: a_fefifo_s7f -Tue 01:05: INFO : Info (12128): Elaborating entity "a_fefifo_s7f" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|a_fefifo_s7f:fifo_state" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_4i7.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: cntr_4i7 -Tue 01:05: INFO : Info (12128): Elaborating entity "cntr_4i7" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|a_fefifo_s7f:fifo_state|cntr_4i7:count_usedw" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_4ob1.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: dpram_4ob1 -Tue 01:05: INFO : Info (12128): Elaborating entity "dpram_4ob1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_muu1.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: altsyncram_muu1 -Tue 01:05: INFO : Info (12128): Elaborating entity "altsyncram_muu1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1" -Tue 01:05: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_ohb.tdf -Tue 01:05: INFO : Info (12023): Found entity 1: cntr_ohb -Tue 01:05: INFO : Info (12128): Elaborating entity "cntr_ohb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|cntr_ohb:rd_ptr_count" -Tue 01:05: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_13" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_13.vhdl(109): object "inst_ln31_streamingblock_underflow" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_13.vhdl(110): object "inst_ln31_streamingblock_overflow" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_13.vhdl(111): object "inst_ln31_streamingblock_dbg_empty" assigned a value but never read -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_13.vhdl(112): object "inst_ln31_streamingblock_dbg_stall" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock" -Tue 01:05: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs.vhdl(106): object "inst_ln47_alterafifo_full" assigned a value but never read -Tue 01:05: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_1536_512_1536_aclr_afv510_aev8_of_uf" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_1536_512_1536_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo" -Tue 01:05: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_1536_512_1536_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" -Tue 01:05: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_1536_512_1536_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_1536_512_1536_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "lpm_width" = "1536" -Tue 01:06: INFO : Info (12134): Parameter "lpm_widthu" = "9" -Tue 01:06: INFO : Info (12134): Parameter "lpm_numwords" = "512" -Tue 01:06: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" -Tue 01:06: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:06: INFO : Info (12134): Parameter "almost_full_value" = "510" -Tue 01:06: INFO : Info (12134): Parameter "almost_empty_value" = "8" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_uqh1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: scfifo_uqh1 -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo_uqh1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_1536_512_1536_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_uqh1:auto_generated" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_d1c1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: a_dpfifo_d1c1 -Tue 01:06: INFO : Info (12128): Elaborating entity "a_dpfifo_d1c1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_1536_512_1536_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_uqh1:auto_generated|a_dpfifo_d1c1:dpfifo" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_opb1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dpram_opb1 -Tue 01:06: INFO : Info (12128): Elaborating entity "dpram_opb1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_1536_512_1536_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_uqh1:auto_generated|a_dpfifo_d1c1:dpfifo|dpram_opb1:FIFOram" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_85v1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_85v1 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_85v1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_1536_1536_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_1536_512_1536_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_uqh1:auto_generated|a_dpfifo_d1c1:dpfifo|dpram_opb1:FIFOram|altsyncram_85v1:altsyncram1" -Tue 01:06: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_17" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_17.vhdl(110): object "inst_ln31_streamingblock_underflow" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_17.vhdl(111): object "inst_ln31_streamingblock_overflow" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_17.vhdl(112): object "inst_ln31_streamingblock_dbg_empty" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_17.vhdl(113): object "inst_ln31_streamingblock_dbg_stall" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs.vhdl(109): object "inst_ln47_alterafifo_full" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs.vhdl(113): object "inst_ln47_alterafifo_wr_data_count" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo" -Tue 01:06: INFO : Info (12128): Elaborating entity "dcfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "lpm_width" = "32" -Tue 01:06: INFO : Info (12134): Parameter "lpm_widthu" = "9" -Tue 01:06: INFO : Info (12134): Parameter "lpm_numwords" = "512" -Tue 01:06: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" -Tue 01:06: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:06: INFO : Info (12134): Parameter "delay_rdusedw" = "1" -Tue 01:06: INFO : Info (12134): Parameter "delay_wrusedw" = "1" -Tue 01:06: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" -Tue 01:06: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" -Tue 01:06: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_lg62.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dcfifo_lg62 -Tue 01:06: INFO : Info (12128): Elaborating entity "dcfifo_lg62" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_28e1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_28e1 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_28e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_0md.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: alt_synch_pipe_0md -Tue 01:06: INFO : Info (12128): Elaborating entity "alt_synch_pipe_0md" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|alt_synch_pipe_0md:rs_dgwp" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_ve9.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dffpipe_ve9 -Tue 01:06: INFO : Info (12128): Elaborating entity "dffpipe_ve9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe6" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_1md.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: alt_synch_pipe_1md -Tue 01:06: INFO : Info (12128): Elaborating entity "alt_synch_pipe_1md" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|alt_synch_pipe_1md:ws_dgrp" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_0f9.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dffpipe_0f9 -Tue 01:06: INFO : Info (12128): Elaborating entity "dffpipe_0f9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe9" -Tue 01:06: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_19" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_19.vhdl(107): object "inst_ln31_streamingblock_underflow" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_19.vhdl(108): object "inst_ln31_streamingblock_overflow" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_19.vhdl(109): object "inst_ln31_streamingblock_dbg_empty" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_19.vhdl(110): object "inst_ln31_streamingblock_dbg_stall" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "StreamFifo_altera_1536_1536_512_pushin_sl5_pullout_el1_singleclock_errflgs" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19|StreamFifo_altera_1536_1536_512_pushin_sl5_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_1536_1536_512_pushin_sl5_pullout_el1_singleclock_errflgs.vhdl(104): object "inst_ln47_alterafifo_full" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_1536_512_1536_aclr_afv474_of_uf" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19|StreamFifo_altera_1536_1536_512_pushin_sl5_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_1536_512_1536_aclr_afv474_of_uf:inst_ln47_alterafifo" -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19|StreamFifo_altera_1536_1536_512_pushin_sl5_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_1536_512_1536_aclr_afv474_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19|StreamFifo_altera_1536_1536_512_pushin_sl5_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_1536_512_1536_aclr_afv474_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19|StreamFifo_altera_1536_1536_512_pushin_sl5_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_1536_512_1536_aclr_afv474_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "lpm_width" = "1536" -Tue 01:06: INFO : Info (12134): Parameter "lpm_widthu" = "9" -Tue 01:06: INFO : Info (12134): Parameter "lpm_numwords" = "512" -Tue 01:06: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" -Tue 01:06: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:06: INFO : Info (12134): Parameter "almost_full_value" = "474" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_qfe1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: scfifo_qfe1 -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo_qfe1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19|StreamFifo_altera_1536_1536_512_pushin_sl5_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_1536_512_1536_aclr_afv474_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_qfe1:auto_generated" -Tue 01:06: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_21" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_21:Stream_21" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_21.vhdl(108): object "inst_ln31_streamingblock_underflow" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_21.vhdl(109): object "inst_ln31_streamingblock_overflow" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_21.vhdl(110): object "inst_ln31_streamingblock_dbg_empty" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_21.vhdl(111): object "inst_ln31_streamingblock_dbg_stall" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "PCIeStreaming_2_3" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(470): object "requestencoder_i_read_done" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(471): object "requestencoder_i_dma_read_req" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(472): object "requestencoder_i_dma_read_addr" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(473): object "requestencoder_i_dma_read_len" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(474): object "requestencoder_i_dma_read_be" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(475): object "requestencoder_i_dma_read_tag" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(476): object "requestencoder_i_dma_read_wide_addr" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(485): object "requestencoder_i_interrupt_ctl_valid" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(486): object "requestencoder_i_interrupt_ctl_enable_id" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(534): object "slavestreamingbarparser_i_sth1_bufinfo_ring_info_valid" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(535): object "slavestreamingbarparser_i_sth1_bufinfo_ring_info_addr" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(536): object "slavestreamingbarparser_i_sth1_bufinfo_ring_info_data" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(537): object "slavestreamingbarparser_i_sth1_bufinfo_ring_info_config_valid" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(538): object "slavestreamingbarparser_i_sth1_bufinfo_ring_info_config_invalid" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(539): object "slavestreamingbarparser_i_sth1_ring_info_stop" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(552): object "slavestreamingcreditsbarparser_i_sth1_host_cred_index" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(553): object "slavestreamingcreditsbarparser_i_sth1_host_cred_update" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(554): object "slavestreamingcreditsbarparser_i_sth1_host_cred_wrap" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(589): object "pcieslavestreamtohost0_compl_be" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "MappedRegBlock_921618fecb8cf8badc2cf71cbe32b185" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|MappedRegBlock_921618fecb8cf8badc2cf71cbe32b185:inst_ln130_mappedregblock" -Tue 01:06: INFO : Info (12128): Elaborating entity "ReadComplRequestArbiter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|ReadComplRequestArbiter:ReadComplRequestArbiter_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "FastRequestArbiter_req1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|ReadComplRequestArbiter:ReadComplRequestArbiter_i|FastRequestArbiter_req1:internal_arbiter_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "priority_encoder" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|ReadComplRequestArbiter:ReadComplRequestArbiter_i|FastRequestArbiter_req1:internal_arbiter_i|priority_encoder:pencoder" -Tue 01:06: INFO : Info (12128): Elaborating entity "fast_request_arbiter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|ReadComplRequestArbiter:ReadComplRequestArbiter_i|FastRequestArbiter_req1:internal_arbiter_i|fast_request_arbiter:fast_request_arbiter_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "RequestEncoder" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at RequestEncoder.vhdl(167): object "wr_req_buffer_i_full" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at RequestEncoder.vhdl(170): object "wr_req_data_buffer_i_full" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at RequestEncoder.vhdl(171): object "wr_req_data_buffer_i_empty" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "write_request_encoder" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|write_request_encoder:inst_ln9_writerequestencoderexternal" -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_115_512_115_aclr_fwft" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "lpm_width" = "115" -Tue 01:06: INFO : Info (12134): Parameter "lpm_widthu" = "9" -Tue 01:06: INFO : Info (12134): Parameter "lpm_numwords" = "512" -Tue 01:06: INFO : Info (12134): Parameter "lpm_showahead" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" -Tue 01:06: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_84b1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: scfifo_84b1 -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo_84b1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_fab1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: a_dpfifo_fab1 -Tue 01:06: INFO : Info (12128): Elaborating entity "a_dpfifo_fab1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_n8j1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_n8j1 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_n8j1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_am8.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: cmpr_am8 -Tue 01:06: INFO : Info (12128): Elaborating entity "cmpr_am8" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|cmpr_am8:almost_full_comparer" -Tue 01:06: INFO : Info (12128): Elaborating entity "cmpr_am8" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|cmpr_am8:three_comparison" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_nhb.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: cntr_nhb -Tue 01:06: INFO : Info (12128): Elaborating entity "cntr_nhb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|cntr_nhb:rd_ptr_msb" -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_128_512_128_aclr_afv448" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_128_512_128_aclr_afv448:wr_req_data_buffer_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_128_512_128_aclr_afv448:wr_req_data_buffer_i|scfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_128_512_128_aclr_afv448:wr_req_data_buffer_i|scfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_128_512_128_aclr_afv448:wr_req_data_buffer_i|scfifo:inst_ln38_mwfifo" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "lpm_width" = "128" -Tue 01:06: INFO : Info (12134): Parameter "lpm_widthu" = "9" -Tue 01:06: INFO : Info (12134): Parameter "lpm_numwords" = "512" -Tue 01:06: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" -Tue 01:06: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:06: INFO : Info (12134): Parameter "almost_full_value" = "448" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_7ee1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: scfifo_7ee1 -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo_7ee1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_128_512_128_aclr_afv448:wr_req_data_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_7ee1:auto_generated" -Tue 01:06: INFO : Info (12128): Elaborating entity "TagGenerator" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|TagGenerator:TagGenerator_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "MemWriteRequestArbiter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|MemWriteRequestArbiter:MemWriteRequestArbiter_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "FastRequestArbiter_req4" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|MemWriteRequestArbiter:MemWriteRequestArbiter_i|FastRequestArbiter_req4:internal_arbiter_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "priority_encoder" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|MemWriteRequestArbiter:MemWriteRequestArbiter_i|FastRequestArbiter_req4:internal_arbiter_i|priority_encoder:pencoder" -Tue 01:06: INFO : Info (12128): Elaborating entity "fast_request_arbiter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|MemWriteRequestArbiter:MemWriteRequestArbiter_i|FastRequestArbiter_req4:internal_arbiter_i|fast_request_arbiter:fast_request_arbiter_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "SlaveStreamingRingConfigBarParser" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|SlaveStreamingRingConfigBarParser:SlaveStreamingBarParser_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "SlaveStreamingCreditsBarParser" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|SlaveStreamingCreditsBarParser:SlaveStreamingCreditsBarParser_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "PCIeSlaveStreamFromHost" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0" -Tue 01:06: INFO : Info (12128): Elaborating entity "pcie_slave_streaming_sfh_ring" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring" -Tue 01:06: INFO : Info (12128): Elaborating entity "rg_buffer_info" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_info:rg_info" -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_info:rg_info|AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg" -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_info:rg_info|AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_info:rg_info|AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_info:rg_info|AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "address_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "address_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "byte_size" = "8" -Tue 01:06: INFO : Info (12134): Parameter "byteena_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "byteena_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "byteena_reg_b" = "CLOCK1" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_core_a" = "USE_INPUT_CLKEN" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_core_b" = "USE_INPUT_CLKEN" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_input_a" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_input_b" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_output_a" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_output_b" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "stratixv" -Tue 01:06: INFO : Info (12134): Parameter "ecc_pipeline_stage_enabled" = "FALSE" -Tue 01:06: INFO : Info (12134): Parameter "enable_ecc" = "FALSE" -Tue 01:06: INFO : Info (12134): Parameter "implement_in_les" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "indata_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "indata_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "indata_reg_b" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "init_file" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "init_file_layout" = "PORT_A" -Tue 01:06: INFO : Info (12134): Parameter "maximum_depth" = "0" -Tue 01:06: INFO : Info (12134): Parameter "numwords_a" = "2" -Tue 01:06: INFO : Info (12134): Parameter "numwords_b" = "2" -Tue 01:06: INFO : Info (12134): Parameter "operation_mode" = "DUAL_PORT" -Tue 01:06: INFO : Info (12134): Parameter "outdata_aclr_a" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "outdata_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" -Tue 01:06: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" -Tue 01:06: INFO : Info (12134): Parameter "power_up_uninitialized" = "FALSE" -Tue 01:06: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" -Tue 01:06: INFO : Info (12134): Parameter "rdcontrol_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK1" -Tue 01:06: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" -Tue 01:06: INFO : Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" -Tue 01:06: INFO : Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" -Tue 01:06: INFO : Info (12134): Parameter "stratixiv_m144k_allow_dual_clocks" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "width_a" = "8" -Tue 01:06: INFO : Info (12134): Parameter "width_b" = "8" -Tue 01:06: INFO : Info (12134): Parameter "width_byteena_a" = "1" -Tue 01:06: INFO : Info (12134): Parameter "width_byteena_b" = "1" -Tue 01:06: INFO : Info (12134): Parameter "width_eccstatus" = "3" -Tue 01:06: INFO : Info (12134): Parameter "widthad_a" = "1" -Tue 01:06: INFO : Info (12134): Parameter "widthad_b" = "1" -Tue 01:06: INFO : Info (12134): Parameter "wrcontrol_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "wrcontrol_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "altsyncram" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_j034.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_j034 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_j034" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_info:rg_info|AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_j034:auto_generated" -Tue 01:06: INFO : Info (12128): Elaborating entity "rg_buffer_sfh" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen" -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg" -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "address_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "address_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "byte_size" = "8" -Tue 01:06: INFO : Info (12134): Parameter "byteena_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "byteena_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "byteena_reg_b" = "CLOCK1" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_core_a" = "USE_INPUT_CLKEN" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_core_b" = "USE_INPUT_CLKEN" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_input_a" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_input_b" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_output_a" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_output_b" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "stratixv" -Tue 01:06: INFO : Info (12134): Parameter "ecc_pipeline_stage_enabled" = "FALSE" -Tue 01:06: INFO : Info (12134): Parameter "enable_ecc" = "FALSE" -Tue 01:06: INFO : Info (12134): Parameter "implement_in_les" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "indata_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "indata_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "indata_reg_b" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "init_file" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "init_file_layout" = "PORT_A" -Tue 01:06: INFO : Info (12134): Parameter "maximum_depth" = "0" -Tue 01:06: INFO : Info (12134): Parameter "numwords_a" = "512" -Tue 01:06: INFO : Info (12134): Parameter "numwords_b" = "512" -Tue 01:06: INFO : Info (12134): Parameter "operation_mode" = "DUAL_PORT" -Tue 01:06: INFO : Info (12134): Parameter "outdata_aclr_a" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "outdata_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" -Tue 01:06: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" -Tue 01:06: INFO : Info (12134): Parameter "power_up_uninitialized" = "FALSE" -Tue 01:06: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" -Tue 01:06: INFO : Info (12134): Parameter "rdcontrol_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK1" -Tue 01:06: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" -Tue 01:06: INFO : Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" -Tue 01:06: INFO : Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" -Tue 01:06: INFO : Info (12134): Parameter "stratixiv_m144k_allow_dual_clocks" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "width_a" = "32" -Tue 01:06: INFO : Info (12134): Parameter "width_b" = "32" -Tue 01:06: INFO : Info (12134): Parameter "width_byteena_a" = "1" -Tue 01:06: INFO : Info (12134): Parameter "width_byteena_b" = "1" -Tue 01:06: INFO : Info (12134): Parameter "width_eccstatus" = "3" -Tue 01:06: INFO : Info (12134): Parameter "widthad_a" = "9" -Tue 01:06: INFO : Info (12134): Parameter "widthad_b" = "9" -Tue 01:06: INFO : Info (12134): Parameter "wrcontrol_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "wrcontrol_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "altsyncram" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_9a34.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_9a34 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_9a34" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated" -Tue 01:06: INFO : Info (12128): Elaborating entity "pcie_posted_credits_writer" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer" -Tue 01:06: INFO : Info (12128): Elaborating entity "posted_credits_fifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo" -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_2_16_2_aclr_fwft" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft" -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "lpm_width" = "2" -Tue 01:06: INFO : Info (12134): Parameter "lpm_widthu" = "4" -Tue 01:06: INFO : Info (12134): Parameter "lpm_numwords" = "16" -Tue 01:06: INFO : Info (12134): Parameter "lpm_showahead" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" -Tue 01:06: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_dva1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: scfifo_dva1 -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo_dva1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_k5b1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: a_dpfifo_k5b1 -Tue 01:06: INFO : Info (12128): Elaborating entity "a_dpfifo_k5b1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_1vi1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_1vi1 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_1vi1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo|altsyncram_1vi1:FIFOram" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_5m8.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: cmpr_5m8 -Tue 01:06: INFO : Info (12128): Elaborating entity "cmpr_5m8" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo|cmpr_5m8:almost_full_comparer" -Tue 01:06: INFO : Info (12128): Elaborating entity "cmpr_5m8" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo|cmpr_5m8:three_comparison" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_ihb.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: cntr_ihb -Tue 01:06: INFO : Info (12128): Elaborating entity "cntr_ihb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo|cntr_ihb:rd_ptr_msb" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_vh7.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: cntr_vh7 -Tue 01:06: INFO : Info (12128): Elaborating entity "cntr_vh7" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo|cntr_vh7:usedw_counter" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_jhb.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: cntr_jhb -Tue 01:06: INFO : Info (12128): Elaborating entity "cntr_jhb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo|cntr_jhb:wr_ptr" -Tue 01:06: INFO : Info (12128): Elaborating entity "PCIeSlaveStreamToHost" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeSlaveStreamToHost.vhdl(207): object "stream_ring_compl_fifo_underflow" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "pcie_slave_streaming_sth_ring" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring" -Tue 01:06: INFO : Info (12128): Elaborating entity "sth_compl_fifo_debug" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo" -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of" -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "lpm_width" = "60" -Tue 01:06: INFO : Info (12134): Parameter "lpm_widthu" = "4" -Tue 01:06: INFO : Info (12134): Parameter "lpm_numwords" = "16" -Tue 01:06: INFO : Info (12134): Parameter "lpm_showahead" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" -Tue 01:06: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:06: INFO : Info (12134): Parameter "almost_full_value" = "14" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_36e1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: scfifo_36e1 -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo_36e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_gpb1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: a_dpfifo_gpb1 -Tue 01:06: INFO : Info (12128): Elaborating entity "a_dpfifo_gpb1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_92j1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_92j1 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_92j1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram" -Tue 01:06: INFO : Info (12128): Elaborating entity "rg_buffer_sth" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_sth:\gen_buffers:0:buf_gen" -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_sth:\gen_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg:wrapped_AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg" -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_sth:\gen_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg:wrapped_AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg|altsyncram:inst_ln100_mwblockmem" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_sth:\gen_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg:wrapped_AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg|altsyncram:inst_ln100_mwblockmem" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_sth:\gen_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg:wrapped_AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg|altsyncram:inst_ln100_mwblockmem" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "address_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "address_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "byte_size" = "8" -Tue 01:06: INFO : Info (12134): Parameter "byteena_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "byteena_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "byteena_reg_b" = "CLOCK1" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_core_a" = "USE_INPUT_CLKEN" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_core_b" = "USE_INPUT_CLKEN" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_input_a" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_input_b" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_output_a" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_output_b" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "stratixv" -Tue 01:06: INFO : Info (12134): Parameter "ecc_pipeline_stage_enabled" = "FALSE" -Tue 01:06: INFO : Info (12134): Parameter "enable_ecc" = "FALSE" -Tue 01:06: INFO : Info (12134): Parameter "implement_in_les" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "indata_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "indata_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "indata_reg_b" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "init_file" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "init_file_layout" = "PORT_A" -Tue 01:06: INFO : Info (12134): Parameter "maximum_depth" = "0" -Tue 01:06: INFO : Info (12134): Parameter "numwords_a" = "256" -Tue 01:06: INFO : Info (12134): Parameter "numwords_b" = "256" -Tue 01:06: INFO : Info (12134): Parameter "operation_mode" = "DUAL_PORT" -Tue 01:06: INFO : Info (12134): Parameter "outdata_aclr_a" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "outdata_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "outdata_reg_a" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "outdata_reg_b" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "power_up_uninitialized" = "FALSE" -Tue 01:06: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" -Tue 01:06: INFO : Info (12134): Parameter "rdcontrol_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK1" -Tue 01:06: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" -Tue 01:06: INFO : Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" -Tue 01:06: INFO : Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" -Tue 01:06: INFO : Info (12134): Parameter "stratixiv_m144k_allow_dual_clocks" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "width_a" = "128" -Tue 01:06: INFO : Info (12134): Parameter "width_b" = "128" -Tue 01:06: INFO : Info (12134): Parameter "width_byteena_a" = "1" -Tue 01:06: INFO : Info (12134): Parameter "width_byteena_b" = "1" -Tue 01:06: INFO : Info (12134): Parameter "width_eccstatus" = "3" -Tue 01:06: INFO : Info (12134): Parameter "widthad_a" = "8" -Tue 01:06: INFO : Info (12134): Parameter "widthad_b" = "8" -Tue 01:06: INFO : Info (12134): Parameter "wrcontrol_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "wrcontrol_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "altsyncram" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_j024.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_j024 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_j024" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_sth:\gen_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg:wrapped_AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg|altsyncram:inst_ln100_mwblockmem|altsyncram_j024:auto_generated" -Tue 01:06: INFO : Info (12128): Elaborating entity "rg_buffer_info_sth" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_info_sth:g_info" -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_info_sth:g_info|AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg" -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_info_sth:g_info|AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_info_sth:g_info|AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_info_sth:g_info|AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "address_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "address_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "byte_size" = "8" -Tue 01:06: INFO : Info (12134): Parameter "byteena_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "byteena_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "byteena_reg_b" = "CLOCK1" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_core_a" = "USE_INPUT_CLKEN" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_core_b" = "USE_INPUT_CLKEN" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_input_a" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_input_b" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_output_a" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "clock_enable_output_b" = "BYPASS" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "stratixv" -Tue 01:06: INFO : Info (12134): Parameter "ecc_pipeline_stage_enabled" = "FALSE" -Tue 01:06: INFO : Info (12134): Parameter "enable_ecc" = "FALSE" -Tue 01:06: INFO : Info (12134): Parameter "implement_in_les" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "indata_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "indata_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "indata_reg_b" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "init_file" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "init_file_layout" = "PORT_A" -Tue 01:06: INFO : Info (12134): Parameter "maximum_depth" = "0" -Tue 01:06: INFO : Info (12134): Parameter "numwords_a" = "2" -Tue 01:06: INFO : Info (12134): Parameter "numwords_b" = "2" -Tue 01:06: INFO : Info (12134): Parameter "operation_mode" = "DUAL_PORT" -Tue 01:06: INFO : Info (12134): Parameter "outdata_aclr_a" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "outdata_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" -Tue 01:06: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" -Tue 01:06: INFO : Info (12134): Parameter "power_up_uninitialized" = "FALSE" -Tue 01:06: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" -Tue 01:06: INFO : Info (12134): Parameter "rdcontrol_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK1" -Tue 01:06: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" -Tue 01:06: INFO : Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" -Tue 01:06: INFO : Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" -Tue 01:06: INFO : Info (12134): Parameter "stratixiv_m144k_allow_dual_clocks" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "width_a" = "9" -Tue 01:06: INFO : Info (12134): Parameter "width_b" = "9" -Tue 01:06: INFO : Info (12134): Parameter "width_byteena_a" = "1" -Tue 01:06: INFO : Info (12134): Parameter "width_byteena_b" = "1" -Tue 01:06: INFO : Info (12134): Parameter "width_eccstatus" = "3" -Tue 01:06: INFO : Info (12134): Parameter "widthad_a" = "1" -Tue 01:06: INFO : Info (12134): Parameter "widthad_b" = "1" -Tue 01:06: INFO : Info (12134): Parameter "wrcontrol_aclr_a" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "wrcontrol_aclr_b" = "NONE" -Tue 01:06: INFO : Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" -Tue 01:06: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "altsyncram" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_l034.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_l034 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_l034" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_info_sth:g_info|AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_l034:auto_generated" -Tue 01:06: INFO : Info (12128): Elaborating entity "MappedElementAdapterForwarder" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedElementAdapterForwarder:MappedElementAdapterForwarder_pcie_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "PerfMonitor" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PerfMonitor:PerformanceMonitor_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "perf_monitor" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PerfMonitor:PerformanceMonitor_i|perf_monitor:inst_ln11_perfmonitorext" -Tue 01:06: INFO : Info (12128): Elaborating entity "start_of_day_reset" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|start_of_day_reset:inst_ln9_startofdayreset" -Tue 01:06: INFO : Info (12128): Elaborating entity "MAX4PCIeSlaveInterface" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(537): object "pcieslaveinterface_imp_qsfp_top_i2c_scl_drv" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(538): object "pcieslaveinterface_imp_qsfp_top_i2c_sda_drv" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(539): object "pcieslaveinterface_imp_qsfp_top_i2c_lpmode" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(540): object "pcieslaveinterface_imp_qsfp_top_i2c_modsell" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(541): object "pcieslaveinterface_imp_qsfp_top_i2c_resetl" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(542): object "pcieslaveinterface_imp_qsfp_mid_i2c_scl_drv" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(543): object "pcieslaveinterface_imp_qsfp_mid_i2c_sda_drv" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(544): object "pcieslaveinterface_imp_qsfp_mid_i2c_lpmode" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(545): object "pcieslaveinterface_imp_qsfp_mid_i2c_modsell" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(546): object "pcieslaveinterface_imp_qsfp_mid_i2c_resetl" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(547): object "pcieslaveinterface_imp_qsfp_bot_i2c_scl_drv" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(548): object "pcieslaveinterface_imp_qsfp_bot_i2c_sda_drv" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(549): object "pcieslaveinterface_imp_qsfp_bot_i2c_lpmode" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(550): object "pcieslaveinterface_imp_qsfp_bot_i2c_modsell" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(551): object "pcieslaveinterface_imp_qsfp_bot_i2c_resetl" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(552): object "pcieslaveinterface_imp_ptp_phy_mdio_scl_from_host" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(553): object "pcieslaveinterface_imp_ptp_phy_mdio_sda_from_host" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "max_SV_pcie_slave" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp" -Tue 01:06: INFO : Warning (10873): Using initial value X (don't care) for net "tx_reg_compl_data[63..32]" at max_SV_pcie_slave.vhd(86) -Tue 01:06: INFO : Info (12128): Elaborating entity "compl_fifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo" -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "lpm_width" = "45" -Tue 01:06: INFO : Info (12134): Parameter "lpm_widthu" = "5" -Tue 01:06: INFO : Info (12134): Parameter "lpm_numwords" = "32" -Tue 01:06: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" -Tue 01:06: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:06: INFO : Info (12134): Parameter "almost_full_value" = "20" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_09e1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: scfifo_09e1 -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo_09e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_gsb1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: a_dpfifo_gsb1 -Tue 01:06: INFO : Info (12128): Elaborating entity "a_dpfifo_gsb1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_56f.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: a_fefifo_56f -Tue 01:06: INFO : Info (12128): Elaborating entity "a_fefifo_56f" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|a_fefifo_56f:fifo_state" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_0i7.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: cntr_0i7 -Tue 01:06: INFO : Info (12128): Elaborating entity "cntr_0i7" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|a_fefifo_56f:fifo_state|cntr_0i7:count_usedw" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_emb1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dpram_emb1 -Tue 01:06: INFO : Info (12128): Elaborating entity "dpram_emb1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|dpram_emb1:FIFOram" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_8ou1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_8ou1 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_8ou1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|dpram_emb1:FIFOram|altsyncram_8ou1:altsyncram1" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_khb.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: cntr_khb -Tue 01:06: INFO : Info (12128): Elaborating entity "cntr_khb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|cntr_khb:rd_ptr_count" -Tue 01:06: INFO : Info (12128): Elaborating entity "max_pcie_slave_req_dispatcher" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_pcie_slave_req_dispatcher:PCIeSlaveReqDispatcher_imp" -Tue 01:06: INFO : Info (12128): Elaborating entity "StratixPCIeInterface" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "max_SV_pcie_tx" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_tx.vhd(166): object "dma_write_count_reset" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_tx.vhd(193): object "qword_aligned" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "pcie_tx_fifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "lpm_width" = "132" -Tue 01:06: INFO : Info (12134): Parameter "lpm_widthu" = "6" -Tue 01:06: INFO : Info (12134): Parameter "lpm_numwords" = "64" -Tue 01:06: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" -Tue 01:06: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:06: INFO : Info (12134): Parameter "almost_full_value" = "48" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_tae1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: scfifo_tae1 -Tue 01:06: INFO : Info (12128): Elaborating entity "scfifo_tae1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_3ub1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: a_dpfifo_3ub1 -Tue 01:06: INFO : Info (12128): Elaborating entity "a_dpfifo_3ub1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated|a_dpfifo_3ub1:dpfifo" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_b6f.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: a_fefifo_b6f -Tue 01:06: INFO : Info (12128): Elaborating entity "a_fefifo_b6f" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated|a_dpfifo_3ub1:dpfifo|a_fefifo_b6f:fifo_state" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1i7.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: cntr_1i7 -Tue 01:06: INFO : Info (12128): Elaborating entity "cntr_1i7" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated|a_dpfifo_3ub1:dpfifo|a_fefifo_b6f:fifo_state|cntr_1i7:count_usedw" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_snb1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dpram_snb1 -Tue 01:06: INFO : Info (12128): Elaborating entity "dpram_snb1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated|a_dpfifo_3ub1:dpfifo|dpram_snb1:FIFOram" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_8uu1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_8uu1 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_8uu1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated|a_dpfifo_3ub1:dpfifo|dpram_snb1:FIFOram|altsyncram_8uu1:altsyncram1" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_lhb.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: cntr_lhb -Tue 01:06: INFO : Info (12128): Elaborating entity "cntr_lhb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated|a_dpfifo_3ub1:dpfifo|cntr_lhb:rd_ptr_count" -Tue 01:06: INFO : Info (12128): Elaborating entity "max_SV_pcie_rx" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_rx:StratixVPCIeRX_i" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(112): object "data_stream_aligned" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(128): object "bars_hit_r" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(130): object "bar4_hit_r" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(141): object "rx_st_err_reg" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(159): object "rx_st_eop_r" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(161): object "rx_st_empty_r" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(165): object "reg_bar0" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(165): object "reg_bar2" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "PCIeEA" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeEA.vhdl(148): object "slave_from_host_fifo_full" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_34_512_34_dualclock_aclr" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host" -Tue 01:06: INFO : Info (12128): Elaborating entity "dcfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "lpm_width" = "34" -Tue 01:06: INFO : Info (12134): Parameter "lpm_widthu" = "9" -Tue 01:06: INFO : Info (12134): Parameter "lpm_numwords" = "512" -Tue 01:06: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" -Tue 01:06: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:06: INFO : Info (12134): Parameter "delay_rdusedw" = "1" -Tue 01:06: INFO : Info (12134): Parameter "delay_wrusedw" = "1" -Tue 01:06: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" -Tue 01:06: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" -Tue 01:06: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_au42.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dcfifo_au42 -Tue 01:06: INFO : Info (12128): Elaborating entity "dcfifo_au42" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo|dcfifo_au42:auto_generated" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_68e1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_68e1 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_68e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo|dcfifo_au42:auto_generated|altsyncram_68e1:fifo_ram" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_2md.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: alt_synch_pipe_2md -Tue 01:06: INFO : Info (12128): Elaborating entity "alt_synch_pipe_2md" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo|dcfifo_au42:auto_generated|alt_synch_pipe_2md:rs_dgwp" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_1f9.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dffpipe_1f9 -Tue 01:06: INFO : Info (12128): Elaborating entity "dffpipe_1f9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo|dcfifo_au42:auto_generated|alt_synch_pipe_2md:rs_dgwp|dffpipe_1f9:dffpipe6" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_3md.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: alt_synch_pipe_3md -Tue 01:06: INFO : Info (12128): Elaborating entity "alt_synch_pipe_3md" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo|dcfifo_au42:auto_generated|alt_synch_pipe_3md:ws_dgrp" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_2f9.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dffpipe_2f9 -Tue 01:06: INFO : Info (12128): Elaborating entity "dffpipe_2f9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo|dcfifo_au42:auto_generated|alt_synch_pipe_3md:ws_dgrp|dffpipe_2f9:dffpipe9" -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo" -Tue 01:06: INFO : Info (12128): Elaborating entity "dcfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "lpm_width" = "34" -Tue 01:06: INFO : Info (12134): Parameter "lpm_widthu" = "9" -Tue 01:06: INFO : Info (12134): Parameter "lpm_numwords" = "512" -Tue 01:06: INFO : Info (12134): Parameter "lpm_showahead" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" -Tue 01:06: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:06: INFO : Info (12134): Parameter "delay_rdusedw" = "1" -Tue 01:06: INFO : Info (12134): Parameter "delay_wrusedw" = "1" -Tue 01:06: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" -Tue 01:06: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" -Tue 01:06: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_tk52.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dcfifo_tk52 -Tue 01:06: INFO : Info (12128): Elaborating entity "dcfifo_tk52" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo|dcfifo_tk52:auto_generated" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_t0c1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_t0c1 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_t0c1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo|dcfifo_tk52:auto_generated|altsyncram_t0c1:fifo_ram" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_4md.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: alt_synch_pipe_4md -Tue 01:06: INFO : Info (12128): Elaborating entity "alt_synch_pipe_4md" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo|dcfifo_tk52:auto_generated|alt_synch_pipe_4md:rs_dgwp" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_3f9.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dffpipe_3f9 -Tue 01:06: INFO : Info (12128): Elaborating entity "dffpipe_3f9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo|dcfifo_tk52:auto_generated|alt_synch_pipe_4md:rs_dgwp|dffpipe_3f9:dffpipe6" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_5md.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: alt_synch_pipe_5md -Tue 01:06: INFO : Info (12128): Elaborating entity "alt_synch_pipe_5md" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo|dcfifo_tk52:auto_generated|alt_synch_pipe_5md:ws_dgrp" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_4f9.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dffpipe_4f9 -Tue 01:06: INFO : Info (12128): Elaborating entity "dffpipe_4f9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo|dcfifo_tk52:auto_generated|alt_synch_pipe_5md:ws_dgrp|dffpipe_4f9:dffpipe9" -Tue 01:06: INFO : Info (12128): Elaborating entity "StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock.vhdl(100): object "inst_ln70_alterafifo_full" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock.vhdl(102): object "inst_ln70_alterafifo_wr_data_count" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo" -Tue 01:06: INFO : Info (12128): Elaborating entity "dcfifo_mixed_widths" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo" -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "lpm_width" = "128" -Tue 01:06: INFO : Info (12134): Parameter "lpm_widthu" = "7" -Tue 01:06: INFO : Info (12134): Parameter "lpm_numwords" = "128" -Tue 01:06: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" -Tue 01:06: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:06: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:06: INFO : Info (12134): Parameter "delay_rdusedw" = "1" -Tue 01:06: INFO : Info (12134): Parameter "delay_wrusedw" = "1" -Tue 01:06: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" -Tue 01:06: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" -Tue 01:06: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" -Tue 01:06: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" -Tue 01:06: INFO : Info (12134): Parameter "lpm_width_r" = "64" -Tue 01:06: INFO : Info (12134): Parameter "lpm_widthu_r" = "8" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_ip52.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dcfifo_ip52 -Tue 01:06: INFO : Info (12128): Elaborating entity "dcfifo_ip52" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_hab.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: a_gray2bin_hab -Tue 01:06: INFO : Info (12128): Elaborating entity "a_gray2bin_hab" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|a_gray2bin_hab:wrptr_g_gray2bin" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_fv6.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: a_graycounter_fv6 -Tue 01:06: INFO : Info (12128): Elaborating entity "a_graycounter_fv6" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|a_graycounter_fv6:rdptr_g1p" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_cdc.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: a_graycounter_cdc -Tue 01:06: INFO : Info (12128): Elaborating entity "a_graycounter_cdc" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|a_graycounter_cdc:wrptr_g1p" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_q9e1.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: altsyncram_q9e1 -Tue 01:06: INFO : Info (12128): Elaborating entity "altsyncram_q9e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_hkd.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: alt_synch_pipe_hkd -Tue 01:06: INFO : Info (12128): Elaborating entity "alt_synch_pipe_hkd" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|alt_synch_pipe_hkd:rs_dgwp" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dffpipe_gd9 -Tue 01:06: INFO : Info (12128): Elaborating entity "dffpipe_gd9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|alt_synch_pipe_hkd:rs_dgwp|dffpipe_gd9:dffpipe12" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_fd9.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dffpipe_fd9 -Tue 01:06: INFO : Info (12128): Elaborating entity "dffpipe_fd9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|dffpipe_fd9:ws_brp" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_ikd.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: alt_synch_pipe_ikd -Tue 01:06: INFO : Info (12128): Elaborating entity "alt_synch_pipe_ikd" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|alt_synch_pipe_ikd:ws_dgrp" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_hd9.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: dffpipe_hd9 -Tue 01:06: INFO : Info (12128): Elaborating entity "dffpipe_hd9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|alt_synch_pipe_ikd:ws_dgrp|dffpipe_hd9:dffpipe16" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_206.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: cmpr_206 -Tue 01:06: INFO : Info (12128): Elaborating entity "cmpr_206" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|cmpr_206:rdempty_eq_comp" -Tue 01:06: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_ptd.tdf -Tue 01:06: INFO : Info (12023): Found entity 1: cntr_ptd -Tue 01:06: INFO : Info (12128): Elaborating entity "cntr_ptd" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|cntr_ptd:cntr_b" -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv496" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv496:ftb_MappedElementsSwitchPCIeEA" -Tue 01:06: INFO : Info (12128): Elaborating entity "AlteraClockGenerator_250_200_STREAM" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "StratixVClockManager_in250_out_f200p0dc50_f200p180dc50" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVClockManager_in250_out_f200p0dc50_f200p180dc50.vhdl(295): object "altera_pll_i_fboutclk" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "altera_pll" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll:altera_pll_i" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at altera_pll.v(398): object "cntsel_temp" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at altera_pll.v(400): object "gnd" assigned a value but never read -Tue 01:06: INFO : Warning (10034): Output port "lvds_clk" at altera_pll.v(295) has no driver -Tue 01:06: INFO : Warning (10034): Output port "loaden" at altera_pll.v(296) has no driver -Tue 01:06: INFO : Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus -Tue 01:06: INFO : Info (12130): Elaborated megafunction instantiation "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll:altera_pll_i" -Tue 01:06: INFO : Info (12133): Instantiated megafunction "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll:altera_pll_i" with the following parameter: -Tue 01:06: INFO : Info (12134): Parameter "fractional_vco_multiplier" = "false" -Tue 01:06: INFO : Info (12134): Parameter "reference_clock_frequency" = "250.0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "operation_mode" = "normal" -Tue 01:06: INFO : Info (12134): Parameter "number_of_clocks" = "2" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency0" = "200.0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift0" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle0" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency1" = "200.0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift1" = "2500 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle1" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency2" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift2" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle2" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency3" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift3" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle3" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency4" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift4" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle4" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency5" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift5" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle5" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency6" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift6" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle6" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency7" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift7" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle7" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency8" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift8" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle8" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency9" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift9" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle9" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency10" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift10" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle10" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency11" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift11" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle11" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency12" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift12" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle12" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency13" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift13" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle13" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency14" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift14" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle14" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency15" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift15" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle15" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency16" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift16" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle16" = "50" -Tue 01:06: INFO : Info (12134): Parameter "output_clock_frequency17" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "phase_shift17" = "0 ps" -Tue 01:06: INFO : Info (12134): Parameter "duty_cycle17" = "50" -Tue 01:06: INFO : Info (12134): Parameter "pll_type" = "General" -Tue 01:06: INFO : Info (12134): Parameter "m_cnt_hi_div" = "1" -Tue 01:06: INFO : Info (12134): Parameter "m_cnt_lo_div" = "1" -Tue 01:06: INFO : Info (12134): Parameter "n_cnt_hi_div" = "1" -Tue 01:06: INFO : Info (12134): Parameter "n_cnt_lo_div" = "1" -Tue 01:06: INFO : Info (12134): Parameter "m_cnt_bypass_en" = "true" -Tue 01:06: INFO : Info (12134): Parameter "n_cnt_bypass_en" = "true" -Tue 01:06: INFO : Info (12134): Parameter "m_cnt_odd_div_duty_en" = "false" -Tue 01:06: INFO : Info (12134): Parameter "n_cnt_odd_div_duty_en" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div0" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div0" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst0" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst0" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en0" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en0" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div1" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div1" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst1" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst1" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en1" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en1" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div2" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div2" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst2" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst2" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en2" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en2" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div3" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div3" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst3" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst3" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en3" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en3" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div4" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div4" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst4" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst4" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en4" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en4" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div5" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div5" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst5" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst5" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en5" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en5" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div6" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div6" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst6" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst6" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en6" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en6" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div7" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div7" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst7" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst7" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en7" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en7" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div8" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div8" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst8" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst8" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en8" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en8" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div9" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div9" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst9" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst9" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en9" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en9" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div10" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div10" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst10" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst10" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en10" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en10" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div11" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div11" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst11" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst11" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en11" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en11" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div12" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div12" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst12" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst12" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en12" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en12" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div13" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div13" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst13" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst13" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en13" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en13" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div14" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div14" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst14" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst14" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en14" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en14" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div15" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div15" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst15" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst15" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en15" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en15" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div16" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div16" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst16" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst16" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en16" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en16" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_hi_div17" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_lo_div17" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_prst17" = "1" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst17" = "0" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_bypass_en17" = "false" -Tue 01:06: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en17" = "false" -Tue 01:06: INFO : Info (12134): Parameter "pll_output_clk_frequency" = "0 MHz" -Tue 01:06: INFO : Info (12134): Parameter "pll_vco_div" = "1" -Tue 01:06: INFO : Info (12134): Parameter "pll_cp_current" = "5" -Tue 01:06: INFO : Info (12134): Parameter "pll_bwctrl" = "18000" -Tue 01:06: INFO : Info (12134): Parameter "pll_fractional_division" = "1" -Tue 01:06: INFO : Info (12128): Elaborating entity "altera_pll_reconfig_top" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "dyn_phase_shift" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst" -Tue 01:06: INFO : Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_0" -Tue 01:06: INFO : Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_1" -Tue 01:06: INFO : Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_2" -Tue 01:06: INFO : Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_3" -Tue 01:06: INFO : Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_4" -Tue 01:06: INFO : Info (12128): Elaborating entity "self_reset" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|self_reset:self_reset_inst" -Tue 01:06: INFO : Info (12128): Elaborating entity "dprio_mux" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dprio_mux:dprio_mux_inst" -Tue 01:06: INFO : Info (12128): Elaborating entity "fpll_dprio_init" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|fpll_dprio_init:fpll_dprio_init_inst" -Tue 01:06: INFO : Info (12128): Elaborating entity "MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena:clockgen_altclkctrl_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena_altclkctrl_tmg" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena:clockgen_altclkctrl_i|MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena_altclkctrl_tmg:MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena_altclkctrl_tmg_component" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena.vhd(58): object "clkselect" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "StratixPCIeBase" for hierarchy "StratixPCIeBase:PCIeBase_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "StratixVHardIPPCIe" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(514): object "pcie_sv_hard_ip_i_lmi_ack" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(515): object "pcie_sv_hard_ip_i_lmi_dout" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(518): object "pcie_sv_hard_ip_i_tl_cfg_sts" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(519): object "pcie_sv_hard_ip_i_pme_to_sr" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(520): object "pcie_sv_hard_ip_i_currentspeed" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(521): object "pcie_sv_hard_ip_i_derr_cor_ext_rcv" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(522): object "pcie_sv_hard_ip_i_derr_cor_ext_rpl" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(523): object "pcie_sv_hard_ip_i_derr_rpl" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(524): object "pcie_sv_hard_ip_i_dlup" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(525): object "pcie_sv_hard_ip_i_dlup_exit" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(526): object "pcie_sv_hard_ip_i_ev128ns" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(527): object "pcie_sv_hard_ip_i_ev1us" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(528): object "pcie_sv_hard_ip_i_hotrst_exit" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(529): object "pcie_sv_hard_ip_i_int_status" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(530): object "pcie_sv_hard_ip_i_l2_exit" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(531): object "pcie_sv_hard_ip_i_lane_act" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(533): object "pcie_sv_hard_ip_i_rx_par_err" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(534): object "pcie_sv_hard_ip_i_tx_par_err" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(535): object "pcie_sv_hard_ip_i_cfg_par_err" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(536): object "pcie_sv_hard_ip_i_ko_cpl_spc_header" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(537): object "pcie_sv_hard_ip_i_ko_cpl_spc_data" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(546): object "pcie_sv_hard_ip_i_tx_cred_datafccp" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(547): object "pcie_sv_hard_ip_i_tx_cred_datafcnp" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(548): object "pcie_sv_hard_ip_i_tx_cred_datafcp" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(549): object "pcie_sv_hard_ip_i_tx_cred_fchipcons" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(550): object "pcie_sv_hard_ip_i_tx_cred_fcinfinite" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(551): object "pcie_sv_hard_ip_i_tx_cred_hdrfccp" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(552): object "pcie_sv_hard_ip_i_tx_cred_hdrfcnp" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(553): object "pcie_sv_hard_ip_i_tx_cred_hdrfcp" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(557): object "pcie_sv_hard_ip_i_pld_clk_inuse" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(558): object "pcie_sv_hard_ip_i_testin_zero" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "pcie_SV_hard_ip" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i" -Tue 01:06: INFO : Info (12128): Elaborating entity "altpcie_sv_hip_ast_hwtcl" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst" -Tue 01:06: INFO : Warning (10764): Verilog HDL warning at altpcie_sv_hip_ast_hwtcl.v(1082): converting signed shift amount to unsigned -Tue 01:06: INFO : Warning (10242): Verilog HDL Function Declaration warning at altpcie_sv_hip_ast_hwtcl.v(1044): variable "return_string" may have a Don't Care value because it may not be assigned a value in every possible path through the statements preceding its use -Tue 01:06: INFO : Warning (10230): Verilog HDL assignment warning at altpcie_sv_hip_ast_hwtcl.v(1044): truncated value with size 208 to match size of target (200) -Tue 01:06: INFO : Warning (10764): Verilog HDL warning at altpcie_sv_hip_ast_hwtcl.v(1092): converting signed shift amount to unsigned -Tue 01:06: INFO : Warning (10230): Verilog HDL assignment warning at altpcie_sv_hip_ast_hwtcl.v(2361): truncated value with size 2 to match size of target (1) -Tue 01:06: INFO : Warning (10230): Verilog HDL assignment warning at altpcie_sv_hip_ast_hwtcl.v(2362): truncated value with size 2 to match size of target (1) -Tue 01:06: INFO : Warning (10230): Verilog HDL assignment warning at altpcie_sv_hip_ast_hwtcl.v(2363): truncated value with size 2 to match size of target (1) -Tue 01:06: INFO : Warning (10230): Verilog HDL assignment warning at altpcie_sv_hip_ast_hwtcl.v(2364): truncated value with size 2 to match size of target (1) -Tue 01:06: INFO : Info (12128): Elaborating entity "altpcie_hip_256_pipen1b" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b" -Tue 01:06: INFO : Warning (10242): Verilog HDL Function Declaration warning at altpcie_hip_256_pipen1b.v(931): variable "return_string" may have a Don't Care value because it may not be assigned a value in every possible path through the statements preceding its use -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1306): object rst_ctrl_rxanalogreset used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1307): object rst_ctrl_rxdigitalreset used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1308): object rst_ctrl_xcvr_powerdown used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1309): object rst_ctrl_txdigitalreset used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1645): object phystatus0_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1646): object phystatus1_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1647): object phystatus2_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1648): object phystatus3_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1649): object phystatus4_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1650): object phystatus5_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1651): object phystatus6_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1652): object phystatus7_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1653): object rxdata0_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1654): object rxdata1_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1655): object rxdata2_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1656): object rxdata3_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1657): object rxdata4_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1658): object rxdata5_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1659): object rxdata6_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1660): object rxdata7_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1661): object rxdatak0_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1662): object rxdatak1_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1663): object rxdatak2_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1664): object rxdatak3_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1665): object rxdatak4_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1666): object rxdatak5_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1667): object rxdatak6_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1668): object rxdatak7_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1669): object rxelecidle0_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1670): object rxelecidle1_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1671): object rxelecidle2_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1672): object rxelecidle3_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1673): object rxelecidle4_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1674): object rxelecidle5_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1675): object rxelecidle6_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1676): object rxelecidle7_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1685): object rxstatus0_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1686): object rxstatus1_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1687): object rxstatus2_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1688): object rxstatus3_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1689): object rxstatus4_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1690): object rxstatus5_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1691): object rxstatus6_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1692): object rxstatus7_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1717): object rxvalid0_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1718): object rxvalid1_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1719): object rxvalid2_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1720): object rxvalid3_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1721): object rxvalid4_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1722): object rxvalid5_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1723): object rxvalid6_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1724): object rxvalid7_ext32b used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1726): object pipe32_sim_rxdata0 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1727): object pipe32_sim_rxdata1 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1728): object pipe32_sim_rxdata2 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1729): object pipe32_sim_rxdata3 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1730): object pipe32_sim_rxdata4 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1731): object pipe32_sim_rxdata5 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1732): object pipe32_sim_rxdata6 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1733): object pipe32_sim_rxdata7 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1734): object pipe32_sim_rxdatak0 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1735): object pipe32_sim_rxdatak1 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1736): object pipe32_sim_rxdatak2 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1737): object pipe32_sim_rxdatak3 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1738): object pipe32_sim_rxdatak4 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1739): object pipe32_sim_rxdatak5 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1740): object pipe32_sim_rxdatak6 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1741): object pipe32_sim_rxdatak7 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1742): object pipe32_sim_rxvalid0 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1743): object pipe32_sim_rxvalid1 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1744): object pipe32_sim_rxvalid2 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1745): object pipe32_sim_rxvalid3 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1746): object pipe32_sim_rxvalid4 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1747): object pipe32_sim_rxvalid5 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1748): object pipe32_sim_rxvalid6 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1749): object pipe32_sim_rxvalid7 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1750): object pipe32_sim_rxelecidle0 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1751): object pipe32_sim_rxelecidle1 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1752): object pipe32_sim_rxelecidle2 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1753): object pipe32_sim_rxelecidle3 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1754): object pipe32_sim_rxelecidle4 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1755): object pipe32_sim_rxelecidle5 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1756): object pipe32_sim_rxelecidle6 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1757): object pipe32_sim_rxelecidle7 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1758): object pipe32_sim_phystatus0 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1759): object pipe32_sim_phystatus1 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1760): object pipe32_sim_phystatus2 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1761): object pipe32_sim_phystatus3 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1762): object pipe32_sim_phystatus4 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1763): object pipe32_sim_phystatus5 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1764): object pipe32_sim_phystatus6 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1765): object pipe32_sim_phystatus7 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1766): object pipe32_sim_rxstatus0 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1767): object pipe32_sim_rxstatus1 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1768): object pipe32_sim_rxstatus2 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1769): object pipe32_sim_rxstatus3 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1770): object pipe32_sim_rxstatus4 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1771): object pipe32_sim_rxstatus5 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1772): object pipe32_sim_rxstatus6 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1773): object pipe32_sim_rxstatus7 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1774): object pipe32_sim_rxdataskip0 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1775): object pipe32_sim_rxdataskip1 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1776): object pipe32_sim_rxdataskip2 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1777): object pipe32_sim_rxdataskip3 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1778): object pipe32_sim_rxdataskip4 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1779): object pipe32_sim_rxdataskip5 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1780): object pipe32_sim_rxdataskip6 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1781): object pipe32_sim_rxdataskip7 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1782): object pipe32_sim_rxblkst0 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1783): object pipe32_sim_rxblkst1 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1784): object pipe32_sim_rxblkst2 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1785): object pipe32_sim_rxblkst3 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1786): object pipe32_sim_rxblkst4 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1787): object pipe32_sim_rxblkst5 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1788): object pipe32_sim_rxblkst6 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1789): object pipe32_sim_rxblkst7 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1790): object pipe32_sim_rxsynchd0 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1791): object pipe32_sim_rxsynchd1 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1792): object pipe32_sim_rxsynchd2 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1793): object pipe32_sim_rxsynchd3 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1794): object pipe32_sim_rxsynchd4 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1795): object pipe32_sim_rxsynchd5 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1796): object pipe32_sim_rxsynchd6 used but never assigned -Tue 01:06: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1797): object pipe32_sim_rxsynchd7 used but never assigned -Tue 01:06: INFO : Info (12128): Elaborating entity "altpcie_rs_hip" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|altpcie_rs_hip:g_soft_reset.altpcie_rs_hip" -Tue 01:06: INFO : Warning (10230): Verilog HDL assignment warning at altpcie_rs_hip.v(86): truncated value with size 2 to match size of target (1) -Tue 01:06: INFO : Info (12128): Elaborating entity "sv_xcvr_pipe_native" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_xcvr_pipe_native.sv(452): object "w_pll_tx_pcie_fb_clk" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_xcvr_pipe_native.sv(453): object "w_pll_tx_pll_fb_sw" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "sv_xcvr_emsip_adapter" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_emsip_adapter:sv_xcvr_emsip_adapter_inst" -Tue 01:06: INFO : Warning (10034): Output port "rxfreqtxcmuplllock[4]" at sv_xcvr_emsip_adapter.sv(104) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[916..914]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[912..910]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[812..810]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[808..806]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[708..706]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[704..702]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[604..602]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[600..598]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[500..498]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[496..494]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[396..394]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[392..390]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[292..290]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[288..286]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[188..186]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[184..182]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[84..82]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[80..78]" at sv_xcvr_emsip_adapter.sv(119) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[108]" at sv_xcvr_emsip_adapter.sv(120) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[95]" at sv_xcvr_emsip_adapter.sv(120) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[82]" at sv_xcvr_emsip_adapter.sv(120) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[69]" at sv_xcvr_emsip_adapter.sv(120) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[56]" at sv_xcvr_emsip_adapter.sv(120) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[43]" at sv_xcvr_emsip_adapter.sv(120) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[30]" at sv_xcvr_emsip_adapter.sv(120) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[17]" at sv_xcvr_emsip_adapter.sv(120) has no driver -Tue 01:06: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[4]" at sv_xcvr_emsip_adapter.sv(120) has no driver -Tue 01:06: INFO : Info (12128): Elaborating entity "sv_xcvr_plls" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_plls:sv_xcvr_tx_plls_inst" -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_xcvr_plls.sv(131): object "atx_avmm_blockselect" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_xcvr_plls.sv(132): object "atx_avmm_readdata" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_xcvr_plls.sv(133): object "atx_mux_avmm_blockselect" assigned a value but never read -Tue 01:06: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_xcvr_plls.sv(134): object "atx_mux_avmm_readdata" assigned a value but never read -Tue 01:06: INFO : Info (12128): Elaborating entity "sv_xcvr_native" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native" -Tue 01:06: INFO : Info (12128): Elaborating entity "sv_pma" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma" -Tue 01:06: INFO : Info (12128): Elaborating entity "sv_rx_pma" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_rx_pma:rx_pma.sv_rx_pma_inst" -Tue 01:06: INFO : Warning (10034): Output port "clk33pcs[4]" at sv_rx_pma.sv(90) has no driver -Tue 01:06: INFO : Warning (10034): Output port "rdlpbkp[4]" at sv_rx_pma.sv(109) has no driver -Tue 01:06: INFO : Warning (10034): Output port "rdlpbkn[4]" at sv_rx_pma.sv(110) has no driver -Tue 01:06: INFO : Warning (10034): Output port "refclk_to_cdr[4]" at sv_rx_pma.sv(112) has no driver -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_tx_pma" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_tx_pma_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[0].sv_tx_pma_ch_inst" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_tx_pma_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[4].sv_tx_pma_ch_inst" -Tue 01:07: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_tx_pma_ch.sv(178): object "w_txelecidl" assigned a value but never read -Tue 01:07: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_tx_pma_ch.sv(179): object "w_rxdetclk" assigned a value but never read -Tue 01:07: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_tx_pma_ch.sv(180): object "w_txdetrx" assigned a value but never read -Tue 01:07: INFO : Warning (10034): Output port "avmmreaddata_buf" at sv_tx_pma_ch.sv(131) has no driver -Tue 01:07: INFO : Warning (10034): Output port "dataout" at sv_tx_pma_ch.sv(87) has no driver -Tue 01:07: INFO : Warning (10034): Output port "rxdetectvalid" at sv_tx_pma_ch.sv(88) has no driver -Tue 01:07: INFO : Warning (10034): Output port "rxfound" at sv_tx_pma_ch.sv(89) has no driver -Tue 01:07: INFO : Warning (10034): Output port "blockselect_buf" at sv_tx_pma_ch.sv(134) has no driver -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_pcs" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_pipe_gen1_2_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_pipe_gen1_2_rbc:inst_sv_hssi_pipe_gen1_2" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_common_pcs_pma_interface_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_common_pcs_pma_interface_rbc:inst_sv_hssi_common_pcs_pma_interface" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_pipe_gen3_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_pipe_gen3_rbc:inst_sv_hssi_pipe_gen3" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_tx_pcs_pma_interface_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_tx_pcs_pma_interface_rbc:inst_sv_hssi_tx_pcs_pma_interface" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_tx_pld_pcs_interface_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_tx_pld_pcs_interface_rbc:inst_sv_hssi_tx_pld_pcs_interface" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_common_pld_pcs_interface_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_common_pld_pcs_interface_rbc:inst_sv_hssi_common_pld_pcs_interface" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_rx_pld_pcs_interface_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_rx_pld_pcs_interface_rbc:inst_sv_hssi_rx_pld_pcs_interface" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_rx_pcs_pma_interface_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_rx_pcs_pma_interface_rbc:inst_sv_hssi_rx_pcs_pma_interface" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[1].inst_sv_pcs_ch" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[1].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[1].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[2].inst_sv_pcs_ch" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[2].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[2].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[3].inst_sv_pcs_ch" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[3].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[3].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[4].inst_sv_pcs_ch" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_pipe_gen1_2_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[4].inst_sv_pcs_ch|sv_hssi_pipe_gen1_2_rbc:inst_sv_hssi_pipe_gen1_2" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_pipe_gen3_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[4].inst_sv_pcs_ch|sv_hssi_pipe_gen3_rbc:inst_sv_hssi_pipe_gen3" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[4].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[4].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[5].inst_sv_pcs_ch" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_pipe_gen1_2_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[5].inst_sv_pcs_ch|sv_hssi_pipe_gen1_2_rbc:inst_sv_hssi_pipe_gen1_2" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_pipe_gen3_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[5].inst_sv_pcs_ch|sv_hssi_pipe_gen3_rbc:inst_sv_hssi_pipe_gen3" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[5].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[5].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[6].inst_sv_pcs_ch" -Tue 01:07: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[6].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[6].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[7].inst_sv_pcs_ch" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[7].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[7].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[8].inst_sv_pcs_ch" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[8].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[8].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_xcvr_avmm" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_xcvr_avmm:inst_sv_xcvr_avmm" -Tue 01:08: INFO : Warning (10030): Net "rx_ltrltd_ovr[4]" at sv_xcvr_avmm.sv(179) has no driver or initial value, using a default initial value '0' -Tue 01:08: INFO : Warning (10030): Net "rx_ltr_val[4]" at sv_xcvr_avmm.sv(180) has no driver or initial value, using a default initial value '0' -Tue 01:08: INFO : Warning (10030): Net "rx_ltd_val[4]" at sv_xcvr_avmm.sv(181) has no driver or initial value, using a default initial value '0' -Tue 01:08: INFO : Warning (10034): Output port "pma_eyemonitor[24..20]" at sv_xcvr_avmm.sv(81) has no driver -Tue 01:08: INFO : Warning (10034): Output port "pma_hardoccalen[4]" at sv_xcvr_avmm.sv(82) has no driver -Tue 01:08: INFO : Warning (10034): Output port "pma_adcecapture[4]" at sv_xcvr_avmm.sv(83) has no driver -Tue 01:08: INFO : Warning (10034): Output port "pma_adcestandby[4]" at sv_xcvr_avmm.sv(84) has no driver -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_reconfig_bundle_to_xcvr" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_xcvr_avmm:inst_sv_xcvr_avmm|sv_reconfig_bundle_to_xcvr:avmm_interface_insts[0].sv_reconfig_bundle_to_xcvr_inst" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_xcvr_avmm_csr" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_xcvr_avmm:inst_sv_xcvr_avmm|sv_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_resync" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_xcvr_avmm:inst_sv_xcvr_avmm|sv_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|alt_xcvr_resync:gen_status_reg_tx.alt_xcvr_resync_inst" -Tue 01:08: INFO : Info (12128): Elaborating entity "MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1:pcie_altclkctrl_i" -Tue 01:08: INFO : Info (12128): Elaborating entity "MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1_altclkctrl_blh" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1:pcie_altclkctrl_i|MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1_altclkctrl_blh:MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1_altclkctrl_blh_component" -Tue 01:08: INFO : Warning (10036): Verilog HDL or VHDL warning at MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1.vhd(58): object "clkselect" assigned a value but never read -Tue 01:08: INFO : Info (12128): Elaborating entity "TransceiverReconfig" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i" -Tue 01:08: INFO : Info (12128): Elaborating entity "pcie_xcvr_reconfig_SV" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1" -Tue 01:08: INFO : Warning (10230): Verilog HDL assignment warning at pcie_xcvr_reconfig_SV.v(66): truncated value with size 32 to match size of target (8) -Tue 01:08: INFO : Info (12128): Elaborating entity "pcie_reconfig_SV" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst" -Tue 01:08: INFO : Warning (10036): Verilog HDL or VHDL warning at alt_xcvr_reconfig.sv(200): object "done" assigned a value but never read -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_resync" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_resync:inst_reconfig_reset_sync" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_arbiter" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_arbiter:arbiter" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_direct" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_direct:direct.sc_direct" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_arbiter_acq" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_direct:direct.sc_direct|alt_arbiter_acq:mutex_inst" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_soc" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_reconfig_cpu" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench:the_alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a" -Tue 01:08: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a|altsyncram:the_altsyncram" -Tue 01:08: INFO : Info (12130): Elaborated megafunction instantiation "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a|altsyncram:the_altsyncram" -Tue 01:08: INFO : Info (12133): Instantiated megafunction "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a|altsyncram:the_altsyncram" with the following parameter: -Tue 01:08: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" -Tue 01:08: INFO : Info (12134): Parameter "init_file" = "alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_a.mif" -Tue 01:08: INFO : Info (12134): Parameter "maximum_depth" = "0" -Tue 01:08: INFO : Info (12134): Parameter "numwords_a" = "32" -Tue 01:08: INFO : Info (12134): Parameter "numwords_b" = "32" -Tue 01:08: INFO : Info (12134): Parameter "operation_mode" = "DUAL_PORT" -Tue 01:08: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" -Tue 01:08: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" -Tue 01:08: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" -Tue 01:08: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" -Tue 01:08: INFO : Info (12134): Parameter "width_a" = "32" -Tue 01:08: INFO : Info (12134): Parameter "width_b" = "32" -Tue 01:08: INFO : Info (12134): Parameter "widthad_a" = "5" -Tue 01:08: INFO : Info (12134): Parameter "widthad_b" = "5" -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_b5t1.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: altsyncram_b5t1 -Tue 01:08: INFO : Info (12128): Elaborating entity "altsyncram_b5t1" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_b5t1:auto_generated" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b" -Tue 01:08: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b|altsyncram:the_altsyncram" -Tue 01:08: INFO : Info (12130): Elaborated megafunction instantiation "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b|altsyncram:the_altsyncram" -Tue 01:08: INFO : Info (12133): Instantiated megafunction "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b|altsyncram:the_altsyncram" with the following parameter: -Tue 01:08: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" -Tue 01:08: INFO : Info (12134): Parameter "init_file" = "alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_b.mif" -Tue 01:08: INFO : Info (12134): Parameter "maximum_depth" = "0" -Tue 01:08: INFO : Info (12134): Parameter "numwords_a" = "32" -Tue 01:08: INFO : Info (12134): Parameter "numwords_b" = "32" -Tue 01:08: INFO : Info (12134): Parameter "operation_mode" = "DUAL_PORT" -Tue 01:08: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" -Tue 01:08: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" -Tue 01:08: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" -Tue 01:08: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" -Tue 01:08: INFO : Info (12134): Parameter "width_a" = "32" -Tue 01:08: INFO : Info (12134): Parameter "width_b" = "32" -Tue 01:08: INFO : Info (12134): Parameter "widthad_a" = "5" -Tue 01:08: INFO : Info (12134): Parameter "widthad_b" = "5" -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_c5t1.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: altsyncram_c5t1 -Tue 01:08: INFO : Info (12128): Elaborating entity "altsyncram_c5t1" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_c5t1:auto_generated" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:reconfig_cpu_data_master_translator" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:reconfig_cpu_instruction_master_translator" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:reconfig_mem_mem_translator" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:reconfig_ctrl_ctrl_translator" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:reconfig_cpu_data_master_translator_avalon_universal_master_0_agent" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:reconfig_cpu_instruction_master_translator_avalon_universal_master_0_agent" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:reconfig_mem_mem_translator_avalon_universal_slave_0_agent" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:reconfig_mem_mem_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:reconfig_mem_mem_translator_avalon_universal_slave_0_agent_rsp_fifo" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router:addr_router" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_default_decode" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router:addr_router|alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_default_decode:the_default_decode" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001:addr_router_001" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001_default_decode" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001:addr_router_001|alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001_default_decode:the_default_decode" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router:id_router" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_default_decode" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router:id_router|alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_default_decode:the_default_decode" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001:id_router_001" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001_default_decode" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001:id_router_001|alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001_default_decode:the_default_decode" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux_001" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux_001:cmd_xbar_demux_001" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux:cmd_xbar_mux" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux_001" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux_001:cmd_xbar_mux_001" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux_001" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux_001:rsp_xbar_mux_001" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_irq_mapper" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_irq_mapper:irq_mapper" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|altera_reset_controller:rst_controller" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_ram" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu_ram:alt_xcvr_reconfig_cpu_ram_inst" -Tue 01:08: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu_ram:alt_xcvr_reconfig_cpu_ram_inst|altsyncram:altsyncram_component" -Tue 01:08: INFO : Info (12130): Elaborated megafunction instantiation "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu_ram:alt_xcvr_reconfig_cpu_ram_inst|altsyncram:altsyncram_component" -Tue 01:08: INFO : Info (12133): Instantiated megafunction "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu_ram:alt_xcvr_reconfig_cpu_ram_inst|altsyncram:altsyncram_component" with the following parameter: -Tue 01:08: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" -Tue 01:08: INFO : Info (12134): Parameter "byteena_reg_b" = "CLOCK0" -Tue 01:08: INFO : Info (12134): Parameter "byte_size" = "8" -Tue 01:08: INFO : Info (12134): Parameter "clock_enable_input_a" = "NORMAL" -Tue 01:08: INFO : Info (12134): Parameter "clock_enable_input_b" = "NORMAL" -Tue 01:08: INFO : Info (12134): Parameter "clock_enable_output_a" = "NORMAL" -Tue 01:08: INFO : Info (12134): Parameter "clock_enable_output_b" = "NORMAL" -Tue 01:08: INFO : Info (12134): Parameter "indata_reg_b" = "CLOCK0" -Tue 01:08: INFO : Info (12134): Parameter "init_file" = "alt_xcvr_reconfig_cpu_ram.hex" -Tue 01:08: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" -Tue 01:08: INFO : Info (12134): Parameter "lpm_type" = "altsyncram" -Tue 01:08: INFO : Info (12134): Parameter "numwords_a" = "1024" -Tue 01:08: INFO : Info (12134): Parameter "numwords_b" = "1024" -Tue 01:08: INFO : Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT" -Tue 01:08: INFO : Info (12134): Parameter "outdata_aclr_a" = "NONE" -Tue 01:08: INFO : Info (12134): Parameter "outdata_aclr_b" = "NONE" -Tue 01:08: INFO : Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" -Tue 01:08: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" -Tue 01:08: INFO : Info (12134): Parameter "power_up_uninitialized" = "FALSE" -Tue 01:08: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" -Tue 01:08: INFO : Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" -Tue 01:08: INFO : Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" -Tue 01:08: INFO : Info (12134): Parameter "widthad_a" = "10" -Tue 01:08: INFO : Info (12134): Parameter "widthad_b" = "10" -Tue 01:08: INFO : Info (12134): Parameter "width_a" = "32" -Tue 01:08: INFO : Info (12134): Parameter "width_b" = "32" -Tue 01:08: INFO : Info (12134): Parameter "width_byteena_a" = "4" -Tue 01:08: INFO : Info (12134): Parameter "width_byteena_b" = "4" -Tue 01:08: INFO : Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ru53.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: altsyncram_ru53 -Tue 01:08: INFO : Info (12128): Elaborating entity "altsyncram_ru53" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu_ram:alt_xcvr_reconfig_cpu_ram_inst|altsyncram:altsyncram_component|altsyncram_ru53:auto_generated" -Tue 01:08: INFO : Warning (113015): Width of data items in "alt_xcvr_reconfig_cpu_ram.hex" is greater than the memory width. Wrapping data items to subsequent addresses. Found 128 warnings, reporting 10 -Tue 01:08: INFO : Warning (113009): Data at line (2) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. -Tue 01:08: INFO : Warning (113009): Data at line (3) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. -Tue 01:08: INFO : Warning (113009): Data at line (4) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. -Tue 01:08: INFO : Warning (113009): Data at line (5) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. -Tue 01:08: INFO : Warning (113009): Data at line (6) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. -Tue 01:08: INFO : Warning (113009): Data at line (7) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. -Tue 01:08: INFO : Warning (113009): Data at line (8) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. -Tue 01:08: INFO : Warning (113009): Data at line (9) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. -Tue 01:08: INFO : Warning (113009): Data at line (10) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. -Tue 01:08: INFO : Warning (113009): Data at line (11) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. -Tue 01:08: INFO : Info (12128): Elaborating entity "altera_wait_generate" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|altera_wait_generate:altera_wait_generate_inst" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cal_seq" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_cal_seq:cal_seq" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_basic" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_xcvr_reconfig_basic" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_xrbasic_lif" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_xrbasic_lif_csr" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|sv_xrbasic_lif_csr:lif_csr" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_xrbasic_l2p_rom" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|sv_xrbasic_lif_csr:lif_csr|sv_xrbasic_l2p_rom:l2pch" -Tue 01:08: INFO : Warning (10030): Net "rom_l2p_ch.data_a" at sv_xrbasic_l2p_rom.sv(59) has no driver or initial value, using a default initial value '0' -Tue 01:08: INFO : Warning (10030): Net "rom_l2p_ch.waddr_a" at sv_xrbasic_l2p_rom.sv(59) has no driver or initial value, using a default initial value '0' -Tue 01:08: INFO : Warning (10030): Net "rom_l2p_ch.we_a" at sv_xrbasic_l2p_rom.sv(59) has no driver or initial value, using a default initial value '0' -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_xrbasic_l2p_addr" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|sv_xrbasic_lif_csr:lif_csr|sv_xrbasic_l2p_addr:l2paddr" -Tue 01:08: INFO : Info (12128): Elaborating entity "csr_mux" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|csr_mux:pif_tbus_mux" -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_xcvr_arbiter" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|alt_xcvr_arbiter:pif[0].pif_arb" -Tue 01:08: INFO : Info (12128): Elaborating entity "sv_reconfig_bundle_to_basic" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_reconfig_bundle_to_basic:bundle" -Tue 01:08: INFO : Info (12128): Elaborating entity "MAX4CPLDInterface" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level" -Tue 01:08: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4CPLDInterface.vhdl(328): object "cpld_io_ext_inst_maxring_a_top_sb_fb" assigned a value but never read -Tue 01:08: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4CPLDInterface.vhdl(329): object "cpld_io_ext_inst_maxring_a_bottom_sb_fb" assigned a value but never read -Tue 01:08: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4CPLDInterface.vhdl(330): object "cpld_io_ext_inst_maxring_b_modtx_sb_fb" assigned a value but never read -Tue 01:08: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4CPLDInterface.vhdl(331): object "cpld_io_ext_inst_maxring_b_modrx_sb_fb" assigned a value but never read -Tue 01:08: INFO : Info (12128): Elaborating entity "max4_cpld_ioexpand" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_ioexpand:cpld_io_ext_inst" -Tue 01:08: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_TOP_ALERT" at max4_cpld_ioexpand.vhd(59) -Tue 01:08: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_TOP_SDA_fb" at max4_cpld_ioexpand.vhd(61) -Tue 01:08: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_TOP_SCL_fb" at max4_cpld_ioexpand.vhd(63) -Tue 01:08: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_TOP_modprsl" at max4_cpld_ioexpand.vhd(64) -Tue 01:08: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_MID_ALERT" at max4_cpld_ioexpand.vhd(69) -Tue 01:08: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_MID_SDA_fb" at max4_cpld_ioexpand.vhd(71) -Tue 01:08: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_MID_SCL_fb" at max4_cpld_ioexpand.vhd(73) -Tue 01:08: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_MID_modprsl" at max4_cpld_ioexpand.vhd(74) -Tue 01:08: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_BOT_ALERT" at max4_cpld_ioexpand.vhd(79) -Tue 01:08: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_BOT_SDA_fb" at max4_cpld_ioexpand.vhd(81) -Tue 01:08: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_BOT_SCL_fb" at max4_cpld_ioexpand.vhd(83) -Tue 01:08: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_BOT_modprsl" at max4_cpld_ioexpand.vhd(84) -Tue 01:08: INFO : Info (12128): Elaborating entity "MAXEvents" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|MAXEvents:max_events" -Tue 01:08: INFO : Info (12128): Elaborating entity "max_events" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|MAXEvents:max_events|max_events:inst_ln89_maxevents" -Tue 01:08: INFO : Info (12128): Elaborating entity "max4_cpld_flash_if" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst" -Tue 01:08: INFO : Warning (272007): Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 -Tue 01:08: INFO : Info (12128): Elaborating entity "dcfifo_mixed_widths" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo" -Tue 01:08: INFO : Info (12130): Elaborated megafunction instantiation "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo" -Tue 01:08: INFO : Info (12133): Instantiated megafunction "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo" with the following parameter: -Tue 01:08: INFO : Info (12134): Parameter "add_ram_output_register" = "OFF" -Tue 01:08: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" -Tue 01:08: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" -Tue 01:08: INFO : Info (12134): Parameter "delay_rdusedw" = "1" -Tue 01:08: INFO : Info (12134): Parameter "delay_wrusedw" = "1" -Tue 01:08: INFO : Info (12134): Parameter "intended_device_family" = "unused" -Tue 01:08: INFO : Info (12134): Parameter "lpm_numwords" = "512" -Tue 01:08: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:08: INFO : Info (12134): Parameter "lpm_width" = "64" -Tue 01:08: INFO : Info (12134): Parameter "lpm_width_r" = "64" -Tue 01:08: INFO : Info (12134): Parameter "lpm_widthu" = "9" -Tue 01:08: INFO : Info (12134): Parameter "lpm_widthu_r" = "9" -Tue 01:08: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:08: INFO : Info (12134): Parameter "rdsync_delaypipe" = "0" -Tue 01:08: INFO : Info (12134): Parameter "read_aclr_synch" = "OFF" -Tue 01:08: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:08: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:08: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" -Tue 01:08: INFO : Info (12134): Parameter "wrsync_delaypipe" = "0" -Tue 01:08: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" -Tue 01:08: INFO : Info (12134): Parameter "lpm_type" = "dcfifo_mixed_widths" -Tue 01:08: INFO : Warning (287001): Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_hj62.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: dcfifo_hj62 -Tue 01:08: INFO : Info (12128): Elaborating entity "dcfifo_hj62" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated" -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_c8e1.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: altsyncram_c8e1 -Tue 01:08: INFO : Info (12128): Elaborating entity "altsyncram_c8e1" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram" -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_6md.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: alt_synch_pipe_6md -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_synch_pipe_6md" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|alt_synch_pipe_6md:rs_dgwp" -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_5f9.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: dffpipe_5f9 -Tue 01:08: INFO : Info (12128): Elaborating entity "dffpipe_5f9" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|alt_synch_pipe_6md:rs_dgwp|dffpipe_5f9:dffpipe6" -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_7md.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: alt_synch_pipe_7md -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_synch_pipe_7md" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|alt_synch_pipe_7md:ws_dgrp" -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_6f9.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: dffpipe_6f9 -Tue 01:08: INFO : Info (12128): Elaborating entity "dffpipe_6f9" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|alt_synch_pipe_7md:ws_dgrp|dffpipe_6f9:dffpipe9" -Tue 01:08: INFO : Warning (272007): Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 -Tue 01:08: INFO : Info (12128): Elaborating entity "dcfifo_mixed_widths" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo" -Tue 01:08: INFO : Info (12130): Elaborated megafunction instantiation "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo" -Tue 01:08: INFO : Info (12133): Instantiated megafunction "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo" with the following parameter: -Tue 01:08: INFO : Info (12134): Parameter "add_ram_output_register" = "OFF" -Tue 01:08: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" -Tue 01:08: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" -Tue 01:08: INFO : Info (12134): Parameter "delay_rdusedw" = "1" -Tue 01:08: INFO : Info (12134): Parameter "delay_wrusedw" = "1" -Tue 01:08: INFO : Info (12134): Parameter "intended_device_family" = "unused" -Tue 01:08: INFO : Info (12134): Parameter "lpm_numwords" = "512" -Tue 01:08: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" -Tue 01:08: INFO : Info (12134): Parameter "lpm_width" = "64" -Tue 01:08: INFO : Info (12134): Parameter "lpm_width_r" = "64" -Tue 01:08: INFO : Info (12134): Parameter "lpm_widthu" = "9" -Tue 01:08: INFO : Info (12134): Parameter "lpm_widthu_r" = "9" -Tue 01:08: INFO : Info (12134): Parameter "overflow_checking" = "ON" -Tue 01:08: INFO : Info (12134): Parameter "rdsync_delaypipe" = "0" -Tue 01:08: INFO : Info (12134): Parameter "read_aclr_synch" = "OFF" -Tue 01:08: INFO : Info (12134): Parameter "underflow_checking" = "ON" -Tue 01:08: INFO : Info (12134): Parameter "use_eab" = "ON" -Tue 01:08: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" -Tue 01:08: INFO : Info (12134): Parameter "wrsync_delaypipe" = "0" -Tue 01:08: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" -Tue 01:08: INFO : Info (12134): Parameter "lpm_type" = "dcfifo_mixed_widths" -Tue 01:08: INFO : Warning (287001): Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_0q52.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: dcfifo_0q52 -Tue 01:08: INFO : Info (12128): Elaborating entity "dcfifo_0q52" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo|dcfifo_0q52:auto_generated" -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_8md.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: alt_synch_pipe_8md -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_synch_pipe_8md" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo|dcfifo_0q52:auto_generated|alt_synch_pipe_8md:rs_dgwp" -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_7f9.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: dffpipe_7f9 -Tue 01:08: INFO : Info (12128): Elaborating entity "dffpipe_7f9" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo|dcfifo_0q52:auto_generated|alt_synch_pipe_8md:rs_dgwp|dffpipe_7f9:dffpipe5" -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_9md.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: alt_synch_pipe_9md -Tue 01:08: INFO : Info (12128): Elaborating entity "alt_synch_pipe_9md" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo|dcfifo_0q52:auto_generated|alt_synch_pipe_9md:ws_dgrp" -Tue 01:08: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_8f9.tdf -Tue 01:08: INFO : Info (12023): Found entity 1: dffpipe_8f9 -Tue 01:08: INFO : Info (12128): Elaborating entity "dffpipe_8f9" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo|dcfifo_0q52:auto_generated|alt_synch_pipe_9md:ws_dgrp|dffpipe_8f9:dffpipe8" -Tue 01:08: INFO : Warning (12030): Port "rx_cal_busy" on the entity instantiation of "inst_sv_xcvr_native" is connected to a signal of width 8. The formal width of the signal in the module is 9. The extra bits will be left dangling without any fan-out logic. -Tue 01:08: INFO : Warning (12030): Port "tx_cal_busy" on the entity instantiation of "inst_sv_xcvr_native" is connected to a signal of width 8. The formal width of the signal in the module is 9. The extra bits will be left dangling without any fan-out logic. -Tue 01:08: INFO : Warning (12030): Port "rx_signaldetect" on the entity instantiation of "sv_xcvr_emsip_adapter_inst" is connected to a signal of width 9. The formal width of the signal in the module is 8. The extra bits will be left dangling without any fan-out logic. -Tue 01:08: INFO : Info (12206): 2 design partitions require synthesis -Tue 01:08: INFO : Info (12210): Partition "Top" requires synthesis because its netlist type is Source File -Tue 01:08: INFO : Info (12210): Partition "MAX4FPGATop:MAX4MaiaFabricTop_i" requires synthesis because its netlist type is Source File -Tue 01:08: INFO : Info (12209): No design partitions will skip synthesis in the current incremental compilation -Tue 01:08: INFO : Warning (14284): Synthesized away the following node(s): -Tue 01:08: INFO : Warning (14285): Synthesized away the following LCELL buffer node(s): -Tue 01:08: INFO : Warning (14320): Synthesized away node "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|phase_done" -Tue 01:08: INFO : Warning (14320): Synthesized away node "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dprio_read" -Tue 01:08: INFO : Warning (14285): Synthesized away the following RAM node(s): -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[16]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[17]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[18]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[19]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[20]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[21]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[22]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[23]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[24]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[25]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[26]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[27]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[28]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[29]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[30]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[31]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[58]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[59]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[60]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[61]" -Tue 01:08: INFO : Warning (14284): Synthesized away the following node(s): -Tue 01:08: INFO : Warning (14285): Synthesized away the following RAM node(s): -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[34]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[35]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[36]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[37]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[38]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[39]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[40]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[41]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[42]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[43]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[44]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[45]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[46]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[47]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[48]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[49]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[50]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[51]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[52]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[53]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[54]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[55]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[56]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[57]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[58]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[59]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[60]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[61]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[62]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[63]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|dpram_emb1:FIFOram|altsyncram_8ou1:altsyncram1|q_b[11]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|dpram_emb1:FIFOram|altsyncram_8ou1:altsyncram1|q_b[12]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[2]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[3]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[4]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[5]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[6]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[7]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[8]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[9]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[10]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[11]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[12]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[13]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[14]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[15]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[16]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[17]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[18]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[19]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[20]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[21]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[22]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[23]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[24]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[25]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[26]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[27]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[28]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[29]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[30]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[31]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[2]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[3]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[4]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[5]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[6]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[7]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[8]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[9]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[10]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[11]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[12]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[13]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[14]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[15]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[16]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[17]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[18]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[19]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[20]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[21]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[22]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[23]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[24]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[25]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[26]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[27]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[28]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[29]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[30]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[31]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[0]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[1]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[2]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[3]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[4]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[5]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[6]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[7]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[5]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[6]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[7]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[8]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[9]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[10]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[11]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[12]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[13]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[14]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[15]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[16]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[17]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[18]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[19]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[20]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[21]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[22]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[23]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[24]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[25]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[26]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[27]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[28]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[29]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[30]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[31]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[5]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[6]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[7]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[8]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[9]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[10]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[11]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[12]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[13]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[14]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[15]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[16]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[17]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[18]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[19]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[20]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[21]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[22]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[23]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[24]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[25]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[26]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[27]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[28]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[29]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[30]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[31]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[5]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[6]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[7]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[8]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[9]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[10]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[11]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[12]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[13]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[14]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[15]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[16]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[17]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[18]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[19]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[20]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[21]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[22]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[23]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[24]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[25]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[26]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[27]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[28]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[29]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[30]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[31]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[5]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[6]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[7]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[8]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[9]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[10]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[11]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[12]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[13]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[14]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[15]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[16]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[17]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[18]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[19]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[20]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[21]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[22]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[23]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[24]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[25]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[26]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[27]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[28]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[29]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[30]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[31]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[0]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[1]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[72]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[82]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[83]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[84]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[85]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[86]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[87]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[88]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[89]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[90]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[91]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[92]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[93]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[94]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[95]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[96]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[97]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[98]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[99]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[100]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[101]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[102]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[103]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[104]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[105]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[106]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[107]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[108]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[109]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[110]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[111]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[112]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[113]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[114]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[0]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[1]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[2]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[3]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[4]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[5]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[6]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[7]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[8]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[9]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[10]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[11]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[12]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[13]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[14]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[15]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[16]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[17]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[18]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[19]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[20]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[21]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[22]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[23]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[24]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[25]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[26]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[0]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[1]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[2]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[3]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[4]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[5]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[6]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[7]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[8]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[9]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[10]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[11]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[12]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[13]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[14]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[15]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[16]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[17]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[18]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[19]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[20]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[21]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[22]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[23]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[24]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[25]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[26]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[32]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[33]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[34]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[35]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[36]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[37]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[38]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[39]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[40]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[41]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[42]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[43]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[44]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[45]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[46]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[47]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[48]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[49]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[50]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[51]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[52]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[53]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[54]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[55]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[56]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[57]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[58]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[64]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[65]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[66]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[67]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[68]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[69]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[70]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[71]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[72]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[73]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[74]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[75]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[76]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[77]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[78]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[79]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[80]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[81]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[82]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[83]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[84]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[85]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[86]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[87]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[88]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[89]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[90]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[96]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[97]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[98]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[99]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[100]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[101]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[102]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[103]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[104]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[105]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[106]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[107]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[108]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[109]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[110]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[111]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[112]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[113]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[114]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[115]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[116]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[117]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[118]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[119]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[120]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[121]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[122]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[0]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[2]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[17]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[18]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[35]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[36]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[37]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[38]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[39]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[40]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[41]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[42]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[43]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[44]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[45]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[46]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[47]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[48]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[49]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[50]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[51]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[52]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[53]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[54]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[55]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[56]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[57]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[58]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[59]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[60]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[61]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[62]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[63]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[64]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[65]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[66]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[67]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[68]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[69]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[70]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[0]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[12]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[13]" -Tue 01:08: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[14]" -Tue 01:09: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[15]" -Tue 01:09: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[16]" -Tue 01:09: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[17]" -Tue 01:09: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[18]" -Tue 01:09: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[67]" -Tue 01:09: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[68]" -Tue 01:09: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[69]" -Tue 01:09: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[70]" -Tue 01:09: INFO : Info (286031): Timing-Driven Synthesis is running on partition "Top" -Tue 01:09: INFO : Warning (14284): Synthesized away the following node(s): -Tue 01:09: INFO : Warning (14285): Synthesized away the following LCELL buffer node(s): -Tue 01:09: INFO : Warning (14320): Synthesized away node "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst|gnd" -Tue 01:09: INFO : Info (19000): Inferred 1 megafunctions from design logic -Tue 01:09: INFO : Info (276029): Inferred altsyncram megafunction from the following design logic: "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|sv_xrbasic_lif_csr:lif_csr|sv_xrbasic_l2p_rom:l2pch|rom_l2p_ch_rtl_0" -Tue 01:09: INFO : Info (286033): Parameter OPERATION_MODE set to BIDIR_DUAL_PORT -Tue 01:09: INFO : Info (286033): Parameter WIDTH_A set to 32 -Tue 01:09: INFO : Info (286033): Parameter WIDTH_B set to 32 -Tue 01:09: INFO : Info (286033): Parameter WIDTHAD_A set to 7 -Tue 01:09: INFO : Info (286033): Parameter WIDTHAD_B set to 7 -Tue 01:09: INFO : Info (286033): Parameter NUMWORDS_A set to 128 -Tue 01:09: INFO : Info (286033): Parameter NUMWORDS_B set to 128 -Tue 01:09: INFO : Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED -Tue 01:09: INFO : Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED -Tue 01:09: INFO : Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 -Tue 01:09: INFO : Info (286033): Parameter INDATA_REG_B set to CLOCK0 -Tue 01:09: INFO : Info (286033): Parameter WRCONTROL_WRADDRESS_REG_B set to CLOCK0 -Tue 01:09: INFO : Info (286033): Parameter INDATA_ACLR_A set to NONE -Tue 01:09: INFO : Info (286033): Parameter WRCONTROL_ACLR_A set to NONE -Tue 01:09: INFO : Info (286033): Parameter ADDRESS_ACLR_A set to NONE -Tue 01:09: INFO : Info (286033): Parameter ADDRESS_ACLR_B set to NONE -Tue 01:09: INFO : Info (286033): Parameter OUTDATA_ACLR_B set to NONE -Tue 01:09: INFO : Info (286033): Parameter RAM_BLOCK_TYPE set to M20K -Tue 01:09: INFO : Info (286033): Parameter INIT_FILE set to db/MAX4MAIAPeripheryTop.ram0_sv_xrbasic_l2p_rom_a2c9d7fe.hdl.mif -Tue 01:09: INFO : Info (12130): Elaborated megafunction instantiation "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|sv_xrbasic_lif_csr:lif_csr|sv_xrbasic_l2p_rom:l2pch|altsyncram:rom_l2p_ch_rtl_0" -Tue 01:09: INFO : Info (12133): Instantiated megafunction "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|sv_xrbasic_lif_csr:lif_csr|sv_xrbasic_l2p_rom:l2pch|altsyncram:rom_l2p_ch_rtl_0" with the following parameter: -Tue 01:09: INFO : Info (12134): Parameter "OPERATION_MODE" = "BIDIR_DUAL_PORT" -Tue 01:09: INFO : Info (12134): Parameter "WIDTH_A" = "32" -Tue 01:09: INFO : Info (12134): Parameter "WIDTH_B" = "32" -Tue 01:09: INFO : Info (12134): Parameter "WIDTHAD_A" = "7" -Tue 01:09: INFO : Info (12134): Parameter "WIDTHAD_B" = "7" -Tue 01:09: INFO : Info (12134): Parameter "NUMWORDS_A" = "128" -Tue 01:09: INFO : Info (12134): Parameter "NUMWORDS_B" = "128" -Tue 01:09: INFO : Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED" -Tue 01:09: INFO : Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" -Tue 01:09: INFO : Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" -Tue 01:09: INFO : Info (12134): Parameter "INDATA_REG_B" = "CLOCK0" -Tue 01:09: INFO : Info (12134): Parameter "WRCONTROL_WRADDRESS_REG_B" = "CLOCK0" -Tue 01:09: INFO : Info (12134): Parameter "INDATA_ACLR_A" = "NONE" -Tue 01:09: INFO : Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" -Tue 01:09: INFO : Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" -Tue 01:09: INFO : Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" -Tue 01:09: INFO : Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" -Tue 01:09: INFO : Info (12134): Parameter "RAM_BLOCK_TYPE" = "M20K" -Tue 01:09: INFO : Info (12134): Parameter "INIT_FILE" = "db/MAX4MAIAPeripheryTop.ram0_sv_xrbasic_l2p_rom_a2c9d7fe.hdl.mif" -Tue 01:09: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_dr72.tdf -Tue 01:09: INFO : Info (12023): Found entity 1: altsyncram_dr72 -Tue 01:09: INFO : Info (19000): Inferred 2 megafunctions from design logic -Tue 01:09: INFO : Info (276034): Inferred altshift_taps megafunction from the following design logic: "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_24_5:node_id143_nodewordlevelshift|reg_ln457_shifter2_rtl_0" -Tue 01:09: INFO : Info (286033): Parameter NUMBER_OF_TAPS set to 1 -Tue 01:09: INFO : Info (286033): Parameter TAP_DISTANCE set to 5 -Tue 01:09: INFO : Info (286033): Parameter WIDTH set to 23 -Tue 01:09: INFO : Info (286033): Parameter POWER_UP_STATE set to DONT_CARE -Tue 01:10: INFO : Info (276034): Inferred altshift_taps megafunction from the following design logic: "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830:inst_ln130_mappedregblock|mapped_register:inst_ln504_mappedregblock|mapped_registers_rtl_0" -Tue 01:10: INFO : Info (286033): Parameter NUMBER_OF_TAPS set to 1 -Tue 01:10: INFO : Info (286033): Parameter TAP_DISTANCE set to 4 -Tue 01:10: INFO : Info (286033): Parameter WIDTH set to 8 -Tue 01:10: INFO : Info (286033): Parameter POWER_UP_STATE set to DONT_CARE -Tue 01:10: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_24_5:node_id143_nodewordlevelshift|altshift_taps:reg_ln457_shifter2_rtl_0" -Tue 01:10: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_24_5:node_id143_nodewordlevelshift|altshift_taps:reg_ln457_shifter2_rtl_0" with the following parameter: -Tue 01:10: INFO : Info (12134): Parameter "NUMBER_OF_TAPS" = "1" -Tue 01:10: INFO : Info (12134): Parameter "TAP_DISTANCE" = "5" -Tue 01:10: INFO : Info (12134): Parameter "WIDTH" = "23" -Tue 01:10: INFO : Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" -Tue 01:10: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_2u31.tdf -Tue 01:10: INFO : Info (12023): Found entity 1: shift_taps_2u31 -Tue 01:10: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_d9e1.tdf -Tue 01:10: INFO : Info (12023): Found entity 1: altsyncram_d9e1 -Tue 01:10: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_tif.tdf -Tue 01:10: INFO : Info (12023): Found entity 1: cntr_tif -Tue 01:10: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_dac.tdf -Tue 01:10: INFO : Info (12023): Found entity 1: cmpr_dac -Tue 01:10: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830:inst_ln130_mappedregblock|mapped_register:inst_ln504_mappedregblock|altshift_taps:mapped_registers_rtl_0" -Tue 01:10: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830:inst_ln130_mappedregblock|mapped_register:inst_ln504_mappedregblock|altshift_taps:mapped_registers_rtl_0" with the following parameter: -Tue 01:10: INFO : Info (12134): Parameter "NUMBER_OF_TAPS" = "1" -Tue 01:10: INFO : Info (12134): Parameter "TAP_DISTANCE" = "4" -Tue 01:10: INFO : Info (12134): Parameter "WIDTH" = "8" -Tue 01:10: INFO : Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" -Tue 01:10: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_ks31.tdf -Tue 01:10: INFO : Info (12023): Found entity 1: shift_taps_ks31 -Tue 01:10: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_f6e1.tdf -Tue 01:10: INFO : Info (12023): Found entity 1: altsyncram_f6e1 -Tue 01:10: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_rif.tdf -Tue 01:10: INFO : Info (12023): Found entity 1: cntr_rif -Tue 01:10: INFO : Warning (12241): 5 hierarchies have connectivity warnings - see the Connectivity Checks report folder -Tue 01:10: INFO : Info (281020): Starting Logic Optimization and Technology Mapping for Top Partition -Tue 01:10: INFO : Info (17049): 179 registers lost all their fanouts during netlist optimizations. -Tue 01:10: INFO : Info (21057): Implemented 3303 device resources after synthesis - the final resource count might be different -Tue 01:10: INFO : Info (21058): Implemented 18 input pins -Tue 01:10: INFO : Info (21059): Implemented 10 output pins -Tue 01:10: INFO : Info (21060): Implemented 26 bidirectional pins -Tue 01:10: INFO : Info (21061): Implemented 2832 logic cells -Tue 01:10: INFO : Info (21064): Implemented 236 RAM segments -Tue 01:10: INFO : Info (21065): Implemented 2 PLLs -Tue 01:10: INFO : Info (21071): Implemented 1 partitions -Tue 01:10: INFO : Info (281019): Starting Logic Optimization and Technology Mapping for Partition MAX4FPGATop:MAX4MaiaFabricTop_i -Tue 01:10: INFO : Critical Warning (18061): Ignored Power-Up Level option on the following registers -Tue 01:10: INFO : Critical Warning (18010): Register MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|mapped_elements_reset_i will power up to Low -Tue 01:10: INFO : Info (17049): 340 registers lost all their fanouts during netlist optimizations. -Tue 01:10: INFO : Info (21057): Implemented 32900 device resources after synthesis - the final resource count might be different -Tue 01:10: INFO : Info (21058): Implemented 364 input pins -Tue 01:10: INFO : Info (21059): Implemented 317 output pins -Tue 01:10: INFO : Info (21061): Implemented 27558 logic cells -Tue 01:10: INFO : Info (21064): Implemented 4661 RAM segments -Tue 01:10: INFO : Info (144001): Generated suppressed messages file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/map/altera_quartus/MAX4MAIAPeripheryTop.map.smsg -Tue 01:10: INFO : Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1007 warnings -Tue 01:10: INFO : Info: Peak virtual memory: 2095 megabytes -Tue 01:10: INFO : Info: Processing ended: Tue Aug 25 01:10:52 2015 -Tue 01:10: INFO : Info: Elapsed time: 00:05:48 -Tue 01:10: INFO : Info: Total CPU time (on all processors): 00:05:44 -Tue 01:10: INFO : quartus_map ended (01:10:53 25/08/15, time elapsed: 5 mins, 53 secs) -Tue 01:10: INFO : quartus_map peak virtual memory: 2095 -Tue 01:10: INFO : Build pass 'QuartusMap' took 353.827 s. -Tue 01:10: PROGRESS: (3/16) - Generate Incremental Netlist (QuartusCdb) -Tue 01:10: INFO : Starting quartus_cdb. (01:10:53 25/08/15) -Tue 01:10: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_cdb MAX4MAIAPeripheryTop --64bit --write_settings_files=off --merge=on -Tue 01:11: INFO : Info: ******************************************************************* -Tue 01:11: INFO : Info: Running Quartus II 64-Bit Partition Merge -Tue 01:11: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version -Tue 01:11: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. -Tue 01:11: INFO : Info: Your use of Altera Corporation's design tools, logic functions -Tue 01:11: INFO : Info: and other software and tools, and its AMPP partner logic -Tue 01:11: INFO : Info: functions, and any output files from any of the foregoing -Tue 01:11: INFO : Info: (including device programming or simulation files), and any -Tue 01:11: INFO : Info: associated documentation or information are expressly subject -Tue 01:11: INFO : Info: to the terms and conditions of the Altera Program License -Tue 01:11: INFO : Info: Subscription Agreement, Altera MegaCore Function License -Tue 01:11: INFO : Info: Agreement, or other applicable license agreement, including, -Tue 01:11: INFO : Info: without limitation, that your use is for the sole purpose of -Tue 01:11: INFO : Info: programming logic devices manufactured by Altera and sold by -Tue 01:11: INFO : Info: Altera or its authorized distributors. Please refer to the -Tue 01:11: INFO : Info: applicable agreement for further details. -Tue 01:11: INFO : Info: Processing started: Tue Aug 25 01:10:57 2015 -Tue 01:11: INFO : Info: Command: quartus_cdb MAX4MAIAPeripheryTop --write_settings_files=off --merge=on -Tue 01:11: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/map/altera_quartus/quartus.ini -Tue 01:11: INFO : Info (35007): Using synthesis netlist for partition "Top" -Tue 01:11: INFO : Info (35007): Using synthesis netlist for partition "MAX4FPGATop:MAX4MaiaFabricTop_i" -Tue 01:11: INFO : Info (35002): Resolved and merged 2 partition(s) -Tue 01:11: INFO : Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" -Tue 01:11: INFO : Info (16011): Adding 218 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL -Tue 01:11: INFO : Info (35048): Found 123 ports with constant drivers. For more information, refer to the Partition Merger report -Tue 01:11: INFO : Info (35047): Found 190 ports with no fan-out. For more information, refer to the Partition Merger report -Tue 01:11: INFO : Warning (35016): Found partition port(s) not driving logic, possibly wasting area -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|rx_st_bar[1]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|rx_st_bar[3]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|rx_st_bar[5]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|rx_st_bar[6]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|rx_st_bar[7]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[13]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[14]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[15]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[16]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[17]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[18]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[19]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[20]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[21]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[22]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[23]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[24]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[25]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[26]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[27]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic -Tue 01:11: INFO : Warning (35039): Only the first 20 ports are reported. For a full list of ports, refer to the Partition Warnings panel in the Partition Merge report -Tue 01:11: INFO : Warning (21074): Design contains 2 input pin(s) that do not drive logic -Tue 01:11: INFO : Warning (15610): No output dependent on input pin "left_pll_ref_clk" -Tue 01:11: INFO : Warning (15610): No output dependent on input pin "right_pll_ref_clk" -Tue 01:11: INFO : Info (21057): Implemented 35559 device resources after synthesis - the final resource count might be different -Tue 01:11: INFO : Info (21058): Implemented 18 input pins -Tue 01:11: INFO : Info (21059): Implemented 10 output pins -Tue 01:11: INFO : Info (21060): Implemented 26 bidirectional pins -Tue 01:11: INFO : Info (21061): Implemented 30428 logic cells -Tue 01:11: INFO : Info (21064): Implemented 4897 RAM segments -Tue 01:11: INFO : Info (21065): Implemented 2 PLLs -Tue 01:11: INFO : Info: Quartus II 64-Bit Partition Merge was successful. 0 errors, 25 warnings -Tue 01:11: INFO : Info: Peak virtual memory: 1248 megabytes -Tue 01:11: INFO : Info: Processing ended: Tue Aug 25 01:11:15 2015 -Tue 01:11: INFO : Info: Elapsed time: 00:00:18 -Tue 01:11: INFO : Info: Total CPU time (on all processors): 00:00:18 -Tue 01:11: INFO : quartus_cdb ended (01:11:15 25/08/15, time elapsed: 22 secs) -Tue 01:11: INFO : quartus_cdb peak virtual memory: 1248 -Tue 01:11: INFO : Build pass 'QuartusCdb' took 22.2573 s. -Tue 01:11: PROGRESS: (4/16) - Generate Resource Report (AlteraResourceUsageBuildPass) -Tue 01:11: INFO : Build pass 'AlteraResourceUsageBuildPass' took 723.210 ms. -Tue 01:11: PROGRESS: (5/16) - Generate Annotated Source Code (AlteraResourceAnnotationBuildPass) -Tue 01:11: INFO : Annotating source files (old source files in build directory will be removed first)... -Tue 01:11: INFO : Not deleting directory (does not exist): src_annotated_preliminary_FetchSubTupleKernel -Tue 01:11: INFO : annotated 3 source files -Tue 01:11: INFO : Annotating source files (old source files in build directory will be removed first)... -Tue 01:11: INFO : Not deleting directory (does not exist): src_annotated_preliminary -Tue 01:11: INFO : annotated 3 source files -Tue 01:11: INFO : Build pass 'AlteraResourceAnnotationBuildPass' took 2.14182 s. -Tue 01:11: PROGRESS: (6/16) - Analyse Resource Usage (AlteraResourceCounterPass) -Tue 01:11: PROGRESS: -Tue 01:11: PROGRESS: About to start chip vendor Map/Place/Route toolflow. This will take some time. -Tue 01:11: PROGRESS: For this compile, we estimate this process may take up to 30 minutes. -Tue 01:11: PROGRESS: We recommend running in simulation to verify correctness before building hardware. -Tue 01:11: PROGRESS: -Tue 01:11: PROGRESS: PRELIMINARY RESOURCE USAGE -Tue 01:11: PROGRESS: Logic utilization: 14257 / 262400 (5.43%) -Tue 01:11: PROGRESS: Multipliers (18x18): 0 / 3926 (0.00%) -Tue 01:11: PROGRESS: Block memory (bits): 2264309 / 52572160 (4.31%) -Tue 01:11: PROGRESS: -Tue 01:11: INFO : Build pass 'AlteraResourceCounterPass' took 1.37551 ms. -Tue 01:11: PROGRESS: (7/16) - Place and Route DFE (AlteraMPPR) -Tue 01:11: PROGRESS: Executing MPPR with 1 cost table and 1 thread. -Tue 01:11: PROGRESS: MPPR: Starting 1 cost table -Tue 01:11: INFO : Created new sub build manager running in: /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/./FetchSubTuple_MAIA_DFE/scratch/altera_quartus/ct1 -Tue 01:11: INFO : For detailed output from this sub build manager see: /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/./FetchSubTuple_MAIA_DFE/scratch/altera_quartus/ct1/_build.log -Tue 01:30: PROGRESS: MPPR: Cost table 1 met timing with score 0 (best score 0) -Tue 01:30: INFO : Build pass 'AlteraMPPR' took 1144.51 s. -Tue 01:30: PROGRESS: (8/16) - Generate Configuration (QuartusAsm) -Tue 01:30: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/ct1/altera_quartus/db" "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus" -Tue 01:30: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/ct1/altera_quartus/incremental_db" "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus" -Tue 01:30: INFO : Running command: ln -sf "../../map/altera_quartus/MAX4MAIAPeripheryTop.qpf" -Tue 01:30: INFO : Running command: ln -sf "../../map/altera_quartus/MAX4MAIAPeripheryTop.qsf" -Tue 01:30: INFO : Running command: ln -sf "../../map/altera_quartus/quartus.ini" -Tue 01:30: INFO : Creating timing report for cost table(s): 1 -Tue 01:30: INFO : Running command: ln -sf "../../map/altera_quartus/MAX4MAIAPeripheryTop.sdc" -Tue 01:30: INFO : Starting quartus_asm. (01:30:23 25/08/15) -Tue 01:30: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_asm MAX4MAIAPeripheryTop --64bit --write_settings_files=off -Tue 01:30: INFO : Timing report successfully written. -Tue 01:31: INFO : Info: ******************************************************************* -Tue 01:31: INFO : Info: Running Quartus II 64-Bit Assembler -Tue 01:31: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version -Tue 01:31: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. -Tue 01:31: INFO : Info: Your use of Altera Corporation's design tools, logic functions -Tue 01:31: INFO : Info: and other software and tools, and its AMPP partner logic -Tue 01:31: INFO : Info: functions, and any output files from any of the foregoing -Tue 01:31: INFO : Info: (including device programming or simulation files), and any -Tue 01:31: INFO : Info: associated documentation or information are expressly subject -Tue 01:31: INFO : Info: to the terms and conditions of the Altera Program License -Tue 01:31: INFO : Info: Subscription Agreement, Altera MegaCore Function License -Tue 01:31: INFO : Info: Agreement, or other applicable license agreement, including, -Tue 01:31: INFO : Info: without limitation, that your use is for the sole purpose of -Tue 01:31: INFO : Info: programming logic devices manufactured by Altera and sold by -Tue 01:31: INFO : Info: Altera or its authorized distributors. Please refer to the -Tue 01:31: INFO : Info: applicable agreement for further details. -Tue 01:31: INFO : Info: Processing started: Tue Aug 25 01:30:28 2015 -Tue 01:31: INFO : Info: Command: quartus_asm MAX4MAIAPeripheryTop --write_settings_files=off -Tue 01:31: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini -Tue 01:31: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:31: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:31: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:31: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:31: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:31: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:31: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:31: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:31: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:31: INFO : Info (115030): Assembler is generating device programming files -Tue 01:31: INFO : Info: Quartus II 64-Bit Assembler was successful. 0 errors, 9 warnings -Tue 01:31: INFO : Info: Peak virtual memory: 1820 megabytes -Tue 01:31: INFO : Info: Processing ended: Tue Aug 25 01:31:55 2015 -Tue 01:31: INFO : Info: Elapsed time: 00:01:27 -Tue 01:31: INFO : Info: Total CPU time (on all processors): 00:01:25 -Tue 01:31: INFO : quartus_asm ended (01:31:57 25/08/15, time elapsed: 1 min, 33 secs) -Tue 01:31: INFO : quartus_asm peak virtual memory: 1820 -Tue 01:31: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.asm.rpt" "MAX4MAIAPeripheryTop.asm.stage1.rpt" -Tue 01:31: INFO : Deleting /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.asm.rpt -Tue 01:31: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.sof" "MAX4MAIAPeripheryTop.stage1.sof" -Tue 01:31: INFO : Deleting /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.sof -Tue 01:31: INFO : Build pass 'QuartusAsm' took 94.4709 s. -Tue 01:31: PROGRESS: (9/16) - Convert Programming File (QuartusCpf) -Tue 01:31: INFO : Starting quartus_cpf for periphery/core split rbf. (01:31:57 25/08/15) -Tue 01:31: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_cpf --64bit -c "MAX4MAIAPeripheryTop.cof" -Tue 01:32: INFO : Info: ******************************************************************* -Tue 01:32: INFO : Info: Running Quartus II 64-Bit Convert_programming_file -Tue 01:32: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version -Tue 01:32: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. -Tue 01:32: INFO : Info: Your use of Altera Corporation's design tools, logic functions -Tue 01:32: INFO : Info: and other software and tools, and its AMPP partner logic -Tue 01:32: INFO : Info: functions, and any output files from any of the foregoing -Tue 01:32: INFO : Info: (including device programming or simulation files), and any -Tue 01:32: INFO : Info: associated documentation or information are expressly subject -Tue 01:32: INFO : Info: to the terms and conditions of the Altera Program License -Tue 01:32: INFO : Info: Subscription Agreement, Altera MegaCore Function License -Tue 01:32: INFO : Info: Agreement, or other applicable license agreement, including, -Tue 01:32: INFO : Info: without limitation, that your use is for the sole purpose of -Tue 01:32: INFO : Info: programming logic devices manufactured by Altera and sold by -Tue 01:32: INFO : Info: Altera or its authorized distributors. Please refer to the -Tue 01:32: INFO : Info: applicable agreement for further details. -Tue 01:32: INFO : Info: Processing started: Tue Aug 25 01:31:59 2015 -Tue 01:32: INFO : Info: Command: quartus_cpf -c MAX4MAIAPeripheryTop.cof -Tue 01:32: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini -Tue 01:32: INFO : Info: Quartus II 64-Bit Convert_programming_file was successful. 0 errors, 0 warnings -Tue 01:32: INFO : Info: Peak virtual memory: 978 megabytes -Tue 01:32: INFO : Info: Processing ended: Tue Aug 25 01:32:11 2015 -Tue 01:32: INFO : Info: Elapsed time: 00:00:12 -Tue 01:32: INFO : Info: Total CPU time (on all processors): 00:00:12 -Tue 01:32: INFO : quartus_cpf ended (01:32:13 25/08/15, time elapsed: 15 secs) -Tue 01:32: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.core.rbf" "MAX4MAIAPeripheryTop.core.stage1.rbf" -Tue 01:32: INFO : Deleting /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.core.rbf -Tue 01:32: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.periph.rbf" "MAX4MAIAPeripheryTop.periph.stage1.rbf" -Tue 01:32: INFO : Deleting /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.periph.rbf -Tue 01:32: INFO : Starting quartus_cpf for full rbf. (01:32:13 25/08/15) -Tue 01:32: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_cpf --64bit -c "MAX4MAIAPeripheryTop_full.cof" -Tue 01:32: INFO : Info: ******************************************************************* -Tue 01:32: INFO : Info: Running Quartus II 64-Bit Convert_programming_file -Tue 01:32: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version -Tue 01:32: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. -Tue 01:32: INFO : Info: Your use of Altera Corporation's design tools, logic functions -Tue 01:32: INFO : Info: and other software and tools, and its AMPP partner logic -Tue 01:32: INFO : Info: functions, and any output files from any of the foregoing -Tue 01:32: INFO : Info: (including device programming or simulation files), and any -Tue 01:32: INFO : Info: associated documentation or information are expressly subject -Tue 01:32: INFO : Info: to the terms and conditions of the Altera Program License -Tue 01:32: INFO : Info: Subscription Agreement, Altera MegaCore Function License -Tue 01:32: INFO : Info: Agreement, or other applicable license agreement, including, -Tue 01:32: INFO : Info: without limitation, that your use is for the sole purpose of -Tue 01:32: INFO : Info: programming logic devices manufactured by Altera and sold by -Tue 01:32: INFO : Info: Altera or its authorized distributors. Please refer to the -Tue 01:32: INFO : Info: applicable agreement for further details. -Tue 01:32: INFO : Info: Processing started: Tue Aug 25 01:32:15 2015 -Tue 01:32: INFO : Info: Command: quartus_cpf -c MAX4MAIAPeripheryTop_full.cof -Tue 01:32: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini -Tue 01:32: INFO : Info: Quartus II 64-Bit Convert_programming_file was successful. 0 errors, 0 warnings -Tue 01:32: INFO : Info: Peak virtual memory: 974 megabytes -Tue 01:32: INFO : Info: Processing ended: Tue Aug 25 01:32:27 2015 -Tue 01:32: INFO : Info: Elapsed time: 00:00:12 -Tue 01:32: INFO : Info: Total CPU time (on all processors): 00:00:13 -Tue 01:32: INFO : quartus_cpf ended (01:32:29 25/08/15, time elapsed: 16 secs) -Tue 01:32: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.rbf" "MAX4MAIAPeripheryTop.stage1.rbf" -Tue 01:32: INFO : Deleting /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.rbf -Tue 01:32: INFO : Build pass 'QuartusCpf' took 31.8588 s. -Tue 01:32: PROGRESS: (10/16) - Update Checksum (UpdateChecksumBuildPass) -Tue 01:32: INFO : Build pass 'UpdateChecksumBuildPass' took 171.413 ms. -Tue 01:32: PROGRESS: (11/16) - Generate Incremental Netlist (QuartusCdb) -Tue 01:32: INFO : Starting quartus_cdb. (01:32:29 25/08/15) -Tue 01:32: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_cdb MAX4MAIAPeripheryTop --64bit --write_settings_files=off --update_mif -Tue 01:32: INFO : Info: ******************************************************************* -Tue 01:32: INFO : Info: Running Quartus II 64-Bit MIF/HEX Update -Tue 01:32: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version -Tue 01:32: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. -Tue 01:32: INFO : Info: Your use of Altera Corporation's design tools, logic functions -Tue 01:32: INFO : Info: and other software and tools, and its AMPP partner logic -Tue 01:32: INFO : Info: functions, and any output files from any of the foregoing -Tue 01:32: INFO : Info: (including device programming or simulation files), and any -Tue 01:32: INFO : Info: associated documentation or information are expressly subject -Tue 01:32: INFO : Info: to the terms and conditions of the Altera Program License -Tue 01:32: INFO : Info: Subscription Agreement, Altera MegaCore Function License -Tue 01:32: INFO : Info: Agreement, or other applicable license agreement, including, -Tue 01:32: INFO : Info: without limitation, that your use is for the sole purpose of -Tue 01:32: INFO : Info: programming logic devices manufactured by Altera and sold by -Tue 01:32: INFO : Info: Altera or its authorized distributors. Please refer to the -Tue 01:32: INFO : Info: applicable agreement for further details. -Tue 01:32: INFO : Info: Processing started: Tue Aug 25 01:32:34 2015 -Tue 01:32: INFO : Info: Command: quartus_cdb MAX4MAIAPeripheryTop --write_settings_files=off --update_mif -Tue 01:32: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini -Tue 01:32: INFO : Warning (39023): Can't find Memory Initialization File alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_a.mif -- skipped updates for this file -Tue 01:32: INFO : Warning (39023): Can't find Memory Initialization File alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_b.mif -- skipped updates for this file -Tue 01:32: INFO : Warning (39023): Can't find Memory Initialization File alt_xcvr_reconfig_cpu_ram.hex -- skipped updates for this file -Tue 01:32: INFO : Info (39024): Processed the following Memory Initialization File(s) -Tue 01:32: INFO : Info (39025): Processed Memory Initialization File /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/32x512_ROM_SINGLE_PORT_ireg_checksum.mif -Tue 01:32: INFO : Info (39025): Processed Memory Initialization File /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/db/MAX4MAIAPeripheryTop.ram0_sv_xrbasic_l2p_rom_a2c9d7fe.hdl.mif -Tue 01:32: INFO : Info: Quartus II 64-Bit MIF/HEX Update was successful. 0 errors, 3 warnings -Tue 01:32: INFO : Info: Peak virtual memory: 1636 megabytes -Tue 01:32: INFO : Info: Processing ended: Tue Aug 25 01:32:49 2015 -Tue 01:32: INFO : Info: Elapsed time: 00:00:15 -Tue 01:32: INFO : Info: Total CPU time (on all processors): 00:00:14 -Tue 01:32: INFO : quartus_cdb ended (01:32:49 25/08/15, time elapsed: 19 secs) -Tue 01:32: INFO : quartus_cdb peak virtual memory: 1636 -Tue 01:32: INFO : Build pass 'QuartusCdb' took 19.5574 s. -Tue 01:32: PROGRESS: (12/16) - Generate Configuration (QuartusAsm) -Tue 01:32: INFO : Starting quartus_asm. (01:32:49 25/08/15) -Tue 01:32: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_asm MAX4MAIAPeripheryTop --64bit --write_settings_files=off -Tue 01:32: INFO : Checking for file hash changes... -Tue 01:32: INFO : Hash changed for file: 'db' -Tue 01:34: INFO : Info: ******************************************************************* -Tue 01:34: INFO : Info: Running Quartus II 64-Bit Assembler -Tue 01:34: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version -Tue 01:34: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. -Tue 01:34: INFO : Info: Your use of Altera Corporation's design tools, logic functions -Tue 01:34: INFO : Info: and other software and tools, and its AMPP partner logic -Tue 01:34: INFO : Info: functions, and any output files from any of the foregoing -Tue 01:34: INFO : Info: (including device programming or simulation files), and any -Tue 01:34: INFO : Info: associated documentation or information are expressly subject -Tue 01:34: INFO : Info: to the terms and conditions of the Altera Program License -Tue 01:34: INFO : Info: Subscription Agreement, Altera MegaCore Function License -Tue 01:34: INFO : Info: Agreement, or other applicable license agreement, including, -Tue 01:34: INFO : Info: without limitation, that your use is for the sole purpose of -Tue 01:34: INFO : Info: programming logic devices manufactured by Altera and sold by -Tue 01:34: INFO : Info: Altera or its authorized distributors. Please refer to the -Tue 01:34: INFO : Info: applicable agreement for further details. -Tue 01:34: INFO : Info: Processing started: Tue Aug 25 01:32:53 2015 -Tue 01:34: INFO : Info: Command: quartus_asm MAX4MAIAPeripheryTop --write_settings_files=off -Tue 01:34: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini -Tue 01:34: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:34: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:34: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:34: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:34: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:34: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:34: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:34: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:34: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. -Tue 01:34: INFO : Info (115030): Assembler is generating device programming files -Tue 01:34: INFO : Info: Quartus II 64-Bit Assembler was successful. 0 errors, 9 warnings -Tue 01:34: INFO : Info: Peak virtual memory: 1826 megabytes -Tue 01:34: INFO : Info: Processing ended: Tue Aug 25 01:34:23 2015 -Tue 01:34: INFO : Info: Elapsed time: 00:01:30 -Tue 01:34: INFO : Info: Total CPU time (on all processors): 00:01:29 -Tue 01:34: INFO : quartus_asm ended (01:34:25 25/08/15, time elapsed: 1 min, 36 secs) -Tue 01:34: INFO : quartus_asm peak virtual memory: 1826 -Tue 01:34: INFO : Build pass 'QuartusAsm' took 96.5240 s. -Tue 01:34: PROGRESS: (13/16) - Convert Programming File (QuartusCpf) -Tue 01:34: INFO : Starting quartus_cpf for periphery/core split rbf. (01:34:25 25/08/15) -Tue 01:34: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_cpf --64bit -c "MAX4MAIAPeripheryTop.cof" -Tue 01:34: INFO : Checking for file hash changes... -Tue 01:34: INFO : No hash for file: 'MAX4MAIAPeripheryTop.sof' -Tue 01:34: INFO : Hash changed for file: 'MAX4MAIAPeripheryTop.cof' -Tue 01:34: INFO : Info: ******************************************************************* -Tue 01:34: INFO : Info: Running Quartus II 64-Bit Convert_programming_file -Tue 01:34: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version -Tue 01:34: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. -Tue 01:34: INFO : Info: Your use of Altera Corporation's design tools, logic functions -Tue 01:34: INFO : Info: and other software and tools, and its AMPP partner logic -Tue 01:34: INFO : Info: functions, and any output files from any of the foregoing -Tue 01:34: INFO : Info: (including device programming or simulation files), and any -Tue 01:34: INFO : Info: associated documentation or information are expressly subject -Tue 01:34: INFO : Info: to the terms and conditions of the Altera Program License -Tue 01:34: INFO : Info: Subscription Agreement, Altera MegaCore Function License -Tue 01:34: INFO : Info: Agreement, or other applicable license agreement, including, -Tue 01:34: INFO : Info: without limitation, that your use is for the sole purpose of -Tue 01:34: INFO : Info: programming logic devices manufactured by Altera and sold by -Tue 01:34: INFO : Info: Altera or its authorized distributors. Please refer to the -Tue 01:34: INFO : Info: applicable agreement for further details. -Tue 01:34: INFO : Info: Processing started: Tue Aug 25 01:34:27 2015 -Tue 01:34: INFO : Info: Command: quartus_cpf -c MAX4MAIAPeripheryTop.cof -Tue 01:34: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini -Tue 01:34: INFO : Info: Quartus II 64-Bit Convert_programming_file was successful. 0 errors, 0 warnings -Tue 01:34: INFO : Info: Peak virtual memory: 978 megabytes -Tue 01:34: INFO : Info: Processing ended: Tue Aug 25 01:34:39 2015 -Tue 01:34: INFO : Info: Elapsed time: 00:00:12 -Tue 01:34: INFO : Info: Total CPU time (on all processors): 00:00:12 -Tue 01:34: INFO : quartus_cpf ended (01:34:41 25/08/15, time elapsed: 15 secs) -Tue 01:34: INFO : Starting quartus_cpf for full rbf. (01:34:41 25/08/15) -Tue 01:34: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_cpf --64bit -c "MAX4MAIAPeripheryTop_full.cof" -Tue 01:34: INFO : Checking for file hash changes... -Tue 01:34: INFO : Hash changed for file: 'MAX4MAIAPeripheryTop_full.cof' -Tue 01:34: INFO : No hash for file: 'MAX4MAIAPeripheryTop.sof' -Tue 01:34: INFO : Info: ******************************************************************* -Tue 01:34: INFO : Info: Running Quartus II 64-Bit Convert_programming_file -Tue 01:34: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version -Tue 01:34: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. -Tue 01:34: INFO : Info: Your use of Altera Corporation's design tools, logic functions -Tue 01:34: INFO : Info: and other software and tools, and its AMPP partner logic -Tue 01:34: INFO : Info: functions, and any output files from any of the foregoing -Tue 01:34: INFO : Info: (including device programming or simulation files), and any -Tue 01:34: INFO : Info: associated documentation or information are expressly subject -Tue 01:34: INFO : Info: to the terms and conditions of the Altera Program License -Tue 01:34: INFO : Info: Subscription Agreement, Altera MegaCore Function License -Tue 01:34: INFO : Info: Agreement, or other applicable license agreement, including, -Tue 01:34: INFO : Info: without limitation, that your use is for the sole purpose of -Tue 01:34: INFO : Info: programming logic devices manufactured by Altera and sold by -Tue 01:34: INFO : Info: Altera or its authorized distributors. Please refer to the -Tue 01:34: INFO : Info: applicable agreement for further details. -Tue 01:34: INFO : Info: Processing started: Tue Aug 25 01:34:42 2015 -Tue 01:34: INFO : Info: Command: quartus_cpf -c MAX4MAIAPeripheryTop_full.cof -Tue 01:34: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini -Tue 01:34: INFO : Info: Quartus II 64-Bit Convert_programming_file was successful. 0 errors, 0 warnings -Tue 01:34: INFO : Info: Peak virtual memory: 970 megabytes -Tue 01:34: INFO : Info: Processing ended: Tue Aug 25 01:34:54 2015 -Tue 01:34: INFO : Info: Elapsed time: 00:00:12 -Tue 01:34: INFO : Info: Total CPU time (on all processors): 00:00:12 -Tue 01:34: INFO : quartus_cpf ended (01:34:56 25/08/15, time elapsed: 15 secs) -Tue 01:34: INFO : Build pass 'QuartusCpf' took 30.8015 s. -Tue 01:34: PROGRESS: (14/16) - Generate Resource Report (AlteraResourceUsageBuildPass) -Tue 01:34: INFO : Build pass 'AlteraResourceUsageBuildPass' took 712.778 ms. -Tue 01:34: PROGRESS: (15/16) - Generate Annotated Source Code (AlteraResourceAnnotationBuildPass) -Tue 01:34: INFO : Annotating source files (old source files in build directory will be removed first)... -Tue 01:34: INFO : Not deleting directory (does not exist): src_annotated_FetchSubTupleKernel -Tue 01:34: INFO : annotated 3 source files -Tue 01:34: INFO : Annotating source files (old source files in build directory will be removed first)... -Tue 01:34: INFO : Not deleting directory (does not exist): src_annotated -Tue 01:34: INFO : annotated 3 source files -Tue 01:34: INFO : Build pass 'AlteraResourceAnnotationBuildPass' took 2.11077 s. -Tue 01:34: PROGRESS: (16/16) - Generate MaxFile (GenerateMaxFileAltera) -Tue 01:34: INFO : Running command: "/vol/cc/opt/maxeler/maxcompiler-2014.1/bin/maxfilestitch" -a -w -m 1 -b 20150825 "../MaxCompilerDesignData.dat" "asm/altera_quartus/MAX4MAIAPeripheryTop.periph.rbf" "asm/altera_quartus/MAX4MAIAPeripheryTop.core.rbf" "FetchSubTuple.max" 67b6c6186b4f6a114e52a841d88780ebb43ec63e66d8bc566453924c6a70b1dc 0 2>&1 | tee maxfilestitch.log ; exit ${PIPESTATUS[0]} -Tue 01:35: INFO : Input files: -Tue 01:35: INFO : DAT: ../MaxCompilerDesignData.dat -Tue 01:35: INFO : Periph RBF: asm/altera_quartus/MAX4MAIAPeripheryTop.periph.rbf -Tue 01:35: INFO : Core RBF: asm/altera_quartus/MAX4MAIAPeripheryTop.core.rbf -Tue 01:35: INFO : Output files: -Tue 01:35: INFO : MAX: FetchSubTuple.max -Tue 01:35: INFO : Hash: 67b6c6186b4f6a114e52a841d88780ebb43ec63e66d8bc566453924c6a70b1dc -Tue 01:35: INFO : Timing score: 0 -Tue 01:35: INFO : Build pass 'GenerateMaxFileAltera' took 4.36575 s. -Tue 01:35: INFO : Final result files after build: -Tue 01:35: INFO : Running command: ln -sf "../scratch/FetchSubTuple-FetchSubTupleKernel-original.pxg" -Tue 01:35: INFO : FetchSubTuple-FetchSubTupleKernel-original.pxg (BuildFilePXG) -Tue 01:35: INFO : Running command: ln -sf "../scratch/FetchSubTupleKernel_Configuration.txt" -Tue 01:35: INFO : FetchSubTupleKernel_Configuration.txt (BuildFile) -Tue 01:35: INFO : Running command: ln -sf "../scratch/FetchSubTupleKernel_NodeDiary.txt" -Tue 01:35: INFO : FetchSubTupleKernel_NodeDiary.txt (BuildFile) -Tue 01:35: INFO : Running command: ln -sf "../scratch/FetchSubTuple-FetchSubTupleKernel-final-hardware.pxg" -Tue 01:35: INFO : FetchSubTuple-FetchSubTupleKernel-final-hardware.pxg (BuildFilePXG) -Tue 01:35: INFO : Running command: ln -sf "../scratch/FetchSubTuple.xml" -Tue 01:35: INFO : FetchSubTuple.xml (BuildFile) -Tue 01:35: INFO : Running command: ln -sf "../scratch/FetchSubTuple.h" -Tue 01:35: INFO : FetchSubTuple.h (BuildFileSlicH) -Tue 01:35: INFO : Running command: ln -sf "../scratch/altera_quartus/FetchSubTuple_map.mxru" -Tue 01:35: INFO : FetchSubTuple_map.mxru (BuildFileMXRU) -Tue 01:35: INFO : Running command: ln -sf "../scratch/altera_quartus/ct1/altera_quartus/MAX4MAIAPeripheryTop.sta.rpt.tns" -Tue 01:35: INFO : MAX4MAIAPeripheryTop.sta.rpt.tns (BuildFileStaTns) -Tue 01:35: INFO : Running command: ln -sf "../scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.sof" -Tue 01:35: INFO : MAX4MAIAPeripheryTop.sof (BuildFileStage2SOF) -Tue 01:35: INFO : Running command: ln -sf "../scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.core.rbf" -Tue 01:35: INFO : MAX4MAIAPeripheryTop.core.rbf (BuildFileStage2CoreRBF) -Tue 01:35: INFO : Running command: ln -sf "../scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.periph.rbf" -Tue 01:35: INFO : MAX4MAIAPeripheryTop.periph.rbf (BuildFileStage2PeriphRBF) -Tue 01:35: INFO : Running command: ln -sf "../scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.rbf" -Tue 01:35: INFO : MAX4MAIAPeripheryTop.rbf (BuildFileStage2FullRBF) -Tue 01:35: INFO : Running command: ln -sf "../scratch/altera_quartus/FetchSubTuple_fit.mxru" -Tue 01:35: INFO : FetchSubTuple_fit.mxru (BuildFileMXRU) -Tue 01:35: INFO : Running command: ln -sf "../scratch/altera_quartus/FetchSubTuple.max" -Tue 01:35: INFO : FetchSubTuple.max (BuildFileMaxFile) -Tue 01:35: PROGRESS: -Tue 01:35: PROGRESS: FINAL RESOURCE USAGE -Tue 01:35: PROGRESS: Logic utilization: 14025 / 262400 (5.34%) -Tue 01:35: PROGRESS: Primary FFs: 23981 / 524800 (4.57%) -Tue 01:35: PROGRESS: Secondary FFs: 690 / 524800 (0.13%) -Tue 01:35: PROGRESS: Multipliers (18x18): 0 / 3926 (0.00%) -Tue 01:35: PROGRESS: DSP blocks: 0 / 1963 (0.00%) -Tue 01:35: PROGRESS: Block memory (M20K): 143 / 2567 (5.57%) -Tue 01:35: PROGRESS: -Tue 01:35: PROGRESS: MaxFile: /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/FetchSubTuple_MAIA_DFE/results/FetchSubTuple.max (MD5Sum: bb2f03f826a94300704cafca107e810f) -Tue 01:35: INFO : Waiting for any outstanding jobs to finish... -Tue 01:35: INFO : Timing Analyser shutting down. -Tue 01:35: INFO : Timing Report: /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-24wide-noalign/./FetchSubTuple_MAIA_DFE/timingreport/index.html -Tue 01:35: PROGRESS: Build completed: Tue Aug 25 01:35:04 BST 2015 (took 31 mins, 11 secs) +Sat 21:48: PROGRESS: MaxCompiler version: 2014.1 +Sat 21:48: PROGRESS: Build "FetchSubTuple" start time: Sat Sep 05 21:48:46 BST 2015 +Sat 21:48: PROGRESS: Main build process running as user pburovsk on host cccad3.doc.ic.ac.uk +Sat 21:48: INFO : Loading build properties from bundled MaxCompiler_build.conf... +Sat 21:48: INFO : No default external build property file has been specified. +Sat 21:48: INFO : (Set environment variable MAXCOMPILER_DEFAULT_CONF_FILE to assign one) +Sat 21:48: INFO : Loading user build properties from: /mnt/ccnas/pburovsk/.MaxCompiler_build_user.conf +Sat 21:48: INFO : No user-specified external build property file has been specified. +Sat 21:48: INFO : (Set environment variable MAXCOMPILER_BUILD_CONF_FILE to assign one) +Sat 21:48: PROGRESS: Build location: /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/./FetchSubTuple_MAIA_DFE +Sat 21:48: PROGRESS: Detailed build log available in "_build.log" +Sat 21:48: INFO : Created build manager FetchSubTuple (FetchSubTuple_MAIA_DFE Sat Sep 05 21:48:46 BST 2015). (21:48:46 05/09/15) +Sat 21:48: INFO : Working in dir: /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/./FetchSubTuple_MAIA_DFE +Sat 21:48: INFO : Java class path (2 paths): +Sat 21:48: INFO : /vol/cc/opt/maxeler/maxcompiler-2014.1/lib/MaxCompiler.jar +Sat 21:48: INFO : . +Sat 21:48: INFO : Java process started by 'main' method in class 'FetchSubTupleManager'. +Sat 21:48: INFO : build.arbitrated_core_cache parameter is blank, not using core-cache +Sat 21:48: INFO : Checking license files in directory: /vol/cc/opt/maxeler/maxcompiler-2014.1/licenses +Sat 21:48: INFO : All license signatures valid. +Sat 21:48: INFO : Backing-up source-files (old source files in build directory will be removed first)... +Sat 21:48: INFO : Source directories: ../src +Sat 21:48: INFO : Not deleting directory (does not exist): src +Sat 21:48: INFO : Copying source-files took 10.7003 ms +Sat 21:48: USER : +Sat 21:48: USER : ENGINE BUILD PARAMETERS +Sat 21:48: USER : Build name: FetchSubTuple_MAIA_DFE +Sat 21:48: USER : DFEModel: MAIA +Sat 21:48: USER : maxFileName: FetchSubTuple +Sat 21:48: USER : target: DFE +Sat 21:48: USER : enableMPCX: true +Sat 21:48: PROGRESS: Instantiating kernel "FetchSubTupleKernel" +Sat 21:48: INFO : Manager Configuration: +Sat 21:48: INFO : ManagerConfiguration.allowNonMultipleTransitions = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.board = MAX4848A [Init: null, init: MAX4848A] +Sat 21:48: INFO : ManagerConfiguration.build.buildEffort = MEDIUM [Init: MEDIUM] +Sat 21:48: INFO : ManagerConfiguration.build.enableChipScopeInserter = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.build.enableTimingAnalysis = true [Init: true] +Sat 21:48: INFO : ManagerConfiguration.build.level = FULL_BUILD [Init: FULL_BUILD] +Sat 21:48: INFO : ManagerConfiguration.build.mpprContinueAfterMeetingTiming = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.build.mpprCtMax = 1 [Init: 1] +Sat 21:48: INFO : ManagerConfiguration.build.mpprCtMin = 1 [Init: 1] +Sat 21:48: INFO : ManagerConfiguration.build.mpprParallelism = 1 [Init: 1] +Sat 21:48: INFO : ManagerConfiguration.build.mpprRetryMissesThrshld = 0 [Init: 0] +Sat 21:48: INFO : ManagerConfiguration.build.optGoal = AREA [Init: AREA] +Sat 21:48: INFO : ManagerConfiguration.build.physSynthAsyncPipelining = AUTO [Init: AUTO] +Sat 21:48: INFO : ManagerConfiguration.build.physSynthCombLogic = AUTO [Init: AUTO] +Sat 21:48: INFO : ManagerConfiguration.build.physSynthCombLogicForArea = AUTO [Init: AUTO] +Sat 21:48: INFO : ManagerConfiguration.build.physSynthEffort = AUTO [Init: AUTO] +Sat 21:48: INFO : ManagerConfiguration.build.physSynthRegDuplication = AUTO [Init: AUTO] +Sat 21:48: INFO : ManagerConfiguration.build.physSynthRetiming = AUTO [Init: AUTO] +Sat 21:48: INFO : ManagerConfiguration.build.physicalSynthesis = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.buildTarget = DFE [Init: null, init: DFE] +Sat 21:48: INFO : ManagerConfiguration.debug.chipscopeCaptureDepth = 4096 [Init: 4096] +Sat 21:48: INFO : ManagerConfiguration.debug.fifoUnderOverFlowRegs = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.debug.memCtlDebugRegs = true [Init: true] +Sat 21:48: INFO : ManagerConfiguration.debug.memCtlExtraDebugRegs = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.debug.memMarginingSupport = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.debug.memPhyDebugRegister = NONE [Init: NONE] +Sat 21:48: INFO : ManagerConfiguration.debug.memPllLockDebugRegs = true [Init: true] +Sat 21:48: INFO : ManagerConfiguration.debug.streamStatus = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.debug.streamStatusChecksums = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.addressGeneratorsInSlowClock = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.arbitrationMode = ROUND_ROBIN [Init: ROUND_ROBIN] +Sat 21:48: INFO : ManagerConfiguration.dram.burstSize = 8 [Init: 8] +Sat 21:48: INFO : ManagerConfiguration.dram.cmdFifoInReg = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.cmdFifoLutRam = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.cmdFifoRegInRam = true [Init: true] +Sat 21:48: INFO : ManagerConfiguration.dram.cmdFifoSize = 31 [Init: 31] +Sat 21:48: INFO : ManagerConfiguration.dram.commandEchoModeEnabled = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.commandEchoModeFifoDepth = 512 [Init: 512] +Sat 21:48: INFO : ManagerConfiguration.dram.commandEchoModeStreamAlmostEmptyLatency = 792 [Init: 792] +Sat 21:48: INFO : ManagerConfiguration.dram.commandEchoModeStreamAlmostEmptyLatency = 8 [Init: 8] +Sat 21:48: INFO : ManagerConfiguration.dram.commandEchoModeStreamStallLatency = 8 [Init: 8] +Sat 21:48: INFO : ManagerConfiguration.dram.dataFifoDepth = 512 [Init: 512] +Sat 21:48: INFO : ManagerConfiguration.dram.dataFifoLutRam = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.dataFifoWidth = 792 [Init: 792] +Sat 21:48: INFO : ManagerConfiguration.dram.eccMode = true [Init: false, change: true] +Sat 21:48: INFO : ManagerConfiguration.dram.fabricDataFifoReg = true [Init: true] +Sat 21:48: INFO : ManagerConfiguration.dram.fabricRdDataFifoReg = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.flagSupport = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.highPrioStream = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.max2CompatMode = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.max4m_MAIA_MCP_UseRefClk = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.max4qrateMode = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.memCmdIncSize = 8 [Init: 8] +Sat 21:48: INFO : ManagerConfiguration.dram.memCmdStartAddrSize = 32 [Init: 32] +Sat 21:48: INFO : ManagerConfiguration.dram.onCardMemFreq = 400.0 [Init: 0.0, change: 400.0] +Sat 21:48: INFO : ManagerConfiguration.dram.parEccDebugStream = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.parityEccWidth = 72 [Init: 0, change: 72] +Sat 21:48: INFO : ManagerConfiguration.dram.parityMode = true [Init: false, change: true] +Sat 21:48: INFO : ManagerConfiguration.dram.perdqsPhaseDetect = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.dram.performanceMode = true [Init: true] +Sat 21:48: INFO : ManagerConfiguration.enableMPCX = true [Init: false, init: true] +Sat 21:48: INFO : ManagerConfiguration.maxring.maxringConnections = [] [Init: []] +Sat 21:48: INFO : ManagerConfiguration.maxring.maxringNumLanes = {} [Init: {}] +Sat 21:48: INFO : ManagerConfiguration.multiCycleMappedMemoryBus = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.network.qsfpBotMode = QSFP_OFF [Init: QSFP_OFF] +Sat 21:48: INFO : ManagerConfiguration.network.qsfpMidMode = QSFP_OFF [Init: QSFP_OFF] +Sat 21:48: INFO : ManagerConfiguration.network.qsfpTopMode = QSFP_OFF [Init: QSFP_OFF] +Sat 21:48: INFO : ManagerConfiguration.pcie.numPCIeLanes = 8 [Init: 0, change: 8] +Sat 21:48: INFO : ManagerConfiguration.pcie.pcieFastClock = true [Init: false, change: true] +Sat 21:48: INFO : ManagerConfiguration.pcie.streamFromHostMaxNum = 0 [Init: 0] +Sat 21:48: INFO : ManagerConfiguration.pcie.streamToHostMaxNum = 0 [Init: 0] +Sat 21:48: INFO : ManagerConfiguration.persona.boardModel = MAX4848A [Init: null, change: MAX4848A] +Sat 21:48: INFO : ManagerConfiguration.persona.ddr3Enable = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.persona.ddr3Frq = 400.0 [Init: 400.0] +Sat 21:48: INFO : ManagerConfiguration.persona.ddr3Qmode = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.persona.disableMultiplePersona = true [Init: true] +Sat 21:48: INFO : ManagerConfiguration.persona.dynamic_scaling = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.persona.maxRingLocal = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.persona.maxRingOptical = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.persona.maxringDataRate = 2500.0 [Init: 2500.0] +Sat 21:48: INFO : ManagerConfiguration.persona.maxringOpticalDataRate = 10000.0 [Init: 10000.0] +Sat 21:48: INFO : ManagerConfiguration.persona.mode = InitMode [Init: InitMode] +Sat 21:48: INFO : ManagerConfiguration.persona.networkPTP = OFF [Init: OFF] +Sat 21:48: INFO : ManagerConfiguration.persona.networkQSFP_BOT = QSFP_OFF [Init: QSFP_OFF] +Sat 21:48: INFO : ManagerConfiguration.persona.networkQSFP_MID = QSFP_OFF [Init: QSFP_OFF] +Sat 21:48: INFO : ManagerConfiguration.persona.networkQSFP_TOP = QSFP_OFF [Init: QSFP_OFF] +Sat 21:48: INFO : ManagerConfiguration.persona.panMaxRingA = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.persona.panMaxRingB = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.persona.personaInterfaceVersion = 1 [Init: 1] +Sat 21:48: INFO : ManagerConfiguration.persona.qdr2Enable = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.persona.qdr2Frq = 550.0 [Init: 550.0] +Sat 21:48: INFO : ManagerConfiguration.persona.streamClks = 1 [Init: 1] +Sat 21:48: INFO : ManagerConfiguration.persona.streamFrq = [200.0] [Init: [150.0], change: [200.0]] +Sat 21:48: INFO : ManagerConfiguration.persona.streamPs = [0] [Init: [0]] +Sat 21:48: INFO : ManagerConfiguration.persona.usePCIeGen1 = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.simulation.nativeFloatingPoint = false [Init: false] +Sat 21:48: INFO : ManagerConfiguration.streamClockFrq = 200 [Init: 100, change: 200] +Sat 21:48: INFO : ManagerConfiguration.useLegacyStreamFIFOs = false [Init: false] +Sat 21:48: INFO : +Sat 21:48: INFO : -- +Sat 21:48: INFO : Running manager compiler graph-pass: GenerateMXGInfo +Sat 21:48: INFO : Running manager compiler graph-pass: CalculateBandwidthForward +Sat 21:48: INFO : Running manager compiler graph-pass: CalculateBandwidthBackward +Sat 21:48: INFO : Running manager compiler graph-pass: ScheduleStallLatency +Sat 21:48: INFO : Running manager compiler graph-pass: ClockWidthAssignment +Sat 21:48: INFO : Running manager compiler graph-pass: InsertDualAspectLogic +Sat 21:48: INFO : Running manager compiler graph-pass: ClockWidthAssignment +Sat 21:48: INFO : Running manager compiler graph-pass: InsertPullPushAdapter +Sat 21:48: INFO : Running manager compiler graph-pass: ClockWidthAssignment +Sat 21:48: INFO : Running manager compiler graph-pass: InsertStreamFifos +Sat 21:48: INFO : Running manager compiler graph-pass: ClockWidthAssignment +Sat 21:48: INFO : Running manager compiler graph-pass: InsertStreamStatus +Sat 21:48: INFO : Running manager compiler graph-pass: InsertChipscope +Sat 21:48: INFO : Inserted 0 chipscope manager nodes. +Sat 21:48: INFO : Running manager compiler graph-pass: ClockWidthAssignment +Sat 21:48: PROGRESS: +Sat 21:48: PROGRESS: Compiling kernel "FetchSubTupleKernel" +Sat 21:48: INFO : Configuration: +Sat 21:48: INFO : KernelConfiguration.additionalInputPipelining = 64 [Init: 64] +Sat 21:48: INFO : KernelConfiguration.allowDSPCascading = true [Init: true] +Sat 21:48: INFO : KernelConfiguration.allowInputsOutputsBeforeFlushNode = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.allowZeroLatencyNodeHold = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.board = MAX4848A [Init: MAX2116B, change: MAX4848A] +Sat 21:48: INFO : KernelConfiguration.bramBitsThreshold = 2080 [Init: 2080] +Sat 21:48: INFO : KernelConfiguration.buildTarget = HARDWARE [Init: NONE, change: HARDWARE] +Sat 21:48: INFO : KernelConfiguration.cePipelining = 2 [Init: 2] +Sat 21:48: INFO : KernelConfiguration.clockPhaseBalanceThreshold = 0.1 [Init: 0.1] +Sat 21:48: INFO : KernelConfiguration.clockPhasingRetries = 50 [Init: 50] +Sat 21:48: INFO : KernelConfiguration.dumpNeighboursString = [Init: ] +Sat 21:48: INFO : KernelConfiguration.enableCeReplication = true [Init: true] +Sat 21:48: INFO : KernelConfiguration.enableClockPhasePartitioning = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.enableDebugIOControlRegs = true [Init: true] +Sat 21:48: INFO : KernelConfiguration.enableDummyBuild = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.enableKernelProfiler = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.enablePipelinedComputeController = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.enableShadowRegister = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.enableSmartKernelControl = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.fifoSrlRegisterStages = 1 [Init: 1] +Sat 21:48: INFO : KernelConfiguration.flushOnInputDataCongtiguous = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.hardwareDebugDepth = 512 [Init: 512] +Sat 21:48: INFO : KernelConfiguration.hwHierarchyMode = UNSET [Init: UNSET] +Sat 21:48: INFO : KernelConfiguration.latencyAnnotation = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.latencyAnnotationIOs = [Init: null] +Sat 21:48: INFO : KernelConfiguration.maxCoalescedFifoWidth = 2147483647 [Init: 2147483647] +Sat 21:48: INFO : KernelConfiguration.maxPreAdderFanOut = 1 [Init: 1] +Sat 21:48: INFO : KernelConfiguration.netlistMode = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.numPhotonStateMachines = 1 [Init: 1] +Sat 21:48: INFO : KernelConfiguration.optimizations.ceCounterRegisterDuplication = 1 [Init: 1] +Sat 21:48: INFO : KernelConfiguration.optimizations.conditionalArithmetic = true [Init: true] +Sat 21:48: INFO : KernelConfiguration.optimizations.counterChainWrapPipelining = 0 [Init: 0] +Sat 21:48: INFO : KernelConfiguration.optimizations.dspAddChain = OPTIMISE [Init: null, Init after BuildTarget change: OPTIMISE] +Sat 21:48: INFO : KernelConfiguration.optimizations.enableActiveFanoutReduction = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.optimizations.enableBUFGCE = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.optimizations.enableBetterInputRegistering = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.optimizations.enableBetterRegistering = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.optimizations.enableFIFOCoalescingAcrossPlacementConstraints = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.optimizations.enableFifoCoalescing = true [Init: true] +Sat 21:48: INFO : KernelConfiguration.optimizations.enableFullPrecisionBinaryOpConstants = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.optimizations.enableIntegratedRounding = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.optimizations.enableMappedMemoryHostReadBack = true [Init: true] +Sat 21:48: INFO : KernelConfiguration.optimizations.enableMultiCycleReset = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.optimizations.enablePowerTwoFloatMult = true [Init: true] +Sat 21:48: INFO : KernelConfiguration.optimizations.enableRedundantNodeDeletion = true [Init: true] +Sat 21:48: INFO : KernelConfiguration.optimizations.enableStateMachineRegisterMerging = true [Init: true] +Sat 21:48: INFO : KernelConfiguration.optimizations.inputFlushDistanceFactor = 0 [Init: 0] +Sat 21:48: INFO : KernelConfiguration.optimizations.minimumStaticFIFOSplitDepth = 1 [Init: 1] +Sat 21:48: INFO : KernelConfiguration.optimizations.optimizationTechnique = DEFAULT [Init: DEFAULT] +Sat 21:48: INFO : KernelConfiguration.optimizations.triAdd = true [Init: true] +Sat 21:48: INFO : KernelConfiguration.partialReconfBlockName = [Init: ] +Sat 21:48: INFO : KernelConfiguration.partialReconfMode = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.partialReconfTemplate = false [Init: false] +Sat 21:48: INFO : KernelConfiguration.replicateNodeCeLog2NumPartitions = 0 [Init: 0] +Sat 21:48: INFO : KernelConfiguration.romBRAMBitsThreshold = 2080 [Init: 2080] +Sat 21:48: INFO : KernelConfiguration.simulation.ramAddressCollisionBehaviour = EXCEPTION [Init: EXCEPTION] +Sat 21:48: INFO : KernelConfiguration.simulation.ramOutOfBoundsAccessBehaviour = EXCEPTION [Init: EXCEPTION] +Sat 21:48: INFO : KernelConfiguration.simulation.simProgressMessageFrequency = 0 [Init: 0] +Sat 21:48: INFO : +Sat 21:48: INFO : -- +Sat 21:48: INFO : Writing current graph to: FetchSubTuple-FetchSubTupleKernel-original.pxg +Sat 21:48: INFO : Running kernel graph-pass 'GeneratePXG'. +Sat 21:48: INFO : Graph-pass 'GeneratePXG' took 2.97490 s (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'MarkConstantPass'. +Sat 21:48: INFO : Graph-pass 'MarkConstantPass' took 15.5748 ms (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'ReachabilityPass'. +Sat 21:48: INFO : Graph-pass 'ReachabilityPass' took 91.7307 ms (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'FindInputsLeadingToFlush'. +Sat 21:48: INFO : Graph-pass 'FindInputsLeadingToFlush' took 964.424 µs (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'CheckForStatefulToFlushViolations'. +Sat 21:48: INFO : Graph-pass 'CheckForStatefulToFlushViolations' took 1.69530 ms (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'CheckForInputToFlushViolations'. +Sat 21:48: INFO : Graph-pass 'CheckForInputToFlushViolations' took 4.80617 ms (1 iterations) +Sat 21:48: INFO : Not deleting directory (does not exist): neighbours +Sat 21:48: INFO : Running Photon pre-schedule graph optimisations +Sat 21:48: INFO : Running kernel graph-pass 'AlignOrEradicatePrintfs'. +Sat 21:48: INFO : Graph-pass 'AlignOrEradicatePrintfs' took 8.64448 ms (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'FoldConstantsPass'. +Sat 21:48: INFO : Graph-pass 'FoldConstantsPass' took 15.6878 ms (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'OptimiseNodesPass'. +Sat 21:48: INFO : Graph-pass 'OptimiseNodesPass' took 157.799 ms (2 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'DeleteRedundantNodes'. +Sat 21:48: INFO : Graph-pass 'DeleteRedundantNodes' took 1.09879 ms (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'AlteraDSPExtractionGraphPass'. +Sat 21:48: INFO : Optimized 0 sub-graphs into DSP multiply/add chains +Sat 21:48: INFO : Graph-pass 'AlteraDSPExtractionGraphPass' took 126.336 ms (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'TriAddExtractionPass'. +Sat 21:48: INFO : Graph-pass 'TriAddExtractionPass' took 5.50113 ms (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'ConditionalAddExtractionPass'. +Sat 21:48: INFO : Optimized 0 sub-graphs into conditional adds/subs/triadds. +Sat 21:48: INFO : Graph-pass 'ConditionalAddExtractionPass' took 8.52841 ms (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'PO2FPMultOptimiser'. +Sat 21:48: INFO : Graph-pass 'PO2FPMultOptimiser' took 3.42937 ms (1 iterations) +Sat 21:48: INFO : Logging Photon stats to: FetchSubTupleKernel_photon_stats.csv +Sat 21:48: INFO : Running kernel graph-pass 'StatsPass'. +Sat 21:48: INFO : Graph-pass 'StatsPass' took 14.9913 ms (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'CollectNumericExceptions'. +Sat 21:48: INFO : Graph-pass 'CollectNumericExceptions' took 1.35396 ms (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'StreamOffsetDivExpand'. +Sat 21:48: INFO : Graph-pass 'StreamOffsetDivExpand' took 2.35128 ms (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'FindIllegalLoops'. +Sat 21:48: INFO : Graph-pass 'FindIllegalLoops' took 2.43765 s (1 iterations) +Sat 21:48: INFO : Scheduling Photon graph (pass 1) +Sat 21:48: INFO : Running kernel graph-pass 'MarkConstantPass'. +Sat 21:48: INFO : Graph-pass 'MarkConstantPass' took 6.65043 ms (1 iterations) +Sat 21:48: INFO : Running kernel graph-pass 'MIPScheduler'. +Sat 21:48: INFO : Running command: "/vol/cc/opt/maxeler/maxcompiler-2014.1/bin/glpsol" --intopt --model "scheduler.mod" --data "FetchSubTupleKernel_scheduler_1_C.dat" --display "FetchSubTupleKernel_scheduler_1_C.out" --log "FetchSubTupleKernel_scheduler_1_C.log" +Sat 21:48: INFO : GLPSOL: GLPK LP/MIP Solver (modified by Maxeler Technologies Inc., October 2013), v4.52 +Sat 21:48: INFO : Parameter(s) specified in the command line: +Sat 21:48: INFO : --intopt --model scheduler.mod --data FetchSubTupleKernel_scheduler_1_C.dat +Sat 21:48: INFO : --display FetchSubTupleKernel_scheduler_1_C.out --log FetchSubTupleKernel_scheduler_1_C.log +Sat 21:48: INFO : Reading model section from scheduler.mod... +Sat 21:48: INFO : 95 lines were read +Sat 21:48: INFO : Reading data section from FetchSubTupleKernel_scheduler_1_C.dat... +Sat 21:48: INFO : 22740 lines were read +Sat 21:48: INFO : Generating schedulingEquation... +Sat 21:48: INFO : Generating bufferingEquation... +Sat 21:48: INFO : Generating afterFlushNode... +Sat 21:48: INFO : Generating forcePairConstraints... +Sat 21:48: INFO : Generating forceAtEnd... +Sat 21:48: INFO : Generating autoVarLatencyUserMin... +Sat 21:48: INFO : Generating autoVarLatencyUserMax... +Sat 21:48: INFO : Generating fifos... +Sat 21:48: INFO : Model has been successfully generated +Sat 21:48: INFO : GLPK Integer Optimizer, v4.52 +Sat 21:48: INFO : 11997 rows, 7122 columns, 33549 non-zeros +Sat 21:48: INFO : 7122 integer variables, none of which are binary +Sat 21:48: INFO : Preprocessing... +Sat 21:48: INFO : 11996 rows, 7119 columns, 29988 non-zeros +Sat 21:48: INFO : 7119 integer variables, none of which are binary +Sat 21:48: INFO : Scaling... +Sat 21:48: INFO : A: min|aij| = 1.000e+00 max|aij| = 1.000e+00 ratio = 1.000e+00 +Sat 21:48: INFO : Problem data seem to be well scaled +Sat 21:48: INFO : Constructing initial basis... +Sat 21:48: INFO : Size of triangular part is 11996 +Sat 21:48: INFO : Solving LP relaxation... +Sat 21:48: INFO : GLPK Simplex Optimizer, v4.52 +Sat 21:48: INFO : 11996 rows, 7119 columns, 29988 non-zeros +Sat 21:48: INFO : 0: obj = 0.000000000e+00 infeas = 1.828e+03 (0) +Sat 21:48: INFO : 500: obj = 0.000000000e+00 infeas = 1.254e+03 (0) +Sat 21:48: INFO : 1000: obj = 1.520000000e+02 infeas = 6.000e+02 (0) +Sat 21:48: INFO : 1500: obj = 4.487000000e+03 infeas = 4.140e+02 (0) +Sat 21:48: INFO : 2000: obj = 9.337000000e+03 infeas = 2.140e+02 (0) +Sat 21:48: INFO : 2500: obj = 9.337000000e+03 infeas = 2.120e+02 (0) +Sat 21:48: INFO : 3000: obj = 1.333300000e+04 infeas = 7.300e+01 (0) +Sat 21:48: INFO : 3500: obj = 1.488800000e+04 infeas = 3.600e+01 (0) +Sat 21:48: INFO : * 3646: obj = 1.684100000e+04 infeas = 0.000e+00 (0) +Sat 21:48: INFO : * 4000: obj = 1.684100000e+04 infeas = 0.000e+00 (0) +Sat 21:48: INFO : * 4500: obj = 1.682300000e+04 infeas = 0.000e+00 (0) +Sat 21:48: INFO : * 5000: obj = 1.682300000e+04 infeas = 0.000e+00 (0) +Sat 21:48: INFO : * 5500: obj = 1.682200000e+04 infeas = 0.000e+00 (0) +Sat 21:49: INFO : * 5995: obj = 1.680800000e+04 infeas = 0.000e+00 (0) +Sat 21:49: INFO : OPTIMAL LP SOLUTION FOUND +Sat 21:49: INFO : Integer optimization begins... +Sat 21:49: INFO : + 5995: mip = not found yet >= -inf (1; 0) +Sat 21:49: INFO : + 5995: >>>>> 1.680800000e+04 >= 1.680800000e+04 0.0% (1; 0) +Sat 21:49: INFO : + 5995: mip = 1.680800000e+04 >= tree is empty 0.0% (0; 1) +Sat 21:49: INFO : INTEGER OPTIMAL SOLUTION FOUND +Sat 21:49: INFO : Time used: 2.5 secs +Sat 21:49: INFO : Memory used: 27.8 Mb (29162080 bytes) +Sat 21:49: INFO : Model has been successfully processed +Sat 21:49: INFO : Graph-pass 'MIPScheduler' took 3.37948 s (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'SubstituteEqPlaceholders'. +Sat 21:49: INFO : Graph-pass 'SubstituteEqPlaceholders' took 1.17690 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'ScheduleApplier'. +Sat 21:49: INFO : Graph-pass 'ScheduleApplier' took 18.2579 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'StatsPass'. +Sat 21:49: INFO : Graph-pass 'StatsPass' took 14.4186 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'ReachabilityPass'. +Sat 21:49: INFO : Graph-pass 'ReachabilityPass' took 12.7134 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'CheckForInputToFlushViolations'. +Sat 21:49: INFO : Graph-pass 'CheckForInputToFlushViolations' took 3.58380 ms (1 iterations) +Sat 21:49: INFO : Running Photon post-schedule graph optimisations (pass 1) +Sat 21:49: INFO : Running kernel graph-pass 'TapFIFOsPass'. +Sat 21:49: INFO : Graph-pass 'TapFIFOsPass' took 9.83260 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'FoldFIFOsPass'. +Sat 21:49: INFO : Graph-pass 'FoldFIFOsPass' took 1.62949 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'ValidateFIFOs'. +Sat 21:49: INFO : Graph-pass 'ValidateFIFOs' took 1.43071 ms (1 iterations) +Sat 21:49: INFO : Scheduling Photon graph (pass 2) +Sat 21:49: INFO : Running kernel graph-pass 'MarkConstantPass'. +Sat 21:49: INFO : Graph-pass 'MarkConstantPass' took 1.87781 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'RemoveDistMeasurementNodes'. +Sat 21:49: INFO : Graph-pass 'RemoveDistMeasurementNodes' took 21.3910 µs (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'SubstituteEqPlaceholders'. +Sat 21:49: INFO : Graph-pass 'SubstituteEqPlaceholders' took 948.173 µs (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'ScheduleApplier'. +Sat 21:49: INFO : Graph-pass 'ScheduleApplier' took 399.731 ms (1 iterations) +Sat 21:49: INFO : Maximum stream latency for kernel 'FetchSubTupleKernel': 20 +Sat 21:49: INFO : Using user logic for flush. +Sat 21:49: INFO : Running kernel graph-pass 'StatsPass'. +Sat 21:49: INFO : Graph-pass 'StatsPass' took 21.7918 ms (1 iterations) +Sat 21:49: INFO : Running Photon post-schedule graph optimisations (pass 2) +Sat 21:49: INFO : Running kernel graph-pass 'TapFIFOsPass'. +Sat 21:49: INFO : Graph-pass 'TapFIFOsPass' took 244.324 ms (2 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'FoldFIFOsPass'. +Sat 21:49: INFO : Graph-pass 'FoldFIFOsPass' took 3.75644 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'MarkConstantPass'. +Sat 21:49: INFO : Graph-pass 'MarkConstantPass' took 2.53637 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'ScheduleAsserter'. +Sat 21:49: INFO : Graph-pass 'ScheduleAsserter' took 13.0703 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'ReplaceEvalStreamOffsetNodes'. +Sat 21:49: INFO : Graph-pass 'ReplaceEvalStreamOffsetNodes' took 714.392 µs (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'FIFOCoalesceRespectingPlacementPass'. +Sat 21:49: INFO : Graph-pass 'FIFOCoalesceRespectingPlacementPass' took 11.4025 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'FIFOReport'. +Sat 21:49: INFO : Graph-pass 'FIFOReport' took 12.3680 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'StatsPass'. +Sat 21:49: INFO : Graph-pass 'StatsPass' took 8.33874 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'RemoveUntypedConstants'. +Sat 21:49: INFO : Graph-pass 'RemoveUntypedConstants' took 288.436 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'VariableSizeMappedRegInserter'. +Sat 21:49: INFO : Graph-pass 'VariableSizeMappedRegInserter' took 822.616 µs (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'MarkConstantPass'. +Sat 21:49: INFO : Graph-pass 'MarkConstantPass' took 785.080 µs (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'MakeMaxFileNodeData'. +Sat 21:49: INFO : Graph-pass 'MakeMaxFileNodeData' took 179.154 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'MoveFanoutRegsForwards'. +Sat 21:49: INFO : Graph-pass 'MoveFanoutRegsForwards' took 1.93939 ms (1 iterations) +Sat 21:49: INFO : Optimization report for Kernel 'FetchSubTupleKernel'. +Sat 21:49: INFO : Enabled optimizations: +Sat 21:49: INFO : DSP-MultAdd +Sat 21:49: INFO : Tri-Adder +Sat 21:49: INFO : Conditional (Tri)Adds/Subs/AddSubs +Sat 21:49: INFO : Power-of-2 Floating Point +Sat 21:49: INFO : Fifo Coalescing +Sat 21:49: INFO : Creating a preliminary MaxCompilerDesignData.dat. (@ CoreCompile FetchSubTupleKernel) +Sat 21:49: INFO : Running kernel graph-pass 'WeightBasedCEPartitioner'. +Sat 21:49: INFO : Partitioning design into 1 CE domain(s) to minimize global signal fanout. +Sat 21:49: INFO : Graph-pass 'WeightBasedCEPartitioner' took 111.045 µs (1 iterations) +Sat 21:49: INFO : Using maximum counter CE delay chain length 5 +Sat 21:49: INFO : CE Partition 0 Clock Phase 0 : Nodes=5067 (use fill=139, use flush=4) Fill counters=1 (+20 delay regs) Flush counters=1 (+6 delay regs) +Sat 21:49: INFO : Running kernel graph-pass 'FindWriteableMappedMemories'. +Sat 21:49: INFO : Graph-pass 'FindWriteableMappedMemories' took 759.677 µs (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'MarkConstantPass'. +Sat 21:49: INFO : Graph-pass 'MarkConstantPass' took 1.99336 ms (1 iterations) +Sat 21:49: INFO : Running kernel graph-pass 'MaxConstantLatency'. +Sat 21:49: INFO : Graph-pass 'MaxConstantLatency' took 2.64572 ms (1 iterations) +Sat 21:49: INFO : Maximum constant latency: 0 +Sat 21:49: INFO : Running kernel graph-pass 'PhotonMaxDCTopEntity'. +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 5 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 5 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (6 bits wide), cost 0 RAMB18-equivalents, and 6 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (6 bits wide), cost 0 RAMB18-equivalents, and 6 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 10 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 10 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (1 bits wide), cost 0 RAMB18-equivalents, and 1 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 4 (2 bits wide), cost 0 RAMB18-equivalents, and 2 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 4 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Implementing static multi-stage delay of 1 (64 bits wide), cost 0 RAMB18-equivalents, and 64 SRL32s. Made from: 0 x 0 BRAMs, Straggler BRAM 0, SRL of length 1 +Sat 21:49: INFO : Graph-pass 'PhotonMaxDCTopEntity' took 11.3526 s (1 iterations) +Sat 21:49: INFO : Writing current graph to: FetchSubTuple-FetchSubTupleKernel-final-hardware.pxg +Sat 21:49: INFO : Running kernel graph-pass 'GeneratePXG'. +Sat 21:49: INFO : Graph-pass 'GeneratePXG' took 2.82142 s (1 iterations) +Sat 21:49: INFO : Running manager compiler graph-pass: GenerateMXGInfo +Sat 21:49: INFO : Running manager compiler graph-pass: GenerateSlicHostCode +Sat 21:49: INFO : Generating SLIC interface information +Sat 21:49: INFO : Generating SLIC code for interface 'default' +Sat 21:49: INFO : Skipping blacklisted scalar parameter 'FetchSubTupleKernel.current_run_cycle_count' +Sat 21:49: INFO : Interface 'default' depends on parameter 'numCycles' +Sat 21:49: INFO : Interface 'default' depends on parameter 'numInputs' +Sat 21:49: INFO : Generating XML description for Maxfile +Sat 21:49: INFO : Generating XML description for mode 'default' +Sat 21:49: INFO : Skipping blacklisted scalar parameter 'FetchSubTupleKernel.current_run_cycle_count' +Sat 21:49: INFO : Interface 'default' depends on parameter 'numCycles' +Sat 21:49: INFO : Interface 'default' depends on parameter 'numInputs' +Sat 21:49: INFO : Adding SLIC sections to the maxfile +Sat 21:49: INFO : Adding user files to the maxfile +Sat 21:49: INFO : Generating SLIC include file +Sat 21:49: INFO : Done generating SLIC interface information +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:49: INFO : All asynchronous jobs are now completed. +Sat 21:49: INFO : Control Streams: Connecting block MappedElementsSwitchPCIeEA with select value: 1 +Sat 21:49: INFO : Running command: quartus_fit --version 2>&1 > quartus_version_test +Sat 21:49: INFO : ERROR: ld.so: object '/vol/cc/opt/maxeler/maxcompiler-2014.1/lib/maxeleros-sim/lib/libmaxeleros.so' from LD_PRELOAD cannot be preloaded: ignored. +Sat 21:49: INFO : Detected Quartus II version 13.1 +Sat 21:49: INFO : Running ' lmutil lmdiag -n quartus' +Sat 21:49: INFO : Successfully checked out license for Quartus (quartus) +Sat 21:49: INFO : Updating the preliminary MaxCompilerDesignData.dat. (@ Main build) +Sat 21:49: INFO : Deleting /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxCompilerDesignData.dat +Sat 21:49: PROGRESS: Generating input files (VHDL, netlists, MegaWizard/CoreGen) +Sat 21:49: INFO : Not deleting directory (does not exist): tmp +Sat 21:49: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; qmegawiz --64bit -silent module=altclkctrl -f:MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1.txt MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1.vhd > qmegawiz.log +Sat 21:49: INFO : Not deleting directory (does not exist): tmp +Sat 21:49: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; qmegawiz --64bit -silent module=altclkctrl -f:MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena.txt MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena.vhd > qmegawiz.log +Sat 21:50: INFO : Mapped register report: +Sat 21:50: INFO : 0 SFA_FORWARD_EN 4bytes +Sat 21:50: INFO : 4 dbg_stall_vector 1bytes +Sat 21:50: INFO : 5 io_output_force_disabled 1bytes +Sat 21:50: INFO : 6 io_sizes_force_disabled 1bytes +Sat 21:50: INFO : 7 io_input_force_disabled 1bytes +Sat 21:50: INFO : 8 run_cycle_count 6bytes +Sat 21:50: INFO : e current_run_cycle_count 6bytes +Sat 21:50: INFO : 14 dbg_ctld_empty 1bytes +Sat 21:50: INFO : 15 dbg_ctld_almost_empty 1bytes +Sat 21:50: INFO : 16 dbg_ctld_done 1bytes +Sat 21:50: INFO : 17 dbg_ctld_read 1bytes +Sat 21:50: INFO : 18 dbg_ctld_request 1bytes +Sat 21:50: INFO : 19 dbg_flush_start 1bytes +Sat 21:50: INFO : 1a dbg_full_level 1bytes +Sat 21:50: INFO : 1b dbg_flush_start_level 1bytes +Sat 21:50: INFO : 1c dbg_done_out 1bytes +Sat 21:50: INFO : 1d dbg_flushing 1bytes +Sat 21:50: INFO : 1e dbg_fill_level 1bytes +Sat 21:50: INFO : 1f dbg_flush_level 1bytes +Sat 21:50: INFO : 20 dbg_ctld_read_pipe_dbg 1bytes +Sat 21:50: INFO : 21 dbg_out_valid 1bytes +Sat 21:50: INFO : 22 dbg_out_stall 1bytes +Sat 21:50: INFO : 23 dynpcie_sth0_sth_compl_fifo_flags 1bytes +Sat 21:50: INFO : 24 clock_counters_base_clock_cclk 2bytes +Sat 21:50: INFO : 26 clock_counters_STREAM 2bytes +Sat 21:50: INFO : 28 clock_counters_clk_pcie 2bytes +Sat 21:50: INFO : 2a seen_reset_reset_n 1bytes +Sat 21:50: INFO : 2b seen_reset_STREAM_rst 1bytes +Sat 21:50: INFO : 2c seen_reset_STREAM_rst_delay 1bytes +Sat 21:50: INFO : 2d seen_reset_PCIE_rst 1bytes +Sat 21:50: INFO : 2e seen_reset_PCIE_rst_delay 1bytes +Sat 21:50: INFO : 2f seen_toggle_crash_input 1bytes +Sat 21:50: INFO : Mapped register chain length = 48 +Sat 21:50: INFO : Mapped memory report: +Sat 21:50: INFO : Memory 'MappedClockControl.STREAM_CLKPRIM' @ 4063232 +Sat 21:50: INFO : Memory 'MappedDRP.CHECKSUM' @ 3932160 +Sat 21:50: INFO : Memory 'Monitoring.PERFMONITOR' @ 3866624 +Sat 21:50: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:50: INFO : All asynchronous jobs are now completed. +Sat 21:50: INFO : Waiting for any external asynchronous jobs to complete (e.g. MegaWizard/CoreGen)... +Sat 21:50: INFO : All asynchronous jobs are now completed. +Sat 21:50: PROGRESS: Running back-end build (16 phases) +Sat 21:50: PROGRESS: (1/16) - Prepare MaxFile Data (GenerateMaxFileDataFile) +Sat 21:50: INFO : Build pass 'GenerateMaxFileDataFile' took 33.4043 ms. +Sat 21:50: PROGRESS: (2/16) - Prepare for Placement (QuartusMap) +Sat 21:50: INFO : Starting quartus_map. (21:50:05 05/09/15) +Sat 21:50: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_map MAX4MAIAPeripheryTop --64bit --parallel=1 +Sat 21:50: INFO : Info: ******************************************************************* +Sat 21:50: INFO : Info: Running Quartus II 64-Bit Analysis & Synthesis +Sat 21:50: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version +Sat 21:50: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. +Sat 21:50: INFO : Info: Your use of Altera Corporation's design tools, logic functions +Sat 21:50: INFO : Info: and other software and tools, and its AMPP partner logic +Sat 21:50: INFO : Info: functions, and any output files from any of the foregoing +Sat 21:50: INFO : Info: (including device programming or simulation files), and any +Sat 21:50: INFO : Info: associated documentation or information are expressly subject +Sat 21:50: INFO : Info: to the terms and conditions of the Altera Program License +Sat 21:50: INFO : Info: Subscription Agreement, Altera MegaCore Function License +Sat 21:50: INFO : Info: Agreement, or other applicable license agreement, including, +Sat 21:50: INFO : Info: without limitation, that your use is for the sole purpose of +Sat 21:50: INFO : Info: programming logic devices manufactured by Altera and sold by +Sat 21:50: INFO : Info: Altera or its authorized distributors. Please refer to the +Sat 21:50: INFO : Info: applicable agreement for further details. +Sat 21:50: INFO : Info: Processing started: Sat Sep 5 21:50:09 2015 +Sat 21:50: INFO : Info: Command: quartus_map MAX4MAIAPeripheryTop --parallel=1 +Sat 21:50: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/map/altera_quartus/quartus.ini +Sat 21:50: INFO : Critical Warning (12473): User specified to use only one processors but 16 processors were detected which could be used to decrease run time. +Sat 21:50: INFO : Info (12021): Found 6 design units, including 3 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_primitives.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: dff_ce_asyncsr-altera +Sat 21:50: INFO : Info (12022): Found design unit 2: dff_ce_syncsr-altera +Sat 21:50: INFO : Info (12022): Found design unit 3: dff_ce_syncsr_ne-altera +Sat 21:50: INFO : Info (12023): Found entity 1: dff_ce_asyncsr +Sat 21:50: INFO : Info (12023): Found entity 2: dff_ce_syncsr +Sat 21:50: INFO : Info (12023): Found entity 3: dff_ce_syncsr_ne +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PhotonDesignControl.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PhotonDesignControl-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: PhotonDesignControl +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/rg_buffer_sfh.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: rg_buffer_sfh-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: rg_buffer_sfh +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/rg_buffer_info.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: rg_buffer_info-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: rg_buffer_info +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/posted_credits_fifo.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: posted_credits_fifo-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: posted_credits_fifo +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_2_16_2_aclr_fwft.vhdl(101) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_2_16_2_aclr_fwft.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_2_16_2_aclr_fwft-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_2_16_2_aclr_fwft +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/rg_buffer_sth.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: rg_buffer_sth-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: rg_buffer_sth +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/rg_buffer_info_sth.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: rg_buffer_info_sth-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: rg_buffer_info_sth +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/sth_compl_fifo_debug.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: sth_compl_fifo_debug-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: sth_compl_fifo_debug +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of.vhdl(106) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../compl_fifo.vhdl(104) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/compl_fifo.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: compl_fifo-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: compl_fifo +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../pcie_tx_fifo.vhdl(104) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_tx_fifo.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: pcie_tx_fifo-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: pcie_tx_fifo +Sat 21:50: INFO : Info (12021): Found 2 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/cross_clock_pkg.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: cross_clock_pkg +Sat 21:50: INFO : Info (12022): Found design unit 2: cross_clock_pkg-body +Sat 21:50: INFO : Info (12021): Found 4 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/strobe_to_strobe.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: strobe_to_strobe_prim-altera +Sat 21:50: INFO : Info (12022): Found design unit 2: strobe_to_strobe-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: strobe_to_strobe_prim +Sat 21:50: INFO : Info (12023): Found entity 2: strobe_to_strobe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/max4_cpld_flash_if/max4_cpld_flash_if.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: max4_cpld_flash_if-struct +Sat 21:50: INFO : Info (12023): Found entity 1: max4_cpld_flash_if +Sat 21:50: INFO : Info (12021): Found 4 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/basic_synchroniser/basic_synchroniser.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: basic_synchroniser_prim-altera +Sat 21:50: INFO : Info (12022): Found design unit 2: basic_synchroniser-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: basic_synchroniser_prim +Sat 21:50: INFO : Info (12023): Found entity 2: basic_synchroniser +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/max_events/max_events.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: max_events-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: max_events +Sat 21:50: INFO : Info (12021): Found 4 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/level_synchroniser/level_synchroniser.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: level_synchroniser_prim-altera +Sat 21:50: INFO : Info (12022): Found design unit 2: level_synchroniser-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: level_synchroniser_prim +Sat 21:50: INFO : Info (12023): Found entity 2: level_synchroniser +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/max4_cpld_ioexpand/max4_cpld_ioexpand.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: max4_cpld_ioexpand-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: max4_cpld_ioexpand +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_xcvr_reconfig_SV.v +Sat 21:50: INFO : Info (12023): Found entity 1: pcie_xcvr_reconfig_SV +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV.v +Sat 21:50: INFO : Info (12023): Found entity 1: pcie_reconfig_SV +Sat 21:50: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_xcvr_functions.sv +Sat 21:50: INFO : Info (12022): Found design unit 1: altera_xcvr_functions (SystemVerilog) (pcie_reconfig_SV) +Sat 21:50: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_h.sv +Sat 21:50: INFO : Info (12022): Found design unit 1: sv_xcvr_h (SystemVerilog) (pcie_reconfig_SV) +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_resync.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_resync +Sat 21:50: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_h.sv +Sat 21:50: INFO : Info (12022): Found design unit 1: alt_xcvr_reconfig_h (SystemVerilog) (pcie_reconfig_SV) +Sat 21:50: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_dfe_cal_sweep_h.sv +Sat 21:50: INFO : Info (12022): Found design unit 1: sv_xcvr_dfe_cal_sweep_h (SystemVerilog) (pcie_reconfig_SV) +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cal_seq.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cal_seq +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xreconf_cif.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xreconf_cif +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xreconf_uif.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xreconf_uif +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xreconf_basic_acq.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xreconf_basic_acq +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_analog.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_analog +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_analog_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_analog_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xreconf_analog_datactrl.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xreconf_analog_datactrl +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xreconf_analog_rmw.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xreconf_analog_rmw +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xreconf_analog_ctrlsm.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xreconf_analog_ctrlsm +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_offset_cancellation.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_offset_cancellation +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_offset_cancellation_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_offset_cancellation_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_eyemon.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_eyemon +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_eyemon_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_eyemon_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_eyemon_ctrl_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_eyemon_ctrl_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_eyemon_ber_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_eyemon_ber_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/ber_reader_dcfifo.v +Sat 21:50: INFO : Info (12023): Found entity 1: ber_reader_dcfifo +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/step_to_mon_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: step_to_mon_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/mon_to_step_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: mon_to_step_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_reg_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_reg_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_cal_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_cal_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_cal_sweep_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_cal_sweep_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_cal_sweep_datapath_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_cal_sweep_datapath_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_oc_cal_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_oc_cal_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_pi_phase_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_pi_phase_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_step_to_mon_en_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_step_to_mon_en_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_adapt_tap_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_adapt_tap_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_ctrl_mux_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_ctrl_mux_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_local_reset_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_local_reset_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_cal_sim_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_cal_sim_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dfe_adapt_tap_sim_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dfe_adapt_tap_sim_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_adce.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_adce +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_adce_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_adce_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_adce_datactrl_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_adce_datactrl_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_sv.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_cal.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_cal +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_control.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_control +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_datapath.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_datapath +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_pll_reset.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_pll_reset +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_eye_width.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_eye_width +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_align_clk.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_align_clk +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_get_sum.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_dcd_get_sum +Sat 21:50: INFO : Info (12021): Found 0 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_dcd_cal_sim_model.sv +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_mif.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_mif +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_reconfig_mif.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_reconfig_mif +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_reconfig_mif_ctrl.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_reconfig_mif_ctrl +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_reconfig_mif_avmm.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_reconfig_mif_avmm +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_pll.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_pll +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_reconfig_pll.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_reconfig_pll +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_reconfig_pll_ctrl.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_reconfig_pll_ctrl +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_soc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_soc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_ram.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_ram +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_direct.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_direct +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xrbasic_l2p_addr.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xrbasic_l2p_addr +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xrbasic_l2p_ch.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xrbasic_l2p_ch +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xrbasic_l2p_rom.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xrbasic_l2p_rom +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xrbasic_lif_csr.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xrbasic_lif_csr +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xrbasic_lif.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xrbasic_lif +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_xcvr_reconfig_basic.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_reconfig_basic +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_arbiter_acq.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_arbiter_acq +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_basic.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_basic +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_arbiter.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_arbiter +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_m2s.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_m2s +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_wait_generate.v +Sat 21:50: INFO : Info (12023): Found entity 1: altera_wait_generate +Sat 21:50: INFO : Info (12021): Found 3 design units, including 3 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_csr_selector.sv +Sat 21:50: INFO : Info (12023): Found entity 1: csr_mux +Sat 21:50: INFO : Info (12023): Found entity 2: csr_indexed_write_mux +Sat 21:50: INFO : Info (12023): Found entity 3: csr_indexed_read_only_reg +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/sv_reconfig_bundle_to_basic.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_reconfig_bundle_to_basic +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu.v +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu +Sat 21:50: INFO : Info (12021): Found 3 design units, including 3 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_reconfig_cpu.v +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module +Sat 21:50: INFO : Info (12023): Found entity 2: alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module +Sat 21:50: INFO : Info (12023): Found entity 3: alt_xcvr_reconfig_cpu_reconfig_cpu +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench.v +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0.v +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0 +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_irq_mapper.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_irq_mapper +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_reset_controller.v +Sat 21:50: INFO : Info (12023): Found entity 1: altera_reset_controller +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_reset_synchronizer.v +Sat 21:50: INFO : Info (12023): Found entity 1: altera_reset_synchronizer +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_merlin_master_translator.sv +Sat 21:50: INFO : Info (12023): Found entity 1: altera_merlin_master_translator +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_merlin_slave_translator.sv +Sat 21:50: INFO : Info (12023): Found entity 1: altera_merlin_slave_translator +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_merlin_master_agent.sv +Sat 21:50: INFO : Info (12023): Found entity 1: altera_merlin_master_agent +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_merlin_slave_agent.sv +Sat 21:50: INFO : Info (12023): Found entity 1: altera_merlin_slave_agent +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_merlin_burst_uncompressor.sv +Sat 21:50: INFO : Info (12023): Found entity 1: altera_merlin_burst_uncompressor +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_avalon_sc_fifo.v +Sat 21:50: INFO : Info (12023): Found entity 1: altera_avalon_sc_fifo +Sat 21:50: INFO : Info (12021): Found 2 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_default_decode +Sat 21:50: INFO : Info (12023): Found entity 2: alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router +Sat 21:50: INFO : Info (12021): Found 2 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001_default_decode +Sat 21:50: INFO : Info (12023): Found entity 2: alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_default_decode +Sat 21:50: INFO : Info (12023): Found entity 2: alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router +Sat 21:50: INFO : Info (12021): Found 2 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001_default_decode +Sat 21:50: INFO : Info (12023): Found entity 2: alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001 +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux_001.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux_001 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/altera_merlin_arbitrator.sv +Sat 21:50: INFO : Info (12023): Found entity 1: altera_merlin_arbitrator +Sat 21:50: INFO : Info (12023): Found entity 2: altera_merlin_arb_adder +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux_001.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux_001 +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_xcvr_reconfig_SV/pcie_reconfig_SV/alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux_001.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux_001 +Sat 21:50: INFO : Info (12021): Found 4 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1/MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1_altclkctrl_blh-RTL +Sat 21:50: INFO : Info (12022): Found design unit 2: mwaltclkctrl_quartusv13_1_0_gclk_numclk_1-RTL +Sat 21:50: INFO : Info (12023): Found entity 1: MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1_altclkctrl_blh +Sat 21:50: INFO : Info (12023): Found entity 2: MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: pcie_SV_hard_ip-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: pcie_SV_hard_ip +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/altpcie_sv_hip_ast_hwtcl.v +Sat 21:50: INFO : Info (12023): Found entity 1: altpcie_sv_hip_ast_hwtcl +Sat 21:50: INFO : Warning (10229): Verilog HDL Expression warning at altpcie_hip_256_pipen1b.v(1142): truncated literal to match 128 bits +Sat 21:50: INFO : Info (12021): Found 7 design units, including 7 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/altpcie_hip_256_pipen1b.v +Sat 21:50: INFO : Info (12023): Found entity 1: altpcie_hip_256_pipen1b +Sat 21:50: INFO : Info (12023): Found entity 2: altpcie_hip_bitsync2 +Sat 21:50: INFO : Info (12023): Found entity 3: altpcie_hip_bitsync +Sat 21:50: INFO : Info (12023): Found entity 4: altpcie_hip_vecsync2 +Sat 21:50: INFO : Info (12023): Found entity 5: altpcie_hip_vecsync +Sat 21:50: INFO : Info (12023): Found entity 6: hd_altpe3_hip_eq_bypass_ph3 +Sat 21:50: INFO : Info (12023): Found entity 7: hip_eq_dprio +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/altpcie_rs_serdes.v +Sat 21:50: INFO : Info (12023): Found entity 1: altpcie_rs_serdes +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/altpcie_rs_hip.v +Sat 21:50: INFO : Info (12023): Found entity 1: altpcie_rs_hip +Sat 21:50: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/altera_xcvr_functions.sv +Sat 21:50: INFO : Info (12022): Found design unit 1: altera_xcvr_functions (SystemVerilog) (pcie_SV_hard_ip) +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_pcs.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_pcs +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_pcs_ch.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_pcs_ch +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_pma.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_pma +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_reconfig_bundle_to_xcvr.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_reconfig_bundle_to_xcvr +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_reconfig_bundle_to_ip.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_reconfig_bundle_to_ip +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_reconfig_bundle_merger.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_reconfig_bundle_merger +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_rx_pma.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_rx_pma +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_tx_pma.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_tx_pma +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_tx_pma_ch.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_tx_pma_ch +Sat 21:50: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_h.sv +Sat 21:50: INFO : Info (12022): Found design unit 1: sv_xcvr_h (SystemVerilog) (pcie_SV_hard_ip) +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_avmm_csr.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_avmm_csr +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_avmm_dcd.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_avmm_dcd +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_avmm.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_avmm +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_data_adapter.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_data_adapter +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_native.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_native +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_plls.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_plls +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/alt_xcvr_resync.sv +Sat 21:50: INFO : Info (12023): Found entity 1: alt_xcvr_resync +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_10g_rx_pcs_rbc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_hssi_10g_rx_pcs_rbc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_10g_tx_pcs_rbc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_hssi_10g_tx_pcs_rbc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_8g_rx_pcs_rbc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_hssi_8g_rx_pcs_rbc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_8g_tx_pcs_rbc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_hssi_8g_tx_pcs_rbc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_8g_pcs_aggregate_rbc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_hssi_8g_pcs_aggregate_rbc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_common_pcs_pma_interface_rbc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_hssi_common_pcs_pma_interface_rbc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_common_pld_pcs_interface_rbc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_hssi_common_pld_pcs_interface_rbc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_pipe_gen1_2_rbc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_hssi_pipe_gen1_2_rbc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_pipe_gen3_rbc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_hssi_pipe_gen3_rbc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_rx_pcs_pma_interface_rbc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_hssi_rx_pcs_pma_interface_rbc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_rx_pld_pcs_interface_rbc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_hssi_rx_pld_pcs_interface_rbc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_tx_pcs_pma_interface_rbc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_hssi_tx_pcs_pma_interface_rbc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_hssi_tx_pld_pcs_interface_rbc.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_hssi_tx_pld_pcs_interface_rbc +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_emsip_adapter.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_emsip_adapter +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/sv_xcvr_pipe_native.sv +Sat 21:50: INFO : Info (12023): Found entity 1: sv_xcvr_pipe_native +Sat 21:50: INFO : Info (12021): Found 1 design units, including 0 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/alt_xcvr_reconfig_h.sv +Sat 21:50: INFO : Info (12022): Found design unit 1: alt_xcvr_reconfig_h (SystemVerilog) (pcie_SV_hard_ip) +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_SV_hard_ip/pcie_SV_hard_ip/altpcie_reconfig_driver.sv +Sat 21:50: INFO : Info (12023): Found entity 1: altpcie_reconfig_driver +Sat 21:50: INFO : Info (12021): Found 4 design units, including 2 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena/MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena_altclkctrl_tmg-RTL +Sat 21:50: INFO : Info (12022): Found design unit 2: mwaltclkctrl_quartusv13_1_0_auto_numclk_1_ena-RTL +Sat 21:50: INFO : Info (12023): Found entity 1: MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena_altclkctrl_tmg +Sat 21:50: INFO : Info (12023): Found entity 2: MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena +Sat 21:50: INFO : Info (12021): Found 6 design units, including 6 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_pll_reconfig_top/altera_pll_reconfig_top.v +Sat 21:50: INFO : Info (12023): Found entity 1: altera_pll_reconfig_top +Sat 21:50: INFO : Info (12023): Found entity 2: self_reset +Sat 21:50: INFO : Info (12023): Found entity 3: dprio_mux +Sat 21:50: INFO : Info (12023): Found entity 4: fpll_dprio_init +Sat 21:50: INFO : Info (12023): Found entity 5: dyn_phase_shift +Sat 21:50: INFO : Info (12023): Found entity 6: generic_lcell_comb +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "shreg_extract" at ../../../reset_control/reset_control.vhd(35) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/reset_control/reset_control.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: reset_control-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: reset_control +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../max_SV_pcie_rx/max_SV_pcie_rx.vhd(157) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/max_SV_pcie_rx/max_SV_pcie_rx.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: max_SV_pcie_rx-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: max_SV_pcie_rx +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../max_SV_pcie_tx/max_SV_pcie_tx.vhd(170) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/max_SV_pcie_tx/max_SV_pcie_tx.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: max_SV_pcie_tx-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: max_SV_pcie_tx +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../max_pcie_slave_req_dispatcher/max_pcie_slave_req_dispatcher.vhd(65) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/max_pcie_slave_req_dispatcher/max_pcie_slave_req_dispatcher.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: max_pcie_slave_req_dispatcher-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: max_pcie_slave_req_dispatcher +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../max_SV_pcie_slave/max_SV_pcie_slave.vhd(322) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/max_SV_pcie_slave/max_SV_pcie_slave.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: max_SV_pcie_slave-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: max_SV_pcie_slave +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/start_of_day_reset/start_of_day_reset.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: start_of_day_reset-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: start_of_day_reset +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/perf_monitor/perf_monitor.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: perf_monitor-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: perf_monitor +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_posted_credits_writer/pcie_posted_credits_writer.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: pcie_posted_credits_writer-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: pcie_posted_credits_writer +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_slave_streaming_sfh_ring/pcie_slave_streaming_sfh_ring.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: pcie_slave_streaming_sfh_ring-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: pcie_slave_streaming_sfh_ring +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/pcie_slave_streaming_sth_ring/pcie_slave_streaming_sth_ring.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: pcie_slave_streaming_sth_ring-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: pcie_slave_streaming_sth_ring +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/fast_request_arbiter/fast_request_arbiter.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: fast_request_arbiter-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: fast_request_arbiter +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/priority_encoder/priority_encoder.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: priority_encoder-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: priority_encoder +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/write_request_encoder/write_request_encoder.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: write_request_encoder-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: write_request_encoder +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/mapped_register_readable/mapped_register_readable.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: mapped_register_readable-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: mapped_register_readable +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../dualaspectmuxpipe_mux2/dualaspectmuxpipe_mux2.vhd(40) +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "max_fanout" at ../../../dualaspectmuxpipe_mux2/dualaspectmuxpipe_mux2.vhd(43) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/dualaspectmuxpipe_mux2/dualaspectmuxpipe_mux2.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: dualaspectmuxpipe_mux2-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: dualaspectmuxpipe_mux2 +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../dualaspectmuxpipe_mux4/dualaspectmuxpipe_mux4.vhd(40) +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "max_fanout" at ../../../dualaspectmuxpipe_mux4/dualaspectmuxpipe_mux4.vhd(43) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/dualaspectmuxpipe_mux4/dualaspectmuxpipe_mux4.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: dualaspectmuxpipe_mux4-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: dualaspectmuxpipe_mux4 +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../dualaspectmuxpipe_counter/dualaspectmuxpipe_counter.vhd(55) +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "max_fanout" at ../../../dualaspectmuxpipe_counter/dualaspectmuxpipe_counter.vhd(64) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/dualaspectmuxpipe_counter/dualaspectmuxpipe_counter.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: dualaspectmuxpipe_counter-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: dualaspectmuxpipe_counter +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../dualaspectreg_int/dualaspectreg_int.vhd(27) +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "max_fanout" at ../../../dualaspectreg_int/dualaspectreg_int.vhd(37) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/dualaspectreg_int/dualaspectreg_int.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: dualaspectreg_int-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: dualaspectreg_int +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "max_fanout" at ../../../mapped_register/mapped_register.vhd(27) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/mapped_register/mapped_register.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: mapped_register-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: mapped_register +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49/FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49-StateMachine +Sat 21:50: INFO : Info (12023): Found entity 1: FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SimpleSR/SimpleSR.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SimpleSR-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SimpleSR +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33/FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33-StateMachine +Sat 21:50: INFO : Info (12023): Found entity 1: FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/signal_forwarding_adapter/signal_forwarding_adapter.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: signal_forwarding_adapter-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: signal_forwarding_adapter +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/common_packet_parser/common_packet_parser.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: common_packet_parser-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: common_packet_parser +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/mapped_memories_adapter/mapped_memories_adapter.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: mapped_memories_adapter-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: mapped_memories_adapter +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/mapped_memories_controller_core/mapped_memories_controller_core.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: mapped_memories_controller_core-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: mapped_memories_controller_core +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/mapped_registers_controller/mapped_registers_controller.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: mapped_registers_controller-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: mapped_registers_controller +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/mec_switch_arbiter/mec_switch_arbiter.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: mec_switch_arbiter-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: mec_switch_arbiter +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/mapped_clock_control/mapped_clock_control.vhd +Sat 21:50: INFO : Info (12022): Found design unit 1: mapped_clock_control-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: mapped_clock_control +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/mec_switch_arbiter_i.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: mec_switch_arbiter_i-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: mec_switch_arbiter_i +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MappedClockControl_id_3e.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MappedClockControl_id_3e-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MappedClockControl_id_3e +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/stream_clkprim_lock_count_32.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: stream_clkprim_lock_count_32-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: stream_clkprim_lock_count_32 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SanityBlock_cclk_STREAM_clk_pcie.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SanityBlock_cclk_STREAM_clk_pcie-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SanityBlock_cclk_STREAM_clk_pcie +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/mapped_element_switch/mapped_element_switch.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: mapped_element_switch-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: mapped_element_switch +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/mapped_element_switch/src_to_dst_control.quartus.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: src_to_dst_control-rtl +Sat 21:50: INFO : Info (12023): Found entity 1: src_to_dst_control +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MAX4MAIAPeripheryTop.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MAX4MAIAPeripheryTop-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MAX4MAIAPeripheryTop +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MAX4CPLDInterface.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MAX4CPLDInterface-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MAX4CPLDInterface +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MAXEvents.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MAXEvents-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MAXEvents +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/StratixPCIeBase.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: StratixPCIeBase-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: StratixPCIeBase +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/TransceiverReconfig.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: TransceiverReconfig-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: TransceiverReconfig +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../StratixVHardIPPCIe.vhdl(503) +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../StratixVHardIPPCIe.vhdl(510) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/StratixVHardIPPCIe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: StratixVHardIPPCIe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: StratixVHardIPPCIe +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraClockGenerator_250_200_STREAM.vhdl(107) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraClockGenerator_250_200_STREAM.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraClockGenerator_250_200_STREAM-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraClockGenerator_250_200_STREAM +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../StratixVClockManager_in250_out_f200p0dc50_f200p180dc50.vhdl(276) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/StratixVClockManager_in250_out_f200p0dc50_f200p180dc50.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: StratixVClockManager_in250_out_f200p0dc50_f200p180dc50-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: StratixVClockManager_in250_out_f200p0dc50_f200p180dc50 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MAX4FPGATop.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MAX4FPGATop-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MAX4FPGATop +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv496.vhdl(113) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv496.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv496-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv496 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126.vhdl(115) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PCIeEA.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PCIeEA-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PCIeEA +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384.vhdl(113) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384 +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_34_512_34_dualclock_aclr.vhdl(110) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_34_512_34_dualclock_aclr.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_34_512_34_dualclock_aclr-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_34_512_34_dualclock_aclr +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/StratixPCIeInterface.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: StratixPCIeInterface-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: StratixPCIeInterface +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MAX4PCIeSlaveInterface.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MAX4PCIeSlaveInterface-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MAX4PCIeSlaveInterface +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/FPGAWrapperEntity_Manager_FetchSubTuple.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: FPGAWrapperEntity_Manager_FetchSubTuple-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: FPGAWrapperEntity_Manager_FetchSubTuple +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PerfMonitor.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PerfMonitor-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PerfMonitor +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MappedElementAdapterForwarder.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MappedElementAdapterForwarder-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MappedElementAdapterForwarder +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PCIeStreaming_2_3.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PCIeStreaming_2_3-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PCIeStreaming_2_3 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PCIeSlaveStreamFromHost.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PCIeSlaveStreamFromHost-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PCIeSlaveStreamFromHost +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PCIeSlaveStreamToHost.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PCIeSlaveStreamToHost-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PCIeSlaveStreamToHost +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SlaveStreamingCreditsBarParser.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SlaveStreamingCreditsBarParser-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SlaveStreamingCreditsBarParser +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SlaveStreamingRingConfigBarParser.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SlaveStreamingRingConfigBarParser-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SlaveStreamingRingConfigBarParser +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MemWriteRequestArbiter.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MemWriteRequestArbiter-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MemWriteRequestArbiter +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/FastRequestArbiter_req4.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: FastRequestArbiter_req4-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: FastRequestArbiter_req4 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/TagGenerator.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: TagGenerator-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: TagGenerator +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/RequestEncoder.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: RequestEncoder-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: RequestEncoder +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_128_512_128_aclr_afv448.vhdl(104) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_128_512_128_aclr_afv448.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_128_512_128_aclr_afv448-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_128_512_128_aclr_afv448 +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_115_512_115_aclr_fwft.vhdl(101) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_115_512_115_aclr_fwft.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_115_512_115_aclr_fwft-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_115_512_115_aclr_fwft +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/ReadComplRequestArbiter.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: ReadComplRequestArbiter-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: ReadComplRequestArbiter +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/FastRequestArbiter_req1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: FastRequestArbiter_req1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: FastRequestArbiter_req1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MappedRegBlock_921618fecb8cf8badc2cf71cbe32b185.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MappedRegBlock_921618fecb8cf8badc2cf71cbe32b185-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MappedRegBlock_921618fecb8cf8badc2cf71cbe32b185 +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../Manager_FetchSubTuple.vhdl(407) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_21.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_21-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_21 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477.vhdl(115) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_19.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_19-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_19 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/StreamFifo_altera_4096_4096_512_pushin_sl5_pullout_el1_singleclock_errflgs.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: StreamFifo_altera_4096_4096_512_pushin_sl5_pullout_el1_singleclock_errflgs-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: StreamFifo_altera_4096_4096_512_pushin_sl5_pullout_el1_singleclock_errflgs +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_4096_512_4096_aclr_afv474_of_uf.vhdl(106) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_4096_512_4096_aclr_afv474_of_uf.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_4096_512_4096_aclr_afv474_of_uf-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_4096_512_4096_aclr_afv474_of_uf +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_17.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_17-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_17 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7.vhdl(117) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_13.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_13-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_13 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_4096_512_4096_aclr_afv510_aev8_of_uf.vhdl(109) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_4096_512_4096_aclr_afv510_aev8_of_uf.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_4096_512_4096_aclr_afv510_aev8_of_uf-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_4096_512_4096_aclr_afv510_aev8_of_uf +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_15.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_15-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_15 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_128_512_128_aclr_afv477_of_uf.vhdl(106) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_128_512_128_aclr_afv477_of_uf.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_128_512_128_aclr_afv477_of_uf-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_128_512_128_aclr_afv477_of_uf +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_11.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_11-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_11 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_8.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_8-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_8 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/DualAspectMux_4096_128_COUNTER_PIPELINED_LIMITED.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: DualAspectMux_4096_128_COUNTER_PIPELINED_LIMITED-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: DualAspectMux_4096_128_COUNTER_PIPELINED_LIMITED +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/DualAspectCounterPipelined_128_4096.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: DualAspectCounterPipelined_128_4096-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: DualAspectCounterPipelined_128_4096 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_4.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_4-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_4 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/DualAspectMux_128_32_COUNTER_PIPELINED.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: DualAspectMux_128_32_COUNTER_PIPELINED-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: DualAspectMux_128_32_COUNTER_PIPELINED +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/DualAspectCounterPipelined_32_128.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: DualAspectCounterPipelined_32_128-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: DualAspectCounterPipelined_32_128 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_Stream_1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_Stream_1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/DualAspectReg_128_4096.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: DualAspectReg_128_4096-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: DualAspectReg_128_4096 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/WrapperNodeIO_output.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: WrapperNodeIO_output-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: WrapperNodeIO_output +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/WrapperNodeIO_sizes.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: WrapperNodeIO_sizes-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: WrapperNodeIO_sizes +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/WrapperNodeIO_input.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: WrapperNodeIO_input-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: WrapperNodeIO_input +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "buffer_type" at ../../../FetchSubTupleKernel_streamwrapper.vhdl(347) +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "buffer_type" at ../../../FetchSubTupleKernel_streamwrapper.vhdl(348) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/FetchSubTupleKernel_streamwrapper.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: FetchSubTupleKernel_streamwrapper-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: FetchSubTupleKernel_streamwrapper +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/FlushLevelCounter_1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: FlushLevelCounter_1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: FlushLevelCounter_1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/FillLevelCounter_0.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: FillLevelCounter_0-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: FillLevelCounter_0 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MappedRegBlock_b5497fa47497f5c6632937a587d5df01.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MappedRegBlock_b5497fa47497f5c6632937a587d5df01-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MappedRegBlock_b5497fa47497f5c6632937a587d5df01 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/FetchSubTupleKernel.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: FetchSubTupleKernel-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: FetchSubTupleKernel +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_EQ_48_0_UNSIGNED_48_0_UNSIGNED_growbits_pipe1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCFixed_EQ_48_0_UNSIGNED_48_0_UNSIGNED_growbits_pipe1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCFixed_EQ_48_0_UNSIGNED_48_0_UNSIGNED_growbits_pipe1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/StateMachineEntity_FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: StateMachineEntity_FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: StateMachineEntity_FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/OutputRegisterEntity_48with_reset.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: OutputRegisterEntity_48with_reset-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: OutputRegisterEntity_48with_reset +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PhotonMUX_1_2_64_nopipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PhotonMUX_1_2_64_nopipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PhotonMUX_1_2_64_nopipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_64x1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MultiStageDelay_64x1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MultiStageDelay_64x1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_64x1_reg1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SRLDelay_64x1_reg1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SRLDelay_64x1_reg1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PhotonBitwiseOp_1_Andnopipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PhotonBitwiseOp_1_Andnopipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PhotonBitwiseOp_1_Andnopipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_EQ_2_0_UNSIGNED_2_0_UNSIGNED_growbits_nopipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCFixed_EQ_2_0_UNSIGNED_2_0_UNSIGNED_growbits_nopipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCFixed_EQ_2_0_UNSIGNED_2_0_UNSIGNED_growbits_nopipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PhotonMUX_1_2_2_nopipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PhotonMUX_1_2_2_nopipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PhotonMUX_1_2_2_nopipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_2x4.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MultiStageDelay_2x4-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MultiStageDelay_2x4 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_2x4_reg1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SRLDelay_2x4_reg1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SRLDelay_2x4_reg1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/Pulse_cycles1_initT.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: Pulse_cycles1_initT-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: Pulse_cycles1_initT +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_1x4.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MultiStageDelay_1x4-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MultiStageDelay_1x4 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_1x4_reg1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SRLDelay_1x4_reg1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SRLDelay_1x4_reg1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_2x1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MultiStageDelay_2x1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MultiStageDelay_2x1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_2x1_reg1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SRLDelay_2x1_reg1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SRLDelay_2x1_reg1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_ADD_2_0_UNSIGNED_2_0_UNSIGNED_nogrowbits_nopipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCFixed_ADD_2_0_UNSIGNED_2_0_UNSIGNED_nogrowbits_nopipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCFixed_ADD_2_0_UNSIGNED_2_0_UNSIGNED_nogrowbits_nopipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_SUB_2_0_UNSIGNED_2_0_UNSIGNED_nogrowbits_nopipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCFixed_SUB_2_0_UNSIGNED_2_0_UNSIGNED_nogrowbits_nopipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCFixed_SUB_2_0_UNSIGNED_2_0_UNSIGNED_nogrowbits_nopipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/InputRegisterEntity2013_4096.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: InputRegisterEntity2013_4096-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: InputRegisterEntity2013_4096 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_1x4_reg2.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SRLDelay_1x4_reg2-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SRLDelay_1x4_reg2 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PhotonBitwiseNot_1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PhotonBitwiseNot_1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PhotonBitwiseNot_1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PhotonBitwiseOp_1_Andpipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PhotonBitwiseOp_1_Andpipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PhotonBitwiseOp_1_Andpipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_1x10.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MultiStageDelay_1x10-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MultiStageDelay_1x10 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_1x10_reg1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SRLDelay_1x10_reg1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SRLDelay_1x10_reg1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PhotonBitwiseOp_1_Orpipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PhotonBitwiseOp_1_Orpipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PhotonBitwiseOp_1_Orpipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_GT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCFixed_GT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCFixed_GT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_LT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCFixed_LT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCFixed_LT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PhotonMUX_1_2_1_pipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PhotonMUX_1_2_1_pipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PhotonMUX_1_2_1_pipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_LT_2_0_UNSIGNED_2_0_UNSIGNED_growbits_nopipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCFixed_LT_2_0_UNSIGNED_2_0_UNSIGNED_growbits_nopipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCFixed_LT_2_0_UNSIGNED_2_0_UNSIGNED_growbits_nopipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/WordLevelShifter_Left_Circular_1_64_6.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: WordLevelShifter_Left_Circular_1_64_6-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: WordLevelShifter_Left_Circular_1_64_6 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCSingleLUTConstDiv_n3_d3_quotient_remainder_lat0.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCSingleLUTConstDiv_n3_d3_quotient_remainder_lat0-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCSingleLUTConstDiv_n3_d3_quotient_remainder_lat0 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCSingleLUTConstDiv_n4_d3_quotient_remainder_lat0.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCSingleLUTConstDiv_n4_d3_quotient_remainder_lat0-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCSingleLUTConstDiv_n4_d3_quotient_remainder_lat0 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCSingleLUTConstDiv_n5_d3_quotient_remainder_lat0.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCSingleLUTConstDiv_n5_d3_quotient_remainder_lat0-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCSingleLUTConstDiv_n5_d3_quotient_remainder_lat0 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCSingleLUTConstDiv_n6_d3_quotient_remainder_lat0.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCSingleLUTConstDiv_n6_d3_quotient_remainder_lat0-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCSingleLUTConstDiv_n6_d3_quotient_remainder_lat0 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_6x1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MultiStageDelay_6x1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MultiStageDelay_6x1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_6x1_reg1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SRLDelay_6x1_reg1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SRLDelay_6x1_reg1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PhotonMUX_1_2_6_nopipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PhotonMUX_1_2_6_nopipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PhotonMUX_1_2_6_nopipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_ADD_7_0_UNSIGNED_7_0_UNSIGNED_nogrowbits_nopipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCFixed_ADD_7_0_UNSIGNED_7_0_UNSIGNED_nogrowbits_nopipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCFixed_ADD_7_0_UNSIGNED_7_0_UNSIGNED_nogrowbits_nopipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixedCast_6_0_UNSIGNED_7_0_UNSIGNED_TONEAR_nopipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCFixedCast_6_0_UNSIGNED_7_0_UNSIGNED_TONEAR_nopipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCFixedCast_6_0_UNSIGNED_7_0_UNSIGNED_TONEAR_nopipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixed_LT_6_0_UNSIGNED_6_0_UNSIGNED_growbits_pipe1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCFixed_LT_6_0_UNSIGNED_6_0_UNSIGNED_growbits_pipe1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCFixed_LT_6_0_UNSIGNED_6_0_UNSIGNED_growbits_pipe1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MaxDCFixedCast_32_0_UNSIGNED_6_0_UNSIGNED_TONEAR_pipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MaxDCFixedCast_32_0_UNSIGNED_6_0_UNSIGNED_TONEAR_pipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MaxDCFixedCast_32_0_UNSIGNED_6_0_UNSIGNED_TONEAR_pipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/PhotonMUX_1_2_32_pipe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: PhotonMUX_1_2_32_pipe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: PhotonMUX_1_2_32_pipe +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/InputRegisterEntity2013_32.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: InputRegisterEntity2013_32-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: InputRegisterEntity2013_32 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_1x5.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MultiStageDelay_1x5-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MultiStageDelay_1x5 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_1x5_reg1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SRLDelay_1x5_reg1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SRLDelay_1x5_reg1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MultiStageDelay_1x1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MultiStageDelay_1x1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MultiStageDelay_1x1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_1x1_reg1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SRLDelay_1x1_reg1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SRLDelay_1x1_reg1 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/StateMachineEntity_FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: StateMachineEntity_FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: StateMachineEntity_FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MappedDRP_Addr_3c0000_ChecksumMappedDRP.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MappedDRP_Addr_3c0000_ChecksumMappedDRP-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MappedDRP_Addr_3c0000_ChecksumMappedDRP +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/ChecksumMappedDRP_RAM.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: ChecksumMappedDRP_RAM-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: ChecksumMappedDRP_RAM +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SRLDelay_1x2_reg1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SRLDelay_1x2_reg1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SRLDelay_1x2_reg1 +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0.vhdl(219) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/SignalForwardingEA.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: SignalForwardingEA-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: SignalForwardingEA +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/CommonPacketParser_SignalForwarding.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: CommonPacketParser_SignalForwarding-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: CommonPacketParser_SignalForwarding +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/ControlMux.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: ControlMux-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: ControlMux +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1.vhdl(328) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1 +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_36_512_36_dualclock_aclr.vhdl(110) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_36_512_36_dualclock_aclr.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_36_512_36_dualclock_aclr-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_36_512_36_dualclock_aclr +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "box_type" at ../../../AlteraFifoEntity_71_512_71_dualclock_aclr.vhdl(110) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/AlteraFifoEntity_71_512_71_dualclock_aclr.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: AlteraFifoEntity_71_512_71_dualclock_aclr-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: AlteraFifoEntity_71_512_71_dualclock_aclr +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MappedMemoriesEA.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MappedMemoriesEA-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MappedMemoriesEA +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/CommonPacketParser_MappedMemories.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: CommonPacketParser_MappedMemories-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: CommonPacketParser_MappedMemories +Sat 21:50: INFO : Warning (10335): Unrecognized synthesis attribute "keep_hierarchy" at ../../../MappedRegistersController_48.vhdl(193) +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MappedRegistersController_48.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MappedRegistersController_48-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MappedRegistersController_48 +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MappedRegistersEA.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MappedRegistersEA-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MappedRegistersEA +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/CommonPacketParser_MappedRegisters.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: CommonPacketParser_MappedRegisters-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: CommonPacketParser_MappedRegisters +Sat 21:50: INFO : Info (12021): Found 2 design units, including 1 entities, in source file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe.vhdl +Sat 21:50: INFO : Info (12022): Found design unit 1: MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe-MaxDC +Sat 21:50: INFO : Info (12023): Found entity 1: MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe +Sat 21:50: INFO : Info (12127): Elaborating entity "MAX4MAIAPeripheryTop" for the top level hierarchy +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(541): object "pciebase_i_sim_pipe_rate" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(542): object "pciebase_i_sim_ltssmstate" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(543): object "pciebase_i_eidleinfersel0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(544): object "pciebase_i_eidleinfersel1" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(545): object "pciebase_i_eidleinfersel2" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(546): object "pciebase_i_eidleinfersel3" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(547): object "pciebase_i_eidleinfersel4" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(548): object "pciebase_i_eidleinfersel5" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(549): object "pciebase_i_eidleinfersel6" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(550): object "pciebase_i_eidleinfersel7" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(551): object "pciebase_i_powerdown0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(552): object "pciebase_i_powerdown1" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(553): object "pciebase_i_powerdown2" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(554): object "pciebase_i_powerdown3" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(555): object "pciebase_i_powerdown4" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(556): object "pciebase_i_powerdown5" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(557): object "pciebase_i_powerdown6" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(558): object "pciebase_i_powerdown7" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(559): object "pciebase_i_rxpolarity0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(560): object "pciebase_i_rxpolarity1" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(561): object "pciebase_i_rxpolarity2" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(562): object "pciebase_i_rxpolarity3" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(563): object "pciebase_i_rxpolarity4" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(564): object "pciebase_i_rxpolarity5" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(565): object "pciebase_i_rxpolarity6" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(566): object "pciebase_i_rxpolarity7" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(567): object "pciebase_i_txcompl0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(568): object "pciebase_i_txcompl1" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(569): object "pciebase_i_txcompl2" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(570): object "pciebase_i_txcompl3" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(571): object "pciebase_i_txcompl4" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(572): object "pciebase_i_txcompl5" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(573): object "pciebase_i_txcompl6" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(574): object "pciebase_i_txcompl7" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(575): object "pciebase_i_txdata0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(576): object "pciebase_i_txdata1" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(577): object "pciebase_i_txdata2" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(578): object "pciebase_i_txdata3" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(579): object "pciebase_i_txdata4" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(580): object "pciebase_i_txdata5" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(581): object "pciebase_i_txdata6" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(582): object "pciebase_i_txdata7" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(583): object "pciebase_i_txdatak0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(584): object "pciebase_i_txdatak1" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(585): object "pciebase_i_txdatak2" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(586): object "pciebase_i_txdatak3" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(587): object "pciebase_i_txdatak4" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(588): object "pciebase_i_txdatak5" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(589): object "pciebase_i_txdatak6" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(590): object "pciebase_i_txdatak7" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(591): object "pciebase_i_txdetectrx0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(592): object "pciebase_i_txdetectrx1" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(593): object "pciebase_i_txdetectrx2" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(594): object "pciebase_i_txdetectrx3" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(595): object "pciebase_i_txdetectrx4" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(596): object "pciebase_i_txdetectrx5" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(597): object "pciebase_i_txdetectrx6" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(598): object "pciebase_i_txdetectrx7" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(599): object "pciebase_i_txelecidle0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(600): object "pciebase_i_txelecidle1" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(601): object "pciebase_i_txelecidle2" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(602): object "pciebase_i_txelecidle3" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(603): object "pciebase_i_txelecidle4" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(604): object "pciebase_i_txelecidle5" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(605): object "pciebase_i_txelecidle6" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(606): object "pciebase_i_txelecidle7" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(607): object "pciebase_i_txdeemph0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(608): object "pciebase_i_txdeemph1" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(609): object "pciebase_i_txdeemph2" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(610): object "pciebase_i_txdeemph3" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(611): object "pciebase_i_txdeemph4" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(612): object "pciebase_i_txdeemph5" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(613): object "pciebase_i_txdeemph6" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(614): object "pciebase_i_txdeemph7" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(615): object "pciebase_i_txswing0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(616): object "pciebase_i_txswing1" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(617): object "pciebase_i_txswing2" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(618): object "pciebase_i_txswing3" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(619): object "pciebase_i_txswing4" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(620): object "pciebase_i_txswing5" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(621): object "pciebase_i_txswing6" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(622): object "pciebase_i_txswing7" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(623): object "pciebase_i_txmargin0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(624): object "pciebase_i_txmargin1" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(625): object "pciebase_i_txmargin2" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(626): object "pciebase_i_txmargin3" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(627): object "pciebase_i_txmargin4" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(628): object "pciebase_i_txmargin5" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(629): object "pciebase_i_txmargin6" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(630): object "pciebase_i_txmargin7" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(643): object "max4_cpld_top_level_qsfp_top_i2c_scl_fb" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(644): object "max4_cpld_top_level_qsfp_top_i2c_sda_fb" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(645): object "max4_cpld_top_level_qsfp_top_i2c_alert" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(646): object "max4_cpld_top_level_qsfp_top_i2c_modprsl" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(647): object "max4_cpld_top_level_qsfp_mid_i2c_scl_fb" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(648): object "max4_cpld_top_level_qsfp_mid_i2c_sda_fb" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(649): object "max4_cpld_top_level_qsfp_mid_i2c_alert" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(650): object "max4_cpld_top_level_qsfp_mid_i2c_modprsl" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(651): object "max4_cpld_top_level_qsfp_bot_i2c_scl_fb" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(652): object "max4_cpld_top_level_qsfp_bot_i2c_sda_fb" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(653): object "max4_cpld_top_level_qsfp_bot_i2c_alert" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4MAIAPeripheryTop.vhdl(654): object "max4_cpld_top_level_qsfp_bot_i2c_modprsl" assigned a value but never read +Sat 21:50: INFO : Info (12128): Elaborating entity "MAX4FPGATop" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i" +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(724): object "wrapper_pcie_pcie_control_sfh_done" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(726): object "wrapper_pcie_pcie_control_sth_stall" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(743): object "max4pcieslaveinterface_i_flush" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(745): object "max4pcieslaveinterface_i_soft_reset" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(746): object "max4pcieslaveinterface_i_throttle_limit" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(773): object "max4pcieslaveinterface_i_maxring_s_fh" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(774): object "max4pcieslaveinterface_i_maxring_s_set_highz_n" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(775): object "max4pcieslaveinterface_i_maxring_id_fh" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(776): object "max4pcieslaveinterface_i_maxring_id_set_highz_n" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(790): object "max4pcieslaveinterface_i_ptp_phy_sresetn" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(791): object "max4pcieslaveinterface_i_compl_fifo_flags" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(794): object "max4pcieslaveinterface_i_compute_reset_n" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(801): object "max4pcieslaveinterface_i_local_ifpga_session_key" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(907): object "ftb_archange_mappedelementsswitchpcieea_dbg_empty" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(908): object "ftb_archange_mappedelementsswitchpcieea_dbg_stall" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(911): object "ftb_archange_mappedelementsswitchpcieea_outputstream_push_done" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(914): object "ftb_mappedelementsswitchpcieea_full" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4FPGATop.vhdl(916): object "ftb_mappedelementsswitchpcieea_wr_data_count" assigned a value but never read +Sat 21:50: INFO : Info (12128): Elaborating entity "FPGAWrapperEntity_Manager_FetchSubTuple" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper" +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(631): object "inst_ln11_synchroniser_level_dst" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(632): object "inst_ln11_synchroniser1_level_dst" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(633): object "inst_ln11_synchroniser2_level_dst" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(645): object "inst_ln32_mappedclockcontrol_clkbuf_clksel0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(708): object "signalforwardingadapter_i_port_out_sysmon_reset" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(709): object "signalforwardingadapter_i_port_out_pcc_switch_regs" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(710): object "signalforwardingadapter_i_port_out_pcc_start" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at FPGAWrapperEntity_Manager_FetchSubTuple.vhdl(711): object "signalforwardingadapter_i_port_out_pcc_reset" assigned a value but never read +Sat 21:50: INFO : Info (12128): Elaborating entity "basic_synchroniser" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|basic_synchroniser:inst_ln11_synchroniser" +Sat 21:50: INFO : Info (12128): Elaborating entity "basic_synchroniser_prim" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|basic_synchroniser:inst_ln11_synchroniser|basic_synchroniser_prim:\g_wide:0:g_width1:sync_level_src" +Sat 21:50: INFO : Warning (10542): VHDL Variable Declaration warning at basic_synchroniser.vhd(67): used initial value expression for variable "n" because variable was never assigned a value +Sat 21:50: INFO : Info (12128): Elaborating entity "dff_ce_asyncsr" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|basic_synchroniser:inst_ln11_synchroniser|basic_synchroniser_prim:\g_wide:0:g_width1:sync_level_src|dff_ce_asyncsr:\g_slice_packing:0:i_sync0" +Sat 21:50: INFO : Info (12128): Elaborating entity "LPM_FF" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|basic_synchroniser:inst_ln11_synchroniser|basic_synchroniser_prim:\g_wide:0:g_width1:sync_level_src|dff_ce_asyncsr:\g_slice_packing:0:i_sync0|LPM_FF:dff" +Sat 21:50: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|basic_synchroniser:inst_ln11_synchroniser|basic_synchroniser_prim:\g_wide:0:g_width1:sync_level_src|dff_ce_asyncsr:\g_slice_packing:0:i_sync0|LPM_FF:dff" +Sat 21:50: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|basic_synchroniser:inst_ln11_synchroniser|basic_synchroniser_prim:\g_wide:0:g_width1:sync_level_src|dff_ce_asyncsr:\g_slice_packing:0:i_sync0|LPM_FF:dff" with the following parameter: +Sat 21:50: INFO : Info (12134): Parameter "LPM_WIDTH" = "1" +Sat 21:50: INFO : Info (12134): Parameter "LPM_AVALUE" = "UNUSED" +Sat 21:50: INFO : Info (12134): Parameter "LPM_SVALUE" = "UNUSED" +Sat 21:50: INFO : Info (12134): Parameter "LPM_PVALUE" = "UNUSED" +Sat 21:50: INFO : Info (12134): Parameter "LPM_FFTYPE" = "DFF" +Sat 21:50: INFO : Info (12134): Parameter "LPM_TYPE" = "DFF" +Sat 21:50: INFO : Info (12134): Parameter "LPM_HINT" = "UNUSED" +Sat 21:50: INFO : Info (12128): Elaborating entity "SanityBlock_cclk_STREAM_clk_pcie" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SanityBlock_cclk_STREAM_clk_pcie:SanityBlock_i" +Sat 21:50: INFO : Info (12128): Elaborating entity "MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SanityBlock_cclk_STREAM_clk_pcie:SanityBlock_i|MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c:MappedRegBlock_i" +Sat 21:50: INFO : Info (12128): Elaborating entity "mapped_register_readable" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SanityBlock_cclk_STREAM_clk_pcie:SanityBlock_i|MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c:MappedRegBlock_i|mapped_register_readable:inst_ln484_mappedregblock" +Sat 21:50: INFO : Info (12128): Elaborating entity "mapped_register_readable" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SanityBlock_cclk_STREAM_clk_pcie:SanityBlock_i|MappedRegBlock_2bbdde8c924fe59e82043c5c8fb8266c:MappedRegBlock_i|mapped_register_readable:inst_ln484_mappedregblock3" +Sat 21:50: INFO : Warning (10445): VHDL Subtype or Type Declaration warning at mapped_register_readable.vhd(74): subtype or type has null range +Sat 21:50: INFO : Info (12128): Elaborating entity "MappedClockControl_id_3e" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedClockControl_id_3e:inst_ln32_mappedclockcontrol" +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedClockControl_id_3e.vhdl(145): object "inst_ln200_mappedclockcontrol_cc_reg_pll_ce" assigned a value but never read +Sat 21:50: INFO : Info (12128): Elaborating entity "stream_clkprim_lock_count_32" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedClockControl_id_3e:inst_ln32_mappedclockcontrol|stream_clkprim_lock_count_32:inst_ln16_plllockinstrumentation" +Sat 21:50: INFO : Info (12128): Elaborating entity "mapped_clock_control" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedClockControl_id_3e:inst_ln32_mappedclockcontrol|mapped_clock_control:inst_ln200_mappedclockcontrol" +Sat 21:50: INFO : Info (12128): Elaborating entity "reset_control" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|reset_control:inst_ln21_resetcontrol" +Sat 21:50: INFO : Info (12128): Elaborating entity "MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe:MappedElementSwitch_i" +Sat 21:50: INFO : Info (12128): Elaborating entity "mapped_element_switch" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe:MappedElementSwitch_i|mapped_element_switch:MappedElementSwitchExternal_i" +Sat 21:50: INFO : Info (12128): Elaborating entity "mec_switch_arbiter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe:MappedElementSwitch_i|mapped_element_switch:MappedElementSwitchExternal_i|mec_switch_arbiter:request_source_arbiter" +Sat 21:50: INFO : Info (12128): Elaborating entity "src_to_dst_control" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedElementSwitch_MappedRegisters_MappedMemories_SignalForwarding_PCIe:MappedElementSwitch_i|mapped_element_switch:MappedElementSwitchExternal_i|src_to_dst_control:request_source_control" +Sat 21:50: INFO : Info (12128): Elaborating entity "MappedRegistersController_48" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedRegistersController_48:MappedRegistersController_i" +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedRegistersController_48.vhdl(168): object "mappedregistersea_i_reserved_0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedRegistersController_48.vhdl(170): object "mappedregistersea_i_is_response_header" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedRegistersController_48.vhdl(172): object "mappedregistersea_i_reserved_1" assigned a value but never read +Sat 21:50: INFO : Info (12128): Elaborating entity "MappedRegistersEA" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedRegistersController_48:MappedRegistersController_i|MappedRegistersEA:MappedRegistersEA_i" +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedRegistersEA.vhdl(148): object "commonpacketparser_i_ea_manual_rdy" assigned a value but never read +Sat 21:50: INFO : Info (12128): Elaborating entity "CommonPacketParser_MappedRegisters" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedRegistersController_48:MappedRegistersController_i|MappedRegistersEA:MappedRegistersEA_i|CommonPacketParser_MappedRegisters:CommonPacketParser_i" +Sat 21:50: INFO : Info (12128): Elaborating entity "common_packet_parser" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedRegistersController_48:MappedRegistersController_i|MappedRegistersEA:MappedRegistersEA_i|CommonPacketParser_MappedRegisters:CommonPacketParser_i|common_packet_parser:CommonPacketParserExternal_MappedRegisters" +Sat 21:50: INFO : Info (12128): Elaborating entity "ControlMux" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedRegistersController_48:MappedRegistersController_i|MappedRegistersEA:MappedRegistersEA_i|CommonPacketParser_MappedRegisters:CommonPacketParser_i|ControlMux:control_mux" +Sat 21:50: INFO : Info (12128): Elaborating entity "mapped_registers_controller" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedRegistersController_48:MappedRegistersController_i|mapped_registers_controller:MappedRegistersControllerExternal_i" +Sat 21:50: INFO : Info (12128): Elaborating entity "MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i" +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1.vhdl(261): object "mappedmemoriesea_i_reserved_0" assigned a value but never read +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1.vhdl(264): object "mappedmemoriesea_i_is_response_header" assigned a value but never read +Sat 21:50: INFO : Info (12128): Elaborating entity "mapped_memories_controller_core" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|mapped_memories_controller_core:MappedMemoriesControllerCoreExternal_i" +Sat 21:50: INFO : Info (12128): Elaborating entity "MappedMemoriesEA" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|MappedMemoriesEA:MappedmemoriesEA_i" +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at MappedMemoriesEA.vhdl(150): object "commonpacketparser_i_ea_manual_rdy" assigned a value but never read +Sat 21:50: INFO : Info (12128): Elaborating entity "CommonPacketParser_MappedMemories" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|MappedMemoriesEA:MappedmemoriesEA_i|CommonPacketParser_MappedMemories:CommonPacketParser_i" +Sat 21:50: INFO : Info (12128): Elaborating entity "mapped_memories_adapter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|mapped_memories_adapter:mapped_memories_domain_adapter_drp" +Sat 21:50: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_71_512_71_dualclock_aclr" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp" +Sat 21:50: INFO : Info (12128): Elaborating entity "dcfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo" +Sat 21:50: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo" +Sat 21:50: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo" with the following parameter: +Sat 21:50: INFO : Info (12134): Parameter "lpm_width" = "71" +Sat 21:50: INFO : Info (12134): Parameter "lpm_widthu" = "9" +Sat 21:50: INFO : Info (12134): Parameter "lpm_numwords" = "512" +Sat 21:50: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:50: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" +Sat 21:50: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:50: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:50: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:50: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:50: INFO : Info (12134): Parameter "delay_rdusedw" = "1" +Sat 21:50: INFO : Info (12134): Parameter "delay_wrusedw" = "1" +Sat 21:50: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" +Sat 21:50: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" +Sat 21:50: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" +Sat 21:50: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" +Sat 21:50: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_cu42.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: dcfifo_cu42 +Sat 21:50: INFO : Info (12128): Elaborating entity "dcfifo_cu42" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_p07.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: a_graycounter_p07 +Sat 21:50: INFO : Info (12128): Elaborating entity "a_graycounter_p07" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|a_graycounter_p07:rdptr_g1p" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_lec.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: a_graycounter_lec +Sat 21:50: INFO : Info (12128): Elaborating entity "a_graycounter_lec" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|a_graycounter_lec:wrptr_g1p" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_88e1.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: altsyncram_88e1 +Sat 21:50: INFO : Info (12128): Elaborating entity "altsyncram_88e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_qld.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: alt_synch_pipe_qld +Sat 21:50: INFO : Info (12128): Elaborating entity "alt_synch_pipe_qld" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|alt_synch_pipe_qld:rs_dgwp" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: dffpipe_pe9 +Sat 21:50: INFO : Info (12128): Elaborating entity "dffpipe_pe9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|alt_synch_pipe_qld:rs_dgwp|dffpipe_pe9:dffpipe12" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: alt_synch_pipe_rld +Sat 21:50: INFO : Info (12128): Elaborating entity "alt_synch_pipe_rld" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|alt_synch_pipe_rld:ws_dgrp" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: dffpipe_qe9 +Sat 21:50: INFO : Info (12128): Elaborating entity "dffpipe_qe9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|alt_synch_pipe_rld:ws_dgrp|dffpipe_qe9:dffpipe15" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_b16.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: cmpr_b16 +Sat 21:50: INFO : Info (12128): Elaborating entity "cmpr_b16" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|cmpr_b16:rdempty_eq_comp" +Sat 21:50: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_36_512_36_dualclock_aclr" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp" +Sat 21:50: INFO : Info (12128): Elaborating entity "dcfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo" +Sat 21:50: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo" +Sat 21:50: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo" with the following parameter: +Sat 21:50: INFO : Info (12134): Parameter "lpm_width" = "36" +Sat 21:50: INFO : Info (12134): Parameter "lpm_widthu" = "9" +Sat 21:50: INFO : Info (12134): Parameter "lpm_numwords" = "512" +Sat 21:50: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:50: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" +Sat 21:50: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:50: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:50: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:50: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:50: INFO : Info (12134): Parameter "delay_rdusedw" = "1" +Sat 21:50: INFO : Info (12134): Parameter "delay_wrusedw" = "1" +Sat 21:50: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" +Sat 21:50: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" +Sat 21:50: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" +Sat 21:50: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" +Sat 21:50: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_eu42.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: dcfifo_eu42 +Sat 21:50: INFO : Info (12128): Elaborating entity "dcfifo_eu42" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_eu42:auto_generated" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_a8e1.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: altsyncram_a8e1 +Sat 21:50: INFO : Info (12128): Elaborating entity "altsyncram_a8e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_eu42:auto_generated|altsyncram_a8e1:fifo_ram" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_sld.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: alt_synch_pipe_sld +Sat 21:50: INFO : Info (12128): Elaborating entity "alt_synch_pipe_sld" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_eu42:auto_generated|alt_synch_pipe_sld:rs_dgwp" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_re9.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: dffpipe_re9 +Sat 21:50: INFO : Info (12128): Elaborating entity "dffpipe_re9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_eu42:auto_generated|alt_synch_pipe_sld:rs_dgwp|dffpipe_re9:dffpipe6" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_tld.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: alt_synch_pipe_tld +Sat 21:50: INFO : Info (12128): Elaborating entity "alt_synch_pipe_tld" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_eu42:auto_generated|alt_synch_pipe_tld:ws_dgrp" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_se9.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: dffpipe_se9 +Sat 21:50: INFO : Info (12128): Elaborating entity "dffpipe_se9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_36_512_36_dualclock_aclr:response_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_eu42:auto_generated|alt_synch_pipe_tld:ws_dgrp|dffpipe_se9:dffpipe9" +Sat 21:50: INFO : Info (12128): Elaborating entity "SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i" +Sat 21:50: INFO : Warning (10036): Verilog HDL or VHDL warning at SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0.vhdl(194): object "signalforwardingea_i_is_response_header" assigned a value but never read +Sat 21:50: INFO : Info (12128): Elaborating entity "SignalForwardingEA" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|SignalForwardingEA:SignalForwardingEA_i" +Sat 21:50: INFO : Info (12128): Elaborating entity "CommonPacketParser_SignalForwarding" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|SignalForwardingEA:SignalForwardingEA_i|CommonPacketParser_SignalForwarding:CommonPacketParser_i" +Sat 21:50: INFO : Info (12128): Elaborating entity "common_packet_parser" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|SignalForwardingEA:SignalForwardingEA_i|CommonPacketParser_SignalForwarding:CommonPacketParser_i|common_packet_parser:CommonPacketParserExternal_SignalForwarding" +Sat 21:50: INFO : Info (12128): Elaborating entity "MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830:inst_ln130_mappedregblock" +Sat 21:50: INFO : Info (12128): Elaborating entity "mapped_register" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830:inst_ln130_mappedregblock|mapped_register:inst_ln504_mappedregblock" +Sat 21:50: INFO : Info (12128): Elaborating entity "signal_forwarding_adapter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|signal_forwarding_adapter:SignalForwardingAdapterExternal_i" +Sat 21:50: INFO : Info (12128): Elaborating entity "MappedDRP_Addr_3c0000_ChecksumMappedDRP" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp" +Sat 21:50: INFO : Info (12128): Elaborating entity "ChecksumMappedDRP_RAM" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i" +Sat 21:50: INFO : Info (12128): Elaborating entity "SRLDelay_1x2_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i|SRLDelay_1x2_reg1:rd_delay" +Sat 21:50: INFO : Info (12128): Elaborating entity "SimpleSR" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i|SRLDelay_1x2_reg1:rd_delay|SimpleSR:inst_ln25_alterasrldelay" +Sat 21:50: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i|altsyncram:checksum_mem" +Sat 21:50: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i|altsyncram:checksum_mem" +Sat 21:50: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i|altsyncram:checksum_mem" with the following parameter: +Sat 21:50: INFO : Info (12134): Parameter "address_aclr_a" = "UNUSED" +Sat 21:50: INFO : Info (12134): Parameter "address_aclr_b" = "NONE" +Sat 21:50: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" +Sat 21:50: INFO : Info (12134): Parameter "byte_size" = "8" +Sat 21:50: INFO : Info (12134): Parameter "byteena_aclr_a" = "UNUSED" +Sat 21:50: INFO : Info (12134): Parameter "byteena_aclr_b" = "NONE" +Sat 21:50: INFO : Info (12134): Parameter "byteena_reg_b" = "CLOCK1" +Sat 21:50: INFO : Info (12134): Parameter "clock_enable_core_a" = "USE_INPUT_CLKEN" +Sat 21:50: INFO : Info (12134): Parameter "clock_enable_core_b" = "USE_INPUT_CLKEN" +Sat 21:50: INFO : Info (12134): Parameter "clock_enable_input_a" = "BYPASS" +Sat 21:50: INFO : Info (12134): Parameter "clock_enable_input_b" = "BYPASS" +Sat 21:50: INFO : Info (12134): Parameter "clock_enable_output_a" = "BYPASS" +Sat 21:50: INFO : Info (12134): Parameter "clock_enable_output_b" = "BYPASS" +Sat 21:50: INFO : Info (12134): Parameter "intended_device_family" = "stratixv" +Sat 21:50: INFO : Info (12134): Parameter "ecc_pipeline_stage_enabled" = "FALSE" +Sat 21:50: INFO : Info (12134): Parameter "enable_ecc" = "FALSE" +Sat 21:50: INFO : Info (12134): Parameter "implement_in_les" = "OFF" +Sat 21:50: INFO : Info (12134): Parameter "indata_aclr_a" = "UNUSED" +Sat 21:50: INFO : Info (12134): Parameter "indata_aclr_b" = "NONE" +Sat 21:50: INFO : Info (12134): Parameter "indata_reg_b" = "CLOCK0" +Sat 21:50: INFO : Info (12134): Parameter "init_file" = "32x512_ROM_SINGLE_PORT_ireg_checksum.mif" +Sat 21:50: INFO : Info (12134): Parameter "init_file_layout" = "PORT_A" +Sat 21:50: INFO : Info (12134): Parameter "maximum_depth" = "0" +Sat 21:50: INFO : Info (12134): Parameter "numwords_a" = "512" +Sat 21:50: INFO : Info (12134): Parameter "numwords_b" = "0" +Sat 21:50: INFO : Info (12134): Parameter "operation_mode" = "ROM" +Sat 21:50: INFO : Info (12134): Parameter "outdata_aclr_a" = "NONE" +Sat 21:50: INFO : Info (12134): Parameter "outdata_aclr_b" = "NONE" +Sat 21:50: INFO : Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" +Sat 21:50: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" +Sat 21:50: INFO : Info (12134): Parameter "power_up_uninitialized" = "FALSE" +Sat 21:50: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" +Sat 21:50: INFO : Info (12134): Parameter "rdcontrol_aclr_b" = "NONE" +Sat 21:50: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK1" +Sat 21:50: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" +Sat 21:50: INFO : Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" +Sat 21:50: INFO : Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" +Sat 21:50: INFO : Info (12134): Parameter "stratixiv_m144k_allow_dual_clocks" = "ON" +Sat 21:50: INFO : Info (12134): Parameter "width_a" = "32" +Sat 21:50: INFO : Info (12134): Parameter "width_b" = "1" +Sat 21:50: INFO : Info (12134): Parameter "width_byteena_a" = "1" +Sat 21:50: INFO : Info (12134): Parameter "width_byteena_b" = "1" +Sat 21:50: INFO : Info (12134): Parameter "width_eccstatus" = "3" +Sat 21:50: INFO : Info (12134): Parameter "widthad_a" = "9" +Sat 21:50: INFO : Info (12134): Parameter "widthad_b" = "1" +Sat 21:50: INFO : Info (12134): Parameter "wrcontrol_aclr_a" = "UNUSED" +Sat 21:50: INFO : Info (12134): Parameter "wrcontrol_aclr_b" = "NONE" +Sat 21:50: INFO : Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" +Sat 21:50: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" +Sat 21:50: INFO : Info (12134): Parameter "lpm_type" = "altsyncram" +Sat 21:50: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_8754.tdf +Sat 21:50: INFO : Info (12023): Found entity 1: altsyncram_8754 +Sat 21:50: INFO : Info (12128): Elaborating entity "altsyncram_8754" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedDRP_Addr_3c0000_ChecksumMappedDRP:checksum_mem_drp|ChecksumMappedDRP_RAM:mappeddrp_addr_3c0000_checksummappeddrp_i|altsyncram:checksum_mem|altsyncram_8754:auto_generated" +Sat 21:50: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity" +Sat 21:51: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel" +Sat 21:51: INFO : Info (12128): Elaborating entity "FetchSubTupleKernel_streamwrapper" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock" +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_streamwrapper.vhdl(264): object "fetchsubtuplekernel_core_output_output_control" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_streamwrapper.vhdl(276): object "control_sm_pcc_finished" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_streamwrapper.vhdl(288): object "control_sm_next_flush_level" assigned a value but never read +Sat 21:51: INFO : Info (12128): Elaborating entity "FetchSubTupleKernel" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core" +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel.vhdl(438): object "node_id2_nodecounterv1_wrap" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel.vhdl(5195): object "node_id4669_nodecounterv1_wrap" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel.vhdl(5202): object "node_id4675_nodecounterv1_wrap" assigned a value but never read +Sat 21:51: INFO : Info (12128): Elaborating entity "PhotonBitwiseNot_1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonBitwiseNot_1:node_id4537_nodenot" +Sat 21:51: INFO : Info (12128): Elaborating entity "StateMachineEntity_FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|StateMachineEntity_FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33:node_id2_nodecounterv1" +Sat 21:51: INFO : Info (12128): Elaborating entity "FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|StateMachineEntity_FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33:node_id2_nodecounterv1|FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33:inst_ln165_statemachineentitycore" +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33.vhdl(258): object "dummy_sensitivity_signal_output_function" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_Counter_32_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_33.vhdl(259): object "dummy_sensitivity_signal_nextstate_function" assigned a value but never read +Sat 21:51: INFO : Info (12128): Elaborating entity "dff_ce_syncsr" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|dff_ce_syncsr:node_id2_nodecounterv1_ce_pipereg_inst_0" +Sat 21:51: INFO : Info (12128): Elaborating entity "LPM_FF" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|dff_ce_syncsr:node_id2_nodecounterv1_ce_pipereg_inst_0|LPM_FF:dff" +Sat 21:51: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|dff_ce_syncsr:node_id2_nodecounterv1_ce_pipereg_inst_0|LPM_FF:dff" +Sat 21:51: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|dff_ce_syncsr:node_id2_nodecounterv1_ce_pipereg_inst_0|LPM_FF:dff" with the following parameter: +Sat 21:51: INFO : Info (12134): Parameter "LPM_WIDTH" = "1" +Sat 21:51: INFO : Info (12134): Parameter "LPM_AVALUE" = "UNUSED" +Sat 21:51: INFO : Info (12134): Parameter "LPM_SVALUE" = "UNUSED" +Sat 21:51: INFO : Info (12134): Parameter "LPM_PVALUE" = "UNUSED" +Sat 21:51: INFO : Info (12134): Parameter "LPM_FFTYPE" = "DFF" +Sat 21:51: INFO : Info (12134): Parameter "LPM_TYPE" = "LPM_FF" +Sat 21:51: INFO : Info (12134): Parameter "LPM_HINT" = "UNUSED" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCFixed_LT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_LT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1:node_id4_nodelt" +Sat 21:51: INFO : Info (12128): Elaborating entity "MultiStageDelay_1x1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x1:node_id4679_nodefifo" +Sat 21:51: INFO : Info (12128): Elaborating entity "SRLDelay_1x1_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x1:node_id4679_nodefifo|SRLDelay_1x1_reg1:SRLDelay" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCFixed_GT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_GT_32_0_UNSIGNED_32_0_UNSIGNED_growbits_pipe1:node_id16_nodegt" +Sat 21:51: INFO : Info (12128): Elaborating entity "PhotonBitwiseOp_1_Orpipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonBitwiseOp_1_Orpipe:node_id17_nodeor" +Sat 21:51: INFO : Info (12128): Elaborating entity "PhotonBitwiseOp_1_Andpipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonBitwiseOp_1_Andpipe:node_id18_nodeand" +Sat 21:51: INFO : Info (12128): Elaborating entity "MultiStageDelay_1x5" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x5:node_id4680_nodefifo" +Sat 21:51: INFO : Info (12128): Elaborating entity "SRLDelay_1x5_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x5:node_id4680_nodefifo|SRLDelay_1x5_reg1:SRLDelay" +Sat 21:51: INFO : Info (12128): Elaborating entity "SimpleSR" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x5:node_id4680_nodefifo|SRLDelay_1x5_reg1:SRLDelay|SimpleSR:inst_ln25_alterasrldelay" +Sat 21:51: INFO : Info (12128): Elaborating entity "PhotonBitwiseOp_1_Andnopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonBitwiseOp_1_Andnopipe:node_id159_nodeand" +Sat 21:51: INFO : Info (12128): Elaborating entity "SRLDelay_1x4_reg2" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|SRLDelay_1x4_reg2:inst_ln49_alterasrldelay" +Sat 21:51: INFO : Info (12128): Elaborating entity "SimpleSR" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|SRLDelay_1x4_reg2:inst_ln49_alterasrldelay|SimpleSR:inst_ln25_alterasrldelay" +Sat 21:51: INFO : Info (12128): Elaborating entity "InputRegisterEntity2013_32" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|InputRegisterEntity2013_32:node_id160_nodeinput_sizessizes_data0_reg" +Sat 21:51: INFO : Info (12128): Elaborating entity "PhotonMUX_1_2_32_pipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonMUX_1_2_32_pipe:node_id162_nodemux" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCFixedCast_32_0_UNSIGNED_6_0_UNSIGNED_TONEAR_pipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixedCast_32_0_UNSIGNED_6_0_UNSIGNED_TONEAR_pipe:node_id163_nodecast" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCFixed_LT_6_0_UNSIGNED_6_0_UNSIGNED_growbits_pipe1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_LT_6_0_UNSIGNED_6_0_UNSIGNED_growbits_pipe1:node_id303_nodelt" +Sat 21:51: INFO : Info (12128): Elaborating entity "Pulse_cycles1_initT" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|Pulse_cycles1_initT:node_id165_nodepulse" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCFixedCast_6_0_UNSIGNED_7_0_UNSIGNED_TONEAR_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixedCast_6_0_UNSIGNED_7_0_UNSIGNED_TONEAR_nopipe:node_id169_nodecast" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCFixed_ADD_7_0_UNSIGNED_7_0_UNSIGNED_nogrowbits_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_ADD_7_0_UNSIGNED_7_0_UNSIGNED_nogrowbits_nopipe:node_id171_nodeadd" +Sat 21:51: INFO : Info (12128): Elaborating entity "PhotonMUX_1_2_6_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonMUX_1_2_6_nopipe:node_id168_nodemux" +Sat 21:51: INFO : Info (12128): Elaborating entity "MultiStageDelay_6x1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_6x1:node_id4681_nodefifo" +Sat 21:51: INFO : Info (12128): Elaborating entity "SRLDelay_6x1_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_6x1:node_id4681_nodefifo|SRLDelay_6x1_reg1:SRLDelay" +Sat 21:51: INFO : Info (12128): Elaborating entity "WordLevelShifter_Left_Circular_1_64_6" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_64_6:node_id304_nodewordlevelshift" +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at WordLevelShifter_Left_Circular_1_64_6.vhdl(110): object "inst_ln23_maxdcsinglelutconstdiv3_quotient" assigned a value but never read +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCSingleLUTConstDiv_n6_d3_quotient_remainder_lat0" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_64_6:node_id304_nodewordlevelshift|MaxDCSingleLUTConstDiv_n6_d3_quotient_remainder_lat0:inst_ln23_maxdcsinglelutconstdiv" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCSingleLUTConstDiv_n5_d3_quotient_remainder_lat0" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_64_6:node_id304_nodewordlevelshift|MaxDCSingleLUTConstDiv_n5_d3_quotient_remainder_lat0:inst_ln23_maxdcsinglelutconstdiv1" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCSingleLUTConstDiv_n4_d3_quotient_remainder_lat0" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_64_6:node_id304_nodewordlevelshift|MaxDCSingleLUTConstDiv_n4_d3_quotient_remainder_lat0:inst_ln23_maxdcsinglelutconstdiv2" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCSingleLUTConstDiv_n3_d3_quotient_remainder_lat0" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_64_6:node_id304_nodewordlevelshift|MaxDCSingleLUTConstDiv_n3_d3_quotient_remainder_lat0:inst_ln23_maxdcsinglelutconstdiv3" +Sat 21:51: INFO : Info (12128): Elaborating entity "MultiStageDelay_1x4" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x4:node_id4683_nodefifo" +Sat 21:51: INFO : Info (12128): Elaborating entity "SRLDelay_1x4_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x4:node_id4683_nodefifo|SRLDelay_1x4_reg1:SRLDelay" +Sat 21:51: INFO : Info (12128): Elaborating entity "MultiStageDelay_2x1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_2x1:node_id4684_nodefifo" +Sat 21:51: INFO : Info (12128): Elaborating entity "SRLDelay_2x1_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_2x1:node_id4684_nodefifo|SRLDelay_2x1_reg1:SRLDelay" +Sat 21:51: INFO : Info (12128): Elaborating entity "PhotonMUX_1_2_2_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonMUX_1_2_2_nopipe:node_id571_nodemux" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCFixed_SUB_2_0_UNSIGNED_2_0_UNSIGNED_nogrowbits_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_SUB_2_0_UNSIGNED_2_0_UNSIGNED_nogrowbits_nopipe:node_id576_nodesub" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCFixed_ADD_2_0_UNSIGNED_2_0_UNSIGNED_nogrowbits_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_ADD_2_0_UNSIGNED_2_0_UNSIGNED_nogrowbits_nopipe:node_id573_nodeadd" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCFixed_LT_2_0_UNSIGNED_2_0_UNSIGNED_growbits_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_LT_2_0_UNSIGNED_2_0_UNSIGNED_growbits_nopipe:node_id566_nodelt" +Sat 21:51: INFO : Info (12128): Elaborating entity "PhotonMUX_1_2_1_pipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonMUX_1_2_1_pipe:node_id23_nodemux" +Sat 21:51: INFO : Info (12128): Elaborating entity "MultiStageDelay_1x10" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x10:node_id4686_nodefifo" +Sat 21:51: INFO : Info (12128): Elaborating entity "SRLDelay_1x10_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x10:node_id4686_nodefifo|SRLDelay_1x10_reg1:SRLDelay" +Sat 21:51: INFO : Info (12128): Elaborating entity "SimpleSR" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_1x10:node_id4686_nodefifo|SRLDelay_1x10_reg1:SRLDelay|SimpleSR:inst_ln25_alterasrldelay" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCFixed_EQ_2_0_UNSIGNED_2_0_UNSIGNED_growbits_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_EQ_2_0_UNSIGNED_2_0_UNSIGNED_growbits_nopipe:node_id4491_nodeeq" +Sat 21:51: INFO : Info (12128): Elaborating entity "InputRegisterEntity2013_4096" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|InputRegisterEntity2013_4096:node_id28_nodeinput_inputinput_data0_reg" +Sat 21:51: INFO : Info (12128): Elaborating entity "PhotonMUX_1_2_64_nopipe" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|PhotonMUX_1_2_64_nopipe:node_id4501_nodemux" +Sat 21:51: INFO : Info (12128): Elaborating entity "MultiStageDelay_64x1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_64x1:node_id4701_nodefifo" +Sat 21:51: INFO : Info (12128): Elaborating entity "SRLDelay_64x1_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_64x1:node_id4701_nodefifo|SRLDelay_64x1_reg1:SRLDelay" +Sat 21:51: INFO : Info (12128): Elaborating entity "MultiStageDelay_2x4" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_2x4:node_id5904_nodefifo" +Sat 21:51: INFO : Info (12128): Elaborating entity "SRLDelay_2x4_reg1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_2x4:node_id5904_nodefifo|SRLDelay_2x4_reg1:SRLDelay" +Sat 21:51: INFO : Info (12128): Elaborating entity "SimpleSR" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MultiStageDelay_2x4:node_id5904_nodefifo|SRLDelay_2x4_reg1:SRLDelay|SimpleSR:inst_ln25_alterasrldelay" +Sat 21:51: INFO : Info (12128): Elaborating entity "StateMachineEntity_FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|StateMachineEntity_FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49:node_id4669_nodecounterv1" +Sat 21:51: INFO : Info (12128): Elaborating entity "FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|StateMachineEntity_FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49:node_id4669_nodecounterv1|FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49:inst_ln165_statemachineentitycore" +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49.vhdl(258): object "dummy_sensitivity_signal_output_function" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at FetchSubTupleKernel_Counter_48_NUMERIC_INCREMENTING_1_0_0_false_COUNT_LT_MAX_THEN_WRAP_49.vhdl(259): object "dummy_sensitivity_signal_nextstate_function" assigned a value but never read +Sat 21:51: INFO : Info (12128): Elaborating entity "OutputRegisterEntity_48with_reset" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|OutputRegisterEntity_48with_reset:node_id4672current_run_cycle_count_reg" +Sat 21:51: INFO : Info (12128): Elaborating entity "MaxDCFixed_EQ_48_0_UNSIGNED_48_0_UNSIGNED_growbits_pipe1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|MaxDCFixed_EQ_48_0_UNSIGNED_48_0_UNSIGNED_growbits_pipe1:node_id4678_nodeeq" +Sat 21:51: INFO : Info (12128): Elaborating entity "MappedRegBlock_b5497fa47497f5c6632937a587d5df01" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|MappedRegBlock_b5497fa47497f5c6632937a587d5df01:mapped_reg_block" +Sat 21:51: INFO : Info (12128): Elaborating entity "mapped_register" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|MappedRegBlock_b5497fa47497f5c6632937a587d5df01:mapped_reg_block|mapped_register:inst_ln504_mappedregblock" +Sat 21:51: INFO : Warning (10445): VHDL Subtype or Type Declaration warning at mapped_register.vhd(56): subtype or type has null range +Sat 21:51: INFO : Info (12128): Elaborating entity "mapped_register" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|MappedRegBlock_b5497fa47497f5c6632937a587d5df01:mapped_reg_block|mapped_register:inst_ln504_mappedregblock3" +Sat 21:51: INFO : Info (12128): Elaborating entity "mapped_register_readable" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|MappedRegBlock_b5497fa47497f5c6632937a587d5df01:mapped_reg_block|mapped_register_readable:inst_ln484_mappedregblock1" +Sat 21:51: INFO : Info (12128): Elaborating entity "dff_ce_syncsr_ne" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|dff_ce_syncsr_ne:inst_ln44_alteraflipflops" +Sat 21:51: INFO : Info (12128): Elaborating entity "PhotonDesignControl" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|PhotonDesignControl:control_sm" +Sat 21:51: INFO : Info (12128): Elaborating entity "FillLevelCounter_0" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FillLevelCounter_0:ce_fill_0_0_pdc0" +Sat 21:51: INFO : Info (12128): Elaborating entity "FlushLevelCounter_1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FlushLevelCounter_1:ce_flush_0_1_pdc0" +Sat 21:51: INFO : Info (12128): Elaborating entity "level_synchroniser" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|level_synchroniser:inst_ln11_synchroniser" +Sat 21:51: INFO : Info (12128): Elaborating entity "level_synchroniser_prim" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|level_synchroniser:inst_ln11_synchroniser|level_synchroniser_prim:\g_wide:0:g_width1:sync_level_src" +Sat 21:51: INFO : Warning (10542): VHDL Variable Declaration warning at level_synchroniser.vhd(71): used initial value expression for variable "n" because variable was never assigned a value +Sat 21:51: INFO : Info (12128): Elaborating entity "WrapperNodeIO_input" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|WrapperNodeIO_input:input" +Sat 21:51: INFO : Info (12128): Elaborating entity "WrapperNodeIO_sizes" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|WrapperNodeIO_sizes:sizes" +Sat 21:51: INFO : Info (12128): Elaborating entity "WrapperNodeIO_output" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|WrapperNodeIO_output:output" +Sat 21:51: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_1:Stream_1" +Sat 21:51: INFO : Info (12128): Elaborating entity "DualAspectReg_128_4096" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_1:Stream_1|DualAspectReg_128_4096:inst_ln31_streamingblock" +Sat 21:51: INFO : Info (12128): Elaborating entity "dualaspectreg_int" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_1:Stream_1|DualAspectReg_128_4096:inst_ln31_streamingblock|dualaspectreg_int:inst_ln126_dualaspectreg" +Sat 21:51: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_4" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_4:Stream_4" +Sat 21:51: INFO : Info (12128): Elaborating entity "DualAspectMux_128_32_COUNTER_PIPELINED" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_4:Stream_4|DualAspectMux_128_32_COUNTER_PIPELINED:inst_ln31_streamingblock" +Sat 21:51: INFO : Info (12128): Elaborating entity "DualAspectCounterPipelined_32_128" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_4:Stream_4|DualAspectMux_128_32_COUNTER_PIPELINED:inst_ln31_streamingblock|DualAspectCounterPipelined_32_128:inst_ln31_dualaspectcounterpipelined" +Sat 21:51: INFO : Info (12128): Elaborating entity "dualaspectmuxpipe_counter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_4:Stream_4|DualAspectMux_128_32_COUNTER_PIPELINED:inst_ln31_streamingblock|DualAspectCounterPipelined_32_128:inst_ln31_dualaspectcounterpipelined|dualaspectmuxpipe_counter:inst_ln228_dualaspectcounterpipelined" +Sat 21:51: INFO : Info (12128): Elaborating entity "dualaspectmuxpipe_mux4" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_4:Stream_4|DualAspectMux_128_32_COUNTER_PIPELINED:inst_ln31_streamingblock|DualAspectCounterPipelined_32_128:inst_ln31_dualaspectcounterpipelined|dualaspectmuxpipe_mux4:inst_ln196_dualaspectcounterpipelined" +Sat 21:51: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_8" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_8:Stream_8" +Sat 21:51: INFO : Info (12128): Elaborating entity "DualAspectMux_4096_128_COUNTER_PIPELINED_LIMITED" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_8:Stream_8|DualAspectMux_4096_128_COUNTER_PIPELINED_LIMITED:inst_ln31_streamingblock" +Sat 21:51: INFO : Info (12128): Elaborating entity "DualAspectCounterPipelined_128_4096" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_8:Stream_8|DualAspectMux_4096_128_COUNTER_PIPELINED_LIMITED:inst_ln31_streamingblock|DualAspectCounterPipelined_128_4096:inst_ln31_dualaspectcounterpipelined" +Sat 21:51: INFO : Info (12128): Elaborating entity "dualaspectmuxpipe_counter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_8:Stream_8|DualAspectMux_4096_128_COUNTER_PIPELINED_LIMITED:inst_ln31_streamingblock|DualAspectCounterPipelined_128_4096:inst_ln31_dualaspectcounterpipelined|dualaspectmuxpipe_counter:inst_ln228_dualaspectcounterpipelined" +Sat 21:51: INFO : Info (12128): Elaborating entity "dualaspectmuxpipe_mux4" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_8:Stream_8|DualAspectMux_4096_128_COUNTER_PIPELINED_LIMITED:inst_ln31_streamingblock|DualAspectCounterPipelined_128_4096:inst_ln31_dualaspectcounterpipelined|dualaspectmuxpipe_mux4:inst_ln196_dualaspectcounterpipelined" +Sat 21:51: INFO : Info (12128): Elaborating entity "dualaspectmuxpipe_mux2" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_8:Stream_8|DualAspectMux_4096_128_COUNTER_PIPELINED_LIMITED:inst_ln31_streamingblock|DualAspectCounterPipelined_128_4096:inst_ln31_dualaspectcounterpipelined|dualaspectmuxpipe_mux2:inst_ln196_dualaspectcounterpipelined10" +Sat 21:51: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_11" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11" +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_11.vhdl(108): object "inst_ln31_streamingblock_underflow" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_11.vhdl(109): object "inst_ln31_streamingblock_overflow" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_11.vhdl(110): object "inst_ln31_streamingblock_dbg_empty" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_11.vhdl(111): object "inst_ln31_streamingblock_dbg_stall" assigned a value but never read +Sat 21:51: INFO : Info (12128): Elaborating entity "StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock" +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs.vhdl(107): object "inst_ln47_alterafifo_full" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs.vhdl(111): object "inst_ln47_alterafifo_wr_data_count" assigned a value but never read +Sat 21:51: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo" +Sat 21:51: INFO : Info (12128): Elaborating entity "dcfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo" +Sat 21:51: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo" +Sat 21:51: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo" with the following parameter: +Sat 21:51: INFO : Info (12134): Parameter "lpm_width" = "128" +Sat 21:51: INFO : Info (12134): Parameter "lpm_widthu" = "9" +Sat 21:51: INFO : Info (12134): Parameter "lpm_numwords" = "512" +Sat 21:51: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:51: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" +Sat 21:51: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:51: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:51: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:51: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:51: INFO : Info (12134): Parameter "delay_rdusedw" = "1" +Sat 21:51: INFO : Info (12134): Parameter "delay_wrusedw" = "1" +Sat 21:51: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" +Sat 21:51: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" +Sat 21:51: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" +Sat 21:51: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" +Sat 21:51: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_3r52.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: dcfifo_3r52 +Sat 21:51: INFO : Info (12128): Elaborating entity "dcfifo_3r52" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_qbb.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: a_gray2bin_qbb +Sat 21:51: INFO : Info (12128): Elaborating entity "a_gray2bin_qbb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|a_gray2bin_qbb:wrptr_g_gray2bin" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ebe1.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: altsyncram_ebe1 +Sat 21:51: INFO : Info (12128): Elaborating entity "altsyncram_ebe1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|altsyncram_ebe1:fifo_ram" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_uld.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: alt_synch_pipe_uld +Sat 21:51: INFO : Info (12128): Elaborating entity "alt_synch_pipe_uld" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|alt_synch_pipe_uld:rs_dgwp" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_te9.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: dffpipe_te9 +Sat 21:51: INFO : Info (12128): Elaborating entity "dffpipe_te9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|alt_synch_pipe_uld:rs_dgwp|dffpipe_te9:dffpipe6" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: dffpipe_oe9 +Sat 21:51: INFO : Info (12128): Elaborating entity "dffpipe_oe9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|dffpipe_oe9:ws_brp" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_vld.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: alt_synch_pipe_vld +Sat 21:51: INFO : Info (12128): Elaborating entity "alt_synch_pipe_vld" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|alt_synch_pipe_vld:ws_dgrp" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_ue9.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: dffpipe_ue9 +Sat 21:51: INFO : Info (12128): Elaborating entity "dffpipe_ue9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_11:Stream_11|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_dualclock_aclr_wrusedw_of_uf_pfv477:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_3r52:auto_generated|alt_synch_pipe_vld:ws_dgrp|dffpipe_ue9:dffpipe10" +Sat 21:51: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_15" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15" +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_15.vhdl(107): object "inst_ln31_streamingblock_underflow" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_15.vhdl(108): object "inst_ln31_streamingblock_overflow" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_15.vhdl(109): object "inst_ln31_streamingblock_dbg_empty" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_15.vhdl(110): object "inst_ln31_streamingblock_dbg_stall" assigned a value but never read +Sat 21:51: INFO : Info (12128): Elaborating entity "StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock" +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs.vhdl(104): object "inst_ln47_alterafifo_full" assigned a value but never read +Sat 21:51: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_128_512_128_aclr_afv477_of_uf" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo" +Sat 21:51: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" +Sat 21:51: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" +Sat 21:51: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" with the following parameter: +Sat 21:51: INFO : Info (12134): Parameter "lpm_width" = "128" +Sat 21:51: INFO : Info (12134): Parameter "lpm_widthu" = "9" +Sat 21:51: INFO : Info (12134): Parameter "lpm_numwords" = "512" +Sat 21:51: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:51: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" +Sat 21:51: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:51: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:51: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:51: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:51: INFO : Info (12134): Parameter "almost_full_value" = "477" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_9ee1.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: scfifo_9ee1 +Sat 21:51: INFO : Info (12128): Elaborating entity "scfifo_9ee1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_pvb1.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: a_dpfifo_pvb1 +Sat 21:51: INFO : Info (12128): Elaborating entity "a_dpfifo_pvb1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_s7f.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: a_fefifo_s7f +Sat 21:51: INFO : Info (12128): Elaborating entity "a_fefifo_s7f" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|a_fefifo_s7f:fifo_state" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_4i7.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: cntr_4i7 +Sat 21:51: INFO : Info (12128): Elaborating entity "cntr_4i7" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|a_fefifo_s7f:fifo_state|cntr_4i7:count_usedw" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_4ob1.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: dpram_4ob1 +Sat 21:51: INFO : Info (12128): Elaborating entity "dpram_4ob1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_muu1.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: altsyncram_muu1 +Sat 21:51: INFO : Info (12128): Elaborating entity "altsyncram_muu1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1" +Sat 21:51: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_ohb.tdf +Sat 21:51: INFO : Info (12023): Found entity 1: cntr_ohb +Sat 21:51: INFO : Info (12128): Elaborating entity "cntr_ohb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|cntr_ohb:rd_ptr_count" +Sat 21:51: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_13" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13" +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_13.vhdl(109): object "inst_ln31_streamingblock_underflow" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_13.vhdl(110): object "inst_ln31_streamingblock_overflow" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_13.vhdl(111): object "inst_ln31_streamingblock_dbg_empty" assigned a value but never read +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_13.vhdl(112): object "inst_ln31_streamingblock_dbg_stall" assigned a value but never read +Sat 21:51: INFO : Info (12128): Elaborating entity "StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock" +Sat 21:51: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs.vhdl(106): object "inst_ln47_alterafifo_full" assigned a value but never read +Sat 21:51: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_4096_512_4096_aclr_afv510_aev8_of_uf" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_4096_512_4096_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo" +Sat 21:51: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_4096_512_4096_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" +Sat 21:51: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_4096_512_4096_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_4096_512_4096_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "lpm_width" = "4096" +Sat 21:52: INFO : Info (12134): Parameter "lpm_widthu" = "9" +Sat 21:52: INFO : Info (12134): Parameter "lpm_numwords" = "512" +Sat 21:52: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" +Sat 21:52: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:52: INFO : Info (12134): Parameter "almost_full_value" = "510" +Sat 21:52: INFO : Info (12134): Parameter "almost_empty_value" = "8" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_2rh1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: scfifo_2rh1 +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo_2rh1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_4096_512_4096_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_2rh1:auto_generated" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_h1c1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: a_dpfifo_h1c1 +Sat 21:52: INFO : Info (12128): Elaborating entity "a_dpfifo_h1c1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_4096_512_4096_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_2rh1:auto_generated|a_dpfifo_h1c1:dpfifo" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_spb1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dpram_spb1 +Sat 21:52: INFO : Info (12128): Elaborating entity "dpram_spb1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_4096_512_4096_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_2rh1:auto_generated|a_dpfifo_h1c1:dpfifo|dpram_spb1:FIFOram" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_85v1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_85v1 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_85v1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_13:Stream_13|StreamFifo_altera_4096_4096_512_pullin_pullout_el1_ael2_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_4096_512_4096_aclr_afv510_aev8_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_2rh1:auto_generated|a_dpfifo_h1c1:dpfifo|dpram_spb1:FIFOram|altsyncram_85v1:altsyncram1" +Sat 21:52: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_17" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_17.vhdl(110): object "inst_ln31_streamingblock_underflow" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_17.vhdl(111): object "inst_ln31_streamingblock_overflow" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_17.vhdl(112): object "inst_ln31_streamingblock_dbg_empty" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_17.vhdl(113): object "inst_ln31_streamingblock_dbg_stall" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs.vhdl(109): object "inst_ln47_alterafifo_full" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs.vhdl(113): object "inst_ln47_alterafifo_wr_data_count" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo" +Sat 21:52: INFO : Info (12128): Elaborating entity "dcfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "lpm_width" = "32" +Sat 21:52: INFO : Info (12134): Parameter "lpm_widthu" = "9" +Sat 21:52: INFO : Info (12134): Parameter "lpm_numwords" = "512" +Sat 21:52: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" +Sat 21:52: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:52: INFO : Info (12134): Parameter "delay_rdusedw" = "1" +Sat 21:52: INFO : Info (12134): Parameter "delay_wrusedw" = "1" +Sat 21:52: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" +Sat 21:52: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" +Sat 21:52: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_lg62.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dcfifo_lg62 +Sat 21:52: INFO : Info (12128): Elaborating entity "dcfifo_lg62" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_28e1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_28e1 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_28e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_0md.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: alt_synch_pipe_0md +Sat 21:52: INFO : Info (12128): Elaborating entity "alt_synch_pipe_0md" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|alt_synch_pipe_0md:rs_dgwp" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_ve9.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dffpipe_ve9 +Sat 21:52: INFO : Info (12128): Elaborating entity "dffpipe_ve9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|alt_synch_pipe_0md:rs_dgwp|dffpipe_ve9:dffpipe6" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_1md.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: alt_synch_pipe_1md +Sat 21:52: INFO : Info (12128): Elaborating entity "alt_synch_pipe_1md" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|alt_synch_pipe_1md:ws_dgrp" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_0f9.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dffpipe_0f9 +Sat 21:52: INFO : Info (12128): Elaborating entity "dffpipe_0f9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|alt_synch_pipe_1md:ws_dgrp|dffpipe_0f9:dffpipe9" +Sat 21:52: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_19" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_19.vhdl(107): object "inst_ln31_streamingblock_underflow" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_19.vhdl(108): object "inst_ln31_streamingblock_overflow" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_19.vhdl(109): object "inst_ln31_streamingblock_dbg_empty" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_19.vhdl(110): object "inst_ln31_streamingblock_dbg_stall" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "StreamFifo_altera_4096_4096_512_pushin_sl5_pullout_el1_singleclock_errflgs" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19|StreamFifo_altera_4096_4096_512_pushin_sl5_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_4096_4096_512_pushin_sl5_pullout_el1_singleclock_errflgs.vhdl(104): object "inst_ln47_alterafifo_full" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_4096_512_4096_aclr_afv474_of_uf" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19|StreamFifo_altera_4096_4096_512_pushin_sl5_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_4096_512_4096_aclr_afv474_of_uf:inst_ln47_alterafifo" +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19|StreamFifo_altera_4096_4096_512_pushin_sl5_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_4096_512_4096_aclr_afv474_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19|StreamFifo_altera_4096_4096_512_pushin_sl5_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_4096_512_4096_aclr_afv474_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19|StreamFifo_altera_4096_4096_512_pushin_sl5_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_4096_512_4096_aclr_afv474_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "lpm_width" = "4096" +Sat 21:52: INFO : Info (12134): Parameter "lpm_widthu" = "9" +Sat 21:52: INFO : Info (12134): Parameter "lpm_numwords" = "512" +Sat 21:52: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" +Sat 21:52: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:52: INFO : Info (12134): Parameter "almost_full_value" = "474" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_ufe1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: scfifo_ufe1 +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo_ufe1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_19:Stream_19|StreamFifo_altera_4096_4096_512_pushin_sl5_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_4096_512_4096_aclr_afv474_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_ufe1:auto_generated" +Sat 21:52: INFO : Info (12128): Elaborating entity "Manager_FetchSubTuple_WrapperNodeEntity_Stream_21" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_21:Stream_21" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_21.vhdl(108): object "inst_ln31_streamingblock_underflow" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_21.vhdl(109): object "inst_ln31_streamingblock_overflow" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_21.vhdl(110): object "inst_ln31_streamingblock_dbg_empty" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at Manager_FetchSubTuple_WrapperNodeEntity_Stream_21.vhdl(111): object "inst_ln31_streamingblock_dbg_stall" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "PCIeStreaming_2_3" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(470): object "requestencoder_i_read_done" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(471): object "requestencoder_i_dma_read_req" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(472): object "requestencoder_i_dma_read_addr" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(473): object "requestencoder_i_dma_read_len" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(474): object "requestencoder_i_dma_read_be" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(475): object "requestencoder_i_dma_read_tag" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(476): object "requestencoder_i_dma_read_wide_addr" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(485): object "requestencoder_i_interrupt_ctl_valid" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(486): object "requestencoder_i_interrupt_ctl_enable_id" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(534): object "slavestreamingbarparser_i_sth1_bufinfo_ring_info_valid" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(535): object "slavestreamingbarparser_i_sth1_bufinfo_ring_info_addr" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(536): object "slavestreamingbarparser_i_sth1_bufinfo_ring_info_data" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(537): object "slavestreamingbarparser_i_sth1_bufinfo_ring_info_config_valid" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(538): object "slavestreamingbarparser_i_sth1_bufinfo_ring_info_config_invalid" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(539): object "slavestreamingbarparser_i_sth1_ring_info_stop" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(552): object "slavestreamingcreditsbarparser_i_sth1_host_cred_index" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(553): object "slavestreamingcreditsbarparser_i_sth1_host_cred_update" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(554): object "slavestreamingcreditsbarparser_i_sth1_host_cred_wrap" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeStreaming_2_3.vhdl(589): object "pcieslavestreamtohost0_compl_be" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "MappedRegBlock_921618fecb8cf8badc2cf71cbe32b185" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|MappedRegBlock_921618fecb8cf8badc2cf71cbe32b185:inst_ln130_mappedregblock" +Sat 21:52: INFO : Info (12128): Elaborating entity "ReadComplRequestArbiter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|ReadComplRequestArbiter:ReadComplRequestArbiter_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "FastRequestArbiter_req1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|ReadComplRequestArbiter:ReadComplRequestArbiter_i|FastRequestArbiter_req1:internal_arbiter_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "priority_encoder" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|ReadComplRequestArbiter:ReadComplRequestArbiter_i|FastRequestArbiter_req1:internal_arbiter_i|priority_encoder:pencoder" +Sat 21:52: INFO : Info (12128): Elaborating entity "fast_request_arbiter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|ReadComplRequestArbiter:ReadComplRequestArbiter_i|FastRequestArbiter_req1:internal_arbiter_i|fast_request_arbiter:fast_request_arbiter_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "RequestEncoder" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at RequestEncoder.vhdl(167): object "wr_req_buffer_i_full" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at RequestEncoder.vhdl(170): object "wr_req_data_buffer_i_full" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at RequestEncoder.vhdl(171): object "wr_req_data_buffer_i_empty" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "write_request_encoder" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|write_request_encoder:inst_ln9_writerequestencoderexternal" +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_115_512_115_aclr_fwft" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "lpm_width" = "115" +Sat 21:52: INFO : Info (12134): Parameter "lpm_widthu" = "9" +Sat 21:52: INFO : Info (12134): Parameter "lpm_numwords" = "512" +Sat 21:52: INFO : Info (12134): Parameter "lpm_showahead" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" +Sat 21:52: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_84b1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: scfifo_84b1 +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo_84b1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_fab1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: a_dpfifo_fab1 +Sat 21:52: INFO : Info (12128): Elaborating entity "a_dpfifo_fab1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_n8j1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_n8j1 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_n8j1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_am8.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: cmpr_am8 +Sat 21:52: INFO : Info (12128): Elaborating entity "cmpr_am8" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|cmpr_am8:almost_full_comparer" +Sat 21:52: INFO : Info (12128): Elaborating entity "cmpr_am8" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|cmpr_am8:three_comparison" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_nhb.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: cntr_nhb +Sat 21:52: INFO : Info (12128): Elaborating entity "cntr_nhb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|cntr_nhb:rd_ptr_msb" +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_128_512_128_aclr_afv448" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_128_512_128_aclr_afv448:wr_req_data_buffer_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_128_512_128_aclr_afv448:wr_req_data_buffer_i|scfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_128_512_128_aclr_afv448:wr_req_data_buffer_i|scfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_128_512_128_aclr_afv448:wr_req_data_buffer_i|scfifo:inst_ln38_mwfifo" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "lpm_width" = "128" +Sat 21:52: INFO : Info (12134): Parameter "lpm_widthu" = "9" +Sat 21:52: INFO : Info (12134): Parameter "lpm_numwords" = "512" +Sat 21:52: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" +Sat 21:52: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:52: INFO : Info (12134): Parameter "almost_full_value" = "448" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_7ee1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: scfifo_7ee1 +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo_7ee1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_128_512_128_aclr_afv448:wr_req_data_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_7ee1:auto_generated" +Sat 21:52: INFO : Info (12128): Elaborating entity "TagGenerator" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|TagGenerator:TagGenerator_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "MemWriteRequestArbiter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|MemWriteRequestArbiter:MemWriteRequestArbiter_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "FastRequestArbiter_req4" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|MemWriteRequestArbiter:MemWriteRequestArbiter_i|FastRequestArbiter_req4:internal_arbiter_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "priority_encoder" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|MemWriteRequestArbiter:MemWriteRequestArbiter_i|FastRequestArbiter_req4:internal_arbiter_i|priority_encoder:pencoder" +Sat 21:52: INFO : Info (12128): Elaborating entity "fast_request_arbiter" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|MemWriteRequestArbiter:MemWriteRequestArbiter_i|FastRequestArbiter_req4:internal_arbiter_i|fast_request_arbiter:fast_request_arbiter_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "SlaveStreamingRingConfigBarParser" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|SlaveStreamingRingConfigBarParser:SlaveStreamingBarParser_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "SlaveStreamingCreditsBarParser" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|SlaveStreamingCreditsBarParser:SlaveStreamingCreditsBarParser_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "PCIeSlaveStreamFromHost" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0" +Sat 21:52: INFO : Info (12128): Elaborating entity "pcie_slave_streaming_sfh_ring" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring" +Sat 21:52: INFO : Info (12128): Elaborating entity "rg_buffer_info" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_info:rg_info" +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_info:rg_info|AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg" +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_info:rg_info|AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_info:rg_info|AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_info:rg_info|AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "address_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "address_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "byte_size" = "8" +Sat 21:52: INFO : Info (12134): Parameter "byteena_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "byteena_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "byteena_reg_b" = "CLOCK1" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_core_a" = "USE_INPUT_CLKEN" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_core_b" = "USE_INPUT_CLKEN" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_input_a" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_input_b" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_output_a" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_output_b" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "stratixv" +Sat 21:52: INFO : Info (12134): Parameter "ecc_pipeline_stage_enabled" = "FALSE" +Sat 21:52: INFO : Info (12134): Parameter "enable_ecc" = "FALSE" +Sat 21:52: INFO : Info (12134): Parameter "implement_in_les" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "indata_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "indata_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "indata_reg_b" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "init_file" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "init_file_layout" = "PORT_A" +Sat 21:52: INFO : Info (12134): Parameter "maximum_depth" = "0" +Sat 21:52: INFO : Info (12134): Parameter "numwords_a" = "2" +Sat 21:52: INFO : Info (12134): Parameter "numwords_b" = "2" +Sat 21:52: INFO : Info (12134): Parameter "operation_mode" = "DUAL_PORT" +Sat 21:52: INFO : Info (12134): Parameter "outdata_aclr_a" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "outdata_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" +Sat 21:52: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" +Sat 21:52: INFO : Info (12134): Parameter "power_up_uninitialized" = "FALSE" +Sat 21:52: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" +Sat 21:52: INFO : Info (12134): Parameter "rdcontrol_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK1" +Sat 21:52: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" +Sat 21:52: INFO : Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" +Sat 21:52: INFO : Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" +Sat 21:52: INFO : Info (12134): Parameter "stratixiv_m144k_allow_dual_clocks" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "width_a" = "8" +Sat 21:52: INFO : Info (12134): Parameter "width_b" = "8" +Sat 21:52: INFO : Info (12134): Parameter "width_byteena_a" = "1" +Sat 21:52: INFO : Info (12134): Parameter "width_byteena_b" = "1" +Sat 21:52: INFO : Info (12134): Parameter "width_eccstatus" = "3" +Sat 21:52: INFO : Info (12134): Parameter "widthad_a" = "1" +Sat 21:52: INFO : Info (12134): Parameter "widthad_b" = "1" +Sat 21:52: INFO : Info (12134): Parameter "wrcontrol_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "wrcontrol_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "altsyncram" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_j034.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_j034 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_j034" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_info:rg_info|AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_8x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_j034:auto_generated" +Sat 21:52: INFO : Info (12128): Elaborating entity "rg_buffer_sfh" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen" +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg" +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "address_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "address_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "byte_size" = "8" +Sat 21:52: INFO : Info (12134): Parameter "byteena_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "byteena_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "byteena_reg_b" = "CLOCK1" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_core_a" = "USE_INPUT_CLKEN" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_core_b" = "USE_INPUT_CLKEN" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_input_a" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_input_b" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_output_a" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_output_b" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "stratixv" +Sat 21:52: INFO : Info (12134): Parameter "ecc_pipeline_stage_enabled" = "FALSE" +Sat 21:52: INFO : Info (12134): Parameter "enable_ecc" = "FALSE" +Sat 21:52: INFO : Info (12134): Parameter "implement_in_les" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "indata_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "indata_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "indata_reg_b" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "init_file" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "init_file_layout" = "PORT_A" +Sat 21:52: INFO : Info (12134): Parameter "maximum_depth" = "0" +Sat 21:52: INFO : Info (12134): Parameter "numwords_a" = "512" +Sat 21:52: INFO : Info (12134): Parameter "numwords_b" = "512" +Sat 21:52: INFO : Info (12134): Parameter "operation_mode" = "DUAL_PORT" +Sat 21:52: INFO : Info (12134): Parameter "outdata_aclr_a" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "outdata_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" +Sat 21:52: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" +Sat 21:52: INFO : Info (12134): Parameter "power_up_uninitialized" = "FALSE" +Sat 21:52: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" +Sat 21:52: INFO : Info (12134): Parameter "rdcontrol_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK1" +Sat 21:52: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" +Sat 21:52: INFO : Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" +Sat 21:52: INFO : Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" +Sat 21:52: INFO : Info (12134): Parameter "stratixiv_m144k_allow_dual_clocks" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "width_a" = "32" +Sat 21:52: INFO : Info (12134): Parameter "width_b" = "32" +Sat 21:52: INFO : Info (12134): Parameter "width_byteena_a" = "1" +Sat 21:52: INFO : Info (12134): Parameter "width_byteena_b" = "1" +Sat 21:52: INFO : Info (12134): Parameter "width_eccstatus" = "3" +Sat 21:52: INFO : Info (12134): Parameter "widthad_a" = "9" +Sat 21:52: INFO : Info (12134): Parameter "widthad_b" = "9" +Sat 21:52: INFO : Info (12134): Parameter "wrcontrol_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "wrcontrol_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "altsyncram" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_9a34.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_9a34 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_9a34" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated" +Sat 21:52: INFO : Info (12128): Elaborating entity "pcie_posted_credits_writer" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer" +Sat 21:52: INFO : Info (12128): Elaborating entity "posted_credits_fifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo" +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_2_16_2_aclr_fwft" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft" +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "lpm_width" = "2" +Sat 21:52: INFO : Info (12134): Parameter "lpm_widthu" = "4" +Sat 21:52: INFO : Info (12134): Parameter "lpm_numwords" = "16" +Sat 21:52: INFO : Info (12134): Parameter "lpm_showahead" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" +Sat 21:52: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_dva1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: scfifo_dva1 +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo_dva1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_k5b1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: a_dpfifo_k5b1 +Sat 21:52: INFO : Info (12128): Elaborating entity "a_dpfifo_k5b1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_1vi1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_1vi1 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_1vi1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo|altsyncram_1vi1:FIFOram" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_5m8.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: cmpr_5m8 +Sat 21:52: INFO : Info (12128): Elaborating entity "cmpr_5m8" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo|cmpr_5m8:almost_full_comparer" +Sat 21:52: INFO : Info (12128): Elaborating entity "cmpr_5m8" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo|cmpr_5m8:three_comparison" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_ihb.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: cntr_ihb +Sat 21:52: INFO : Info (12128): Elaborating entity "cntr_ihb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo|cntr_ihb:rd_ptr_msb" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_vh7.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: cntr_vh7 +Sat 21:52: INFO : Info (12128): Elaborating entity "cntr_vh7" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo|cntr_vh7:usedw_counter" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_jhb.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: cntr_jhb +Sat 21:52: INFO : Info (12128): Elaborating entity "cntr_jhb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost0|pcie_posted_credits_writer:posted_credits_writer|posted_credits_fifo:posted_c_fifo|AlteraFifoEntity_2_16_2_aclr_fwft:wrapped_AlteraFifoEntity_2_16_2_aclr_fwft|scfifo:inst_ln38_mwfifo|scfifo_dva1:auto_generated|a_dpfifo_k5b1:dpfifo|cntr_jhb:wr_ptr" +Sat 21:52: INFO : Info (12128): Elaborating entity "PCIeSlaveStreamToHost" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeSlaveStreamToHost.vhdl(207): object "stream_ring_compl_fifo_underflow" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "pcie_slave_streaming_sth_ring" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring" +Sat 21:52: INFO : Info (12128): Elaborating entity "sth_compl_fifo_debug" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo" +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of" +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "lpm_width" = "60" +Sat 21:52: INFO : Info (12134): Parameter "lpm_widthu" = "4" +Sat 21:52: INFO : Info (12134): Parameter "lpm_numwords" = "16" +Sat 21:52: INFO : Info (12134): Parameter "lpm_showahead" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" +Sat 21:52: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:52: INFO : Info (12134): Parameter "almost_full_value" = "14" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_36e1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: scfifo_36e1 +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo_36e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_gpb1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: a_dpfifo_gpb1 +Sat 21:52: INFO : Info (12128): Elaborating entity "a_dpfifo_gpb1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_92j1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_92j1 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_92j1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram" +Sat 21:52: INFO : Info (12128): Elaborating entity "rg_buffer_sth" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_sth:\gen_buffers:0:buf_gen" +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_sth:\gen_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg:wrapped_AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg" +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_sth:\gen_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg:wrapped_AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg|altsyncram:inst_ln100_mwblockmem" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_sth:\gen_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg:wrapped_AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg|altsyncram:inst_ln100_mwblockmem" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_sth:\gen_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg:wrapped_AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg|altsyncram:inst_ln100_mwblockmem" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "address_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "address_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "byte_size" = "8" +Sat 21:52: INFO : Info (12134): Parameter "byteena_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "byteena_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "byteena_reg_b" = "CLOCK1" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_core_a" = "USE_INPUT_CLKEN" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_core_b" = "USE_INPUT_CLKEN" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_input_a" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_input_b" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_output_a" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_output_b" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "stratixv" +Sat 21:52: INFO : Info (12134): Parameter "ecc_pipeline_stage_enabled" = "FALSE" +Sat 21:52: INFO : Info (12134): Parameter "enable_ecc" = "FALSE" +Sat 21:52: INFO : Info (12134): Parameter "implement_in_les" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "indata_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "indata_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "indata_reg_b" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "init_file" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "init_file_layout" = "PORT_A" +Sat 21:52: INFO : Info (12134): Parameter "maximum_depth" = "0" +Sat 21:52: INFO : Info (12134): Parameter "numwords_a" = "256" +Sat 21:52: INFO : Info (12134): Parameter "numwords_b" = "256" +Sat 21:52: INFO : Info (12134): Parameter "operation_mode" = "DUAL_PORT" +Sat 21:52: INFO : Info (12134): Parameter "outdata_aclr_a" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "outdata_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "outdata_reg_a" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "outdata_reg_b" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "power_up_uninitialized" = "FALSE" +Sat 21:52: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" +Sat 21:52: INFO : Info (12134): Parameter "rdcontrol_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK1" +Sat 21:52: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" +Sat 21:52: INFO : Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" +Sat 21:52: INFO : Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" +Sat 21:52: INFO : Info (12134): Parameter "stratixiv_m144k_allow_dual_clocks" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "width_a" = "128" +Sat 21:52: INFO : Info (12134): Parameter "width_b" = "128" +Sat 21:52: INFO : Info (12134): Parameter "width_byteena_a" = "1" +Sat 21:52: INFO : Info (12134): Parameter "width_byteena_b" = "1" +Sat 21:52: INFO : Info (12134): Parameter "width_eccstatus" = "3" +Sat 21:52: INFO : Info (12134): Parameter "widthad_a" = "8" +Sat 21:52: INFO : Info (12134): Parameter "widthad_b" = "8" +Sat 21:52: INFO : Info (12134): Parameter "wrcontrol_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "wrcontrol_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "altsyncram" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_j024.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_j024 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_j024" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_sth:\gen_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg:wrapped_AlteraBlockMem_RAM_TWO_PORT_128x256_RAM_TWO_PORT_ireg_oreg|altsyncram:inst_ln100_mwblockmem|altsyncram_j024:auto_generated" +Sat 21:52: INFO : Info (12128): Elaborating entity "rg_buffer_info_sth" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_info_sth:g_info" +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_info_sth:g_info|AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg" +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_info_sth:g_info|AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_info_sth:g_info|AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_info_sth:g_info|AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "address_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "address_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "byte_size" = "8" +Sat 21:52: INFO : Info (12134): Parameter "byteena_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "byteena_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "byteena_reg_b" = "CLOCK1" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_core_a" = "USE_INPUT_CLKEN" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_core_b" = "USE_INPUT_CLKEN" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_input_a" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_input_b" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_output_a" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "clock_enable_output_b" = "BYPASS" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "stratixv" +Sat 21:52: INFO : Info (12134): Parameter "ecc_pipeline_stage_enabled" = "FALSE" +Sat 21:52: INFO : Info (12134): Parameter "enable_ecc" = "FALSE" +Sat 21:52: INFO : Info (12134): Parameter "implement_in_les" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "indata_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "indata_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "indata_reg_b" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "init_file" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "init_file_layout" = "PORT_A" +Sat 21:52: INFO : Info (12134): Parameter "maximum_depth" = "0" +Sat 21:52: INFO : Info (12134): Parameter "numwords_a" = "2" +Sat 21:52: INFO : Info (12134): Parameter "numwords_b" = "2" +Sat 21:52: INFO : Info (12134): Parameter "operation_mode" = "DUAL_PORT" +Sat 21:52: INFO : Info (12134): Parameter "outdata_aclr_a" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "outdata_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" +Sat 21:52: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" +Sat 21:52: INFO : Info (12134): Parameter "power_up_uninitialized" = "FALSE" +Sat 21:52: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" +Sat 21:52: INFO : Info (12134): Parameter "rdcontrol_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK1" +Sat 21:52: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" +Sat 21:52: INFO : Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" +Sat 21:52: INFO : Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" +Sat 21:52: INFO : Info (12134): Parameter "stratixiv_m144k_allow_dual_clocks" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "width_a" = "9" +Sat 21:52: INFO : Info (12134): Parameter "width_b" = "9" +Sat 21:52: INFO : Info (12134): Parameter "width_byteena_a" = "1" +Sat 21:52: INFO : Info (12134): Parameter "width_byteena_b" = "1" +Sat 21:52: INFO : Info (12134): Parameter "width_eccstatus" = "3" +Sat 21:52: INFO : Info (12134): Parameter "widthad_a" = "1" +Sat 21:52: INFO : Info (12134): Parameter "widthad_b" = "1" +Sat 21:52: INFO : Info (12134): Parameter "wrcontrol_aclr_a" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "wrcontrol_aclr_b" = "NONE" +Sat 21:52: INFO : Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" +Sat 21:52: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "altsyncram" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_l034.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_l034 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_l034" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|rg_buffer_info_sth:g_info|AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_9x2_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_l034:auto_generated" +Sat 21:52: INFO : Info (12128): Elaborating entity "MappedElementAdapterForwarder" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedElementAdapterForwarder:MappedElementAdapterForwarder_pcie_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "PerfMonitor" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PerfMonitor:PerformanceMonitor_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "perf_monitor" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PerfMonitor:PerformanceMonitor_i|perf_monitor:inst_ln11_perfmonitorext" +Sat 21:52: INFO : Info (12128): Elaborating entity "start_of_day_reset" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|start_of_day_reset:inst_ln9_startofdayreset" +Sat 21:52: INFO : Info (12128): Elaborating entity "MAX4PCIeSlaveInterface" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(537): object "pcieslaveinterface_imp_qsfp_top_i2c_scl_drv" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(538): object "pcieslaveinterface_imp_qsfp_top_i2c_sda_drv" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(539): object "pcieslaveinterface_imp_qsfp_top_i2c_lpmode" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(540): object "pcieslaveinterface_imp_qsfp_top_i2c_modsell" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(541): object "pcieslaveinterface_imp_qsfp_top_i2c_resetl" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(542): object "pcieslaveinterface_imp_qsfp_mid_i2c_scl_drv" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(543): object "pcieslaveinterface_imp_qsfp_mid_i2c_sda_drv" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(544): object "pcieslaveinterface_imp_qsfp_mid_i2c_lpmode" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(545): object "pcieslaveinterface_imp_qsfp_mid_i2c_modsell" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(546): object "pcieslaveinterface_imp_qsfp_mid_i2c_resetl" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(547): object "pcieslaveinterface_imp_qsfp_bot_i2c_scl_drv" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(548): object "pcieslaveinterface_imp_qsfp_bot_i2c_sda_drv" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(549): object "pcieslaveinterface_imp_qsfp_bot_i2c_lpmode" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(550): object "pcieslaveinterface_imp_qsfp_bot_i2c_modsell" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(551): object "pcieslaveinterface_imp_qsfp_bot_i2c_resetl" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(552): object "pcieslaveinterface_imp_ptp_phy_mdio_scl_from_host" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4PCIeSlaveInterface.vhdl(553): object "pcieslaveinterface_imp_ptp_phy_mdio_sda_from_host" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "max_SV_pcie_slave" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp" +Sat 21:52: INFO : Warning (10873): Using initial value X (don't care) for net "tx_reg_compl_data[63..32]" at max_SV_pcie_slave.vhd(86) +Sat 21:52: INFO : Info (12128): Elaborating entity "compl_fifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo" +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "lpm_width" = "45" +Sat 21:52: INFO : Info (12134): Parameter "lpm_widthu" = "5" +Sat 21:52: INFO : Info (12134): Parameter "lpm_numwords" = "32" +Sat 21:52: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" +Sat 21:52: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:52: INFO : Info (12134): Parameter "almost_full_value" = "20" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_09e1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: scfifo_09e1 +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo_09e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_gsb1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: a_dpfifo_gsb1 +Sat 21:52: INFO : Info (12128): Elaborating entity "a_dpfifo_gsb1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_56f.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: a_fefifo_56f +Sat 21:52: INFO : Info (12128): Elaborating entity "a_fefifo_56f" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|a_fefifo_56f:fifo_state" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_0i7.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: cntr_0i7 +Sat 21:52: INFO : Info (12128): Elaborating entity "cntr_0i7" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|a_fefifo_56f:fifo_state|cntr_0i7:count_usedw" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_emb1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dpram_emb1 +Sat 21:52: INFO : Info (12128): Elaborating entity "dpram_emb1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|dpram_emb1:FIFOram" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_8ou1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_8ou1 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_8ou1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|dpram_emb1:FIFOram|altsyncram_8ou1:altsyncram1" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_khb.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: cntr_khb +Sat 21:52: INFO : Info (12128): Elaborating entity "cntr_khb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|cntr_khb:rd_ptr_count" +Sat 21:52: INFO : Info (12128): Elaborating entity "max_pcie_slave_req_dispatcher" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_pcie_slave_req_dispatcher:PCIeSlaveReqDispatcher_imp" +Sat 21:52: INFO : Info (12128): Elaborating entity "StratixPCIeInterface" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "max_SV_pcie_tx" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_tx.vhd(166): object "dma_write_count_reset" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_tx.vhd(193): object "qword_aligned" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "pcie_tx_fifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "lpm_width" = "132" +Sat 21:52: INFO : Info (12134): Parameter "lpm_widthu" = "6" +Sat 21:52: INFO : Info (12134): Parameter "lpm_numwords" = "64" +Sat 21:52: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "SCFIFO" +Sat 21:52: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:52: INFO : Info (12134): Parameter "almost_full_value" = "48" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/scfifo_tae1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: scfifo_tae1 +Sat 21:52: INFO : Info (12128): Elaborating entity "scfifo_tae1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_dpfifo_3ub1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: a_dpfifo_3ub1 +Sat 21:52: INFO : Info (12128): Elaborating entity "a_dpfifo_3ub1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated|a_dpfifo_3ub1:dpfifo" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_fefifo_b6f.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: a_fefifo_b6f +Sat 21:52: INFO : Info (12128): Elaborating entity "a_fefifo_b6f" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated|a_dpfifo_3ub1:dpfifo|a_fefifo_b6f:fifo_state" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_1i7.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: cntr_1i7 +Sat 21:52: INFO : Info (12128): Elaborating entity "cntr_1i7" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated|a_dpfifo_3ub1:dpfifo|a_fefifo_b6f:fifo_state|cntr_1i7:count_usedw" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dpram_snb1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dpram_snb1 +Sat 21:52: INFO : Info (12128): Elaborating entity "dpram_snb1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated|a_dpfifo_3ub1:dpfifo|dpram_snb1:FIFOram" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_8uu1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_8uu1 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_8uu1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated|a_dpfifo_3ub1:dpfifo|dpram_snb1:FIFOram|altsyncram_8uu1:altsyncram1" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_lhb.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: cntr_lhb +Sat 21:52: INFO : Info (12128): Elaborating entity "cntr_lhb" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_tx:StratixVPCIeTX_i|pcie_tx_fifo:pcie_tx_fifo_i|scfifo:wrapped_scfifo|scfifo_tae1:auto_generated|a_dpfifo_3ub1:dpfifo|cntr_lhb:rd_ptr_count" +Sat 21:52: INFO : Info (12128): Elaborating entity "max_SV_pcie_rx" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StratixPCIeInterface:StratixPCIeInterface_i|max_SV_pcie_rx:StratixVPCIeRX_i" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(112): object "data_stream_aligned" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(128): object "bars_hit_r" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(130): object "bar4_hit_r" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(141): object "rx_st_err_reg" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(159): object "rx_st_eop_r" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(161): object "rx_st_empty_r" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(165): object "reg_bar0" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at max_SV_pcie_rx.vhd(165): object "reg_bar2" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "PCIeEA" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at PCIeEA.vhdl(148): object "slave_from_host_fifo_full" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_34_512_34_dualclock_aclr" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host" +Sat 21:52: INFO : Info (12128): Elaborating entity "dcfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "lpm_width" = "34" +Sat 21:52: INFO : Info (12134): Parameter "lpm_widthu" = "9" +Sat 21:52: INFO : Info (12134): Parameter "lpm_numwords" = "512" +Sat 21:52: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" +Sat 21:52: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:52: INFO : Info (12134): Parameter "delay_rdusedw" = "1" +Sat 21:52: INFO : Info (12134): Parameter "delay_wrusedw" = "1" +Sat 21:52: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" +Sat 21:52: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" +Sat 21:52: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_au42.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dcfifo_au42 +Sat 21:52: INFO : Info (12128): Elaborating entity "dcfifo_au42" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo|dcfifo_au42:auto_generated" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_68e1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_68e1 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_68e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo|dcfifo_au42:auto_generated|altsyncram_68e1:fifo_ram" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_2md.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: alt_synch_pipe_2md +Sat 21:52: INFO : Info (12128): Elaborating entity "alt_synch_pipe_2md" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo|dcfifo_au42:auto_generated|alt_synch_pipe_2md:rs_dgwp" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_1f9.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dffpipe_1f9 +Sat 21:52: INFO : Info (12128): Elaborating entity "dffpipe_1f9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo|dcfifo_au42:auto_generated|alt_synch_pipe_2md:rs_dgwp|dffpipe_1f9:dffpipe6" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_3md.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: alt_synch_pipe_3md +Sat 21:52: INFO : Info (12128): Elaborating entity "alt_synch_pipe_3md" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo|dcfifo_au42:auto_generated|alt_synch_pipe_3md:ws_dgrp" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_2f9.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dffpipe_2f9 +Sat 21:52: INFO : Info (12128): Elaborating entity "dffpipe_2f9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr:fifo_to_host|dcfifo:inst_ln38_mwfifo|dcfifo_au42:auto_generated|alt_synch_pipe_3md:ws_dgrp|dffpipe_2f9:dffpipe9" +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo" +Sat 21:52: INFO : Info (12128): Elaborating entity "dcfifo" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "lpm_width" = "34" +Sat 21:52: INFO : Info (12134): Parameter "lpm_widthu" = "9" +Sat 21:52: INFO : Info (12134): Parameter "lpm_numwords" = "512" +Sat 21:52: INFO : Info (12134): Parameter "lpm_showahead" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" +Sat 21:52: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:52: INFO : Info (12134): Parameter "delay_rdusedw" = "1" +Sat 21:52: INFO : Info (12134): Parameter "delay_wrusedw" = "1" +Sat 21:52: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" +Sat 21:52: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" +Sat 21:52: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_tk52.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dcfifo_tk52 +Sat 21:52: INFO : Info (12128): Elaborating entity "dcfifo_tk52" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo|dcfifo_tk52:auto_generated" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_t0c1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_t0c1 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_t0c1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo|dcfifo_tk52:auto_generated|altsyncram_t0c1:fifo_ram" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_4md.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: alt_synch_pipe_4md +Sat 21:52: INFO : Info (12128): Elaborating entity "alt_synch_pipe_4md" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo|dcfifo_tk52:auto_generated|alt_synch_pipe_4md:rs_dgwp" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_3f9.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dffpipe_3f9 +Sat 21:52: INFO : Info (12128): Elaborating entity "dffpipe_3f9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo|dcfifo_tk52:auto_generated|alt_synch_pipe_4md:rs_dgwp|dffpipe_3f9:dffpipe6" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_5md.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: alt_synch_pipe_5md +Sat 21:52: INFO : Info (12128): Elaborating entity "alt_synch_pipe_5md" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo|dcfifo_tk52:auto_generated|alt_synch_pipe_5md:ws_dgrp" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_4f9.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dffpipe_4f9 +Sat 21:52: INFO : Info (12128): Elaborating entity "dffpipe_4f9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|PCIeEA:PCIeEA_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv384:slave_from_host_fifo|dcfifo:inst_ln38_mwfifo|dcfifo_tk52:auto_generated|alt_synch_pipe_5md:ws_dgrp|dffpipe_4f9:dffpipe9" +Sat 21:52: INFO : Info (12128): Elaborating entity "StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock.vhdl(100): object "inst_ln70_alterafifo_full" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock.vhdl(102): object "inst_ln70_alterafifo_wr_data_count" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo" +Sat 21:52: INFO : Info (12128): Elaborating entity "dcfifo_mixed_widths" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo" +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "lpm_width" = "128" +Sat 21:52: INFO : Info (12134): Parameter "lpm_widthu" = "7" +Sat 21:52: INFO : Info (12134): Parameter "lpm_numwords" = "128" +Sat 21:52: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "lpm_type" = "DCFIFO" +Sat 21:52: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:52: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:52: INFO : Info (12134): Parameter "delay_rdusedw" = "1" +Sat 21:52: INFO : Info (12134): Parameter "delay_wrusedw" = "1" +Sat 21:52: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "rdsync_delaypipe" = "4" +Sat 21:52: INFO : Info (12134): Parameter "wrsync_delaypipe" = "4" +Sat 21:52: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" +Sat 21:52: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" +Sat 21:52: INFO : Info (12134): Parameter "lpm_width_r" = "64" +Sat 21:52: INFO : Info (12134): Parameter "lpm_widthu_r" = "8" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_ip52.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dcfifo_ip52 +Sat 21:52: INFO : Info (12128): Elaborating entity "dcfifo_ip52" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_gray2bin_hab.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: a_gray2bin_hab +Sat 21:52: INFO : Info (12128): Elaborating entity "a_gray2bin_hab" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|a_gray2bin_hab:wrptr_g_gray2bin" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_fv6.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: a_graycounter_fv6 +Sat 21:52: INFO : Info (12128): Elaborating entity "a_graycounter_fv6" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|a_graycounter_fv6:rdptr_g1p" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/a_graycounter_cdc.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: a_graycounter_cdc +Sat 21:52: INFO : Info (12128): Elaborating entity "a_graycounter_cdc" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|a_graycounter_cdc:wrptr_g1p" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_q9e1.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: altsyncram_q9e1 +Sat 21:52: INFO : Info (12128): Elaborating entity "altsyncram_q9e1" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_hkd.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: alt_synch_pipe_hkd +Sat 21:52: INFO : Info (12128): Elaborating entity "alt_synch_pipe_hkd" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|alt_synch_pipe_hkd:rs_dgwp" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dffpipe_gd9 +Sat 21:52: INFO : Info (12128): Elaborating entity "dffpipe_gd9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|alt_synch_pipe_hkd:rs_dgwp|dffpipe_gd9:dffpipe12" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_fd9.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dffpipe_fd9 +Sat 21:52: INFO : Info (12128): Elaborating entity "dffpipe_fd9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|dffpipe_fd9:ws_brp" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_ikd.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: alt_synch_pipe_ikd +Sat 21:52: INFO : Info (12128): Elaborating entity "alt_synch_pipe_ikd" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|alt_synch_pipe_ikd:ws_dgrp" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_hd9.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: dffpipe_hd9 +Sat 21:52: INFO : Info (12128): Elaborating entity "dffpipe_hd9" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|alt_synch_pipe_ikd:ws_dgrp|dffpipe_hd9:dffpipe16" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_206.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: cmpr_206 +Sat 21:52: INFO : Info (12128): Elaborating entity "cmpr_206" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|cmpr_206:rdempty_eq_comp" +Sat 21:52: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_ptd.tdf +Sat 21:52: INFO : Info (12023): Found entity 1: cntr_ptd +Sat 21:52: INFO : Info (12128): Elaborating entity "cntr_ptd" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|cntr_ptd:cntr_b" +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv496" for hierarchy "MAX4FPGATop:MAX4MaiaFabricTop_i|AlteraFifoEntity_34_512_34_dualclock_aclr_wrusedw_fwft_pfv496:ftb_MappedElementsSwitchPCIeEA" +Sat 21:52: INFO : Info (12128): Elaborating entity "AlteraClockGenerator_250_200_STREAM" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "StratixVClockManager_in250_out_f200p0dc50_f200p180dc50" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVClockManager_in250_out_f200p0dc50_f200p180dc50.vhdl(295): object "altera_pll_i_fboutclk" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "altera_pll" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll:altera_pll_i" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at altera_pll.v(398): object "cntsel_temp" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at altera_pll.v(400): object "gnd" assigned a value but never read +Sat 21:52: INFO : Warning (10034): Output port "lvds_clk" at altera_pll.v(295) has no driver +Sat 21:52: INFO : Warning (10034): Output port "loaden" at altera_pll.v(296) has no driver +Sat 21:52: INFO : Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus +Sat 21:52: INFO : Info (12130): Elaborated megafunction instantiation "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll:altera_pll_i" +Sat 21:52: INFO : Info (12133): Instantiated megafunction "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll:altera_pll_i" with the following parameter: +Sat 21:52: INFO : Info (12134): Parameter "fractional_vco_multiplier" = "false" +Sat 21:52: INFO : Info (12134): Parameter "reference_clock_frequency" = "250.0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "operation_mode" = "normal" +Sat 21:52: INFO : Info (12134): Parameter "number_of_clocks" = "2" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency0" = "200.0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift0" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle0" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency1" = "200.0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift1" = "2500 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle1" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency2" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift2" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle2" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency3" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift3" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle3" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency4" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift4" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle4" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency5" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift5" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle5" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency6" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift6" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle6" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency7" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift7" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle7" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency8" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift8" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle8" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency9" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift9" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle9" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency10" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift10" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle10" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency11" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift11" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle11" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency12" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift12" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle12" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency13" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift13" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle13" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency14" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift14" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle14" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency15" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift15" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle15" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency16" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift16" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle16" = "50" +Sat 21:52: INFO : Info (12134): Parameter "output_clock_frequency17" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "phase_shift17" = "0 ps" +Sat 21:52: INFO : Info (12134): Parameter "duty_cycle17" = "50" +Sat 21:52: INFO : Info (12134): Parameter "pll_type" = "General" +Sat 21:52: INFO : Info (12134): Parameter "m_cnt_hi_div" = "1" +Sat 21:52: INFO : Info (12134): Parameter "m_cnt_lo_div" = "1" +Sat 21:52: INFO : Info (12134): Parameter "n_cnt_hi_div" = "1" +Sat 21:52: INFO : Info (12134): Parameter "n_cnt_lo_div" = "1" +Sat 21:52: INFO : Info (12134): Parameter "m_cnt_bypass_en" = "true" +Sat 21:52: INFO : Info (12134): Parameter "n_cnt_bypass_en" = "true" +Sat 21:52: INFO : Info (12134): Parameter "m_cnt_odd_div_duty_en" = "false" +Sat 21:52: INFO : Info (12134): Parameter "n_cnt_odd_div_duty_en" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div0" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div0" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst0" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst0" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en0" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en0" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div1" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div1" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst1" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst1" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en1" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en1" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div2" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div2" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst2" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst2" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en2" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en2" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div3" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div3" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst3" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst3" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en3" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en3" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div4" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div4" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst4" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst4" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en4" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en4" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div5" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div5" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst5" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst5" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en5" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en5" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div6" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div6" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst6" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst6" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en6" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en6" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div7" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div7" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst7" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst7" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en7" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en7" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div8" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div8" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst8" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst8" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en8" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en8" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div9" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div9" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst9" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst9" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en9" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en9" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div10" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div10" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst10" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst10" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en10" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en10" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div11" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div11" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst11" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst11" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en11" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en11" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div12" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div12" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst12" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst12" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en12" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en12" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div13" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div13" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst13" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst13" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en13" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en13" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div14" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div14" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst14" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst14" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en14" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en14" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div15" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div15" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst15" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst15" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en15" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en15" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div16" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div16" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst16" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst16" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en16" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en16" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_hi_div17" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_lo_div17" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_prst17" = "1" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_ph_mux_prst17" = "0" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_bypass_en17" = "false" +Sat 21:52: INFO : Info (12134): Parameter "c_cnt_odd_div_duty_en17" = "false" +Sat 21:52: INFO : Info (12134): Parameter "pll_output_clk_frequency" = "0 MHz" +Sat 21:52: INFO : Info (12134): Parameter "pll_vco_div" = "1" +Sat 21:52: INFO : Info (12134): Parameter "pll_cp_current" = "5" +Sat 21:52: INFO : Info (12134): Parameter "pll_bwctrl" = "18000" +Sat 21:52: INFO : Info (12134): Parameter "pll_fractional_division" = "1" +Sat 21:52: INFO : Info (12128): Elaborating entity "altera_pll_reconfig_top" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "dyn_phase_shift" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst" +Sat 21:52: INFO : Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_0" +Sat 21:52: INFO : Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_1" +Sat 21:52: INFO : Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_2" +Sat 21:52: INFO : Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_3" +Sat 21:52: INFO : Info (12128): Elaborating entity "generic_lcell_comb" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst|generic_lcell_comb:lcell_cnt_sel_4" +Sat 21:52: INFO : Info (12128): Elaborating entity "self_reset" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|self_reset:self_reset_inst" +Sat 21:52: INFO : Info (12128): Elaborating entity "dprio_mux" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dprio_mux:dprio_mux_inst" +Sat 21:52: INFO : Info (12128): Elaborating entity "fpll_dprio_init" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|fpll_dprio_init:fpll_dprio_init_inst" +Sat 21:52: INFO : Info (12128): Elaborating entity "MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena:clockgen_altclkctrl_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena_altclkctrl_tmg" for hierarchy "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena:clockgen_altclkctrl_i|MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena_altclkctrl_tmg:MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena_altclkctrl_tmg_component" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at MWAltClkCtrl_quartusv13_1_0_AUTO_numclk_1_ena.vhd(58): object "clkselect" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "StratixPCIeBase" for hierarchy "StratixPCIeBase:PCIeBase_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "StratixVHardIPPCIe" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(514): object "pcie_sv_hard_ip_i_lmi_ack" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(515): object "pcie_sv_hard_ip_i_lmi_dout" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(518): object "pcie_sv_hard_ip_i_tl_cfg_sts" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(519): object "pcie_sv_hard_ip_i_pme_to_sr" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(520): object "pcie_sv_hard_ip_i_currentspeed" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(521): object "pcie_sv_hard_ip_i_derr_cor_ext_rcv" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(522): object "pcie_sv_hard_ip_i_derr_cor_ext_rpl" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(523): object "pcie_sv_hard_ip_i_derr_rpl" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(524): object "pcie_sv_hard_ip_i_dlup" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(525): object "pcie_sv_hard_ip_i_dlup_exit" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(526): object "pcie_sv_hard_ip_i_ev128ns" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(527): object "pcie_sv_hard_ip_i_ev1us" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(528): object "pcie_sv_hard_ip_i_hotrst_exit" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(529): object "pcie_sv_hard_ip_i_int_status" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(530): object "pcie_sv_hard_ip_i_l2_exit" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(531): object "pcie_sv_hard_ip_i_lane_act" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(533): object "pcie_sv_hard_ip_i_rx_par_err" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(534): object "pcie_sv_hard_ip_i_tx_par_err" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(535): object "pcie_sv_hard_ip_i_cfg_par_err" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(536): object "pcie_sv_hard_ip_i_ko_cpl_spc_header" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(537): object "pcie_sv_hard_ip_i_ko_cpl_spc_data" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(546): object "pcie_sv_hard_ip_i_tx_cred_datafccp" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(547): object "pcie_sv_hard_ip_i_tx_cred_datafcnp" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(548): object "pcie_sv_hard_ip_i_tx_cred_datafcp" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(549): object "pcie_sv_hard_ip_i_tx_cred_fchipcons" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(550): object "pcie_sv_hard_ip_i_tx_cred_fcinfinite" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(551): object "pcie_sv_hard_ip_i_tx_cred_hdrfccp" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(552): object "pcie_sv_hard_ip_i_tx_cred_hdrfcnp" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(553): object "pcie_sv_hard_ip_i_tx_cred_hdrfcp" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(557): object "pcie_sv_hard_ip_i_pld_clk_inuse" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at StratixVHardIPPCIe.vhdl(558): object "pcie_sv_hard_ip_i_testin_zero" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "pcie_SV_hard_ip" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i" +Sat 21:52: INFO : Info (12128): Elaborating entity "altpcie_sv_hip_ast_hwtcl" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst" +Sat 21:52: INFO : Warning (10764): Verilog HDL warning at altpcie_sv_hip_ast_hwtcl.v(1082): converting signed shift amount to unsigned +Sat 21:52: INFO : Warning (10242): Verilog HDL Function Declaration warning at altpcie_sv_hip_ast_hwtcl.v(1044): variable "return_string" may have a Don't Care value because it may not be assigned a value in every possible path through the statements preceding its use +Sat 21:52: INFO : Warning (10230): Verilog HDL assignment warning at altpcie_sv_hip_ast_hwtcl.v(1044): truncated value with size 208 to match size of target (200) +Sat 21:52: INFO : Warning (10764): Verilog HDL warning at altpcie_sv_hip_ast_hwtcl.v(1092): converting signed shift amount to unsigned +Sat 21:52: INFO : Warning (10230): Verilog HDL assignment warning at altpcie_sv_hip_ast_hwtcl.v(2361): truncated value with size 2 to match size of target (1) +Sat 21:52: INFO : Warning (10230): Verilog HDL assignment warning at altpcie_sv_hip_ast_hwtcl.v(2362): truncated value with size 2 to match size of target (1) +Sat 21:52: INFO : Warning (10230): Verilog HDL assignment warning at altpcie_sv_hip_ast_hwtcl.v(2363): truncated value with size 2 to match size of target (1) +Sat 21:52: INFO : Warning (10230): Verilog HDL assignment warning at altpcie_sv_hip_ast_hwtcl.v(2364): truncated value with size 2 to match size of target (1) +Sat 21:52: INFO : Info (12128): Elaborating entity "altpcie_hip_256_pipen1b" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b" +Sat 21:52: INFO : Warning (10242): Verilog HDL Function Declaration warning at altpcie_hip_256_pipen1b.v(931): variable "return_string" may have a Don't Care value because it may not be assigned a value in every possible path through the statements preceding its use +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1306): object rst_ctrl_rxanalogreset used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1307): object rst_ctrl_rxdigitalreset used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1308): object rst_ctrl_xcvr_powerdown used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1309): object rst_ctrl_txdigitalreset used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1645): object phystatus0_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1646): object phystatus1_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1647): object phystatus2_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1648): object phystatus3_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1649): object phystatus4_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1650): object phystatus5_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1651): object phystatus6_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1652): object phystatus7_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1653): object rxdata0_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1654): object rxdata1_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1655): object rxdata2_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1656): object rxdata3_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1657): object rxdata4_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1658): object rxdata5_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1659): object rxdata6_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1660): object rxdata7_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1661): object rxdatak0_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1662): object rxdatak1_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1663): object rxdatak2_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1664): object rxdatak3_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1665): object rxdatak4_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1666): object rxdatak5_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1667): object rxdatak6_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1668): object rxdatak7_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1669): object rxelecidle0_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1670): object rxelecidle1_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1671): object rxelecidle2_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1672): object rxelecidle3_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1673): object rxelecidle4_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1674): object rxelecidle5_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1675): object rxelecidle6_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1676): object rxelecidle7_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1685): object rxstatus0_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1686): object rxstatus1_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1687): object rxstatus2_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1688): object rxstatus3_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1689): object rxstatus4_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1690): object rxstatus5_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1691): object rxstatus6_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1692): object rxstatus7_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1717): object rxvalid0_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1718): object rxvalid1_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1719): object rxvalid2_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1720): object rxvalid3_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1721): object rxvalid4_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1722): object rxvalid5_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1723): object rxvalid6_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1724): object rxvalid7_ext32b used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1726): object pipe32_sim_rxdata0 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1727): object pipe32_sim_rxdata1 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1728): object pipe32_sim_rxdata2 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1729): object pipe32_sim_rxdata3 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1730): object pipe32_sim_rxdata4 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1731): object pipe32_sim_rxdata5 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1732): object pipe32_sim_rxdata6 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1733): object pipe32_sim_rxdata7 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1734): object pipe32_sim_rxdatak0 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1735): object pipe32_sim_rxdatak1 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1736): object pipe32_sim_rxdatak2 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1737): object pipe32_sim_rxdatak3 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1738): object pipe32_sim_rxdatak4 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1739): object pipe32_sim_rxdatak5 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1740): object pipe32_sim_rxdatak6 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1741): object pipe32_sim_rxdatak7 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1742): object pipe32_sim_rxvalid0 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1743): object pipe32_sim_rxvalid1 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1744): object pipe32_sim_rxvalid2 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1745): object pipe32_sim_rxvalid3 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1746): object pipe32_sim_rxvalid4 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1747): object pipe32_sim_rxvalid5 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1748): object pipe32_sim_rxvalid6 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1749): object pipe32_sim_rxvalid7 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1750): object pipe32_sim_rxelecidle0 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1751): object pipe32_sim_rxelecidle1 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1752): object pipe32_sim_rxelecidle2 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1753): object pipe32_sim_rxelecidle3 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1754): object pipe32_sim_rxelecidle4 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1755): object pipe32_sim_rxelecidle5 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1756): object pipe32_sim_rxelecidle6 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1757): object pipe32_sim_rxelecidle7 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1758): object pipe32_sim_phystatus0 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1759): object pipe32_sim_phystatus1 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1760): object pipe32_sim_phystatus2 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1761): object pipe32_sim_phystatus3 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1762): object pipe32_sim_phystatus4 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1763): object pipe32_sim_phystatus5 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1764): object pipe32_sim_phystatus6 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1765): object pipe32_sim_phystatus7 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1766): object pipe32_sim_rxstatus0 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1767): object pipe32_sim_rxstatus1 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1768): object pipe32_sim_rxstatus2 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1769): object pipe32_sim_rxstatus3 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1770): object pipe32_sim_rxstatus4 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1771): object pipe32_sim_rxstatus5 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1772): object pipe32_sim_rxstatus6 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1773): object pipe32_sim_rxstatus7 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1774): object pipe32_sim_rxdataskip0 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1775): object pipe32_sim_rxdataskip1 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1776): object pipe32_sim_rxdataskip2 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1777): object pipe32_sim_rxdataskip3 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1778): object pipe32_sim_rxdataskip4 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1779): object pipe32_sim_rxdataskip5 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1780): object pipe32_sim_rxdataskip6 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1781): object pipe32_sim_rxdataskip7 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1782): object pipe32_sim_rxblkst0 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1783): object pipe32_sim_rxblkst1 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1784): object pipe32_sim_rxblkst2 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1785): object pipe32_sim_rxblkst3 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1786): object pipe32_sim_rxblkst4 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1787): object pipe32_sim_rxblkst5 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1788): object pipe32_sim_rxblkst6 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1789): object pipe32_sim_rxblkst7 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1790): object pipe32_sim_rxsynchd0 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1791): object pipe32_sim_rxsynchd1 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1792): object pipe32_sim_rxsynchd2 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1793): object pipe32_sim_rxsynchd3 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1794): object pipe32_sim_rxsynchd4 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1795): object pipe32_sim_rxsynchd5 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1796): object pipe32_sim_rxsynchd6 used but never assigned +Sat 21:52: INFO : Warning (10858): Verilog HDL warning at altpcie_hip_256_pipen1b.v(1797): object pipe32_sim_rxsynchd7 used but never assigned +Sat 21:52: INFO : Info (12128): Elaborating entity "altpcie_rs_hip" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|altpcie_rs_hip:g_soft_reset.altpcie_rs_hip" +Sat 21:52: INFO : Warning (10230): Verilog HDL assignment warning at altpcie_rs_hip.v(86): truncated value with size 2 to match size of target (1) +Sat 21:52: INFO : Info (12128): Elaborating entity "sv_xcvr_pipe_native" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_xcvr_pipe_native.sv(452): object "w_pll_tx_pcie_fb_clk" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_xcvr_pipe_native.sv(453): object "w_pll_tx_pll_fb_sw" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "sv_xcvr_emsip_adapter" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_emsip_adapter:sv_xcvr_emsip_adapter_inst" +Sat 21:52: INFO : Warning (10034): Output port "rxfreqtxcmuplllock[4]" at sv_xcvr_emsip_adapter.sv(104) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[916..914]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[912..910]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[812..810]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[808..806]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[708..706]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[704..702]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[604..602]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[600..598]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[500..498]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[496..494]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[396..394]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[392..390]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[292..290]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[288..286]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[188..186]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[184..182]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[84..82]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_in[80..78]" at sv_xcvr_emsip_adapter.sv(119) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[108]" at sv_xcvr_emsip_adapter.sv(120) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[95]" at sv_xcvr_emsip_adapter.sv(120) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[82]" at sv_xcvr_emsip_adapter.sv(120) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[69]" at sv_xcvr_emsip_adapter.sv(120) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[56]" at sv_xcvr_emsip_adapter.sv(120) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[43]" at sv_xcvr_emsip_adapter.sv(120) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[30]" at sv_xcvr_emsip_adapter.sv(120) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[17]" at sv_xcvr_emsip_adapter.sv(120) has no driver +Sat 21:52: INFO : Warning (10034): Output port "out_pcspldif_emsip_tx_special_in[4]" at sv_xcvr_emsip_adapter.sv(120) has no driver +Sat 21:52: INFO : Info (12128): Elaborating entity "sv_xcvr_plls" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_plls:sv_xcvr_tx_plls_inst" +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_xcvr_plls.sv(131): object "atx_avmm_blockselect" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_xcvr_plls.sv(132): object "atx_avmm_readdata" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_xcvr_plls.sv(133): object "atx_mux_avmm_blockselect" assigned a value but never read +Sat 21:52: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_xcvr_plls.sv(134): object "atx_mux_avmm_readdata" assigned a value but never read +Sat 21:52: INFO : Info (12128): Elaborating entity "sv_xcvr_native" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native" +Sat 21:52: INFO : Info (12128): Elaborating entity "sv_pma" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma" +Sat 21:52: INFO : Info (12128): Elaborating entity "sv_rx_pma" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_rx_pma:rx_pma.sv_rx_pma_inst" +Sat 21:52: INFO : Warning (10034): Output port "clk33pcs[4]" at sv_rx_pma.sv(90) has no driver +Sat 21:52: INFO : Warning (10034): Output port "rdlpbkp[4]" at sv_rx_pma.sv(109) has no driver +Sat 21:52: INFO : Warning (10034): Output port "rdlpbkn[4]" at sv_rx_pma.sv(110) has no driver +Sat 21:52: INFO : Warning (10034): Output port "refclk_to_cdr[4]" at sv_rx_pma.sv(112) has no driver +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_tx_pma" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_tx_pma_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[0].sv_tx_pma_ch_inst" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_tx_pma_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pma:inst_sv_pma|sv_tx_pma:tx_pma.sv_tx_pma_inst|sv_tx_pma_ch:tx_pma_insts[4].sv_tx_pma_ch_inst" +Sat 21:53: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_tx_pma_ch.sv(178): object "w_txelecidl" assigned a value but never read +Sat 21:53: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_tx_pma_ch.sv(179): object "w_rxdetclk" assigned a value but never read +Sat 21:53: INFO : Warning (10036): Verilog HDL or VHDL warning at sv_tx_pma_ch.sv(180): object "w_txdetrx" assigned a value but never read +Sat 21:53: INFO : Warning (10034): Output port "avmmreaddata_buf" at sv_tx_pma_ch.sv(131) has no driver +Sat 21:53: INFO : Warning (10034): Output port "dataout" at sv_tx_pma_ch.sv(87) has no driver +Sat 21:53: INFO : Warning (10034): Output port "rxdetectvalid" at sv_tx_pma_ch.sv(88) has no driver +Sat 21:53: INFO : Warning (10034): Output port "rxfound" at sv_tx_pma_ch.sv(89) has no driver +Sat 21:53: INFO : Warning (10034): Output port "blockselect_buf" at sv_tx_pma_ch.sv(134) has no driver +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_pcs" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_pipe_gen1_2_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_pipe_gen1_2_rbc:inst_sv_hssi_pipe_gen1_2" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_common_pcs_pma_interface_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_common_pcs_pma_interface_rbc:inst_sv_hssi_common_pcs_pma_interface" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_pipe_gen3_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_pipe_gen3_rbc:inst_sv_hssi_pipe_gen3" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_tx_pcs_pma_interface_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_tx_pcs_pma_interface_rbc:inst_sv_hssi_tx_pcs_pma_interface" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_tx_pld_pcs_interface_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_tx_pld_pcs_interface_rbc:inst_sv_hssi_tx_pld_pcs_interface" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_common_pld_pcs_interface_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_common_pld_pcs_interface_rbc:inst_sv_hssi_common_pld_pcs_interface" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_rx_pld_pcs_interface_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_rx_pld_pcs_interface_rbc:inst_sv_hssi_rx_pld_pcs_interface" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_rx_pcs_pma_interface_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[0].inst_sv_pcs_ch|sv_hssi_rx_pcs_pma_interface_rbc:inst_sv_hssi_rx_pcs_pma_interface" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[1].inst_sv_pcs_ch" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[1].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[1].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[2].inst_sv_pcs_ch" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[2].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[2].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[3].inst_sv_pcs_ch" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[3].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[3].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[4].inst_sv_pcs_ch" +Sat 21:53: INFO : Info (12128): Elaborating entity "sv_hssi_pipe_gen1_2_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[4].inst_sv_pcs_ch|sv_hssi_pipe_gen1_2_rbc:inst_sv_hssi_pipe_gen1_2" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_hssi_pipe_gen3_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[4].inst_sv_pcs_ch|sv_hssi_pipe_gen3_rbc:inst_sv_hssi_pipe_gen3" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[4].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[4].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[5].inst_sv_pcs_ch" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_hssi_pipe_gen1_2_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[5].inst_sv_pcs_ch|sv_hssi_pipe_gen1_2_rbc:inst_sv_hssi_pipe_gen1_2" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_hssi_pipe_gen3_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[5].inst_sv_pcs_ch|sv_hssi_pipe_gen3_rbc:inst_sv_hssi_pipe_gen3" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[5].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[5].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[6].inst_sv_pcs_ch" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[6].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[6].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[7].inst_sv_pcs_ch" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[7].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[7].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_pcs_ch" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[8].inst_sv_pcs_ch" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_hssi_8g_rx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[8].inst_sv_pcs_ch|sv_hssi_8g_rx_pcs_rbc:inst_sv_hssi_8g_rx_pcs" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_hssi_8g_tx_pcs_rbc" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_pcs:inst_sv_pcs|sv_pcs_ch:ch[8].inst_sv_pcs_ch|sv_hssi_8g_tx_pcs_rbc:inst_sv_hssi_8g_tx_pcs" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_xcvr_avmm" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_xcvr_avmm:inst_sv_xcvr_avmm" +Sat 21:54: INFO : Warning (10030): Net "rx_ltrltd_ovr[4]" at sv_xcvr_avmm.sv(179) has no driver or initial value, using a default initial value '0' +Sat 21:54: INFO : Warning (10030): Net "rx_ltr_val[4]" at sv_xcvr_avmm.sv(180) has no driver or initial value, using a default initial value '0' +Sat 21:54: INFO : Warning (10030): Net "rx_ltd_val[4]" at sv_xcvr_avmm.sv(181) has no driver or initial value, using a default initial value '0' +Sat 21:54: INFO : Warning (10034): Output port "pma_eyemonitor[24..20]" at sv_xcvr_avmm.sv(81) has no driver +Sat 21:54: INFO : Warning (10034): Output port "pma_hardoccalen[4]" at sv_xcvr_avmm.sv(82) has no driver +Sat 21:54: INFO : Warning (10034): Output port "pma_adcecapture[4]" at sv_xcvr_avmm.sv(83) has no driver +Sat 21:54: INFO : Warning (10034): Output port "pma_adcestandby[4]" at sv_xcvr_avmm.sv(84) has no driver +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_reconfig_bundle_to_xcvr" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_xcvr_avmm:inst_sv_xcvr_avmm|sv_reconfig_bundle_to_xcvr:avmm_interface_insts[0].sv_reconfig_bundle_to_xcvr_inst" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_xcvr_avmm_csr" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_xcvr_avmm:inst_sv_xcvr_avmm|sv_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_resync" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|sv_xcvr_pipe_native:g_xcvr.sv_xcvr_pipe_native|sv_xcvr_native:inst_sv_xcvr_native|sv_xcvr_avmm:inst_sv_xcvr_avmm|sv_xcvr_avmm_csr:avmm_interface_insts[0].sv_xcvr_avmm_csr_inst|alt_xcvr_resync:gen_status_reg_tx.alt_xcvr_resync_inst" +Sat 21:54: INFO : Info (12128): Elaborating entity "MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1:pcie_altclkctrl_i" +Sat 21:54: INFO : Info (12128): Elaborating entity "MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1_altclkctrl_blh" for hierarchy "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1:pcie_altclkctrl_i|MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1_altclkctrl_blh:MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1_altclkctrl_blh_component" +Sat 21:54: INFO : Warning (10036): Verilog HDL or VHDL warning at MWAltClkCtrl_quartusv13_1_0_GCLK_numclk_1.vhd(58): object "clkselect" assigned a value but never read +Sat 21:54: INFO : Info (12128): Elaborating entity "TransceiverReconfig" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i" +Sat 21:54: INFO : Info (12128): Elaborating entity "pcie_xcvr_reconfig_SV" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1" +Sat 21:54: INFO : Warning (10230): Verilog HDL assignment warning at pcie_xcvr_reconfig_SV.v(66): truncated value with size 32 to match size of target (8) +Sat 21:54: INFO : Info (12128): Elaborating entity "pcie_reconfig_SV" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst" +Sat 21:54: INFO : Warning (10036): Verilog HDL or VHDL warning at alt_xcvr_reconfig.sv(200): object "done" assigned a value but never read +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_resync" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_resync:inst_reconfig_reset_sync" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_arbiter" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_arbiter:arbiter" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_direct" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_direct:direct.sc_direct" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_arbiter_acq" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_direct:direct.sc_direct|alt_arbiter_acq:mutex_inst" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_soc" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_reconfig_cpu" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench:the_alt_xcvr_reconfig_cpu_reconfig_cpu_test_bench" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a" +Sat 21:54: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a|altsyncram:the_altsyncram" +Sat 21:54: INFO : Info (12130): Elaborated megafunction instantiation "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a|altsyncram:the_altsyncram" +Sat 21:54: INFO : Info (12133): Instantiated megafunction "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a|altsyncram:the_altsyncram" with the following parameter: +Sat 21:54: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" +Sat 21:54: INFO : Info (12134): Parameter "init_file" = "alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_a.mif" +Sat 21:54: INFO : Info (12134): Parameter "maximum_depth" = "0" +Sat 21:54: INFO : Info (12134): Parameter "numwords_a" = "32" +Sat 21:54: INFO : Info (12134): Parameter "numwords_b" = "32" +Sat 21:54: INFO : Info (12134): Parameter "operation_mode" = "DUAL_PORT" +Sat 21:54: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" +Sat 21:54: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" +Sat 21:54: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" +Sat 21:54: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" +Sat 21:54: INFO : Info (12134): Parameter "width_a" = "32" +Sat 21:54: INFO : Info (12134): Parameter "width_b" = "32" +Sat 21:54: INFO : Info (12134): Parameter "widthad_a" = "5" +Sat 21:54: INFO : Info (12134): Parameter "widthad_b" = "5" +Sat 21:54: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_b5t1.tdf +Sat 21:54: INFO : Info (12023): Found entity 1: altsyncram_b5t1 +Sat 21:54: INFO : Info (12128): Elaborating entity "altsyncram_b5t1" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_b5t1:auto_generated" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b" +Sat 21:54: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b|altsyncram:the_altsyncram" +Sat 21:54: INFO : Info (12130): Elaborated megafunction instantiation "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b|altsyncram:the_altsyncram" +Sat 21:54: INFO : Info (12133): Instantiated megafunction "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b|altsyncram:the_altsyncram" with the following parameter: +Sat 21:54: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" +Sat 21:54: INFO : Info (12134): Parameter "init_file" = "alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_b.mif" +Sat 21:54: INFO : Info (12134): Parameter "maximum_depth" = "0" +Sat 21:54: INFO : Info (12134): Parameter "numwords_a" = "32" +Sat 21:54: INFO : Info (12134): Parameter "numwords_b" = "32" +Sat 21:54: INFO : Info (12134): Parameter "operation_mode" = "DUAL_PORT" +Sat 21:54: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" +Sat 21:54: INFO : Info (12134): Parameter "ram_block_type" = "AUTO" +Sat 21:54: INFO : Info (12134): Parameter "rdcontrol_reg_b" = "CLOCK0" +Sat 21:54: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "DONT_CARE" +Sat 21:54: INFO : Info (12134): Parameter "width_a" = "32" +Sat 21:54: INFO : Info (12134): Parameter "width_b" = "32" +Sat 21:54: INFO : Info (12134): Parameter "widthad_a" = "5" +Sat 21:54: INFO : Info (12134): Parameter "widthad_b" = "5" +Sat 21:54: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_c5t1.tdf +Sat 21:54: INFO : Info (12023): Found entity 1: altsyncram_c5t1 +Sat 21:54: INFO : Info (12128): Elaborating entity "altsyncram_c5t1" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_reconfig_cpu:reconfig_cpu|alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b_module:alt_xcvr_reconfig_cpu_reconfig_cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_c5t1:auto_generated" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:reconfig_cpu_data_master_translator" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_merlin_master_translator" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_translator:reconfig_cpu_instruction_master_translator" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:reconfig_mem_mem_translator" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_merlin_slave_translator" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:reconfig_ctrl_ctrl_translator" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:reconfig_cpu_data_master_translator_avalon_universal_master_0_agent" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_merlin_master_agent" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_master_agent:reconfig_cpu_instruction_master_translator_avalon_universal_master_0_agent" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_merlin_slave_agent" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:reconfig_mem_mem_translator_avalon_universal_slave_0_agent" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_merlin_burst_uncompressor" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:reconfig_mem_mem_translator_avalon_universal_slave_0_agent|altera_merlin_burst_uncompressor:uncompressor" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_avalon_sc_fifo" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:reconfig_mem_mem_translator_avalon_universal_slave_0_agent_rsp_fifo" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router:addr_router" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_default_decode" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router:addr_router|alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_default_decode:the_default_decode" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001:addr_router_001" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001_default_decode" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001:addr_router_001|alt_xcvr_reconfig_cpu_mm_interconnect_0_addr_router_001_default_decode:the_default_decode" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router:id_router" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_default_decode" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router:id_router|alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_default_decode:the_default_decode" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001:id_router_001" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001_default_decode" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001:id_router_001|alt_xcvr_reconfig_cpu_mm_interconnect_0_id_router_001_default_decode:the_default_decode" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux:cmd_xbar_demux" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux_001" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_demux_001:cmd_xbar_demux_001" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux:cmd_xbar_mux" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_merlin_arb_adder" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux:cmd_xbar_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux_001" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_cmd_xbar_mux_001:cmd_xbar_mux_001" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_merlin_arbitrator" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux:rsp_xbar_mux|altera_merlin_arbitrator:arb" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux_001" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_mm_interconnect_0:mm_interconnect_0|alt_xcvr_reconfig_cpu_mm_interconnect_0_rsp_xbar_mux_001:rsp_xbar_mux_001" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_irq_mapper" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|alt_xcvr_reconfig_cpu_irq_mapper:irq_mapper" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|altera_reset_controller:rst_controller" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu:alt_xcvr_reconfig_cpu_inst|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cpu_ram" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu_ram:alt_xcvr_reconfig_cpu_ram_inst" +Sat 21:54: INFO : Info (12128): Elaborating entity "altsyncram" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu_ram:alt_xcvr_reconfig_cpu_ram_inst|altsyncram:altsyncram_component" +Sat 21:54: INFO : Info (12130): Elaborated megafunction instantiation "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu_ram:alt_xcvr_reconfig_cpu_ram_inst|altsyncram:altsyncram_component" +Sat 21:54: INFO : Info (12133): Instantiated megafunction "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu_ram:alt_xcvr_reconfig_cpu_ram_inst|altsyncram:altsyncram_component" with the following parameter: +Sat 21:54: INFO : Info (12134): Parameter "address_reg_b" = "CLOCK0" +Sat 21:54: INFO : Info (12134): Parameter "byteena_reg_b" = "CLOCK0" +Sat 21:54: INFO : Info (12134): Parameter "byte_size" = "8" +Sat 21:54: INFO : Info (12134): Parameter "clock_enable_input_a" = "NORMAL" +Sat 21:54: INFO : Info (12134): Parameter "clock_enable_input_b" = "NORMAL" +Sat 21:54: INFO : Info (12134): Parameter "clock_enable_output_a" = "NORMAL" +Sat 21:54: INFO : Info (12134): Parameter "clock_enable_output_b" = "NORMAL" +Sat 21:54: INFO : Info (12134): Parameter "indata_reg_b" = "CLOCK0" +Sat 21:54: INFO : Info (12134): Parameter "init_file" = "alt_xcvr_reconfig_cpu_ram.hex" +Sat 21:54: INFO : Info (12134): Parameter "intended_device_family" = "Stratix V" +Sat 21:54: INFO : Info (12134): Parameter "lpm_type" = "altsyncram" +Sat 21:54: INFO : Info (12134): Parameter "numwords_a" = "1024" +Sat 21:54: INFO : Info (12134): Parameter "numwords_b" = "1024" +Sat 21:54: INFO : Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT" +Sat 21:54: INFO : Info (12134): Parameter "outdata_aclr_a" = "NONE" +Sat 21:54: INFO : Info (12134): Parameter "outdata_aclr_b" = "NONE" +Sat 21:54: INFO : Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED" +Sat 21:54: INFO : Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED" +Sat 21:54: INFO : Info (12134): Parameter "power_up_uninitialized" = "FALSE" +Sat 21:54: INFO : Info (12134): Parameter "read_during_write_mode_mixed_ports" = "OLD_DATA" +Sat 21:54: INFO : Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ" +Sat 21:54: INFO : Info (12134): Parameter "read_during_write_mode_port_b" = "NEW_DATA_NO_NBE_READ" +Sat 21:54: INFO : Info (12134): Parameter "widthad_a" = "10" +Sat 21:54: INFO : Info (12134): Parameter "widthad_b" = "10" +Sat 21:54: INFO : Info (12134): Parameter "width_a" = "32" +Sat 21:54: INFO : Info (12134): Parameter "width_b" = "32" +Sat 21:54: INFO : Info (12134): Parameter "width_byteena_a" = "4" +Sat 21:54: INFO : Info (12134): Parameter "width_byteena_b" = "4" +Sat 21:54: INFO : Info (12134): Parameter "wrcontrol_wraddress_reg_b" = "CLOCK0" +Sat 21:54: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ru53.tdf +Sat 21:54: INFO : Info (12023): Found entity 1: altsyncram_ru53 +Sat 21:54: INFO : Info (12128): Elaborating entity "altsyncram_ru53" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|alt_xcvr_reconfig_cpu_ram:alt_xcvr_reconfig_cpu_ram_inst|altsyncram:altsyncram_component|altsyncram_ru53:auto_generated" +Sat 21:54: INFO : Warning (113015): Width of data items in "alt_xcvr_reconfig_cpu_ram.hex" is greater than the memory width. Wrapping data items to subsequent addresses. Found 128 warnings, reporting 10 +Sat 21:54: INFO : Warning (113009): Data at line (2) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. +Sat 21:54: INFO : Warning (113009): Data at line (3) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. +Sat 21:54: INFO : Warning (113009): Data at line (4) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. +Sat 21:54: INFO : Warning (113009): Data at line (5) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. +Sat 21:54: INFO : Warning (113009): Data at line (6) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. +Sat 21:54: INFO : Warning (113009): Data at line (7) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. +Sat 21:54: INFO : Warning (113009): Data at line (8) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. +Sat 21:54: INFO : Warning (113009): Data at line (9) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. +Sat 21:54: INFO : Warning (113009): Data at line (10) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. +Sat 21:54: INFO : Warning (113009): Data at line (11) of memory initialization file "alt_xcvr_reconfig_cpu_ram.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses. +Sat 21:54: INFO : Info (12128): Elaborating entity "altera_wait_generate" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_soc:soc.sc_soc|altera_wait_generate:altera_wait_generate_inst" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_cal_seq" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_cal_seq:cal_seq" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_reconfig_basic" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_xcvr_reconfig_basic" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_xrbasic_lif" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_xrbasic_lif_csr" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|sv_xrbasic_lif_csr:lif_csr" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_xrbasic_l2p_rom" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|sv_xrbasic_lif_csr:lif_csr|sv_xrbasic_l2p_rom:l2pch" +Sat 21:54: INFO : Warning (10030): Net "rom_l2p_ch.data_a" at sv_xrbasic_l2p_rom.sv(59) has no driver or initial value, using a default initial value '0' +Sat 21:54: INFO : Warning (10030): Net "rom_l2p_ch.waddr_a" at sv_xrbasic_l2p_rom.sv(59) has no driver or initial value, using a default initial value '0' +Sat 21:54: INFO : Warning (10030): Net "rom_l2p_ch.we_a" at sv_xrbasic_l2p_rom.sv(59) has no driver or initial value, using a default initial value '0' +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_xrbasic_l2p_addr" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|sv_xrbasic_lif_csr:lif_csr|sv_xrbasic_l2p_addr:l2paddr" +Sat 21:54: INFO : Info (12128): Elaborating entity "csr_mux" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|csr_mux:pif_tbus_mux" +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_xcvr_arbiter" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|alt_xcvr_arbiter:pif[0].pif_arb" +Sat 21:54: INFO : Info (12128): Elaborating entity "sv_reconfig_bundle_to_basic" for hierarchy "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_reconfig_bundle_to_basic:bundle" +Sat 21:54: INFO : Info (12128): Elaborating entity "MAX4CPLDInterface" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level" +Sat 21:54: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4CPLDInterface.vhdl(328): object "cpld_io_ext_inst_maxring_a_top_sb_fb" assigned a value but never read +Sat 21:54: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4CPLDInterface.vhdl(329): object "cpld_io_ext_inst_maxring_a_bottom_sb_fb" assigned a value but never read +Sat 21:54: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4CPLDInterface.vhdl(330): object "cpld_io_ext_inst_maxring_b_modtx_sb_fb" assigned a value but never read +Sat 21:54: INFO : Warning (10036): Verilog HDL or VHDL warning at MAX4CPLDInterface.vhdl(331): object "cpld_io_ext_inst_maxring_b_modrx_sb_fb" assigned a value but never read +Sat 21:54: INFO : Info (12128): Elaborating entity "max4_cpld_ioexpand" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_ioexpand:cpld_io_ext_inst" +Sat 21:54: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_TOP_ALERT" at max4_cpld_ioexpand.vhd(59) +Sat 21:54: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_TOP_SDA_fb" at max4_cpld_ioexpand.vhd(61) +Sat 21:54: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_TOP_SCL_fb" at max4_cpld_ioexpand.vhd(63) +Sat 21:54: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_TOP_modprsl" at max4_cpld_ioexpand.vhd(64) +Sat 21:54: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_MID_ALERT" at max4_cpld_ioexpand.vhd(69) +Sat 21:54: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_MID_SDA_fb" at max4_cpld_ioexpand.vhd(71) +Sat 21:54: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_MID_SCL_fb" at max4_cpld_ioexpand.vhd(73) +Sat 21:54: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_MID_modprsl" at max4_cpld_ioexpand.vhd(74) +Sat 21:54: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_BOT_ALERT" at max4_cpld_ioexpand.vhd(79) +Sat 21:54: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_BOT_SDA_fb" at max4_cpld_ioexpand.vhd(81) +Sat 21:54: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_BOT_SCL_fb" at max4_cpld_ioexpand.vhd(83) +Sat 21:54: INFO : Warning (10873): Using initial value X (don't care) for net "QSFP_BOT_modprsl" at max4_cpld_ioexpand.vhd(84) +Sat 21:54: INFO : Info (12128): Elaborating entity "MAXEvents" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|MAXEvents:max_events" +Sat 21:54: INFO : Info (12128): Elaborating entity "max_events" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|MAXEvents:max_events|max_events:inst_ln89_maxevents" +Sat 21:54: INFO : Info (12128): Elaborating entity "max4_cpld_flash_if" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst" +Sat 21:54: INFO : Warning (272007): Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 +Sat 21:54: INFO : Info (12128): Elaborating entity "dcfifo_mixed_widths" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo" +Sat 21:54: INFO : Info (12130): Elaborated megafunction instantiation "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo" +Sat 21:54: INFO : Info (12133): Instantiated megafunction "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo" with the following parameter: +Sat 21:54: INFO : Info (12134): Parameter "add_ram_output_register" = "OFF" +Sat 21:54: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" +Sat 21:54: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" +Sat 21:54: INFO : Info (12134): Parameter "delay_rdusedw" = "1" +Sat 21:54: INFO : Info (12134): Parameter "delay_wrusedw" = "1" +Sat 21:54: INFO : Info (12134): Parameter "intended_device_family" = "unused" +Sat 21:54: INFO : Info (12134): Parameter "lpm_numwords" = "512" +Sat 21:54: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:54: INFO : Info (12134): Parameter "lpm_width" = "64" +Sat 21:54: INFO : Info (12134): Parameter "lpm_width_r" = "64" +Sat 21:54: INFO : Info (12134): Parameter "lpm_widthu" = "9" +Sat 21:54: INFO : Info (12134): Parameter "lpm_widthu_r" = "9" +Sat 21:54: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:54: INFO : Info (12134): Parameter "rdsync_delaypipe" = "0" +Sat 21:54: INFO : Info (12134): Parameter "read_aclr_synch" = "OFF" +Sat 21:54: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:54: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:54: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" +Sat 21:54: INFO : Info (12134): Parameter "wrsync_delaypipe" = "0" +Sat 21:54: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" +Sat 21:54: INFO : Info (12134): Parameter "lpm_type" = "dcfifo_mixed_widths" +Sat 21:54: INFO : Warning (287001): Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 +Sat 21:54: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_hj62.tdf +Sat 21:54: INFO : Info (12023): Found entity 1: dcfifo_hj62 +Sat 21:54: INFO : Info (12128): Elaborating entity "dcfifo_hj62" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated" +Sat 21:54: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_c8e1.tdf +Sat 21:54: INFO : Info (12023): Found entity 1: altsyncram_c8e1 +Sat 21:54: INFO : Info (12128): Elaborating entity "altsyncram_c8e1" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram" +Sat 21:54: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_6md.tdf +Sat 21:54: INFO : Info (12023): Found entity 1: alt_synch_pipe_6md +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_synch_pipe_6md" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|alt_synch_pipe_6md:rs_dgwp" +Sat 21:54: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_5f9.tdf +Sat 21:54: INFO : Info (12023): Found entity 1: dffpipe_5f9 +Sat 21:54: INFO : Info (12128): Elaborating entity "dffpipe_5f9" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|alt_synch_pipe_6md:rs_dgwp|dffpipe_5f9:dffpipe6" +Sat 21:54: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_7md.tdf +Sat 21:54: INFO : Info (12023): Found entity 1: alt_synch_pipe_7md +Sat 21:54: INFO : Info (12128): Elaborating entity "alt_synch_pipe_7md" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|alt_synch_pipe_7md:ws_dgrp" +Sat 21:54: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_6f9.tdf +Sat 21:54: INFO : Info (12023): Found entity 1: dffpipe_6f9 +Sat 21:54: INFO : Info (12128): Elaborating entity "dffpipe_6f9" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|alt_synch_pipe_7md:ws_dgrp|dffpipe_6f9:dffpipe9" +Sat 21:54: INFO : Warning (272007): Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 +Sat 21:54: INFO : Info (12128): Elaborating entity "dcfifo_mixed_widths" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo" +Sat 21:54: INFO : Info (12130): Elaborated megafunction instantiation "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo" +Sat 21:54: INFO : Info (12133): Instantiated megafunction "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo" with the following parameter: +Sat 21:54: INFO : Info (12134): Parameter "add_ram_output_register" = "OFF" +Sat 21:54: INFO : Info (12134): Parameter "add_usedw_msb_bit" = "OFF" +Sat 21:54: INFO : Info (12134): Parameter "clocks_are_synchronized" = "FALSE" +Sat 21:54: INFO : Info (12134): Parameter "delay_rdusedw" = "1" +Sat 21:54: INFO : Info (12134): Parameter "delay_wrusedw" = "1" +Sat 21:54: INFO : Info (12134): Parameter "intended_device_family" = "unused" +Sat 21:54: INFO : Info (12134): Parameter "lpm_numwords" = "512" +Sat 21:54: INFO : Info (12134): Parameter "lpm_showahead" = "OFF" +Sat 21:54: INFO : Info (12134): Parameter "lpm_width" = "64" +Sat 21:54: INFO : Info (12134): Parameter "lpm_width_r" = "64" +Sat 21:54: INFO : Info (12134): Parameter "lpm_widthu" = "9" +Sat 21:54: INFO : Info (12134): Parameter "lpm_widthu_r" = "9" +Sat 21:54: INFO : Info (12134): Parameter "overflow_checking" = "ON" +Sat 21:54: INFO : Info (12134): Parameter "rdsync_delaypipe" = "0" +Sat 21:54: INFO : Info (12134): Parameter "read_aclr_synch" = "OFF" +Sat 21:54: INFO : Info (12134): Parameter "underflow_checking" = "ON" +Sat 21:54: INFO : Info (12134): Parameter "use_eab" = "ON" +Sat 21:54: INFO : Info (12134): Parameter "write_aclr_synch" = "OFF" +Sat 21:54: INFO : Info (12134): Parameter "wrsync_delaypipe" = "0" +Sat 21:54: INFO : Info (12134): Parameter "lpm_hint" = "UNUSED" +Sat 21:54: INFO : Info (12134): Parameter "lpm_type" = "dcfifo_mixed_widths" +Sat 21:54: INFO : Warning (287001): Assertion warning: Number of metastability protection registers is not specified. Based on the parameter value CLOCKS_ARE_SYNCHRONIZED=FALSE, the synchronization register chain length between read and write clock domains will be 2 +Sat 21:54: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dcfifo_0q52.tdf +Sat 21:54: INFO : Info (12023): Found entity 1: dcfifo_0q52 +Sat 21:54: INFO : Info (12128): Elaborating entity "dcfifo_0q52" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo|dcfifo_0q52:auto_generated" +Sat 21:54: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_8md.tdf +Sat 21:54: INFO : Info (12023): Found entity 1: alt_synch_pipe_8md +Sat 21:55: INFO : Info (12128): Elaborating entity "alt_synch_pipe_8md" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo|dcfifo_0q52:auto_generated|alt_synch_pipe_8md:rs_dgwp" +Sat 21:55: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_7f9.tdf +Sat 21:55: INFO : Info (12023): Found entity 1: dffpipe_7f9 +Sat 21:55: INFO : Info (12128): Elaborating entity "dffpipe_7f9" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo|dcfifo_0q52:auto_generated|alt_synch_pipe_8md:rs_dgwp|dffpipe_7f9:dffpipe5" +Sat 21:55: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_9md.tdf +Sat 21:55: INFO : Info (12023): Found entity 1: alt_synch_pipe_9md +Sat 21:55: INFO : Info (12128): Elaborating entity "alt_synch_pipe_9md" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo|dcfifo_0q52:auto_generated|alt_synch_pipe_9md:ws_dgrp" +Sat 21:55: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/dffpipe_8f9.tdf +Sat 21:55: INFO : Info (12023): Found entity 1: dffpipe_8f9 +Sat 21:55: INFO : Info (12128): Elaborating entity "dffpipe_8f9" for hierarchy "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:rx_cmd_fifo|dcfifo_0q52:auto_generated|alt_synch_pipe_9md:ws_dgrp|dffpipe_8f9:dffpipe8" +Sat 21:55: INFO : Warning (12030): Port "rx_cal_busy" on the entity instantiation of "inst_sv_xcvr_native" is connected to a signal of width 8. The formal width of the signal in the module is 9. The extra bits will be left dangling without any fan-out logic. +Sat 21:55: INFO : Warning (12030): Port "tx_cal_busy" on the entity instantiation of "inst_sv_xcvr_native" is connected to a signal of width 8. The formal width of the signal in the module is 9. The extra bits will be left dangling without any fan-out logic. +Sat 21:55: INFO : Warning (12030): Port "rx_signaldetect" on the entity instantiation of "sv_xcvr_emsip_adapter_inst" is connected to a signal of width 9. The formal width of the signal in the module is 8. The extra bits will be left dangling without any fan-out logic. +Sat 21:55: INFO : Info (12206): 2 design partitions require synthesis +Sat 21:55: INFO : Info (12210): Partition "Top" requires synthesis because its netlist type is Source File +Sat 21:55: INFO : Info (12210): Partition "MAX4FPGATop:MAX4MaiaFabricTop_i" requires synthesis because its netlist type is Source File +Sat 21:55: INFO : Info (12209): No design partitions will skip synthesis in the current incremental compilation +Sat 21:55: INFO : Warning (14284): Synthesized away the following node(s): +Sat 21:55: INFO : Warning (14285): Synthesized away the following LCELL buffer node(s): +Sat 21:55: INFO : Warning (14320): Synthesized away node "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|phase_done" +Sat 21:55: INFO : Warning (14320): Synthesized away node "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dprio_read" +Sat 21:55: INFO : Warning (14285): Synthesized away the following RAM node(s): +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[16]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[17]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[18]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[19]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[20]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[21]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[22]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[23]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[24]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[25]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[26]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[27]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[28]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[29]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[30]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[31]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[58]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[59]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[60]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4CPLDInterface:max4_cpld_top_level|max4_cpld_flash_if:cpld_flash_ext_inst|dcfifo_mixed_widths:tx_cmd_fifo|dcfifo_hj62:auto_generated|altsyncram_c8e1:fifo_ram|q_b[61]" +Sat 21:55: INFO : Warning (14284): Synthesized away the following node(s): +Sat 21:55: INFO : Warning (14285): Synthesized away the following RAM node(s): +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[34]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[35]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[36]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[37]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[38]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[39]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[40]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[41]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[42]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[43]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[44]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[45]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[46]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[47]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[48]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[49]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[50]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[51]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[52]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[53]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[54]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[55]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[56]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[57]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[58]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[59]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[60]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[61]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[62]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|StreamFifo_altera_128_64_128_pushin_sl1_pushout_singleclock:ftb_ARChange_MappedElementsSwitchPCIeEA|AlteraFifoEntity_128_128_64_dualclock_aclr_wrusedw_pfv126:inst_ln70_alterafifo|dcfifo_mixed_widths:inst_ln56_mwfifo|dcfifo_ip52:auto_generated|altsyncram_q9e1:fifo_ram|q_b[63]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|dpram_emb1:FIFOram|altsyncram_8ou1:altsyncram1|q_b[11]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|compl_fifo:cfifo|scfifo:wrapped_scfifo|scfifo_09e1:auto_generated|a_dpfifo_gsb1:dpfifo|dpram_emb1:FIFOram|altsyncram_8ou1:altsyncram1|q_b[12]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[2]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[3]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[4]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[5]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[6]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[7]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[8]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[9]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[10]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[11]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[12]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[13]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[14]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[15]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[16]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[17]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[18]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[19]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[20]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[21]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[22]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[23]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[24]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[25]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[26]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[27]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[28]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[29]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[30]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[31]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[2]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[3]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[4]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[5]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[6]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[7]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[8]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[9]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[10]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[11]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[12]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[13]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[14]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[15]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[16]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[17]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[18]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[19]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[20]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[21]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[22]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[23]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[24]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[25]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[26]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[27]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[28]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[29]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[30]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost2|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[31]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[0]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[1]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[2]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[3]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[4]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[5]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[6]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamToHost:PCIeSlaveStreamToHost0|pcie_slave_streaming_sth_ring:stream_ring|sth_compl_fifo_debug:\g_dbg:cfifo|AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of:wrapped_AlteraFifoEntity_60_16_60_aclr_afv14_fwft_uf_of|scfifo:inst_ln38_mwfifo|scfifo_36e1:auto_generated|a_dpfifo_gpb1:dpfifo|altsyncram_92j1:FIFOram|q_b[7]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[6]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[7]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[8]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[9]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[10]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[11]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[12]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[13]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[14]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[15]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[16]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[17]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[18]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[19]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[20]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[21]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[22]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[23]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[24]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[25]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[26]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[27]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[28]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[29]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[30]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:3:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[31]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[6]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[7]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[8]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[9]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[10]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[11]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[12]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[13]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[14]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[15]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[16]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[17]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[18]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[19]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[20]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[21]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[22]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[23]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[24]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[25]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[26]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[27]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[28]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[29]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[30]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:2:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[31]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[6]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[7]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[8]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[9]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[10]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[11]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[12]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[13]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[14]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[15]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[16]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[17]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[18]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[19]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[20]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[21]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[22]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[23]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[24]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[25]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[26]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[27]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[28]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[29]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[30]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:1:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[31]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[6]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[7]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[8]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[9]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[10]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[11]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[12]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[13]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[14]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[15]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[16]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[17]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[18]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[19]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[20]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[21]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[22]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[23]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[24]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[25]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[26]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[27]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[28]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[29]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[30]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|PCIeSlaveStreamFromHost:PCIeSlaveStreamFromHost1|pcie_slave_streaming_sfh_ring:stream_ring|rg_buffer_sfh:\gen_word_buffers:0:buf_gen|AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg:wrapped_AlteraBlockMem_RAM_TWO_PORT_32x512_RAM_TWO_PORT_ireg|altsyncram:inst_ln100_mwblockmem|altsyncram_9a34:auto_generated|q_b[31]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[0]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[1]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[72]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[82]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[83]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[84]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[85]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[86]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[87]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[88]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[89]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[90]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[91]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[92]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[93]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[94]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[95]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[96]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[97]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[98]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[99]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[100]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[101]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[102]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[103]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[104]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[105]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[106]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[107]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[108]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[109]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[110]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[111]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[112]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[113]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|PCIeStreaming_2_3:dynpcie|RequestEncoder:RequestEncoder_i|AlteraFifoEntity_115_512_115_aclr_fwft:wr_req_buffer_i|scfifo:inst_ln38_mwfifo|scfifo_84b1:auto_generated|a_dpfifo_fab1:dpfifo|altsyncram_n8j1:FIFOram|q_b[114]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[0]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[1]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[2]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[3]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[4]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[5]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[6]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[7]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[8]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[9]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[10]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[11]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[12]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[13]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[14]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[15]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[16]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[17]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[18]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[19]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[20]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[21]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[22]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[23]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[24]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_17:Stream_17|StreamFifo_altera_32_32_512_pushin_sl2_pullout_el1_ael2_dualclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_32_512_32_dualclock_aclr_rdusedw_wrusedw_of_uf_pfv477_pev7:inst_ln47_alterafifo|dcfifo:inst_ln38_mwfifo|dcfifo_lg62:auto_generated|altsyncram_28e1:fifo_ram|q_b[25]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[0]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[1]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[2]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[3]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[4]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[5]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[6]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[7]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[8]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[9]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[10]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[11]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[12]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[13]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[14]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[15]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[16]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[17]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[18]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[19]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[20]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[21]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[22]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[23]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[24]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[25]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[32]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[33]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[34]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[35]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[36]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[37]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[38]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[39]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[40]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[41]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[42]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[43]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[44]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[45]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[46]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[47]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[48]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[49]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[50]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[51]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[52]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[53]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[54]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[55]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[56]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[57]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[64]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[65]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[66]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[67]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[68]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[69]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[70]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[71]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[72]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[73]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[74]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[75]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[76]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[77]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[78]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[79]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[80]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[81]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[82]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[83]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[84]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[85]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[86]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[87]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[88]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[89]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[96]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[97]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[98]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[99]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[100]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[101]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[102]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[103]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[104]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[105]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[106]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[107]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[108]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[109]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[110]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[111]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[112]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[113]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[114]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[115]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[116]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[117]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[118]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[119]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[120]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_Stream_15:Stream_15|StreamFifo_altera_128_128_512_pushin_sl2_pullout_el1_singleclock_errflgs:inst_ln31_streamingblock|AlteraFifoEntity_128_512_128_aclr_afv477_of_uf:inst_ln47_alterafifo|scfifo:inst_ln38_mwfifo|scfifo_9ee1:auto_generated|a_dpfifo_pvb1:dpfifo|dpram_4ob1:FIFOram|altsyncram_muu1:altsyncram1|q_b[121]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[0]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[2]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[17]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[18]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[35]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[36]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[37]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[38]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[39]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[40]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[41]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[42]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[43]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[44]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[45]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[46]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[47]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[48]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[49]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[50]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[51]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[52]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[53]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[54]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[55]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[56]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[57]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[58]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[59]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[60]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[61]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[62]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[63]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[64]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[65]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[66]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[67]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[68]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[69]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_STREAM|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[70]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[0]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[12]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[13]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[14]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[15]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[16]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[17]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[18]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[67]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[68]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[69]" +Sat 21:55: INFO : Warning (14320): Synthesized away node "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|MappedMemoriesControllerdomain0_drp_domain0domain1_STREAM_domain1:MappedMemoriesController_i|AlteraFifoEntity_71_512_71_dualclock_aclr:request_fifo_drp|dcfifo:inst_ln38_mwfifo|dcfifo_cu42:auto_generated|altsyncram_88e1:fifo_ram|q_b[70]" +Sat 21:55: INFO : Info (286031): Timing-Driven Synthesis is running on partition "Top" +Sat 21:55: INFO : Warning (14284): Synthesized away the following node(s): +Sat 21:55: INFO : Warning (14285): Synthesized away the following LCELL buffer node(s): +Sat 21:55: INFO : Warning (14320): Synthesized away node "AlteraClockGenerator_250_200_STREAM:STREAM0_clock_gen_i|StratixVClockManager_in250_out_f200p0dc50_f200p180dc50:inst_ln11_clockmanager|altera_pll_reconfig_top:altera_pll_reconfig_i|dyn_phase_shift:dyn_phase_shift_inst|gnd" +Sat 21:55: INFO : Info (19000): Inferred 1 megafunctions from design logic +Sat 21:55: INFO : Info (276029): Inferred altsyncram megafunction from the following design logic: "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|sv_xrbasic_lif_csr:lif_csr|sv_xrbasic_l2p_rom:l2pch|rom_l2p_ch_rtl_0" +Sat 21:55: INFO : Info (286033): Parameter OPERATION_MODE set to BIDIR_DUAL_PORT +Sat 21:55: INFO : Info (286033): Parameter WIDTH_A set to 32 +Sat 21:55: INFO : Info (286033): Parameter WIDTH_B set to 32 +Sat 21:55: INFO : Info (286033): Parameter WIDTHAD_A set to 7 +Sat 21:55: INFO : Info (286033): Parameter WIDTHAD_B set to 7 +Sat 21:55: INFO : Info (286033): Parameter NUMWORDS_A set to 128 +Sat 21:55: INFO : Info (286033): Parameter NUMWORDS_B set to 128 +Sat 21:55: INFO : Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED +Sat 21:55: INFO : Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED +Sat 21:55: INFO : Info (286033): Parameter ADDRESS_REG_B set to CLOCK0 +Sat 21:55: INFO : Info (286033): Parameter INDATA_REG_B set to CLOCK0 +Sat 21:56: INFO : Info (286033): Parameter WRCONTROL_WRADDRESS_REG_B set to CLOCK0 +Sat 21:56: INFO : Info (286033): Parameter INDATA_ACLR_A set to NONE +Sat 21:56: INFO : Info (286033): Parameter WRCONTROL_ACLR_A set to NONE +Sat 21:56: INFO : Info (286033): Parameter ADDRESS_ACLR_A set to NONE +Sat 21:56: INFO : Info (286033): Parameter ADDRESS_ACLR_B set to NONE +Sat 21:56: INFO : Info (286033): Parameter OUTDATA_ACLR_B set to NONE +Sat 21:56: INFO : Info (286033): Parameter RAM_BLOCK_TYPE set to M20K +Sat 21:56: INFO : Info (286033): Parameter INIT_FILE set to db/MAX4MAIAPeripheryTop.ram0_sv_xrbasic_l2p_rom_a2c9d7fe.hdl.mif +Sat 21:56: INFO : Info (12130): Elaborated megafunction instantiation "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|sv_xrbasic_lif_csr:lif_csr|sv_xrbasic_l2p_rom:l2pch|altsyncram:rom_l2p_ch_rtl_0" +Sat 21:56: INFO : Info (12133): Instantiated megafunction "StratixPCIeBase:PCIeBase_i|TransceiverReconfig:pcie_xcvr_reconfig_i|pcie_xcvr_reconfig_SV:inst_ln9_tranceiverreconfigext_v13_1|pcie_reconfig_SV:pcie_reconfig_inst|alt_xcvr_reconfig:pcie_reconfig_sv_inst|alt_xcvr_reconfig_basic:basic|sv_xcvr_reconfig_basic:s5|sv_xrbasic_lif:lif[0].logical_if|sv_xrbasic_lif_csr:lif_csr|sv_xrbasic_l2p_rom:l2pch|altsyncram:rom_l2p_ch_rtl_0" with the following parameter: +Sat 21:56: INFO : Info (12134): Parameter "OPERATION_MODE" = "BIDIR_DUAL_PORT" +Sat 21:56: INFO : Info (12134): Parameter "WIDTH_A" = "32" +Sat 21:56: INFO : Info (12134): Parameter "WIDTH_B" = "32" +Sat 21:56: INFO : Info (12134): Parameter "WIDTHAD_A" = "7" +Sat 21:56: INFO : Info (12134): Parameter "WIDTHAD_B" = "7" +Sat 21:56: INFO : Info (12134): Parameter "NUMWORDS_A" = "128" +Sat 21:56: INFO : Info (12134): Parameter "NUMWORDS_B" = "128" +Sat 21:56: INFO : Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED" +Sat 21:56: INFO : Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED" +Sat 21:56: INFO : Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0" +Sat 21:56: INFO : Info (12134): Parameter "INDATA_REG_B" = "CLOCK0" +Sat 21:56: INFO : Info (12134): Parameter "WRCONTROL_WRADDRESS_REG_B" = "CLOCK0" +Sat 21:56: INFO : Info (12134): Parameter "INDATA_ACLR_A" = "NONE" +Sat 21:56: INFO : Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE" +Sat 21:56: INFO : Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE" +Sat 21:56: INFO : Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE" +Sat 21:56: INFO : Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE" +Sat 21:56: INFO : Info (12134): Parameter "RAM_BLOCK_TYPE" = "M20K" +Sat 21:56: INFO : Info (12134): Parameter "INIT_FILE" = "db/MAX4MAIAPeripheryTop.ram0_sv_xrbasic_l2p_rom_a2c9d7fe.hdl.mif" +Sat 21:56: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_dr72.tdf +Sat 21:56: INFO : Info (12023): Found entity 1: altsyncram_dr72 +Sat 21:56: INFO : Info (19000): Inferred 2 megafunctions from design logic +Sat 21:56: INFO : Info (276034): Inferred altshift_taps megafunction from the following design logic: "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_64_6:node_id304_nodewordlevelshift|reg_ln457_shifter3_rtl_0" +Sat 21:56: INFO : Info (286033): Parameter NUMBER_OF_TAPS set to 1 +Sat 21:56: INFO : Info (286033): Parameter TAP_DISTANCE set to 5 +Sat 21:56: INFO : Info (286033): Parameter WIDTH set to 63 +Sat 21:56: INFO : Info (286033): Parameter POWER_UP_STATE set to DONT_CARE +Sat 21:56: INFO : Info (276034): Inferred altshift_taps megafunction from the following design logic: "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830:inst_ln130_mappedregblock|mapped_register:inst_ln504_mappedregblock|mapped_registers_rtl_0" +Sat 21:56: INFO : Info (286033): Parameter NUMBER_OF_TAPS set to 1 +Sat 21:56: INFO : Info (286033): Parameter TAP_DISTANCE set to 4 +Sat 21:56: INFO : Info (286033): Parameter WIDTH set to 8 +Sat 21:56: INFO : Info (286033): Parameter POWER_UP_STATE set to DONT_CARE +Sat 21:57: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_64_6:node_id304_nodewordlevelshift|altshift_taps:reg_ln457_shifter3_rtl_0" +Sat 21:57: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|Manager_FetchSubTuple:wrapper_entity|Manager_FetchSubTuple_WrapperNodeEntity_FetchSubTupleKernel:FetchSubTupleKernel|FetchSubTupleKernel_streamwrapper:inst_ln31_streamingblock|FetchSubTupleKernel:FetchSubTupleKernel_core|WordLevelShifter_Left_Circular_1_64_6:node_id304_nodewordlevelshift|altshift_taps:reg_ln457_shifter3_rtl_0" with the following parameter: +Sat 21:57: INFO : Info (12134): Parameter "NUMBER_OF_TAPS" = "1" +Sat 21:57: INFO : Info (12134): Parameter "TAP_DISTANCE" = "5" +Sat 21:57: INFO : Info (12134): Parameter "WIDTH" = "63" +Sat 21:57: INFO : Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" +Sat 21:57: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_6u31.tdf +Sat 21:57: INFO : Info (12023): Found entity 1: shift_taps_6u31 +Sat 21:57: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_l9e1.tdf +Sat 21:57: INFO : Info (12023): Found entity 1: altsyncram_l9e1 +Sat 21:57: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_tif.tdf +Sat 21:57: INFO : Info (12023): Found entity 1: cntr_tif +Sat 21:57: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_dac.tdf +Sat 21:57: INFO : Info (12023): Found entity 1: cmpr_dac +Sat 21:57: INFO : Info (12130): Elaborated megafunction instantiation "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830:inst_ln130_mappedregblock|mapped_register:inst_ln504_mappedregblock|altshift_taps:mapped_registers_rtl_0" +Sat 21:57: INFO : Info (12133): Instantiated megafunction "MAX4FPGATop:MAX4MaiaFabricTop_i|FPGAWrapperEntity_Manager_FetchSubTuple:wrapper|SignalForwardingAdapter_stream_reset_memory_interrupt_crash_packet_sysmon_reset_pcc_switch_regs_pcc_start_pcc_reset_partial_reconfig_0:SignalForwardingAdapter_i|MappedRegBlock_4cdf0f923c75d2a0461d279b0adb9830:inst_ln130_mappedregblock|mapped_register:inst_ln504_mappedregblock|altshift_taps:mapped_registers_rtl_0" with the following parameter: +Sat 21:57: INFO : Info (12134): Parameter "NUMBER_OF_TAPS" = "1" +Sat 21:57: INFO : Info (12134): Parameter "TAP_DISTANCE" = "4" +Sat 21:57: INFO : Info (12134): Parameter "WIDTH" = "8" +Sat 21:57: INFO : Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE" +Sat 21:57: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_ks31.tdf +Sat 21:57: INFO : Info (12023): Found entity 1: shift_taps_ks31 +Sat 21:57: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_f6e1.tdf +Sat 21:57: INFO : Info (12023): Found entity 1: altsyncram_f6e1 +Sat 21:57: INFO : Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_rif.tdf +Sat 21:57: INFO : Info (12023): Found entity 1: cntr_rif +Sat 21:57: INFO : Warning (12241): 5 hierarchies have connectivity warnings - see the Connectivity Checks report folder +Sat 21:57: INFO : Info (281020): Starting Logic Optimization and Technology Mapping for Top Partition +Sat 21:57: INFO : Info (17049): 179 registers lost all their fanouts during netlist optimizations. +Sat 21:57: INFO : Info (21057): Implemented 3303 device resources after synthesis - the final resource count might be different +Sat 21:57: INFO : Info (21058): Implemented 18 input pins +Sat 21:57: INFO : Info (21059): Implemented 10 output pins +Sat 21:57: INFO : Info (21060): Implemented 26 bidirectional pins +Sat 21:57: INFO : Info (21061): Implemented 2832 logic cells +Sat 21:57: INFO : Info (21064): Implemented 236 RAM segments +Sat 21:57: INFO : Info (21065): Implemented 2 PLLs +Sat 21:57: INFO : Info (21071): Implemented 1 partitions +Sat 21:57: INFO : Info (281019): Starting Logic Optimization and Technology Mapping for Partition MAX4FPGATop:MAX4MaiaFabricTop_i +Sat 21:58: INFO : Critical Warning (18061): Ignored Power-Up Level option on the following registers +Sat 21:58: INFO : Critical Warning (18010): Register MAX4FPGATop:MAX4MaiaFabricTop_i|MAX4PCIeSlaveInterface:MAX4PCIeSlaveInterface_i|max_SV_pcie_slave:PCIeSlaveInterface_imp|mapped_elements_reset_i will power up to Low +Sat 21:58: INFO : Info (17049): 339 registers lost all their fanouts during netlist optimizations. +Sat 21:58: INFO : Info (21057): Implemented 55533 device resources after synthesis - the final resource count might be different +Sat 21:58: INFO : Info (21058): Implemented 364 input pins +Sat 21:58: INFO : Info (21059): Implemented 317 output pins +Sat 21:58: INFO : Info (21061): Implemented 45022 logic cells +Sat 21:58: INFO : Info (21064): Implemented 9830 RAM segments +Sat 21:58: INFO : Info (144001): Generated suppressed messages file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/map/altera_quartus/MAX4MAIAPeripheryTop.map.smsg +Sat 21:58: INFO : Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 999 warnings +Sat 21:58: INFO : Info: Peak virtual memory: 2548 megabytes +Sat 21:58: INFO : Info: Processing ended: Sat Sep 5 21:58:21 2015 +Sat 21:58: INFO : Info: Elapsed time: 00:08:12 +Sat 21:58: INFO : Info: Total CPU time (on all processors): 00:08:09 +Sat 21:58: INFO : quartus_map ended (21:58:22 05/09/15, time elapsed: 8 mins, 16 secs) +Sat 21:58: INFO : quartus_map peak virtual memory: 2548 +Sat 21:58: INFO : Build pass 'QuartusMap' took 496.785 s. +Sat 21:58: PROGRESS: (3/16) - Generate Incremental Netlist (QuartusCdb) +Sat 21:58: INFO : Starting quartus_cdb. (21:58:22 05/09/15) +Sat 21:58: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_cdb MAX4MAIAPeripheryTop --64bit --write_settings_files=off --merge=on +Sat 21:58: INFO : Info: ******************************************************************* +Sat 21:58: INFO : Info: Running Quartus II 64-Bit Partition Merge +Sat 21:58: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version +Sat 21:58: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. +Sat 21:58: INFO : Info: Your use of Altera Corporation's design tools, logic functions +Sat 21:58: INFO : Info: and other software and tools, and its AMPP partner logic +Sat 21:58: INFO : Info: functions, and any output files from any of the foregoing +Sat 21:58: INFO : Info: (including device programming or simulation files), and any +Sat 21:58: INFO : Info: associated documentation or information are expressly subject +Sat 21:58: INFO : Info: to the terms and conditions of the Altera Program License +Sat 21:58: INFO : Info: Subscription Agreement, Altera MegaCore Function License +Sat 21:58: INFO : Info: Agreement, or other applicable license agreement, including, +Sat 21:58: INFO : Info: without limitation, that your use is for the sole purpose of +Sat 21:58: INFO : Info: programming logic devices manufactured by Altera and sold by +Sat 21:58: INFO : Info: Altera or its authorized distributors. Please refer to the +Sat 21:58: INFO : Info: applicable agreement for further details. +Sat 21:58: INFO : Info: Processing started: Sat Sep 5 21:58:26 2015 +Sat 21:58: INFO : Info: Command: quartus_cdb MAX4MAIAPeripheryTop --write_settings_files=off --merge=on +Sat 21:58: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/map/altera_quartus/quartus.ini +Sat 21:58: INFO : Info (35007): Using synthesis netlist for partition "Top" +Sat 21:58: INFO : Info (35007): Using synthesis netlist for partition "MAX4FPGATop:MAX4MaiaFabricTop_i" +Sat 21:58: INFO : Info (35002): Resolved and merged 2 partition(s) +Sat 21:58: INFO : Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" +Sat 21:58: INFO : Info (16011): Adding 218 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL +Sat 21:58: INFO : Info (35048): Found 123 ports with constant drivers. For more information, refer to the Partition Merger report +Sat 21:58: INFO : Info (35047): Found 190 ports with no fan-out. For more information, refer to the Partition Merger report +Sat 21:58: INFO : Warning (35016): Found partition port(s) not driving logic, possibly wasting area +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|rx_st_bar[1]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|rx_st_bar[3]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|rx_st_bar[5]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|rx_st_bar[6]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|rx_st_bar[7]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[13]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[14]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[15]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[16]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[17]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[18]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[19]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[20]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[21]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[22]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[23]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[24]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[25]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[26]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35018): Partition port "MAX4FPGATop:MAX4MaiaFabricTop_i|tl_cfg_ctl[27]", driven by node "StratixPCIeBase:PCIeBase_i|StratixVHardIPPCIe:StratixVHardIPPCIe_i|pcie_SV_hard_ip:pcie_SV_hard_ip_i|altpcie_sv_hip_ast_hwtcl:pcie_sv_hard_ip_inst|altpcie_hip_256_pipen1b:altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip", does not drive logic +Sat 21:58: INFO : Warning (35039): Only the first 20 ports are reported. For a full list of ports, refer to the Partition Warnings panel in the Partition Merge report +Sat 21:58: INFO : Warning (21074): Design contains 2 input pin(s) that do not drive logic +Sat 21:58: INFO : Warning (15610): No output dependent on input pin "left_pll_ref_clk" +Sat 21:58: INFO : Warning (15610): No output dependent on input pin "right_pll_ref_clk" +Sat 21:58: INFO : Info (21057): Implemented 58192 device resources after synthesis - the final resource count might be different +Sat 21:58: INFO : Info (21058): Implemented 18 input pins +Sat 21:58: INFO : Info (21059): Implemented 10 output pins +Sat 21:58: INFO : Info (21060): Implemented 26 bidirectional pins +Sat 21:58: INFO : Info (21061): Implemented 47892 logic cells +Sat 21:58: INFO : Info (21064): Implemented 10066 RAM segments +Sat 21:58: INFO : Info (21065): Implemented 2 PLLs +Sat 21:58: INFO : Info: Quartus II 64-Bit Partition Merge was successful. 0 errors, 25 warnings +Sat 21:58: INFO : Info: Peak virtual memory: 1365 megabytes +Sat 21:58: INFO : Info: Processing ended: Sat Sep 5 21:58:58 2015 +Sat 21:58: INFO : Info: Elapsed time: 00:00:32 +Sat 21:58: INFO : Info: Total CPU time (on all processors): 00:00:31 +Sat 21:58: INFO : quartus_cdb ended (21:58:58 05/09/15, time elapsed: 35 secs) +Sat 21:58: INFO : quartus_cdb peak virtual memory: 1365 +Sat 21:58: INFO : Build pass 'QuartusCdb' took 35.6906 s. +Sat 21:58: PROGRESS: (4/16) - Generate Resource Report (AlteraResourceUsageBuildPass) +Sat 21:58: INFO : Build pass 'AlteraResourceUsageBuildPass' took 1.24644 s. +Sat 21:58: PROGRESS: (5/16) - Generate Annotated Source Code (AlteraResourceAnnotationBuildPass) +Sat 21:58: INFO : Annotating source files (old source files in build directory will be removed first)... +Sat 21:58: INFO : Not deleting directory (does not exist): src_annotated_preliminary_FetchSubTupleKernel +Sat 21:58: INFO : annotated 2 source files +Sat 21:58: INFO : Annotating source files (old source files in build directory will be removed first)... +Sat 21:58: INFO : Not deleting directory (does not exist): src_annotated_preliminary +Sat 21:59: INFO : annotated 2 source files +Sat 21:59: INFO : Build pass 'AlteraResourceAnnotationBuildPass' took 3.80457 s. +Sat 21:59: PROGRESS: (6/16) - Analyse Resource Usage (AlteraResourceCounterPass) +Sat 21:59: PROGRESS: +Sat 21:59: PROGRESS: About to start chip vendor Map/Place/Route toolflow. This will take some time. +Sat 21:59: PROGRESS: For this compile, we estimate this process may take up to 30 minutes. +Sat 21:59: PROGRESS: We recommend running in simulation to verify correctness before building hardware. +Sat 21:59: PROGRESS: +Sat 21:59: PROGRESS: PRELIMINARY RESOURCE USAGE +Sat 21:59: PROGRESS: Logic utilization: 21197 / 262400 (8.08%) +Sat 21:59: PROGRESS: Multipliers (18x18): 0 / 3926 (0.00%) +Sat 21:59: PROGRESS: Block memory (bits): 4890557 / 52572160 (9.30%) +Sat 21:59: PROGRESS: +Sat 21:59: INFO : Build pass 'AlteraResourceCounterPass' took 1.45054 ms. +Sat 21:59: PROGRESS: (7/16) - Place and Route DFE (AlteraMPPR) +Sat 21:59: PROGRESS: Executing MPPR with 1 cost table and 1 thread. +Sat 21:59: PROGRESS: MPPR: Starting 1 cost table +Sat 21:59: INFO : Created new sub build manager running in: /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/./FetchSubTuple_MAIA_DFE/scratch/altera_quartus/ct1 +Sat 21:59: INFO : For detailed output from this sub build manager see: /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/./FetchSubTuple_MAIA_DFE/scratch/altera_quartus/ct1/_build.log +Sat 22:53: PROGRESS: MPPR: Cost table 1 met timing with score 0 (best score 0) +Sat 22:53: INFO : Build pass 'AlteraMPPR' took 3250.39 s. +Sat 22:53: PROGRESS: (8/16) - Generate Configuration (QuartusAsm) +Sat 22:53: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/ct1/altera_quartus/db" "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus" +Sat 22:53: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/ct1/altera_quartus/incremental_db" "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus" +Sat 22:53: INFO : Running command: ln -sf "../../map/altera_quartus/MAX4MAIAPeripheryTop.qpf" +Sat 22:53: INFO : Creating timing report for cost table(s): 1 +Sat 22:53: INFO : Running command: ln -sf "../../map/altera_quartus/MAX4MAIAPeripheryTop.qsf" +Sat 22:53: INFO : Running command: ln -sf "../../map/altera_quartus/quartus.ini" +Sat 22:53: INFO : Running command: ln -sf "../../map/altera_quartus/MAX4MAIAPeripheryTop.sdc" +Sat 22:53: INFO : Starting quartus_asm. (22:53:14 05/09/15) +Sat 22:53: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_asm MAX4MAIAPeripheryTop --64bit --write_settings_files=off +Sat 22:53: INFO : Timing report successfully written. +Sat 22:55: INFO : Info: ******************************************************************* +Sat 22:55: INFO : Info: Running Quartus II 64-Bit Assembler +Sat 22:55: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version +Sat 22:55: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. +Sat 22:55: INFO : Info: Your use of Altera Corporation's design tools, logic functions +Sat 22:55: INFO : Info: and other software and tools, and its AMPP partner logic +Sat 22:55: INFO : Info: functions, and any output files from any of the foregoing +Sat 22:55: INFO : Info: (including device programming or simulation files), and any +Sat 22:55: INFO : Info: associated documentation or information are expressly subject +Sat 22:55: INFO : Info: to the terms and conditions of the Altera Program License +Sat 22:55: INFO : Info: Subscription Agreement, Altera MegaCore Function License +Sat 22:55: INFO : Info: Agreement, or other applicable license agreement, including, +Sat 22:55: INFO : Info: without limitation, that your use is for the sole purpose of +Sat 22:55: INFO : Info: programming logic devices manufactured by Altera and sold by +Sat 22:55: INFO : Info: Altera or its authorized distributors. Please refer to the +Sat 22:55: INFO : Info: applicable agreement for further details. +Sat 22:55: INFO : Info: Processing started: Sat Sep 5 22:53:19 2015 +Sat 22:55: INFO : Info: Command: quartus_asm MAX4MAIAPeripheryTop --write_settings_files=off +Sat 22:55: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini +Sat 22:55: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:55: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:55: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:55: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:55: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:55: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:55: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:55: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:55: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:55: INFO : Info (115030): Assembler is generating device programming files +Sat 22:55: INFO : Info: Quartus II 64-Bit Assembler was successful. 0 errors, 9 warnings +Sat 22:55: INFO : Info: Peak virtual memory: 1957 megabytes +Sat 22:55: INFO : Info: Processing ended: Sat Sep 5 22:55:04 2015 +Sat 22:55: INFO : Info: Elapsed time: 00:01:45 +Sat 22:55: INFO : Info: Total CPU time (on all processors): 00:01:44 +Sat 22:55: INFO : quartus_asm ended (22:55:06 05/09/15, time elapsed: 1 min, 52 secs) +Sat 22:55: INFO : quartus_asm peak virtual memory: 1957 +Sat 22:55: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.asm.rpt" "MAX4MAIAPeripheryTop.asm.stage1.rpt" +Sat 22:55: INFO : Deleting /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.asm.rpt +Sat 22:55: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.sof" "MAX4MAIAPeripheryTop.stage1.sof" +Sat 22:55: INFO : Deleting /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.sof +Sat 22:55: INFO : Build pass 'QuartusAsm' took 113.259 s. +Sat 22:55: PROGRESS: (9/16) - Convert Programming File (QuartusCpf) +Sat 22:55: INFO : Starting quartus_cpf for periphery/core split rbf. (22:55:06 05/09/15) +Sat 22:55: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_cpf --64bit -c "MAX4MAIAPeripheryTop.cof" +Sat 22:55: INFO : Info: ******************************************************************* +Sat 22:55: INFO : Info: Running Quartus II 64-Bit Convert_programming_file +Sat 22:55: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version +Sat 22:55: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. +Sat 22:55: INFO : Info: Your use of Altera Corporation's design tools, logic functions +Sat 22:55: INFO : Info: and other software and tools, and its AMPP partner logic +Sat 22:55: INFO : Info: functions, and any output files from any of the foregoing +Sat 22:55: INFO : Info: (including device programming or simulation files), and any +Sat 22:55: INFO : Info: associated documentation or information are expressly subject +Sat 22:55: INFO : Info: to the terms and conditions of the Altera Program License +Sat 22:55: INFO : Info: Subscription Agreement, Altera MegaCore Function License +Sat 22:55: INFO : Info: Agreement, or other applicable license agreement, including, +Sat 22:55: INFO : Info: without limitation, that your use is for the sole purpose of +Sat 22:55: INFO : Info: programming logic devices manufactured by Altera and sold by +Sat 22:55: INFO : Info: Altera or its authorized distributors. Please refer to the +Sat 22:55: INFO : Info: applicable agreement for further details. +Sat 22:55: INFO : Info: Processing started: Sat Sep 5 22:55:08 2015 +Sat 22:55: INFO : Info: Command: quartus_cpf -c MAX4MAIAPeripheryTop.cof +Sat 22:55: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini +Sat 22:55: INFO : Info: Quartus II 64-Bit Convert_programming_file was successful. 0 errors, 0 warnings +Sat 22:55: INFO : Info: Peak virtual memory: 978 megabytes +Sat 22:55: INFO : Info: Processing ended: Sat Sep 5 22:55:20 2015 +Sat 22:55: INFO : Info: Elapsed time: 00:00:12 +Sat 22:55: INFO : Info: Total CPU time (on all processors): 00:00:12 +Sat 22:55: INFO : quartus_cpf ended (22:55:22 05/09/15, time elapsed: 15 secs) +Sat 22:55: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.core.rbf" "MAX4MAIAPeripheryTop.core.stage1.rbf" +Sat 22:55: INFO : Deleting /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.core.rbf +Sat 22:55: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.periph.rbf" "MAX4MAIAPeripheryTop.periph.stage1.rbf" +Sat 22:55: INFO : Deleting /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.periph.rbf +Sat 22:55: INFO : Starting quartus_cpf for full rbf. (22:55:22 05/09/15) +Sat 22:55: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_cpf --64bit -c "MAX4MAIAPeripheryTop_full.cof" +Sat 22:55: INFO : Info: ******************************************************************* +Sat 22:55: INFO : Info: Running Quartus II 64-Bit Convert_programming_file +Sat 22:55: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version +Sat 22:55: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. +Sat 22:55: INFO : Info: Your use of Altera Corporation's design tools, logic functions +Sat 22:55: INFO : Info: and other software and tools, and its AMPP partner logic +Sat 22:55: INFO : Info: functions, and any output files from any of the foregoing +Sat 22:55: INFO : Info: (including device programming or simulation files), and any +Sat 22:55: INFO : Info: associated documentation or information are expressly subject +Sat 22:55: INFO : Info: to the terms and conditions of the Altera Program License +Sat 22:55: INFO : Info: Subscription Agreement, Altera MegaCore Function License +Sat 22:55: INFO : Info: Agreement, or other applicable license agreement, including, +Sat 22:55: INFO : Info: without limitation, that your use is for the sole purpose of +Sat 22:55: INFO : Info: programming logic devices manufactured by Altera and sold by +Sat 22:55: INFO : Info: Altera or its authorized distributors. Please refer to the +Sat 22:55: INFO : Info: applicable agreement for further details. +Sat 22:55: INFO : Info: Processing started: Sat Sep 5 22:55:24 2015 +Sat 22:55: INFO : Info: Command: quartus_cpf -c MAX4MAIAPeripheryTop_full.cof +Sat 22:55: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini +Sat 22:55: INFO : Info: Quartus II 64-Bit Convert_programming_file was successful. 0 errors, 0 warnings +Sat 22:55: INFO : Info: Peak virtual memory: 974 megabytes +Sat 22:55: INFO : Info: Processing ended: Sat Sep 5 22:55:35 2015 +Sat 22:55: INFO : Info: Elapsed time: 00:00:11 +Sat 22:55: INFO : Info: Total CPU time (on all processors): 00:00:12 +Sat 22:55: INFO : quartus_cpf ended (22:55:37 05/09/15, time elapsed: 15 secs) +Sat 22:55: INFO : Running command: cp -rf "/mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.rbf" "MAX4MAIAPeripheryTop.stage1.rbf" +Sat 22:55: INFO : Deleting /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.rbf +Sat 22:55: INFO : Build pass 'QuartusCpf' took 31.0835 s. +Sat 22:55: PROGRESS: (10/16) - Update Checksum (UpdateChecksumBuildPass) +Sat 22:55: INFO : Build pass 'UpdateChecksumBuildPass' took 169.332 ms. +Sat 22:55: PROGRESS: (11/16) - Generate Incremental Netlist (QuartusCdb) +Sat 22:55: INFO : Starting quartus_cdb. (22:55:38 05/09/15) +Sat 22:55: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_cdb MAX4MAIAPeripheryTop --64bit --write_settings_files=off --update_mif +Sat 22:56: INFO : Info: ******************************************************************* +Sat 22:56: INFO : Info: Running Quartus II 64-Bit MIF/HEX Update +Sat 22:56: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version +Sat 22:56: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. +Sat 22:56: INFO : Info: Your use of Altera Corporation's design tools, logic functions +Sat 22:56: INFO : Info: and other software and tools, and its AMPP partner logic +Sat 22:56: INFO : Info: functions, and any output files from any of the foregoing +Sat 22:56: INFO : Info: (including device programming or simulation files), and any +Sat 22:56: INFO : Info: associated documentation or information are expressly subject +Sat 22:56: INFO : Info: to the terms and conditions of the Altera Program License +Sat 22:56: INFO : Info: Subscription Agreement, Altera MegaCore Function License +Sat 22:56: INFO : Info: Agreement, or other applicable license agreement, including, +Sat 22:56: INFO : Info: without limitation, that your use is for the sole purpose of +Sat 22:56: INFO : Info: programming logic devices manufactured by Altera and sold by +Sat 22:56: INFO : Info: Altera or its authorized distributors. Please refer to the +Sat 22:56: INFO : Info: applicable agreement for further details. +Sat 22:56: INFO : Info: Processing started: Sat Sep 5 22:55:43 2015 +Sat 22:56: INFO : Info: Command: quartus_cdb MAX4MAIAPeripheryTop --write_settings_files=off --update_mif +Sat 22:56: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini +Sat 22:56: INFO : Warning (39023): Can't find Memory Initialization File alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_a.mif -- skipped updates for this file +Sat 22:56: INFO : Warning (39023): Can't find Memory Initialization File alt_xcvr_reconfig_cpu_reconfig_cpu_rf_ram_b.mif -- skipped updates for this file +Sat 22:56: INFO : Warning (39023): Can't find Memory Initialization File alt_xcvr_reconfig_cpu_ram.hex -- skipped updates for this file +Sat 22:56: INFO : Info (39024): Processed the following Memory Initialization File(s) +Sat 22:56: INFO : Info (39025): Processed Memory Initialization File /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/32x512_ROM_SINGLE_PORT_ireg_checksum.mif +Sat 22:56: INFO : Info (39025): Processed Memory Initialization File /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/db/MAX4MAIAPeripheryTop.ram0_sv_xrbasic_l2p_rom_a2c9d7fe.hdl.mif +Sat 22:56: INFO : Info: Quartus II 64-Bit MIF/HEX Update was successful. 0 errors, 3 warnings +Sat 22:56: INFO : Info: Peak virtual memory: 1755 megabytes +Sat 22:56: INFO : Info: Processing ended: Sat Sep 5 22:56:02 2015 +Sat 22:56: INFO : Info: Elapsed time: 00:00:19 +Sat 22:56: INFO : Info: Total CPU time (on all processors): 00:00:19 +Sat 22:56: INFO : quartus_cdb ended (22:56:02 05/09/15, time elapsed: 24 secs) +Sat 22:56: INFO : quartus_cdb peak virtual memory: 1755 +Sat 22:56: INFO : Build pass 'QuartusCdb' took 24.4597 s. +Sat 22:56: PROGRESS: (12/16) - Generate Configuration (QuartusAsm) +Sat 22:56: INFO : Starting quartus_asm. (22:56:02 05/09/15) +Sat 22:56: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_asm MAX4MAIAPeripheryTop --64bit --write_settings_files=off +Sat 22:56: INFO : Checking for file hash changes... +Sat 22:56: INFO : Hash changed for file: 'db' +Sat 22:57: INFO : Info: ******************************************************************* +Sat 22:57: INFO : Info: Running Quartus II 64-Bit Assembler +Sat 22:57: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version +Sat 22:57: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. +Sat 22:57: INFO : Info: Your use of Altera Corporation's design tools, logic functions +Sat 22:57: INFO : Info: and other software and tools, and its AMPP partner logic +Sat 22:57: INFO : Info: functions, and any output files from any of the foregoing +Sat 22:57: INFO : Info: (including device programming or simulation files), and any +Sat 22:57: INFO : Info: associated documentation or information are expressly subject +Sat 22:57: INFO : Info: to the terms and conditions of the Altera Program License +Sat 22:57: INFO : Info: Subscription Agreement, Altera MegaCore Function License +Sat 22:57: INFO : Info: Agreement, or other applicable license agreement, including, +Sat 22:57: INFO : Info: without limitation, that your use is for the sole purpose of +Sat 22:57: INFO : Info: programming logic devices manufactured by Altera and sold by +Sat 22:57: INFO : Info: Altera or its authorized distributors. Please refer to the +Sat 22:57: INFO : Info: applicable agreement for further details. +Sat 22:57: INFO : Info: Processing started: Sat Sep 5 22:56:07 2015 +Sat 22:57: INFO : Info: Command: quartus_asm MAX4MAIAPeripheryTop --write_settings_files=off +Sat 22:57: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini +Sat 22:57: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:57: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:57: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:57: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:57: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:57: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:57: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:57: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:57: INFO : Warning (15104): Quartus II software detected a bonding design. Reconfiguration is not supported for Bonded designs and MIF is not created for this design. +Sat 22:57: INFO : Info (115030): Assembler is generating device programming files +Sat 22:57: INFO : Info: Quartus II 64-Bit Assembler was successful. 0 errors, 9 warnings +Sat 22:57: INFO : Info: Peak virtual memory: 1996 megabytes +Sat 22:57: INFO : Info: Processing ended: Sat Sep 5 22:57:49 2015 +Sat 22:57: INFO : Info: Elapsed time: 00:01:42 +Sat 22:57: INFO : Info: Total CPU time (on all processors): 00:01:40 +Sat 22:57: INFO : quartus_asm ended (22:57:51 05/09/15, time elapsed: 1 min, 48 secs) +Sat 22:57: INFO : quartus_asm peak virtual memory: 1996 +Sat 22:57: INFO : Build pass 'QuartusAsm' took 108.533 s. +Sat 22:57: PROGRESS: (13/16) - Convert Programming File (QuartusCpf) +Sat 22:57: INFO : Starting quartus_cpf for periphery/core split rbf. (22:57:51 05/09/15) +Sat 22:57: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_cpf --64bit -c "MAX4MAIAPeripheryTop.cof" +Sat 22:57: INFO : Checking for file hash changes... +Sat 22:57: INFO : No hash for file: 'MAX4MAIAPeripheryTop.sof' +Sat 22:57: INFO : Hash changed for file: 'MAX4MAIAPeripheryTop.cof' +Sat 22:58: INFO : Info: ******************************************************************* +Sat 22:58: INFO : Info: Running Quartus II 64-Bit Convert_programming_file +Sat 22:58: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version +Sat 22:58: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. +Sat 22:58: INFO : Info: Your use of Altera Corporation's design tools, logic functions +Sat 22:58: INFO : Info: and other software and tools, and its AMPP partner logic +Sat 22:58: INFO : Info: functions, and any output files from any of the foregoing +Sat 22:58: INFO : Info: (including device programming or simulation files), and any +Sat 22:58: INFO : Info: associated documentation or information are expressly subject +Sat 22:58: INFO : Info: to the terms and conditions of the Altera Program License +Sat 22:58: INFO : Info: Subscription Agreement, Altera MegaCore Function License +Sat 22:58: INFO : Info: Agreement, or other applicable license agreement, including, +Sat 22:58: INFO : Info: without limitation, that your use is for the sole purpose of +Sat 22:58: INFO : Info: programming logic devices manufactured by Altera and sold by +Sat 22:58: INFO : Info: Altera or its authorized distributors. Please refer to the +Sat 22:58: INFO : Info: applicable agreement for further details. +Sat 22:58: INFO : Info: Processing started: Sat Sep 5 22:57:52 2015 +Sat 22:58: INFO : Info: Command: quartus_cpf -c MAX4MAIAPeripheryTop.cof +Sat 22:58: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini +Sat 22:58: INFO : Info: Quartus II 64-Bit Convert_programming_file was successful. 0 errors, 0 warnings +Sat 22:58: INFO : Info: Peak virtual memory: 978 megabytes +Sat 22:58: INFO : Info: Processing ended: Sat Sep 5 22:58:04 2015 +Sat 22:58: INFO : Info: Elapsed time: 00:00:12 +Sat 22:58: INFO : Info: Total CPU time (on all processors): 00:00:12 +Sat 22:58: INFO : quartus_cpf ended (22:58:06 05/09/15, time elapsed: 15 secs) +Sat 22:58: INFO : Starting quartus_cpf for full rbf. (22:58:06 05/09/15) +Sat 22:58: INFO : Running command: export LM_LICENSE_FILE="$LM_LICENSE_FILE:$MAXCOMPILERDIR/lib/MaxCompilerQuartusLicense.dat" ; quartus_cpf --64bit -c "MAX4MAIAPeripheryTop_full.cof" +Sat 22:58: INFO : Checking for file hash changes... +Sat 22:58: INFO : Hash changed for file: 'MAX4MAIAPeripheryTop_full.cof' +Sat 22:58: INFO : No hash for file: 'MAX4MAIAPeripheryTop.sof' +Sat 22:58: INFO : Info: ******************************************************************* +Sat 22:58: INFO : Info: Running Quartus II 64-Bit Convert_programming_file +Sat 22:58: INFO : Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version +Sat 22:58: INFO : Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved. +Sat 22:58: INFO : Info: Your use of Altera Corporation's design tools, logic functions +Sat 22:58: INFO : Info: and other software and tools, and its AMPP partner logic +Sat 22:58: INFO : Info: functions, and any output files from any of the foregoing +Sat 22:58: INFO : Info: (including device programming or simulation files), and any +Sat 22:58: INFO : Info: associated documentation or information are expressly subject +Sat 22:58: INFO : Info: to the terms and conditions of the Altera Program License +Sat 22:58: INFO : Info: Subscription Agreement, Altera MegaCore Function License +Sat 22:58: INFO : Info: Agreement, or other applicable license agreement, including, +Sat 22:58: INFO : Info: without limitation, that your use is for the sole purpose of +Sat 22:58: INFO : Info: programming logic devices manufactured by Altera and sold by +Sat 22:58: INFO : Info: Altera or its authorized distributors. Please refer to the +Sat 22:58: INFO : Info: applicable agreement for further details. +Sat 22:58: INFO : Info: Processing started: Sat Sep 5 22:58:08 2015 +Sat 22:58: INFO : Info: Command: quartus_cpf -c MAX4MAIAPeripheryTop_full.cof +Sat 22:58: INFO : Info: Using INI file /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/scratch/altera_quartus/asm/altera_quartus/quartus.ini +Sat 22:58: INFO : Info: Quartus II 64-Bit Convert_programming_file was successful. 0 errors, 0 warnings +Sat 22:58: INFO : Info: Peak virtual memory: 970 megabytes +Sat 22:58: INFO : Info: Processing ended: Sat Sep 5 22:58:21 2015 +Sat 22:58: INFO : Info: Elapsed time: 00:00:13 +Sat 22:58: INFO : Info: Total CPU time (on all processors): 00:00:13 +Sat 22:58: INFO : quartus_cpf ended (22:58:22 05/09/15, time elapsed: 16 secs) +Sat 22:58: INFO : Build pass 'QuartusCpf' took 31.7837 s. +Sat 22:58: PROGRESS: (14/16) - Generate Resource Report (AlteraResourceUsageBuildPass) +Sat 22:58: INFO : Build pass 'AlteraResourceUsageBuildPass' took 1.16470 s. +Sat 22:58: PROGRESS: (15/16) - Generate Annotated Source Code (AlteraResourceAnnotationBuildPass) +Sat 22:58: INFO : Annotating source files (old source files in build directory will be removed first)... +Sat 22:58: INFO : Not deleting directory (does not exist): src_annotated_FetchSubTupleKernel +Sat 22:58: INFO : annotated 2 source files +Sat 22:58: INFO : Annotating source files (old source files in build directory will be removed first)... +Sat 22:58: INFO : Not deleting directory (does not exist): src_annotated +Sat 22:58: INFO : annotated 2 source files +Sat 22:58: INFO : Build pass 'AlteraResourceAnnotationBuildPass' took 3.65198 s. +Sat 22:58: PROGRESS: (16/16) - Generate MaxFile (GenerateMaxFileAltera) +Sat 22:58: INFO : Running command: "/vol/cc/opt/maxeler/maxcompiler-2014.1/bin/maxfilestitch" -a -w -m 1 -b 20150905 "../MaxCompilerDesignData.dat" "asm/altera_quartus/MAX4MAIAPeripheryTop.periph.rbf" "asm/altera_quartus/MAX4MAIAPeripheryTop.core.rbf" "FetchSubTuple.max" 50145a868fd937e49121d2f17784c931bc26d0c178795cb7769f1474bf1506e6 0 2>&1 | tee maxfilestitch.log ; exit ${PIPESTATUS[0]} +Sat 22:58: INFO : Input files: +Sat 22:58: INFO : DAT: ../MaxCompilerDesignData.dat +Sat 22:58: INFO : Periph RBF: asm/altera_quartus/MAX4MAIAPeripheryTop.periph.rbf +Sat 22:58: INFO : Core RBF: asm/altera_quartus/MAX4MAIAPeripheryTop.core.rbf +Sat 22:58: INFO : Output files: +Sat 22:58: INFO : MAX: FetchSubTuple.max +Sat 22:58: INFO : Hash: 50145a868fd937e49121d2f17784c931bc26d0c178795cb7769f1474bf1506e6 +Sat 22:58: INFO : Timing score: 0 +Sat 22:58: INFO : Build pass 'GenerateMaxFileAltera' took 4.49965 s. +Sat 22:58: INFO : Final result files after build: +Sat 22:58: INFO : Running command: ln -sf "../scratch/FetchSubTuple-FetchSubTupleKernel-original.pxg" +Sat 22:58: INFO : FetchSubTuple-FetchSubTupleKernel-original.pxg (BuildFilePXG) +Sat 22:58: INFO : Running command: ln -sf "../scratch/FetchSubTupleKernel_Configuration.txt" +Sat 22:58: INFO : FetchSubTupleKernel_Configuration.txt (BuildFile) +Sat 22:58: INFO : Running command: ln -sf "../scratch/FetchSubTupleKernel_NodeDiary.txt" +Sat 22:58: INFO : FetchSubTupleKernel_NodeDiary.txt (BuildFile) +Sat 22:58: INFO : Running command: ln -sf "../scratch/FetchSubTuple-FetchSubTupleKernel-final-hardware.pxg" +Sat 22:58: INFO : FetchSubTuple-FetchSubTupleKernel-final-hardware.pxg (BuildFilePXG) +Sat 22:58: INFO : Running command: ln -sf "../scratch/FetchSubTuple.xml" +Sat 22:58: INFO : FetchSubTuple.xml (BuildFile) +Sat 22:58: INFO : Running command: ln -sf "../scratch/FetchSubTuple.h" +Sat 22:58: INFO : FetchSubTuple.h (BuildFileSlicH) +Sat 22:58: INFO : Running command: ln -sf "../scratch/altera_quartus/FetchSubTuple_map.mxru" +Sat 22:58: INFO : FetchSubTuple_map.mxru (BuildFileMXRU) +Sat 22:58: INFO : Running command: ln -sf "../scratch/altera_quartus/ct1/altera_quartus/MAX4MAIAPeripheryTop.sta.rpt.tns" +Sat 22:58: INFO : MAX4MAIAPeripheryTop.sta.rpt.tns (BuildFileStaTns) +Sat 22:58: INFO : Running command: ln -sf "../scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.sof" +Sat 22:58: INFO : MAX4MAIAPeripheryTop.sof (BuildFileStage2SOF) +Sat 22:58: INFO : Running command: ln -sf "../scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.core.rbf" +Sat 22:58: INFO : MAX4MAIAPeripheryTop.core.rbf (BuildFileStage2CoreRBF) +Sat 22:58: INFO : Running command: ln -sf "../scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.periph.rbf" +Sat 22:58: INFO : MAX4MAIAPeripheryTop.periph.rbf (BuildFileStage2PeriphRBF) +Sat 22:58: INFO : Running command: ln -sf "../scratch/altera_quartus/asm/altera_quartus/MAX4MAIAPeripheryTop.rbf" +Sat 22:58: INFO : MAX4MAIAPeripheryTop.rbf (BuildFileStage2FullRBF) +Sat 22:58: INFO : Running command: ln -sf "../scratch/altera_quartus/FetchSubTuple_fit.mxru" +Sat 22:58: INFO : FetchSubTuple_fit.mxru (BuildFileMXRU) +Sat 22:58: INFO : Running command: ln -sf "../scratch/altera_quartus/FetchSubTuple.max" +Sat 22:58: INFO : FetchSubTuple.max (BuildFileMaxFile) +Sat 22:58: PROGRESS: +Sat 22:58: PROGRESS: FINAL RESOURCE USAGE +Sat 22:58: PROGRESS: Logic utilization: 20237 / 262400 (7.71%) +Sat 22:58: PROGRESS: Primary FFs: 34316 / 524800 (6.54%) +Sat 22:58: PROGRESS: Secondary FFs: 913 / 524800 (0.17%) +Sat 22:58: PROGRESS: Multipliers (18x18): 0 / 3926 (0.00%) +Sat 22:58: PROGRESS: DSP blocks: 0 / 1963 (0.00%) +Sat 22:58: PROGRESS: Block memory (M20K): 272 / 2567 (10.60%) +Sat 22:58: PROGRESS: +Sat 22:58: PROGRESS: MaxFile: /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/FetchSubTuple_MAIA_DFE/results/FetchSubTuple.max (MD5Sum: 3ad02016e8722865dfe2785807749537) +Sat 22:58: INFO : Waiting for any outstanding jobs to finish... +Sat 22:58: INFO : Timing Analyser shutting down. +Sat 22:58: INFO : Timing Report: /mnt/data/cccad3/pburovsk/dfe-snippets/test/DataStructures/FetchSubTuple/build-64x64bits/./FetchSubTuple_MAIA_DFE/timingreport/index.html +Sat 22:58: PROGRESS: Build completed: Sat Sep 05 22:58:33 BST 2015 (took 1 hour, 9 mins, 47 secs) diff --git a/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/report.txt b/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/report.txt index 86d9377..b747fa1 100644 --- a/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/report.txt +++ b/test/DataStructures/FetchSubTuple/experimental-results/64wide-64bits-shiftreg-simplified-noalign/report.txt @@ -3,83 +3,83 @@ Total resource usage ----------------------------------------------------------------- LUTs FFs BRAMs DSPs 524800 1049600 2567 1963 total available resources for FPGA - 9865 24671 143 0 total resources used - 1.88% 2.35% 5.57% 0.00% % of available - 2748 14903 1 0 used by kernels - 0.52% 1.42% 0.04% 0.00% % of available - 6093 7865 129 0 used by manager - 1.16% 0.75% 5.03% 0.00% % of available - 4557 18878 95 0 stray resources - 0.87% 1.80% 3.70% 0.00% % of available + 19997 35229 272 0 total resources used + 3.81% 3.36% 10.60% 0.00% % of available + 11955 21868 2 0 used by kernels + 2.28% 2.08% 0.08% 0.00% % of available + 7047 11470 257 0 used by manager + 1.34% 1.09% 10.01% 0.00% % of available + 14586 29461 224 0 stray resources + 2.78% 2.81% 8.73% 0.00% % of available High level manager breakdown aggregated by type ----------------------------------------------------------------- LUTs FFs BRAMs DSPs Type Occurrences 39 37 1 0 ChecksumMappedDRP 1 - 538 533 0 0 DualAspectMux 2 - 7 1547 0 0 DualAspectReg 1 - 367 490 88 0 Fifo 6 - 2748 14903 1 0 Kernel 1 + 1325 1432 0 0 DualAspectMux 2 + 13 4266 0 0 DualAspectReg 1 + 387 505 216 0 Fifo 6 + 11955 21868 2 0 Kernel 1 169 216 0 0 MAX4CPLD 1 - 731 1040 2 0 MAX4PCIeSlaveInterface 1 + 800 1023 2 0 MAX4PCIeSlaveInterface 1 34 54 0 0 MAXEvents 1 - 486 84 0 0 MappedElementSwitch 1 - 433 991 5 0 MappedMemoriesController 1 - 115 122 0 0 MappedRegistersControlle 1 - 1647 925 4 0 PCIeBase 1 - 1132 1363 28 0 PCIeSlaveStreaming 1 - 171 204 0 0 PerfMonitor 1 - 17 23 0 0 ResetControl 2 - 114 145 0 0 SanityBlock 1 - 93 91 1 0 SignalForwardingAdapter 1 + 542 88 0 0 MappedElementSwitch 1 + 475 990 5 0 MappedMemoriesController 1 + 123 122 0 0 MappedRegistersControlle 1 + 1647 929 4 0 PCIeBase 1 + 1143 1353 28 0 PCIeSlaveStreaming 1 + 168 205 0 0 PerfMonitor 1 + 17 22 0 0 ResetControl 2 + 71 145 0 0 SanityBlock 1 + 94 83 1 0 SignalForwardingAdapter 1 0 0 0 0 Memory Controller -- 0 0 0 0 Other InterFPGA -- - 1058 1292 8 0 Other MappedElements -- - 2603 3576 36 0 Other PCIe -- + 1166 1302 8 0 Other MappedElements -- + 2598 3537 36 0 Other PCIe -- Kernel breakdown ----------------------------------------------------------------- LUTs FFs BRAMs DSPs category - 2748 14903 1 0 total for all kernels - 0.52% 1.42% 0.04% 0.00% % of total available + 11955 21868 2 0 total for all kernels + 2.28% 2.08% 0.08% 0.00% % of total available Totals for each kernel LUTs FFs BRAMs DSPs Kernel name - 2748 14903 1 0 FetchSubTupleKernel (total) - 0.52% 1.42% 0.04% 0.00% % of total available - 2224 595 1 0 FetchSubTupleKernel (user) - 0.42% 0.06% 0.04% 0.00% % of total available - 336 12413 0 0 FetchSubTupleKernel (scheduling) - 0.06% 1.18% 0.00% 0.00% % of total available - 188 1895 0 0 FetchSubTupleKernel (other Kernel resources) - 0.04% 0.18% 0.00% 0.00% % of total available + 11955 21868 2 0 FetchSubTupleKernel (total) + 2.28% 2.08% 0.08% 0.00% % of total available + 11674 793 2 0 FetchSubTupleKernel (user) + 2.22% 0.08% 0.08% 0.00% % of total available + 214 16616 0 0 FetchSubTupleKernel (scheduling) + 0.04% 1.58% 0.00% 0.00% % of total available + 67 4459 0 0 FetchSubTupleKernel (other Kernel resources) + 0.01% 0.42% 0.00% 0.00% % of total available Manager breakdown ----------------------------------------------------------------- LUTs FFs BRAMs DSPs Type Instance - 2748 14903 1 0 Kernel FetchSubTupleKernel - 75 122 4 0 Fifo Stream_11 - 42 39 39 0 Fifo Stream_13 + 11955 21868 2 0 Kernel FetchSubTupleKernel + 80 123 4 0 Fifo Stream_11 + 43 40 103 0 Fifo Stream_13 38 32 1 0 Fifo Stream_15 - 103 139 1 0 Fifo Stream_17 - 37 33 39 0 Fifo Stream_19 - 7 1547 0 0 DualAspectReg Stream_1 - 72 125 4 0 Fifo Stream_21 - 11 9 0 0 DualAspectMux Stream_4 - 527 524 0 0 DualAspectMux Stream_8 - 731 1040 2 0 MAX4PCIeSlaveInterface MAX4PCIeSlaveInterface_i - 9 12 0 0 ResetControl control_streams_rst_ctl - 486 84 0 0 MappedElementSwitch MappedElementSwitch_i - 433 991 5 0 MappedMemoriesController MappedMemoriesController_i - 115 122 0 0 MappedRegistersControlle MappedRegistersController_i - 171 204 0 0 PerfMonitor perfm - 114 145 0 0 SanityBlock SanityBlock_i - 93 91 1 0 SignalForwardingAdapter SignalForwardingAdapter_i + 108 147 1 0 Fifo Stream_17 + 39 37 103 0 Fifo Stream_19 + 13 4266 0 0 DualAspectReg Stream_1 + 79 126 4 0 Fifo Stream_21 + 18 10 0 0 DualAspectMux Stream_4 + 1307 1422 0 0 DualAspectMux Stream_8 + 800 1023 2 0 MAX4PCIeSlaveInterface MAX4PCIeSlaveInterface_i + 9 11 0 0 ResetControl control_streams_rst_ctl + 542 88 0 0 MappedElementSwitch MappedElementSwitch_i + 475 990 5 0 MappedMemoriesController MappedMemoriesController_i + 123 122 0 0 MappedRegistersControlle MappedRegistersController_i + 168 205 0 0 PerfMonitor perfm + 71 145 0 0 SanityBlock SanityBlock_i + 94 83 1 0 SignalForwardingAdapter SignalForwardingAdapter_i 39 37 1 0 ChecksumMappedDRP checksum_mem_drp - 1132 1363 28 0 PCIeSlaveStreaming dynpcie + 1143 1353 28 0 PCIeSlaveStreaming dynpcie 8 11 0 0 ResetControl reset_controller - 1647 925 4 0 PCIeBase PCIeBase_i + 1647 929 4 0 PCIeBase PCIeBase_i 169 216 0 0 MAX4CPLD cpld_io_ext_inst 34 54 0 0 MAXEvents max_events @@ -88,7 +88,6 @@ Source files annotation report % of total used for each file (note: multiple files may share the same resources) LUTs FFs BRAMs DSPs filename - 19.24% 0.44% 0.70% 0.00% FetchSubTuple.maxj - 20.23% 0.97% 0.70% 0.00% FetchSubTupleKernel.maxj - 25.95% 52.73% 0.70% 0.00% FetchSubTupleManager.maxj - 25.95% 52.73% 0.70% 0.00% [ missing source files ] + 57.24% 1.21% 0.74% 0.00% FetchSubTupleKernel.maxj + 59.45% 49.42% 0.74% 0.00% FetchSubTupleManager.maxj + 100.00% 50.27% 1.47% 0.00% [ missing source files ]