diff --git a/.gitignore b/.gitignore index ba35ae3..acb990d 100644 --- a/.gitignore +++ b/.gitignore @@ -2,4 +2,7 @@ .DS_Store # VSCode files -.vscode \ No newline at end of file +.vscode + +# Build folder +.build \ No newline at end of file diff --git a/LICENSE b/LICENSE index 695945d..8e6f0d7 100644 --- a/LICENSE +++ b/LICENSE @@ -1,6 +1,6 @@ ISC License -Copyright 2021 Silicon Witchery AB +Copyright 2022 Silicon Witchery AB Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, diff --git a/s1.mk b/Makefile similarity index 94% rename from s1.mk rename to Makefile index c1ce364..3e9c711 100644 --- a/s1.mk +++ b/Makefile @@ -1,7 +1,7 @@ +# # Base SDK makefile. -# ------------------ # -# Copyright 2021 Silicon Witchery AB +# Copyright 2022 Silicon Witchery AB # # Permission to use, copy, modify, and/or distribute this software for any # purpose with or without fee is hereby granted, provided that the above @@ -15,7 +15,6 @@ # OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR # PERFORMANCE OF THIS SOFTWARE. # -# ------------------ # You don't need to change anything here, but include this file in your own @@ -26,7 +25,7 @@ # As a minimum, you only need to set these variables from you Makefile. PROJECT_NAME ?= s1_sdk_standalone NRF_SDK_PATH ?= ${HOME}/nRF5_SDK -S1_SDK_PATH ?= s1-sdk +S1_SDK_PATH ?= . # Optionally, you can change the build directory. OUTPUT_DIRECTORY ?= .build @@ -105,6 +104,12 @@ INC_FOLDERS += \ $(NRF_SDK_PATH)/modules/nrfx/hal \ $(NRF_SDK_PATH)/modules/nrfx/mdk \ +# If S1_TEST=1 is passed to the makefile, include the test main.c and config +ifeq ($(S1_TEST), 1) + SRC_FILES += $(S1_SDK_PATH)/s1_tests/s1_tests.c + INC_FOLDERS += $(S1_SDK_PATH)/s1_tests +endif + # Libraries can also be added. LIB_FILES += \ diff --git a/README.md b/README.md index f7a1e87..24a9491 100644 --- a/README.md +++ b/README.md @@ -34,7 +34,7 @@ Most of these tools are available from standard package managers, but you can bu We've designed this SDK so you can add it as a sub-module into your own git projects. The files here are therefore very lightweight and designed to be easy to use. -- `s1.mk` - This is the core makefile that ensures that the nRF code can be built. You should call it with your own `Makefile` where you specify your applications files and any other settings you may want. +- `Makefile` - This is the core makefile that ensures that the nRF code can be built. You should call it with your own `Makefile` where you specify your applications files and any other settings you may want. - `s1.c` - These are the core functions that run on the nRF chip. Access them via `s1.h` @@ -44,6 +44,8 @@ We've designed this SDK so you can add it as a sub-module into your own git proj - `s1.pcf` - The FPGA pin configuration resides here. The names of the pins correspond to the pins of the FPGA, where `Dx` are the exposed pins, and the remaining pins are internal to the module. +- `s1_tests` - This folder includes a test application which the SDK is tested against on every release. Run this application on your module to check it's correctly functional. Note that it sets many different voltages on the Vio and Vaux lines, which may damage external circuitry. It's best run on a bare Popout board without any additional devices connected. To build the test application, run `make S1_TEST=1 NRF_SDK_PATH=...` directly from the SDK folder. + That's it! Again in order to use these files, it's better to look at an example project, and copy that layout for your own application. ## Precautions diff --git a/s1.c b/s1.c index b175c3b..d3116eb 100644 --- a/s1.c +++ b/s1.c @@ -1,26 +1,28 @@ /** * @file s1.c + * * @brief S1 Module Core Functions - * - * Various functions to setup and configure the S1 Module. To access + * + * Various functions to setup and configure the S1 Module. To access * these functions, use the s1.h header file. - * - * @attention Copyright 2021 Silicon Witchery AB * - * Permission to use, copy, modify, and/or distribute this software for any + * @attention Copyright 2022 Silicon Witchery AB + * + * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH - * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, - * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR - * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ #include +#include #include "nrf_gpio.h" #include "nrfx_gpiote.h" @@ -30,47 +32,135 @@ #include "nrf52811.h" #include "s1.h" -// Instances for I2C and SPI +/** + * @brief Instance of the SPI driver to the Flash and FPGA + */ static const nrfx_spim_t spi = NRFX_SPIM_INSTANCE(0); + +/** + * @brief Instance of the I2C driver to the PMIC + */ static const nrfx_twim_t i2c = NRFX_TWIM_INSTANCE(0); -// Interupt driven pending flag for when the FPGA_DONE_PIN goes high +/** + * @brief Interrupt driven pending flag for when the FPGA_DONE_PIN goes high + */ static bool fpga_done_flag_pending = false; -// The PMIC control interface pins and I2C address -#define PMIC_SDA_PIN NRF_GPIO_PIN_MAP(0, 14) -#define PMIC_SCL_PIN NRF_GPIO_PIN_MAP(0, 17) -#define PMIC_I2C_ADDRESS 0x48 - -// ADC input for the battery monitor pin from the PMIC +/** + * @brief Definition of the ADC input pin for battery monitoring. + */ #define PMIC_AMUX_PIN NRF_SAADC_INPUT_AIN1 -static uint8_t pmic_read_reg(uint8_t reg) +/** + * @brief Local function for reading a register of the PMIC. Should not be + * directly accessed, instead use the relevant s1_pmic_...() functions + * to read data. + * + * @param reg: Address of the 8bit register that should be read. + * + * @param data: Pointer to where the read data will be stored. + * + * @returns S1_SUCCESS if okay, or S1_PMIC_COMMUNICATION_ERROR if the PMIC did + * not respond. + */ +static s1_error_t pmic_read_reg(uint8_t reg, uint8_t *data) { - uint8_t rx_buffer; - nrfx_twim_xfer_desc_t i2c_xfer = NRFX_TWIM_XFER_DESC_TXRX(PMIC_I2C_ADDRESS, ®, 1, &rx_buffer, 1); + // Transfer descriptor configured for a 1 byte read, and 1 byte write + nrfx_twim_xfer_desc_t i2c_xfer = + NRFX_TWIM_XFER_DESC_TXRX(0x48, ®, 1, data, 1); + + // Initiate the transfer nrfx_err_t err = nrfx_twim_xfer(&i2c, &i2c_xfer, 0); - if (err != NRF_SUCCESS) + + // Wait until the transfer is complete + while (nrfx_twim_is_busy(&i2c)) + { + } + + // If an error occurs, try again after 100us. This can be needed if the + // PMIC is under load, and the power fluctuates + if (err != NRFX_SUCCESS) { NRFX_DELAY_US(100); - LOG("Double read"); err = nrfx_twim_xfer(&i2c, &i2c_xfer, 0); - APP_ERROR_CHECK(err); + + // Wait until the transfer is complete + while (nrfx_twim_is_busy(&i2c)) + { + } + + // If another error occurs, return a communication error + if (err != NRFX_SUCCESS) + { + return S1_PMIC_COMMUNICATION_ERROR; + } } - return rx_buffer; + + // If transfer was okay, return success + return S1_SUCCESS; } -static void pmic_write_reg(uint8_t reg, uint8_t value) +/** + * @brief Local function for writing a register of the PMIC. Should not be + * directly accessed, instead use the relevant s1_pmic_...() functions + * to write data. + * + * @param reg: Address of the 8bit register that should be written to. + * + * @param data: Value which should be written in the register. + * + * @returns S1_SUCCESS if okay, or S1_PMIC_COMMUNICATION_ERROR if the PMIC did + * not respond. + */ +static s1_error_t pmic_write_reg(uint8_t reg, uint8_t data) { - uint8_t buffer[2]; - nrfx_twim_xfer_desc_t i2c_xfer = NRFX_TWIM_XFER_DESC_TX(0x48, buffer, 2); - buffer[0] = reg; - buffer[1] = value; - APP_ERROR_CHECK(nrfx_twim_xfer(&i2c, &i2c_xfer, 0)); + // Create a two byte buffer with the register and value + uint8_t buffer[2] = {reg, data}; + + // Transfer descriptor configured for a 2 byte write + nrfx_twim_xfer_desc_t i2c_xfer = + NRFX_TWIM_XFER_DESC_TX(0x48, buffer, 2); + + // Initiate the transfer + nrfx_err_t err = nrfx_twim_xfer(&i2c, &i2c_xfer, 0); + + // Wait until the transfer is complete + while (nrfx_twim_is_busy(&i2c)) + { + } + + // If an error occurs, return a communication error + if (err != NRFX_SUCCESS) + { + return S1_PMIC_COMMUNICATION_ERROR; + } + + // If transfer was okay, return success + return S1_SUCCESS; } -s1_error_t flash_tx_rx(uint8_t *tx_buffer, size_t tx_len, - uint8_t *rx_buffer, size_t rx_len) +/** + * @brief Performs a transfer on the SPI bus to the flash or FPGA. + * + * @param tx_buffer: A pointer to where the transmit data is stored. + * + * @param tx_len: Length of the transmit data buffer in bytes. i.e how many + * bytes to write. + * + * @param rx_buffer: A pointer to to where the receive data will be stored. + * + * @param rx_len: Length of the receive buffer in bytes. i.e how many bytes to + * read. + * + * @param sel_fpga: If true, selects the FPGA. If false, selects the flash. + * + * @returns S1_SUCCESS if okay, + * S1_FLASH_FPGA_COMMUNICATION_ERROR if spi bus is busy, or the buffers + * are not within the ram region. i.e not writable. + */ +static s1_error_t spi_tx_rx(uint8_t *tx_buffer, size_t tx_len, + uint8_t *rx_buffer, size_t rx_len, bool sel_fpga) { // SPI hardware configuration nrfx_spim_config_t spi_config = NRFX_SPIM_DEFAULT_CONFIG; @@ -79,15 +169,149 @@ s1_error_t flash_tx_rx(uint8_t *tx_buffer, size_t tx_len, spi_config.sck_pin = SPI_CLK_PIN; spi_config.ss_pin = SPI_CS_PIN; + // If selecting the FPGA, invert the chip select line + if (sel_fpga) + { + spi_config.ss_active_high = true; + } + // Initialise the SPI if it was not already nrfx_spim_init(&spi, &spi_config, NULL, NULL); + // Transfer descriptor for how many bytes to read and write nrfx_spim_xfer_desc_t spi_xfer = NRFX_SPIM_XFER_TRX(tx_buffer, tx_len, rx_buffer, rx_len); - APP_ERROR_CHECK(nrfx_spim_xfer(&spi, &spi_xfer, 0)); + // Initiate the transfer + nrfx_err_t err = nrfx_spim_xfer(&spi, &spi_xfer, 0); - // TODO return error code for SPI errors + // If an error occurs, return a flash error + if (err != NRFX_SUCCESS) + { + return S1_FLASH_FPGA_COMMUNICATION_ERROR; + } + + // If transfer was okay, return success + return S1_SUCCESS; +} + +/** + * @brief Interrupt routine for when the FPGA configuration is complete, and the + * CDONE pin goes high. + * + * @param pin: Pin that caused the trigger. + * + * @param action: The polarity of the interrupt trigger. + */ +static void fpga_done_pin_interrupt(nrfx_gpiote_pin_t pin, + nrf_gpiote_polarity_t action) +{ + if (pin == FPGA_DONE_PIN && action == NRF_GPIOTE_POLARITY_LOTOHI) + { + fpga_done_flag_pending = true; + } +} + +s1_error_t s1_init(void) +{ + // Configure FPGA reset pin as an output. A low signal holds FPGA in reset + nrf_gpio_cfg_output(FPGA_RESET_PIN); + + // Set up done pin as an interrupt. It goes high when the FPGA is loaded + nrfx_gpiote_in_config_t config = NRFX_GPIOTE_CONFIG_IN_SENSE_LOTOHI(true); + config.pull = NRF_GPIO_PIN_PULLUP; + + // Start the GPIOTE driver if not already started + nrfx_gpiote_init(); + + // Add the pin as an input event + nrfx_err_t err = + nrfx_gpiote_in_init(FPGA_DONE_PIN, &config, fpga_done_pin_interrupt); + + // If an error occurs, return an initialisation error + if (err != NRFX_SUCCESS) + { + return S1_INIT_ERROR; + } + + // Enable the event + nrfx_gpiote_in_event_enable(FPGA_DONE_PIN, true); + + // Configure the I2C + nrfx_twim_config_t pmic_twi_config = NRFX_TWIM_DEFAULT_CONFIG; + pmic_twi_config.scl = NRF_GPIO_PIN_MAP(0, 17); + pmic_twi_config.sda = NRF_GPIO_PIN_MAP(0, 14); + + // Initialise the I2C driver + err = nrfx_twim_init(&i2c, &pmic_twi_config, NULL, NULL); + + // If an error occurs, return an initialisation error + if (err != NRFX_SUCCESS) + { + return S1_INIT_ERROR; + } + + // Enable the bus + nrfx_twim_enable(&i2c); + + // Check PMIC Chip ID + uint8_t pmic_chip_id; + s1_error_t s1_err = pmic_read_reg(0x14, &pmic_chip_id); + + // If an error occurs, return a PMIC communication error + if (s1_err != S1_SUCCESS) + { + return S1_PMIC_COMMUNICATION_ERROR; + } + + // If the chip ID is incorrect, also return a PMIC communication error + if (pmic_chip_id != 0x7A) + { + return S1_PMIC_COMMUNICATION_ERROR; + } + + // TODO setup analog pins here + + // Return success once complete + return S1_SUCCESS; +} + +s1_error_t s1_pmic_get_chg(float *voltage, float *current) +{ + uint8_t reg_value; + + // Read the charge voltage register + s1_error_t err = pmic_read_reg(0x26, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Shift down to get only the top 6 bits + reg_value = reg_value >> 2; + + // Convert the register value to a voltage + *voltage = (reg_value * 0.025f) + 3.6f; + + // Read the charge current register + err = pmic_read_reg(0x24, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Shift down to get only the top 6 bits + reg_value = reg_value >> 2; + + // Convert the register value to a current (mA) + *current = (reg_value * 7.5f) + 7.5f; + + // Return success once complete + return S1_SUCCESS; } s1_error_t s1_pmic_set_chg(float voltage, float current) @@ -95,109 +319,479 @@ s1_error_t s1_pmic_set_chg(float voltage, float current) // Check if voltage is a valid range if (voltage < 3.6f || voltage > 4.6f) { - return S1_INVALID_SETTING; + return S1_PMIC_INVALID_VALUE; } - // Set charger target voltage - uint8_t voltage_setting = (uint8_t)((voltage - 3.6f) / 0.025f) << 2; - pmic_write_reg(0x26, voltage_setting | 0b00); - // Check if the current is a valid range if (current < 7.5f || current > 300.0f) { - return S1_INVALID_SETTING; + return S1_PMIC_INVALID_VALUE; + } + + // Set the charging voltage (shifted to be in the top 6 bits of the register) + uint8_t voltage_setting = (uint8_t)round((voltage - 3.6f) / 0.025f) << 2; + + // Apply the voltage, and ensure charging is allowed + s1_error_t err = pmic_write_reg(0x26, voltage_setting | 0b00); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Set the charging current (shifted to be in the top 6 bits of the register) + uint8_t current_setting = (uint8_t)round((current - 7.5f) / 7.5f) << 2; + + // Apply the current, and ensure a 3hr safety timer is set + err = pmic_write_reg(0x24, current_setting | 0b01); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Return success once complete + return S1_SUCCESS; +} + +s1_error_t s1_pmic_get_vaux(float *voltage) +{ + uint8_t reg_value; + + // Read the SBB2 register + s1_error_t err = pmic_read_reg(0x2E, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; } - // Set charge constant current value and keep 3hr safety timer - uint8_t current_setting = (uint8_t)((current - 7.5f) / 7.5f) << 2; - pmic_write_reg(0x24, current_setting | 0b01); + // Check if SBB2 is enabled + bool vaux_en = (reg_value & 0b110) == 0b110; + + // If SBB2 is off, return 0V + if (vaux_en == false) + { + *voltage = 0.0f; + return S1_SUCCESS; + } + + // Otherwise read the current set value + err = pmic_read_reg(0x2D, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // We only need the bottom 7 bits + reg_value = reg_value & 0x7F; + + // Convert the register value to a voltage + *voltage = (reg_value * 0.05f) + 0.8f; + + // Return success once complete + return S1_SUCCESS; } s1_error_t s1_pmic_set_vaux(float voltage) { - // Check if voltage is a valid range + // If 0V, shutdown SBB2 + if (voltage == 0.0f) + { + // Write to the SBB2 en register + s1_error_t err = pmic_write_reg(0x2E, 0x0C); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Return success once complete + return S1_SUCCESS; + } + + // Disallow voltage settings outside of the normal range if (voltage < 0.8f || voltage > 5.5f) { - return S1_INVALID_SETTING; + return S1_PMIC_INVALID_VALUE; } - // If voltage > than 3.46, then LDO0 must not - // be in LSW mode. - if (voltage > 3.46f && (pmic_read_reg(0x39) & 0x08)) + // If voltage > than 3.45 + if (voltage > 3.45f) { - return S1_INVALID_SETTING; + uint8_t reg_value; + + // Read the mode of SBB2 + s1_error_t err = pmic_read_reg(0x39, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // LDO0 must not be in LSW mode, otherwise it'll blow up the FPGA + if ((reg_value & 0x10) == 0x10) + { + return S1_PMIC_INVALID_VALUE; + } } - // If 0V, we shutdown the SSB2 - if (voltage == 0.0f) + // Set the SBB2 target voltage + s1_error_t err = pmic_write_reg(0x2D, (uint8_t)round((voltage - 0.8f) / 0.05f)); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Enable SBB2 as buck-boost, with 1A limit, and discharge resistor enabled + err = pmic_write_reg(0x2E, 0x0E); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Return success once complete + return S1_SUCCESS; +} + +s1_error_t s1_pmic_get_vio(float *voltage, bool *lsw_mode) +{ + uint8_t reg_value; + + // Read the LSW/LDO mode + s1_error_t err = pmic_read_reg(0x39, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) { - pmic_write_reg(0x2E, 0x0C); + return err; + } + + // If in load switch mode + if ((reg_value & 0x10) == 0x10) + { + // Set LSW mode pointer to true + *lsw_mode = true; + + // Check if load switch mode is enabled + if ((reg_value & 0b110) == 0b110) + { + // Set voltage to true + *voltage = 1.0f; + + // Read SBB2 active register + err = pmic_read_reg(0x2E, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // If SBB2 is disabled, notify the user + if ((reg_value & 0b110) != 0b110) + { + return S1_PMIC_VAUX_NOT_ENABLED; + } + + // Return success + return S1_SUCCESS; + } + + // Otherwise set the voltage to false + *voltage = 0.0f; + + // Return success return S1_SUCCESS; } - // Set LDO target voltage - uint8_t voltage_setting = (uint8_t)((voltage - 0.8f) / 0.05f); - pmic_write_reg(0x2D, voltage_setting); + // If in LDO mode + if ((reg_value & 0b110) == 0b110) + { + // Set LSW mode pointer to false + *lsw_mode = false; + + // Read the LDO set voltage + err = pmic_read_reg(0x38, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Convert the register value into a voltage (mask 7 bits) + *voltage = ((float)(reg_value & 0x7F) * 0.025f) + 0.8f; + + // Read the SBB2 (Vaux) register + err = pmic_read_reg(0x2D, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Convert the register value into a voltage + float sbb2_voltage = ((float)(reg_value & 0x7F) * 0.05f) + 0.8f; + + // If sbb2 voltage is too low (including the 100mV dropout) + if (sbb2_voltage < *voltage + 0.1f) + { + // Notify the user + return S1_PMIC_VAUX_TOO_LOW; + } + + // Read SBB2 active register + err = pmic_read_reg(0x2E, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // If SBB2 is disabled, notify the user + if ((reg_value & 0b110) != 0b110) + { + return S1_PMIC_VAUX_NOT_ENABLED; + } + + // Return success once read + return S1_SUCCESS; + } - // Enable SSB2 - // - Buck Boost mode - // - Discharge resistor enable - // - 1A limit - pmic_write_reg(0x2E, 0x0E); + // Otherwise LDO0 is 0V + *voltage = 0.0f; + // Return success once complete return S1_SUCCESS; } -s1_error_t s1_pmic_set_vio(float voltage) +s1_error_t s1_pmic_set_vio(float voltage, bool lsw_mode) { - // Check if voltage is a valid range - // 3.46V limit is to protect FPGA - if (voltage < 0.8f || voltage > 3.46f) + uint8_t reg_value; + + // Read the SBB1 register + s1_error_t err = pmic_read_reg(0x2C, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) { - return S1_INVALID_SETTING; + return err; } - // If 0V, we shutdown the LDO + // Check if fpga is powered off + if ((reg_value & 0b10) == 0) + { + // Prevent configuration if FPGA core rail is off + return S1_PMIC_VFPGA_NOT_ENABLED; + } + + // If the lsw flag was provided + if (lsw_mode) + { + // Read SBB2 set voltage + err = pmic_read_reg(0x2D, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Ensure it is below the 3.45V limit of the FPGA IO + // reg_value = (3.45 - 0.8) / 0.05 = 53 + if ((reg_value & 0x7F) > 53) + { + return S1_PMIC_VAUX_TOO_HIGH; + } + + // If the voltage value is greater than 0V + if (voltage > 0.0f) + { + // Turn on the regulator with LSW mode with discharge enabled + err = pmic_write_reg(0x39, 0x1E); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Return + return S1_SUCCESS; + } + + // Otherwise, turn off the regulator with LSW mode with discharge enabled + err = pmic_write_reg(0x39, 0x1C); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Return + return S1_SUCCESS; + } + + // If user requests 0V if (voltage == 0.0f) { - pmic_write_reg(0x39, 0x0C); + // Turn off the regulator, ensuring LDO mode and discharge resistor is set + err = pmic_write_reg(0x39, 0x0C); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Return return S1_SUCCESS; } - // Set LDO target voltage - uint8_t voltage_setting = (uint8_t)((voltage - 0.8f) / 0.025f); - pmic_write_reg(0x38, voltage_setting); + // Disallow voltage settings outside of the normal range + if (voltage < 0.8f || voltage > 3.45f) + { + return S1_PMIC_INVALID_VALUE; + } + + // Set the output voltage + err = pmic_write_reg(0x38, (uint8_t)round((voltage - 0.8f) / 0.025f)); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } - // Enable LDO0 - // - LDO regulator mode - // - Discharge resistor active - // - Enable - pmic_write_reg(0x39, 0x0E); + // Turn on the regulator with LDO mode set, and discharge enabled + err = pmic_write_reg(0x39, 0x0E); + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Otherwise, check SBB2 (Vaux) set voltage + err = pmic_read_reg(0x2D, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Convert the register value into a voltage (mask 7 bits) + float sbb2_voltage = ((float)(reg_value & 0x7F) * 0.05f) + 0.8f; + + // If sbb2 voltage is too low (including the 100mV dropout) + if (sbb2_voltage < voltage + 0.1f) + { + // Notify the user + return S1_PMIC_VAUX_TOO_LOW; + } + + // Read SBB2 active register + err = pmic_read_reg(0x2E, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // If SBB2 is disabled, notify the user + if ((reg_value & 0b110) != 0b110) + { + return S1_PMIC_VAUX_NOT_ENABLED; + } + + // Return success once complete + return S1_SUCCESS; +} + +s1_error_t s1_pimc_get_vfpga(bool *enable) +{ + uint8_t reg_value; + + // Read the SBB1 register + s1_error_t err = pmic_read_reg(0x2C, ®_value); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Return the value. Second bit represents on or off + *enable = reg_value & 0b10; + + // Return success once complete return S1_SUCCESS; } -void s1_pimc_fpga_vcore(bool enable) +s1_error_t s1_pimc_set_vfpga(bool enable) { - // Ensure SSB1 is 1.2V - pmic_write_reg(0x2B, 0x08); + // Ensure SBB1 is 1.2V (TODO later we can do undervolting tricks) + s1_error_t err = pmic_write_reg(0x2B, 0x08); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } // If enable if (enable) { - // Enable SSB1 - // - 0.333A limit - // - Buck mode - pmic_write_reg(0x2C, 0x7E); - return; + // Enable SBB1 as buck mode with 0.333A limit + err = pmic_write_reg(0x2C, 0x7E); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Return success once complete + return S1_SUCCESS; } - // Disable LDO0 (Vio). Required to avoid - // IO voltages damaging the FPGA core. - pmic_write_reg(0x39, 0x0C); + // Otherwise, first disable LDO0 (Vio) to avoid damaging the FPGA + err = pmic_write_reg(0x39, 0x0C); - // Disable SSB1 (Vfpga) - pmic_write_reg(0x2C, 0x7C); + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Finally, disable SBB1 + err = pmic_write_reg(0x2C, 0x7C); + + // If an error occurs, return it + if (err != S1_SUCCESS) + { + return err; + } + + // Return success once complete + return S1_SUCCESS; } s1_error_t s1_flash_wakeup(void) @@ -205,19 +799,19 @@ s1_error_t s1_flash_wakeup(void) // Wake up the flash uint8_t wake_seq[4] = {0xAB, 0, 0, 0}; uint8_t wake_res[5] = {0}; - flash_tx_rx((uint8_t *)&wake_seq, 4, (uint8_t *)&wake_res, 5); + spi_tx_rx((uint8_t *)&wake_seq, 4, (uint8_t *)&wake_res, 5, false); NRFX_DELAY_US(3); // tRES1 required to come out of sleep // Reset sequence has to happen as two transfers uint8_t reset_seq[3] = {0x66, 0x99}; - flash_tx_rx((uint8_t *)&reset_seq, 1, NULL, 0); - flash_tx_rx((uint8_t *)&reset_seq + 1, 1, NULL, 0); + spi_tx_rx((uint8_t *)&reset_seq, 1, NULL, 0, false); + spi_tx_rx((uint8_t *)&reset_seq + 1, 1, NULL, 0, false); NRFX_DELAY_US(30); // tRST to fully reset // Check if the capacity ID corresponds to 32M uint8_t cap_id_reg[1] = {0x9F}; uint8_t cap_id_res[4] = {0}; - flash_tx_rx((uint8_t *)&cap_id_reg, 1, (uint8_t *)&cap_id_res, 4); + spi_tx_rx((uint8_t *)&cap_id_reg, 1, (uint8_t *)&cap_id_res, 4, false); if (cap_id_res[3] != 0x16) { @@ -231,8 +825,8 @@ void s1_flash_erase_all(void) { // Issue erase sequence uint8_t erase_seq[2] = {0x06, 0x60}; - flash_tx_rx((uint8_t *)&erase_seq, 1, NULL, 0); - flash_tx_rx((uint8_t *)&erase_seq + 1, 1, NULL, 0); + spi_tx_rx((uint8_t *)&erase_seq, 1, NULL, 0, false); + spi_tx_rx((uint8_t *)&erase_seq + 1, 1, NULL, 0, false); } bool s1_flash_is_busy(void) @@ -240,7 +834,7 @@ bool s1_flash_is_busy(void) // Read status register uint8_t status_reg[1] = {0x05}; uint8_t status_res[2] = {0}; - flash_tx_rx((uint8_t *)&status_reg, 1, (uint8_t *)&status_res, 2); + spi_tx_rx((uint8_t *)&status_reg, 1, (uint8_t *)&status_res, 2, false); if (!(status_res[1] & 0x01)) { @@ -250,16 +844,16 @@ bool s1_flash_is_busy(void) return true; } -s1_error_t s1_flash_page_from_image(uint32_t offset, - unsigned char *image) +void s1_flash_page_from_image(uint32_t offset, + unsigned char *image) { uint8_t tx[260]; // Disable write protection tx[0] = 0x06; - flash_tx_rx((uint8_t *)&tx, 1, NULL, 0); + spi_tx_rx((uint8_t *)&tx, 1, NULL, 0, false); - // Write page comand with 24bit address + // Write page command with 24bit address // Lowest byte of address is always 0 tx[0] = 0x02; tx[1] = (uint8_t)(offset >> 16); @@ -268,9 +862,13 @@ s1_error_t s1_flash_page_from_image(uint32_t offset, // Copy page from image and transfer memcpy(tx + 4, image + offset, 256); - flash_tx_rx((uint8_t *)&tx, 260, NULL, 0); + spi_tx_rx((uint8_t *)&tx, 260, NULL, 0, false); +} - // TODO include return codes for SPI errors +s1_error_t flash_tx_rx(uint8_t *tx_buffer, size_t tx_len, + uint8_t *rx_buffer, size_t rx_len) +{ + return spi_tx_rx(tx_buffer, tx_len, rx_buffer, rx_len, false); } void s1_fpga_hold_reset(void) @@ -294,14 +892,6 @@ void s1_fpga_boot(void) nrf_gpio_pin_set(FPGA_RESET_PIN); } -void fpga_done_pin_interrupt(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) -{ - if (pin == FPGA_DONE_PIN && action == NRF_GPIOTE_POLARITY_LOTOHI) - { - fpga_done_flag_pending = true; - } -} - bool s1_fpga_is_booted(void) { if (fpga_done_flag_pending) @@ -312,32 +902,8 @@ bool s1_fpga_is_booted(void) return false; } -s1_error_t s1_init(void) +s1_error_t fpga_tx_rx(uint8_t *tx_buffer, size_t tx_len, + uint8_t *rx_buffer, size_t rx_len) { - // Configure FPGA reset pin as output (low signal holds FPGA in reset) - nrf_gpio_cfg_output(FPGA_RESET_PIN); - - // Set up done pin as an interrupt. Goes high when configuration is done - nrfx_gpiote_in_config_t config = NRFX_GPIOTE_CONFIG_IN_SENSE_LOTOHI(true); - config.pull = NRF_GPIO_PIN_PULLUP; - APP_ERROR_CHECK(nrfx_gpiote_init()); - APP_ERROR_CHECK(nrfx_gpiote_in_init(FPGA_DONE_PIN, &config, fpga_done_pin_interrupt)); - nrfx_gpiote_in_event_enable(FPGA_DONE_PIN, true); - - // I2C hardware configuration - nrfx_twim_config_t pmic_twi_config = NRFX_TWIM_DEFAULT_CONFIG; - pmic_twi_config.scl = PMIC_SCL_PIN; - pmic_twi_config.sda = PMIC_SDA_PIN; - APP_ERROR_CHECK(nrfx_twim_init(&i2c, &pmic_twi_config, NULL, NULL)); - nrfx_twim_enable(&i2c); - - // Check PMIC Chip ID - if (pmic_read_reg(0x14) != 0x7A) - { - return S1_PMIC_ERROR; - } - - // TODO setup analog pins here? - - return S1_SUCCESS; + return spi_tx_rx(tx_buffer, tx_len, rx_buffer, rx_len, true); } \ No newline at end of file diff --git a/s1.h b/s1.h index 906fbb1..0bb7648 100644 --- a/s1.h +++ b/s1.h @@ -1,40 +1,42 @@ /** * @file s1.h + * * @brief S1 Module Core API - * - * Use these functions and macros to configure the S1 Module. All APIs + * + * Use these functions and macros to configure the S1 Module. All APIs * are documented here, and organized by category. - * - * @attention Copyright 2021 Silicon Witchery AB * - * Permission to use, copy, modify, and/or distribute this software for any + * @attention Copyright 2022 Silicon Witchery AB + * + * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH - * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, - * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR - * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR * PERFORMANCE OF THIS SOFTWARE. */ #ifndef _S1_H_ #define _S1_H_ +#include #include "SEGGER_RTT.h" #include "sdk_config.h" /** * @brief Release version of this SDK */ -#define __S1_SDK_VERSION__ "0.3" +#define __S1_SDK_VERSION__ "1.0" /** * @brief Pinout definitions for the nRF52811 chip on the S1 Module. This isn't - * the pinout of the module itself, but rather the internal connections. - * Use them if you want to access the ADC, SPI or Flash + * the pinout of the module itself, but rather the internal connections. + * Use them if you want to access the ADC, SPI or Flash */ #define ADC1_PIN NRF_SAADC_INPUT_AIN2 #define ADC1_PIN_AS_GPIO NRF_GPIO_PIN_MAP(0, 4) @@ -53,9 +55,15 @@ typedef enum { S1_SUCCESS = 0, - S1_PMIC_ERROR, + S1_INIT_ERROR, + S1_PMIC_COMMUNICATION_ERROR, + S1_PMIC_INVALID_VALUE, + S1_PMIC_VAUX_NOT_ENABLED, + S1_PMIC_VAUX_TOO_LOW, + S1_PMIC_VAUX_TOO_HIGH, + S1_PMIC_VFPGA_NOT_ENABLED, + S1_FLASH_FPGA_COMMUNICATION_ERROR, S1_FLASH_ERROR, - S1_INVALID_SETTING, } s1_error_t; /** @@ -65,95 +73,142 @@ typedef enum * configuration previously called, so this can be called from a deep * sleep state in order to reconfigure the IO without changing power * settings. - * - * @return S1_SUCCESS if okay. Error otherwise. + * + * @return S1_SUCCESS if okay, + * S1_INIT_ERROR if GPIOTE or I2C resources are already used, + * S1_PMIC_COMMUNICATION_ERROR if the PMIC did not respond. */ s1_error_t s1_init(void); /******************************************************* - * Power related APIs + * Power related functions *******************************************************/ +/** + * @brief Gets the current settings of the Li charger. + * + * @param voltage: A pointer to where the currently configured set voltage of + * the charger should be stored. + * + * @param current: A pointer to where the currently configured constant current + * setting of the charger should be stored. + * + * @returns S1_SUCCESS if okay, + * S1_PMIC_COMMUNICATION_ERROR if the PMIC did not respond. + */ +s1_error_t s1_pmic_get_chg(float *voltage, float *current); + /** * @brief Sets the charger target voltage and constant current values. Note that * setting incorrect values may damage a connected battery and cause fire * or burns. It's important to check that this configuration matches the * real measured values once a battery is connected. - * + * * @param voltage: The battery max voltage. For Li-Po, this is typically 4.2V. * Can be set between 3.6V and 4.6V in 0.025mV steps. - * + * * @param current: The charging current limit. This should typically be set * to no more than 1 x the mAh capacity of the battery. Can be * set between 7.5mA and 300mA in 7.5mA steps. - * - * @returns S1 status if okay. Error otherwise. + * + * @returns S1_SUCCESS if okay, + * S1_PMIC_COMMUNICATION_ERROR if the PMIC did not respond. */ s1_error_t s1_pmic_set_chg(float voltage, float current); /** - * @brief Set Vaux voltage. Can be set from 0.8V to 5.5V in 50mV steps. Will + * @brief Gets the current Vaux set voltage. + * + * @param voltage: A pointer to where the ready voltage should be stored. + * + * @returns S1_SUCCESS if okay, + * S1_PMIC_COMMUNICATION_ERROR if the PMIC did not respond. + */ +s1_error_t s1_pmic_get_vaux(float *voltage); + +/** + * @brief Set Vaux voltage. Can be set from 0.8V to 5.5V in 50mV steps. Will * return false if Vio is set to Load Switch mode, and Vaux is set to a * value greater than 3.46V. This is to protect the FPGA. - * - * @param voltage: Voltage level. Automatically rounded to the nearest 50mV. A - * value of 0V shuts down the rail. - * - * @returns S1_SUCCESS if okay. Error otherwise. + * + * @param voltage: Voltage level. Automatically rounded to the nearest 50mV. A + * value of 0V shuts down the rail. + * + * @returns S1_SUCCESS if okay, + * S1_PMIC_INVALID_VALUE if voltage is not a valid range, + * S1_PMIC_COMMUNICATION_ERROR if the PMIC did not respond. */ s1_error_t s1_pmic_set_vaux(float voltage); /** - * @brief Set Vio voltage. Can be set from 0.8V to 3.46V in 25mV steps. - * - * @param voltage: Voltage level. Automatically rounded to the nearest 25mV. A - * value of 0V shuts down the rail. - * - * @return S1_SUCCESS if okay. Error otherwise. + * @brief Gets the current Vio set voltage, or the mode of the load switch. + * + * @param voltage: A pointer to where the read voltage should be stored. If + * lsw_mode is true, a voltage of 0 signifies the load switch is + * off, and a value of 1 signifies the load switch is on. + * + * @param lsw_mode: A pointer to where the load swich mode should be stored. + * True if load switch mode is active, false if LDO mode is + * active. + * + * @returns S1_SUCCESS if okay, + * S1_PMIC_VAUX_NOT_ENABLED if Vio is not powered from Vaux, + * S1_PMIC_VAUX_TOO_LOW if Vaux is too low for the LDO to regulate, + * S1_PMIC_COMMUNICATION_ERROR if the PMIC did not respond. */ -s1_error_t s1_pmic_set_vio(float voltage); +s1_error_t s1_pmic_get_vio(float *voltage, bool *lsw_mode); /** - * @brief Switches Vio between Low Dropout Regulator mode and Load Switch mode. - * In Load switch mode, Vio outputs the same voltage as Vaux. Vio cannot - * be set to load switch mode if Vaux greater than 3.46V. This is to - * protect the FPGA. - * - * @param enable: True enables load switch mode, false switches back to - * regulated mode. - * - * @return S1_SUCCESS if okay. Error otherwise. + * @brief Set Vio voltage. Can be set from 0.8V to 3.46V in 25mV steps. + * + * @param voltage: Voltage level. Automatically rounded to the nearest 25mV. A + * value of 0V shuts down the rail. If in load switch mode, a + * value of 0 shuts off the load switch, a value greater than 0 + * turns on the load switch. + * + * @param lsw_mode: If the mode of Vio should be load switch, or LDO. If true, + * the load switch passes through the Vaux voltage, otherwise + * Vio is regulated by an LDO. + * + * @returns S1_SUCCESS if okay, + * S1_PMIC_VAUX_NOT_ENABLED if Vio is not powered from Vaux, + * S1_PMIC_VFPGA_NOT_ENABLED if Vfpga needs to be activated first, + * S1_PMIC_VAUX_TOO_HIGH if Vaux is too high for the load switch mode, + * S1_PMIC_INVALID_VALUE if voltage is not a valid range, + * S1_PMIC_VAUX_TOO_LOW if Vaux is too low for Vio to properly regulate, + * S1_PMIC_COMMUNICATION_ERROR if the PMIC did not respond. */ -s1_error_t s1_pmic_set_vio_lsw(bool enable); +s1_error_t s1_pmic_set_vio(float voltage, bool lsw_mode); /** - * @brief Set Vio voltage. Can be set from 1.7V to 2.0V in 50mV steps. - * - * @param voltage: Voltage level. Automatically rounded to the nearest 50mV. - * - * @returns S1_SUCCESS if okay. Error otherwise. + * @brief Gets the enable state of the FPGA core voltage. + * + * @param enable: A pointer to where the enable value should be stored. + * + * @returns S1_SUCCESS if okay, + * S1_PMIC_COMMUNICATION_ERROR if the PMIC did not respond. */ -s1_error_t s1_pmic_set_vadc(float voltage); +s1_error_t s1_pimc_get_vfpga(bool *enable); /** - * @brief Enable FPGA core and FPGA PLL voltages to 1.2V Disabling also shuts - * down Vio. + * @brief Sets the enable state of the FPGA core voltage. * - * @param enable: Enable the core voltage. + * @param enable: If true, the FPGA is powered, if false the FPGA is shut down. + * + * @returns S1_SUCCESS if okay, + * S1_PMIC_COMMUNICATION_ERROR if the PMIC did not respond. */ -void s1_pimc_fpga_vcore(bool enable); - -void pmic_enable_charging(); +s1_error_t s1_pimc_set_vfpga(bool enable); /******************************************************* - * Flash related APIs + * Flash related functions *******************************************************/ /** * @brief Wakes up the flash if it's asleep. - * - * @return S1_SUCCESS if okay, or S1_FLASH_ERROR if the chip isn't responding - * correctly. + * + * @return S1_SUCCESS if okay, + * S1_FLASH_ERROR if the flash IC did not respond as expected. */ s1_error_t s1_flash_wakeup(void); @@ -163,36 +218,55 @@ s1_error_t s1_flash_wakeup(void); void s1_flash_erase_all(void); /** - * @brief Check if the flash is busy. - * - * @return true if busy. + * @brief Checks if the flash is currently busy with an erase or write operation. + * + * @return True if busy, + * False if idle. */ bool s1_flash_is_busy(void); /** - * @brief Flashes a page at offset address to the flash. - * + * @brief Flashes a page to the flash at a given offset. + * * @param offset: Page offset to flash. - * + * * @param image: Pointer to the start of the binary you wish to flash. - * - * @return true if busy. */ -s1_error_t s1_flash_page_from_image(uint32_t offset, - unsigned char *image); +void s1_flash_page_from_image(uint32_t offset, + unsigned char *image); + +/** + * @brief Performs a transfer on the SPI bus to the flash IC. + * + * @param tx_buffer: A pointer to where the transmit data is stored. + * + * @param tx_len: Length of the transmit data buffer in bytes. i.e how many + * bytes to write. + * + * @param rx_buffer: A pointer to to where the receive data will be stored. + * + * @param rx_len: Length of the receive buffer in bytes. i.e how many bytes to + * read. + * + * @returns S1_SUCCESS if okay, + * S1_FLASH_FPGA_COMMUNICATION_ERROR if spi bus is busy, or the buffers + * are not within the ram region. i.e not writable. + */ +s1_error_t flash_tx_rx(uint8_t *tx_buffer, size_t tx_len, + uint8_t *rx_buffer, size_t rx_len); /******************************************************* - * FPGA related APIs + * FPGA related functions *******************************************************/ /** - * @brief Puts the FPGA into reset. Reccomended to wait 200uS before a - * subsequent flash/fpga operation. + * @brief Puts the FPGA into reset. It's recommended to wait 200uS before a + * subsequent flash or fpga operation. */ void s1_fpga_hold_reset(void); /** - * @brief Passes SPI control to the flash, and releases the FPGA reset to allow + * @brief Passes SPI control to the flash, and releases the FPGA reset to allow * it to boot. This function must be called before communication can be * made between the nRF and the FPGA directly. */ @@ -203,11 +277,34 @@ void s1_fpga_boot(void); * device has correctly configured. Note that this pin may not activate * if the CDONE pin is controlled by the FPGA application to be used for * something else. + * + * @returns True if booted, + * False if reset, or the image could not boot. */ bool s1_fpga_is_booted(void); +/** + * @brief Performs a transfer on the SPI bus to the FPGA. + * + * @param tx_buffer: A pointer to where the transmit data is stored. + * + * @param tx_len: Length of the transmit data buffer in bytes. i.e how many + * bytes to write. + * + * @param rx_buffer: A pointer to to where the receive data will be stored. + * + * @param rx_len: Length of the receive buffer in bytes. i.e how many bytes to + * read. + * + * @returns S1_SUCCESS if okay, + * S1_FLASH_FPGA_COMMUNICATION_ERROR if spi bus is busy, or the buffers + * are not within the ram region. i.e not writable. + */ +s1_error_t fpga_tx_rx(uint8_t *tx_buffer, size_t tx_len, + uint8_t *rx_buffer, size_t rx_len); + /******************************************************* - * RTT based logging Macros + * RTT based logging macros *******************************************************/ /** @@ -216,20 +313,20 @@ bool s1_fpga_is_booted(void); #define LOG_CLEAR() SEGGER_RTT_printf(0, RTT_CTRL_CLEAR "\r"); /** - * @brief A println style logging macro. You can use all the standard printf + * @brief A println style logging macro. You can use all the standard printf * flags. It uses LOG_RAW() */ #define LOG(format, ...) LOG_RAW("\r\n" format, ##__VA_ARGS__) /** - * @brief Logging macro which outputs printf style logs over a JLink debugger. + * @brief Logging macro which outputs printf style logs over a JLink debugger. * To view the terminal, run JLinkRTTViewer.exe. If a debug session is * already active, JLinkRTTClient.exe should be used. Read more about RTT * here: https://wiki.segger.com/RTT - * + * * @param format: printf style format string. - * + * * @param ...: Variadic argument list for printf data. */ #define LOG_RAW(format, ...) \ diff --git a/s1_tests/s1_tests.c b/s1_tests/s1_tests.c new file mode 100644 index 0000000..5da83e7 --- /dev/null +++ b/s1_tests/s1_tests.c @@ -0,0 +1,259 @@ +/** + * @file s1_tests.c + * + * @brief S1 Module tests. + * + * If no main() function is provided, the S1 SDK will automatically build + * this test application. It can be useful to checking proper + * functionality of your device. + * + * @attention Copyright 2022 Silicon Witchery AB + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH + * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, + * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM + * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR + * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "s1.h" + +/** + * @brief Macro for logging passed tests in green. + */ +#define LOG_PASS(cond, format, ...) \ + do \ + { \ + if (cond) \ + { \ + char _debug_log_buffer[SEGGER_RTT_CONFIG_BUFFER_SIZE_UP - 1] = ""; \ + snprintf(_debug_log_buffer, SEGGER_RTT_CONFIG_BUFFER_SIZE_UP - 1, \ + "\r\n" RTT_CTRL_TEXT_BRIGHT_GREEN "[PASS] " RTT_CTRL_RESET format, ##__VA_ARGS__); \ + SEGGER_RTT_Write(0, _debug_log_buffer, strnlen(_debug_log_buffer, SEGGER_RTT_CONFIG_BUFFER_SIZE_UP)); \ + } \ + } while (0) + +/** + * @brief Macro for logging failed tests in red. + */ +#define LOG_FAIL(cond, format, ...) \ + do \ + { \ + if (cond) \ + { \ + char _debug_log_buffer[SEGGER_RTT_CONFIG_BUFFER_SIZE_UP - 1] = ""; \ + snprintf(_debug_log_buffer, SEGGER_RTT_CONFIG_BUFFER_SIZE_UP - 1, \ + "\r\n" RTT_CTRL_TEXT_BRIGHT_RED "[FAIL] " RTT_CTRL_RESET format, ##__VA_ARGS__); \ + SEGGER_RTT_Write(0, _debug_log_buffer, strnlen(_debug_log_buffer, SEGGER_RTT_CONFIG_BUFFER_SIZE_UP)); \ + } \ + } while (0) + +/** + * @brief Test application. + */ +int main(void) +{ + // Error variable we'll use to check all the functions + s1_error_t err; + + // Log some stuff about this project + LOG_CLEAR(); + LOG("S1 Module Tests – Built: %s %s – SDK Version: %s.", + __DATE__, + __TIME__, + __S1_SDK_VERSION__); + + // Initialise the S1 module + err = s1_init(); + LOG_PASS(err == S1_SUCCESS, "S1 started"); + LOG_FAIL(err != S1_SUCCESS, "S1 init error. Code: %d", err); + + // Set the rails to default values + LOG("[INFO] Setting all rails to default values"); + err = s1_pmic_set_vaux(3.55f); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vaux() returned the error code %d", err); + err = s1_pmic_set_vio(3.0f, false); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vio() returned the error code %d", err); + err = s1_pimc_set_vfpga(false); + LOG_FAIL(err != S1_SUCCESS, "s1_pimc_set_vfpga() returned the error code %d", err); + + // Enable Vio and Vfpga to their nominal voltages + LOG("[INFO] Enabling Vfpga and Vio to their nominal voltages"); + err = s1_pimc_set_vfpga(true); + LOG_FAIL(err != S1_SUCCESS, "s1_pimc_set_vfpga() returned the error code %d", err); + err = s1_pmic_set_vio(1.8f, false); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vio() returned the error code %d", err); + + float vio; + bool lsw_mode; + err = s1_pmic_get_vio(&vio, &lsw_mode); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_get_vio() returned the error code %d", err); + LOG_FAIL(vio != 1.8f || lsw_mode == true, "Vio did not configure correctly"); + LOG_PASS(vio == 1.8f && lsw_mode == false, "Vio started correctly"); + + bool vfpga_enabled; + err = s1_pimc_get_vfpga(&vfpga_enabled); + LOG_FAIL(err != S1_SUCCESS, "s1_pimc_get_vfpga() returned the error code %d", err); + LOG_FAIL(vfpga_enabled == false, "Vfpga did not enable"); + LOG_PASS(vfpga_enabled == true, "Vfpga enabled correctly"); + + // Disable Vfpga and make sure Vio disables also + LOG("[INFO] Disabling Vfpga and checking Vio disables also"); + err = s1_pimc_set_vfpga(false); + LOG_FAIL(err != S1_SUCCESS, "s1_pimc_set_vfpga() returned the error code %d", err); + err = s1_pimc_get_vfpga(&vfpga_enabled); + LOG_FAIL(vfpga_enabled == true, "Vfpga did not disable"); + LOG_PASS(vfpga_enabled == false, "Vfpga disabled"); + + err = s1_pmic_get_vio(&vio, &lsw_mode); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_get_vio() returned the error code %d", err); + LOG_FAIL(vio != 0.0f, "Vio did not disable"); + LOG_PASS(vio == 0.0f, "Vio disabled automatically"); + + // Attempt to re-enable Vio without enabling Vfpga first + LOG("[INFO] Attempting to re-enable Vio without enabling Vfpga first"); + err = s1_pmic_set_vio(1.8f, false); + LOG_FAIL(err != S1_PMIC_VFPGA_NOT_ENABLED, "s1_pmic_set_vio() returned the error code %d", err); + LOG_PASS(err == S1_PMIC_VFPGA_NOT_ENABLED, "Vio correctly refused to turn on in LDO mode"); + + err = s1_pmic_set_vio(1.0f, true); + LOG_FAIL(err != S1_PMIC_VFPGA_NOT_ENABLED, "s1_pmic_set_vio() returned the error code %d", err); + LOG_PASS(err == S1_PMIC_VFPGA_NOT_ENABLED, "Vio correctly refused to turn on in LSW mode"); + + // Enable Vfpga again, and attempt to set Vio out of normal ranges + LOG("[INFO] Enabling Vfpga for Vio range tests"); + err = s1_pimc_set_vfpga(true); + LOG_FAIL(err != S1_SUCCESS, "s1_pimc_set_vfpga() returned the error code %d", err); + + err = s1_pmic_set_vio(0.7f, false); + LOG_FAIL(err != S1_PMIC_INVALID_VALUE, "Vio incorrectly set below 0.8V"); + LOG_PASS(err == S1_PMIC_INVALID_VALUE, "Vio correctly refused to set below 0.8V"); + + err = s1_pmic_set_vio(0.8f, false); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vio() returned the error code %d", err); + LOG_PASS(err == S1_SUCCESS, "Vio correctly set to 0.8V"); + + err = s1_pmic_set_vio(3.475f, false); + LOG_FAIL(err != S1_PMIC_INVALID_VALUE, "Vio incorrectly set above 3.45V"); + LOG_PASS(err == S1_PMIC_INVALID_VALUE, "Vio correctly refused to set above 3.45V"); + + err = s1_pmic_set_vio(3.45f, false); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vio() returned the error code %d", err); + LOG_PASS(err == S1_SUCCESS, "Vio correctly set to 3.45V"); + + // Test correct rounding of passed parameters for Vio + LOG("[INFO] Testing correct rounding of Vio voltage parameters"); + err = s1_pmic_set_vio(3.01f, false); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vio() returned the error code %d", err); + err = s1_pmic_get_vio(&vio, &lsw_mode); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_get_vio() returned the error code %d", err); + LOG_FAIL(vio != 3.0f, "Vio did not round down correctly. Vio = %f", (double)vio); + LOG_PASS(vio == 3.0f, "Vio correctly rounded down to 3.0V"); + + err = s1_pmic_set_vio(3.02f, false); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vio() returned the error code %d", err); + err = s1_pmic_get_vio(&vio, &lsw_mode); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_get_vio() returned the error code %d", err); + LOG_FAIL(vio != 3.025f, "Vio did not round up correctly. Vio = %f", (double)vio); + LOG_PASS(vio == 3.025f, "Vio correctly rounded up to 3.025V"); + + // Test Vio warning when Vaux is not in a suitable range + LOG("[INFO] Testing Vio configuration when Vaux is disabled"); + err = s1_pmic_set_vaux(0.0f); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vaux() returned the error code %d", err); + LOG_PASS(err == S1_SUCCESS, "Vaux correctly shutdown"); + + err = s1_pmic_set_vio(1.0f, false); + LOG_FAIL(err != S1_PMIC_VAUX_NOT_ENABLED, "Vio configured incorrectly while Vaux is disabled"); + LOG_PASS(err == S1_PMIC_VAUX_NOT_ENABLED, "Vio correctly returned that Vaux is not enabled"); + + err = s1_pmic_get_vio(&vio, &lsw_mode); + LOG_FAIL(err != S1_PMIC_VAUX_NOT_ENABLED, "s1_pmic_get_vio() returned the error code %d", err); + LOG_FAIL(vio != 1.0f, "Vio did not configure to 1.0V anyway. Vio = %f", (double)vio); + LOG_PASS(vio == 1.0f, "Vio correctly configured to 1.0V anyway"); + + err = s1_pmic_set_vaux(3.0f); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vaux() returned the error code %d", err); + LOG_PASS(err == S1_SUCCESS, "Vaux set to 3.0V"); + + err = s1_pmic_set_vio(2.925f, false); + LOG_FAIL(err != S1_PMIC_VAUX_TOO_LOW, "Vio incorrectly configured to above the LDO dropout threshold. Error = %d", err); + LOG_PASS(err == S1_PMIC_VAUX_TOO_LOW, "Vio correctly returned dropout level warning"); + + err = s1_pmic_get_vio(&vio, &lsw_mode); + LOG_FAIL(vio != 2.925f, "Vio did not configure to 2.925V anyway. Vio = %f", (double)vio); + LOG_PASS(vio == 2.925f, "Vio correctly configured to 2.925V anyway"); + + // Check load switch modes for Vio + LOG("[INFO] Testing Vio load switch modes"); + err = s1_pmic_set_vio(0.0f, true); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vio() returned the error code %d", err); + err = s1_pmic_get_vio(&vio, &lsw_mode); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vio() returned the error code %d", err); + LOG_FAIL(vio != 0.0f || lsw_mode != true, "Vio as load switch (off) not correctly set"); + LOG_PASS(vio == 0.0f && lsw_mode == true, "Vio as load switch (off) correctly set"); + + err = s1_pmic_set_vio(1.0f, true); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vio() returned the error code %d", err); + err = s1_pmic_get_vio(&vio, &lsw_mode); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vio() returned the error code %d", err); + LOG_FAIL(vio != 1.0f || lsw_mode != true, "Vio as load switch (on) not correctly set"); + LOG_PASS(vio == 1.0f && lsw_mode == true, "Vio as load switch (on) correctly set"); + + err = s1_pmic_set_vaux(3.5f); + LOG_FAIL(err != S1_PMIC_INVALID_VALUE, "Vaux incorrectly set to a high voltage while Vio is in load switch mode"); + LOG_PASS(err == S1_PMIC_INVALID_VALUE, "Vaux correctly refused to set to a high voltage while Vio is in load switch mode"); + + err = s1_pmic_set_vio(0.0f, false); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vio() returned the error code %d", err); + err = s1_pmic_set_vaux(3.5f); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vaux() returned the error code %d", err); + err = s1_pmic_set_vio(0.0f, true); + LOG_FAIL(err != S1_PMIC_VAUX_TOO_HIGH, "Vio incorrectly set to load switch mode while Vaux is too high"); + LOG_PASS(err == S1_PMIC_VAUX_TOO_HIGH, "Vio correctly refused to set to load switch mode while Vaux is too high"); + + // Test Vaux ranges + LOG("[INFO] Testing Vaux range limits"); + err = s1_pmic_set_vaux(0.75f); + LOG_FAIL(err != S1_PMIC_INVALID_VALUE, "Vaux incorrectly set below 0.8V"); + LOG_PASS(err == S1_PMIC_INVALID_VALUE, "Vaux correctly refused to set below 0.8V"); + + err = s1_pmic_set_vaux(0.8f); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vaux() returned the error code %d", err); + LOG_PASS(err == S1_SUCCESS, "Vaux correctly set to 0.8V"); + + err = s1_pmic_set_vio(0.0f, false); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vio() returned the error code %d", err); + err = s1_pmic_set_vaux(5.55f); + LOG_FAIL(err != S1_PMIC_INVALID_VALUE, "Vaux incorrectly set above 5.5V"); + LOG_PASS(err == S1_PMIC_INVALID_VALUE, "Vaux correctly refused to set below 5.5V"); + + err = s1_pmic_set_vaux(5.5f); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vaux() returned the error code %d", err); + LOG_PASS(err == S1_SUCCESS, "Vaux correctly set to 5.5V"); + + // Test correct rounding of passed parameters for Vaux + LOG("[INFO] Testing correct rounding of Vaux voltage parameters"); + err = s1_pmic_set_vaux(3.02f); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_aux() returned the error code %d", err); + float vaux; + err = s1_pmic_get_vaux(&vaux); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_get_vaux() returned the error code %d", err); + LOG_FAIL(vaux != 3.0f, "Vaux did not round down correctly. Vio = %f", (double)vaux); + LOG_PASS(vaux == 3.0f, "Vaux correctly rounded down to 3.0V"); + + err = s1_pmic_set_vaux(3.03f); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_set_vaux() returned the error code %d", err); + err = s1_pmic_get_vaux(&vaux); + LOG_FAIL(err != S1_SUCCESS, "s1_pmic_get_vaux() returned the error code %d", err); + LOG_FAIL(vaux != 3.05f, "Vaux did not round up correctly. Vio = %f", (double)vaux); + LOG_PASS(vaux == 3.05f, "Vaux correctly rounded up to 3.05V"); + + return 0; +} \ No newline at end of file diff --git a/s1_tests/sdk_config.h b/s1_tests/sdk_config.h new file mode 100644 index 0000000..5369216 --- /dev/null +++ b/s1_tests/sdk_config.h @@ -0,0 +1,4619 @@ +/** + * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + + +#ifndef SDK_CONFIG_H +#define SDK_CONFIG_H +// <<< Use Configuration Wizard in Context Menu >>>\n +#ifdef USE_APP_CONFIG +#include "app_config.h" +#endif + +//========================================================== + +// nRF_Core + +//========================================================== +// NRF_MPU_LIB_ENABLED - nrf_mpu_lib - Module for MPU +//========================================================== +#ifndef NRF_MPU_LIB_ENABLED +#define NRF_MPU_LIB_ENABLED 0 +#endif +// NRF_MPU_LIB_CLI_CMDS - Enable CLI commands specific to the module. + + +#ifndef NRF_MPU_LIB_CLI_CMDS +#define NRF_MPU_LIB_CLI_CMDS 0 +#endif + +// + +// NRF_STACK_GUARD_ENABLED - nrf_stack_guard - Stack guard +//========================================================== +#ifndef NRF_STACK_GUARD_ENABLED +#define NRF_STACK_GUARD_ENABLED 0 +#endif +// NRF_STACK_GUARD_CONFIG_SIZE - Size of the stack guard. + +// <5=> 32 bytes +// <6=> 64 bytes +// <7=> 128 bytes +// <8=> 256 bytes +// <9=> 512 bytes +// <10=> 1024 bytes +// <11=> 2048 bytes +// <12=> 4096 bytes + +#ifndef NRF_STACK_GUARD_CONFIG_SIZE +#define NRF_STACK_GUARD_CONFIG_SIZE 7 +#endif + +// + +// +//========================================================== + +// nRF_Crypto + +//========================================================== +// NRF_CRYPTO_ENABLED - nrf_crypto - Cryptography library. +//========================================================== +#ifndef NRF_CRYPTO_ENABLED +#define NRF_CRYPTO_ENABLED 0 +#endif +// NRF_CRYPTO_ALLOCATOR - Memory allocator + + +// Choose memory allocator used by nrf_crypto. Default is alloca if possible or nrf_malloc otherwise. If 'User macros' are selected, the user has to create 'nrf_crypto_allocator.h' file that contains NRF_CRYPTO_ALLOC, NRF_CRYPTO_FREE, and NRF_CRYPTO_ALLOC_ON_STACK. +// <0=> Default +// <1=> User macros +// <2=> On stack (alloca) +// <3=> C dynamic memory (malloc) +// <4=> SDK Memory Manager (nrf_malloc) + +#ifndef NRF_CRYPTO_ALLOCATOR +#define NRF_CRYPTO_ALLOCATOR 0 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_ENABLED - Enable the ARM Cryptocell CC310 reduced backend. + +// The CC310 hardware-accelerated cryptography backend with reduced functionality and footprint (only available on nRF52840). +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED - Enable the secp224r1 elliptic curve support using CC310_BL. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP224R1_ENABLED 0 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED - Enable the secp256r1 elliptic curve support using CC310_BL. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED - CC310_BL SHA-256 hash functionality. + + +// CC310_BL backend implementation for hardware-accelerated SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED - nrf_cc310_bl buffers to RAM before running hash operation + + +// Enabling this makes hashing of addresses in FLASH range possible. Size of buffer allocated for hashing is set by NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_ENABLED 0 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE - nrf_cc310_bl hash outputs digests in little endian +// Makes the nrf_cc310_bl hash functions output digests in little endian format. Only for use in nRF SDK DFU! + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE +#define NRF_CRYPTO_BACKEND_CC310_BL_HASH_AUTOMATIC_RAM_BUFFER_SIZE 4096 +#endif + +// NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED - Enable Interrupts while support using CC310 bl. + + +// Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used + +#ifndef NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_BL_INTERRUPTS_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_CC310_ENABLED - Enable the ARM Cryptocell CC310 backend. + +// The CC310 hardware-accelerated cryptography backend (only available on nRF52840). +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_CC310_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED - Enable the AES CBC mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED - Enable the AES CTR mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CTR_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED - Enable the AES ECB mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_ECB_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED - Enable the AES CBC_MAC mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CBC_MAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED - Enable the AES CMAC mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CMAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED - Enable the AES CCM mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED - Enable the AES CCM* mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_AES_CCM_STAR_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED - Enable the CHACHA-POLY mode using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_CHACHA_POLY_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED - Enable the secp160r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED - Enable the secp160r2 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160R2_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED - Enable the secp192r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED - Enable the secp224r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED - Enable the secp256r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED - Enable the secp384r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP384R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED - Enable the secp521r1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP521R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED - Enable the secp160k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP160K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED - Enable the secp192k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP192K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED - Enable the secp224k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP224K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED - Enable the secp256k1 elliptic curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_SECP256K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED - Enable the Curve25519 curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_CURVE25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED - Enable the Ed25519 curve support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_ECC_ED25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED - CC310 SHA-256 hash functionality. + + +// CC310 backend implementation for hardware-accelerated SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED - CC310 SHA-512 hash functionality + + +// CC310 backend implementation for SHA-512 (in software). + +#ifndef NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HASH_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED - CC310 HMAC using SHA-256 + + +// CC310 backend implementation for HMAC using hardware-accelerated SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED - CC310 HMAC using SHA-512 + + +// CC310 backend implementation for HMAC using SHA-512 (in software). + +#ifndef NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_HMAC_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED - Enable RNG support using CC310. + + +#ifndef NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_RNG_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED - Enable Interrupts while support using CC310. + + +// Select a library version compatible with the configuration. When interrupts are disable, a version named _noint must be used + +#ifndef NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED +#define NRF_CRYPTO_BACKEND_CC310_INTERRUPTS_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_CIFRA_ENABLED - Enable the Cifra backend. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_CIFRA_ENABLED +#define NRF_CRYPTO_BACKEND_CIFRA_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED - Enable the AES EAX mode using Cifra. + + +#ifndef NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED +#define NRF_CRYPTO_BACKEND_CIFRA_AES_EAX_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED - Enable the mbed TLS backend. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED - Enable the AES CBC mode mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED - Enable the AES CTR mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CTR_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED - Enable the AES CFB mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CFB_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED - Enable the AES ECB mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_ECB_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED - Enable the AES CBC MAC mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CBC_MAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED - Enable the AES CMAC mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CMAC_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED - Enable the AES CCM mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_CCM_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED - Enable the AES GCM mode using mbed TLS. + + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_AES_GCM_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED - Enable secp192r1 (NIST 192-bit) curve + + +// Enable this setting if you need secp192r1 (NIST 192-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED - Enable secp224r1 (NIST 224-bit) curve + + +// Enable this setting if you need secp224r1 (NIST 224-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED - Enable secp256r1 (NIST 256-bit) curve + + +// Enable this setting if you need secp256r1 (NIST 256-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED - Enable secp384r1 (NIST 384-bit) curve + + +// Enable this setting if you need secp384r1 (NIST 384-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP384R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED - Enable secp521r1 (NIST 521-bit) curve + + +// Enable this setting if you need secp521r1 (NIST 521-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP521R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED - Enable secp192k1 (Koblitz 192-bit) curve + + +// Enable this setting if you need secp192k1 (Koblitz 192-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP192K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED - Enable secp224k1 (Koblitz 224-bit) curve + + +// Enable this setting if you need secp224k1 (Koblitz 224-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP224K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED - Enable secp256k1 (Koblitz 256-bit) curve + + +// Enable this setting if you need secp256k1 (Koblitz 256-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_SECP256K1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED - Enable bp256r1 (Brainpool 256-bit) curve + + +// Enable this setting if you need bp256r1 (Brainpool 256-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED - Enable bp384r1 (Brainpool 384-bit) curve + + +// Enable this setting if you need bp384r1 (Brainpool 384-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP384R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED - Enable bp512r1 (Brainpool 512-bit) curve + + +// Enable this setting if you need bp512r1 (Brainpool 512-bit) support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_BP512R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED - Enable Curve25519 curve + + +// Enable this setting if you need Curve25519 support using MBEDTLS + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_ECC_CURVE25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED - Enable mbed TLS SHA-256 hash functionality. + + +// mbed TLS backend implementation for SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED - Enable mbed TLS SHA-512 hash functionality. + + +// mbed TLS backend implementation for SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HASH_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED - Enable mbed TLS HMAC using SHA-256. + + +// mbed TLS backend implementation for HMAC using SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED - Enable mbed TLS HMAC using SHA-512. + + +// mbed TLS backend implementation for HMAC using SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_MBEDTLS_HMAC_SHA512_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED - Enable the micro-ecc backend. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED - Enable secp192r1 (NIST 192-bit) curve + + +// Enable this setting if you need secp192r1 (NIST 192-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP192R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED - Enable secp224r1 (NIST 224-bit) curve + + +// Enable this setting if you need secp224r1 (NIST 224-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP224R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED - Enable secp256r1 (NIST 256-bit) curve + + +// Enable this setting if you need secp256r1 (NIST 256-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED - Enable secp256k1 (Koblitz 256-bit) curve + + +// Enable this setting if you need secp256k1 (Koblitz 256-bit) support using micro-ecc + +#ifndef NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED +#define NRF_CRYPTO_BACKEND_MICRO_ECC_ECC_SECP256K1_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED - Enable the nRF HW RNG backend. + +// The nRF HW backend provide access to RNG peripheral in nRF5x devices. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED - Enable mbed TLS CTR-DRBG algorithm. + + +// Enable mbed TLS CTR-DRBG standardized by NIST (NIST SP 800-90A Rev. 1). The nRF HW RNG is used as an entropy source for seeding. + +#ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED +#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_OBERON_ENABLED - Enable the Oberon backend + +// The Oberon backend +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_OBERON_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED - Enable the CHACHA-POLY mode using Oberon. + + +#ifndef NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_CHACHA_POLY_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED - Enable secp256r1 curve + + +// Enable this setting if you need secp256r1 curve support using Oberon library + +#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ECC_SECP256R1_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED - Enable Curve25519 ECDH + + +// Enable this setting if you need Curve25519 ECDH support using Oberon library + +#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ECC_CURVE25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED - Enable Ed25519 signature scheme + + +// Enable this setting if you need Ed25519 support using Oberon library + +#ifndef NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_ECC_ED25519_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED - Oberon SHA-256 hash functionality + + +// Oberon backend implementation for SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED - Oberon SHA-512 hash functionality + + +// Oberon backend implementation for SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HASH_SHA512_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED - Oberon HMAC using SHA-256 + + +// Oberon backend implementation for HMAC using SHA-256. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA256_ENABLED 1 +#endif + +// NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED - Oberon HMAC using SHA-512 + + +// Oberon backend implementation for HMAC using SHA-512. + +#ifndef NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED +#define NRF_CRYPTO_BACKEND_OBERON_HMAC_SHA512_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_BACKEND_OPTIGA_ENABLED - Enable the nrf_crypto Optiga Trust X backend. + +// Enables the nrf_crypto backend for Optiga Trust X devices. +//========================================================== +#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ENABLED +#define NRF_CRYPTO_BACKEND_OPTIGA_ENABLED 0 +#endif +// NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED - Optiga backend support for RNG + + +// The Optiga backend provide external chip RNG. + +#ifndef NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED +#define NRF_CRYPTO_BACKEND_OPTIGA_RNG_ENABLED 0 +#endif + +// NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED - Optiga backend support for ECC secp256r1 + + +// The Optiga backend provide external chip ECC using secp256r1. + +#ifndef NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED +#define NRF_CRYPTO_BACKEND_OPTIGA_ECC_SECP256R1_ENABLED 1 +#endif + +// + +// NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED - Big-endian byte order in raw Curve25519 data + + +// Enable big-endian byte order in Curve25519 API, if set to 1. Use little-endian, if set to 0. + +#ifndef NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED +#define NRF_CRYPTO_CURVE25519_BIG_ENDIAN_ENABLED 0 +#endif + +// + +// +//========================================================== + +// nRF_Drivers + +// NRFX_CLOCK_ENABLED - nrfx_clock - CLOCK peripheral driver +//========================================================== +#ifndef NRFX_CLOCK_ENABLED +#define NRFX_CLOCK_ENABLED 1 +#endif +// NRFX_CLOCK_CONFIG_LF_SRC - LF Clock Source + +// <0=> RC +// <1=> XTAL +// <2=> Synth +// <131073=> External Low Swing +// <196609=> External Full Swing + +#ifndef NRFX_CLOCK_CONFIG_LF_SRC +#define NRFX_CLOCK_CONFIG_LF_SRC 1 +#endif + +// NRFX_CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_CLOCK_CONFIG_IRQ_PRIORITY +#define NRFX_CLOCK_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_CLOCK_CONFIG_LOG_ENABLED +#define NRFX_CLOCK_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_CLOCK_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_CLOCK_CONFIG_LOG_LEVEL +#define NRFX_CLOCK_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_INFO_COLOR +#define NRFX_CLOCK_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_CLOCK_CONFIG_DEBUG_COLOR +#define NRFX_CLOCK_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_COMP_ENABLED - nrfx_comp - COMP peripheral driver +//========================================================== +#ifndef NRFX_COMP_ENABLED +#define NRFX_COMP_ENABLED 0 +#endif +// NRFX_COMP_CONFIG_REF - Reference voltage + +// <0=> Internal 1.2V +// <1=> Internal 1.8V +// <2=> Internal 2.4V +// <4=> VDD +// <7=> ARef + +#ifndef NRFX_COMP_CONFIG_REF +#define NRFX_COMP_CONFIG_REF 1 +#endif + +// NRFX_COMP_CONFIG_MAIN_MODE - Main mode + +// <0=> Single ended +// <1=> Differential + +#ifndef NRFX_COMP_CONFIG_MAIN_MODE +#define NRFX_COMP_CONFIG_MAIN_MODE 0 +#endif + +// NRFX_COMP_CONFIG_SPEED_MODE - Speed mode + +// <0=> Low power +// <1=> Normal +// <2=> High speed + +#ifndef NRFX_COMP_CONFIG_SPEED_MODE +#define NRFX_COMP_CONFIG_SPEED_MODE 2 +#endif + +// NRFX_COMP_CONFIG_HYST - Hystheresis + +// <0=> No +// <1=> 50mV + +#ifndef NRFX_COMP_CONFIG_HYST +#define NRFX_COMP_CONFIG_HYST 0 +#endif + +// NRFX_COMP_CONFIG_ISOURCE - Current Source + +// <0=> Off +// <1=> 2.5 uA +// <2=> 5 uA +// <3=> 10 uA + +#ifndef NRFX_COMP_CONFIG_ISOURCE +#define NRFX_COMP_CONFIG_ISOURCE 0 +#endif + +// NRFX_COMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_COMP_CONFIG_INPUT +#define NRFX_COMP_CONFIG_INPUT 0 +#endif + +// NRFX_COMP_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_COMP_CONFIG_IRQ_PRIORITY +#define NRFX_COMP_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_COMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_COMP_CONFIG_LOG_ENABLED +#define NRFX_COMP_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_COMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_COMP_CONFIG_LOG_LEVEL +#define NRFX_COMP_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_COMP_CONFIG_INFO_COLOR +#define NRFX_COMP_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_COMP_CONFIG_DEBUG_COLOR +#define NRFX_COMP_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_GPIOTE_ENABLED - nrfx_gpiote - GPIOTE peripheral driver +//========================================================== +#ifndef NRFX_GPIOTE_ENABLED +#define NRFX_GPIOTE_ENABLED 1 +#endif +// NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins +#ifndef NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1 +#endif + +// NRFX_GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_GPIOTE_CONFIG_IRQ_PRIORITY +#define NRFX_GPIOTE_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_GPIOTE_CONFIG_LOG_ENABLED +#define NRFX_GPIOTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_GPIOTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_GPIOTE_CONFIG_LOG_LEVEL +#define NRFX_GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_INFO_COLOR +#define NRFX_GPIOTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_GPIOTE_CONFIG_DEBUG_COLOR +#define NRFX_GPIOTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PDM_ENABLED - nrfx_pdm - PDM peripheral driver +//========================================================== +#ifndef NRFX_PDM_ENABLED +#define NRFX_PDM_ENABLED 0 +#endif +// NRFX_PDM_CONFIG_MODE - Mode + +// <0=> Stereo +// <1=> Mono + +#ifndef NRFX_PDM_CONFIG_MODE +#define NRFX_PDM_CONFIG_MODE 1 +#endif + +// NRFX_PDM_CONFIG_EDGE - Edge + +// <0=> Left falling +// <1=> Left rising + +#ifndef NRFX_PDM_CONFIG_EDGE +#define NRFX_PDM_CONFIG_EDGE 0 +#endif + +// NRFX_PDM_CONFIG_CLOCK_FREQ - Clock frequency + +// <134217728=> 1000k +// <138412032=> 1032k (default) +// <142606336=> 1067k + +#ifndef NRFX_PDM_CONFIG_CLOCK_FREQ +#define NRFX_PDM_CONFIG_CLOCK_FREQ 138412032 +#endif + +// NRFX_PDM_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_PDM_CONFIG_IRQ_PRIORITY +#define NRFX_PDM_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_PDM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PDM_CONFIG_LOG_ENABLED +#define NRFX_PDM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PDM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PDM_CONFIG_LOG_LEVEL +#define NRFX_PDM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PDM_CONFIG_INFO_COLOR +#define NRFX_PDM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PDM_CONFIG_DEBUG_COLOR +#define NRFX_PDM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_POWER_ENABLED - nrfx_power - POWER peripheral driver +//========================================================== +#ifndef NRFX_POWER_ENABLED +#define NRFX_POWER_ENABLED 0 +#endif +// NRFX_POWER_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_POWER_CONFIG_IRQ_PRIORITY +#define NRFX_POWER_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCEN +#define NRFX_POWER_CONFIG_DEFAULT_DCDCEN 0 +#endif + +// NRFX_POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef NRFX_POWER_CONFIG_DEFAULT_DCDCENHV +#define NRFX_POWER_CONFIG_DEFAULT_DCDCENHV 0 +#endif + +// + +// NRFX_PPI_ENABLED - nrfx_ppi - PPI peripheral allocator +//========================================================== +#ifndef NRFX_PPI_ENABLED +#define NRFX_PPI_ENABLED 0 +#endif +// NRFX_PPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PPI_CONFIG_LOG_ENABLED +#define NRFX_PPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PPI_CONFIG_LOG_LEVEL +#define NRFX_PPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_INFO_COLOR +#define NRFX_PPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PPI_CONFIG_DEBUG_COLOR +#define NRFX_PPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_PWM_ENABLED - nrfx_pwm - PWM peripheral driver +//========================================================== +#ifndef NRFX_PWM_ENABLED +#define NRFX_PWM_ENABLED 0 +#endif +// NRFX_PWM0_ENABLED - Enable PWM0 instance + + +#ifndef NRFX_PWM0_ENABLED +#define NRFX_PWM0_ENABLED 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT0_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT1_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT2_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> + + +#ifndef NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN +#define NRFX_PWM_DEFAULT_CONFIG_OUT3_PIN 31 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz + +#ifndef NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK +#define NRFX_PWM_DEFAULT_CONFIG_BASE_CLOCK 4 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode + +// <0=> Up +// <1=> Up and Down + +#ifndef NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE +#define NRFX_PWM_DEFAULT_CONFIG_COUNT_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE - Top value +#ifndef NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE +#define NRFX_PWM_DEFAULT_CONFIG_TOP_VALUE 1000 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode + +// <0=> Common +// <1=> Grouped +// <2=> Individual +// <3=> Waveform + +#ifndef NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE +#define NRFX_PWM_DEFAULT_CONFIG_LOAD_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_STEP_MODE - Step mode + +// <0=> Auto +// <1=> Triggered + +#ifndef NRFX_PWM_DEFAULT_CONFIG_STEP_MODE +#define NRFX_PWM_DEFAULT_CONFIG_STEP_MODE 0 +#endif + +// NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_PWM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_PWM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_PWM_CONFIG_LOG_ENABLED +#define NRFX_PWM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_PWM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_PWM_CONFIG_LOG_LEVEL +#define NRFX_PWM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PWM_CONFIG_INFO_COLOR +#define NRFX_PWM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_PWM_CONFIG_DEBUG_COLOR +#define NRFX_PWM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_QDEC_ENABLED - nrfx_qdec - QDEC peripheral driver +//========================================================== +#ifndef NRFX_QDEC_ENABLED +#define NRFX_QDEC_ENABLED 0 +#endif +// NRFX_QDEC_CONFIG_REPORTPER - Report period + +// <0=> 10 Samples +// <1=> 40 Samples +// <2=> 80 Samples +// <3=> 120 Samples +// <4=> 160 Samples +// <5=> 200 Samples +// <6=> 240 Samples +// <7=> 280 Samples + +#ifndef NRFX_QDEC_CONFIG_REPORTPER +#define NRFX_QDEC_CONFIG_REPORTPER 0 +#endif + +// NRFX_QDEC_CONFIG_SAMPLEPER - Sample period + +// <0=> 128 us +// <1=> 256 us +// <2=> 512 us +// <3=> 1024 us +// <4=> 2048 us +// <5=> 4096 us +// <6=> 8192 us +// <7=> 16384 us + +#ifndef NRFX_QDEC_CONFIG_SAMPLEPER +#define NRFX_QDEC_CONFIG_SAMPLEPER 7 +#endif + +// NRFX_QDEC_CONFIG_PIO_A - A pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_A +#define NRFX_QDEC_CONFIG_PIO_A 31 +#endif + +// NRFX_QDEC_CONFIG_PIO_B - B pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_B +#define NRFX_QDEC_CONFIG_PIO_B 31 +#endif + +// NRFX_QDEC_CONFIG_PIO_LED - LED pin <0-31> + + +#ifndef NRFX_QDEC_CONFIG_PIO_LED +#define NRFX_QDEC_CONFIG_PIO_LED 31 +#endif + +// NRFX_QDEC_CONFIG_LEDPRE - LED pre +#ifndef NRFX_QDEC_CONFIG_LEDPRE +#define NRFX_QDEC_CONFIG_LEDPRE 511 +#endif + +// NRFX_QDEC_CONFIG_LEDPOL - LED polarity + +// <0=> Active low +// <1=> Active high + +#ifndef NRFX_QDEC_CONFIG_LEDPOL +#define NRFX_QDEC_CONFIG_LEDPOL 1 +#endif + +// NRFX_QDEC_CONFIG_DBFEN - Debouncing enable + + +#ifndef NRFX_QDEC_CONFIG_DBFEN +#define NRFX_QDEC_CONFIG_DBFEN 0 +#endif + +// NRFX_QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable + + +#ifndef NRFX_QDEC_CONFIG_SAMPLE_INTEN +#define NRFX_QDEC_CONFIG_SAMPLE_INTEN 0 +#endif + +// NRFX_QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_QDEC_CONFIG_IRQ_PRIORITY +#define NRFX_QDEC_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_QDEC_CONFIG_LOG_ENABLED +#define NRFX_QDEC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_QDEC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_QDEC_CONFIG_LOG_LEVEL +#define NRFX_QDEC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_INFO_COLOR +#define NRFX_QDEC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_QDEC_CONFIG_DEBUG_COLOR +#define NRFX_QDEC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver +//========================================================== +#ifndef NRFX_RNG_ENABLED +#define NRFX_RNG_ENABLED 0 +#endif +// NRFX_RNG_CONFIG_ERROR_CORRECTION - Error correction + + +#ifndef NRFX_RNG_CONFIG_ERROR_CORRECTION +#define NRFX_RNG_CONFIG_ERROR_CORRECTION 1 +#endif + +// NRFX_RNG_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RNG_CONFIG_IRQ_PRIORITY +#define NRFX_RNG_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_RNG_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RNG_CONFIG_LOG_ENABLED +#define NRFX_RNG_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RNG_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RNG_CONFIG_LOG_LEVEL +#define NRFX_RNG_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_INFO_COLOR +#define NRFX_RNG_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RNG_CONFIG_DEBUG_COLOR +#define NRFX_RNG_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_RTC_ENABLED - nrfx_rtc - RTC peripheral driver +//========================================================== +#ifndef NRFX_RTC_ENABLED +#define NRFX_RTC_ENABLED 0 +#endif +// NRFX_RTC0_ENABLED - Enable RTC0 instance + + +#ifndef NRFX_RTC0_ENABLED +#define NRFX_RTC0_ENABLED 0 +#endif + +// NRFX_RTC1_ENABLED - Enable RTC1 instance + + +#ifndef NRFX_RTC1_ENABLED +#define NRFX_RTC1_ENABLED 0 +#endif + +// NRFX_RTC_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt +#ifndef NRFX_RTC_MAXIMUM_LATENCY_US +#define NRFX_RTC_MAXIMUM_LATENCY_US 2000 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> + + +#ifndef NRFX_RTC_DEFAULT_CONFIG_FREQUENCY +#define NRFX_RTC_DEFAULT_CONFIG_FREQUENCY 32768 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering + + +#ifndef NRFX_RTC_DEFAULT_CONFIG_RELIABLE +#define NRFX_RTC_DEFAULT_CONFIG_RELIABLE 0 +#endif + +// NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_RTC_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_RTC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_RTC_CONFIG_LOG_ENABLED +#define NRFX_RTC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_RTC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_RTC_CONFIG_LOG_LEVEL +#define NRFX_RTC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_INFO_COLOR +#define NRFX_RTC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_RTC_CONFIG_DEBUG_COLOR +#define NRFX_RTC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SAADC_ENABLED - nrfx_saadc - SAADC peripheral driver +//========================================================== +#ifndef NRFX_SAADC_ENABLED +#define NRFX_SAADC_ENABLED 1 +#endif +// NRFX_SAADC_CONFIG_RESOLUTION - Resolution + +// <0=> 8 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit + +#ifndef NRFX_SAADC_CONFIG_RESOLUTION +#define NRFX_SAADC_CONFIG_RESOLUTION 1 +#endif + +// NRFX_SAADC_CONFIG_OVERSAMPLE - Sample period + +// <0=> Disabled +// <1=> 2x +// <2=> 4x +// <3=> 8x +// <4=> 16x +// <5=> 32x +// <6=> 64x +// <7=> 128x +// <8=> 256x + +#ifndef NRFX_SAADC_CONFIG_OVERSAMPLE +#define NRFX_SAADC_CONFIG_OVERSAMPLE 8 +#endif + +// NRFX_SAADC_CONFIG_LP_MODE - Enabling low power mode + + +#ifndef NRFX_SAADC_CONFIG_LP_MODE +#define NRFX_SAADC_CONFIG_LP_MODE 0 +#endif + +// NRFX_SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SAADC_CONFIG_IRQ_PRIORITY +#define NRFX_SAADC_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SAADC_CONFIG_LOG_ENABLED +#define NRFX_SAADC_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SAADC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SAADC_CONFIG_LOG_LEVEL +#define NRFX_SAADC_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_INFO_COLOR +#define NRFX_SAADC_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SAADC_CONFIG_DEBUG_COLOR +#define NRFX_SAADC_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIM_ENABLED - nrfx_spim - SPIM peripheral driver +//========================================================== +#ifndef NRFX_SPIM_ENABLED +#define NRFX_SPIM_ENABLED 1 +#endif +// NRFX_SPIM0_ENABLED - Enable SPIM0 instance + + +#ifndef NRFX_SPIM0_ENABLED +#define NRFX_SPIM0_ENABLED 1 +#endif + +// NRFX_SPIM1_ENABLED - Enable SPIM1 instance + + +#ifndef NRFX_SPIM1_ENABLED +#define NRFX_SPIM1_ENABLED 0 +#endif + +// NRFX_SPIM_MISO_PULL_CFG - MISO pin pull configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRFX_SPIM_MISO_PULL_CFG +#define NRFX_SPIM_MISO_PULL_CFG 1 +#endif + +// NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SPIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIM_CONFIG_LOG_ENABLED +#define NRFX_SPIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIM_CONFIG_LOG_LEVEL +#define NRFX_SPIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_INFO_COLOR +#define NRFX_SPIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIM_CONFIG_DEBUG_COLOR +#define NRFX_SPIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPIS_ENABLED - nrfx_spis - SPIS peripheral driver +//========================================================== +#ifndef NRFX_SPIS_ENABLED +#define NRFX_SPIS_ENABLED 0 +#endif +// NRFX_SPIS0_ENABLED - Enable SPIS0 instance + + +#ifndef NRFX_SPIS0_ENABLED +#define NRFX_SPIS0_ENABLED 0 +#endif + +// NRFX_SPIS1_ENABLED - Enable SPIS1 instance + + +#ifndef NRFX_SPIS1_ENABLED +#define NRFX_SPIS1_ENABLED 0 +#endif + +// NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> + + +#ifndef NRFX_SPIS_DEFAULT_DEF +#define NRFX_SPIS_DEFAULT_DEF 255 +#endif + +// NRFX_SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> + + +#ifndef NRFX_SPIS_DEFAULT_ORC +#define NRFX_SPIS_DEFAULT_ORC 255 +#endif + +// NRFX_SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPIS_CONFIG_LOG_ENABLED +#define NRFX_SPIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPIS_CONFIG_LOG_LEVEL +#define NRFX_SPIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_INFO_COLOR +#define NRFX_SPIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPIS_CONFIG_DEBUG_COLOR +#define NRFX_SPIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SPI_ENABLED - nrfx_spi - SPI peripheral driver +//========================================================== +#ifndef NRFX_SPI_ENABLED +#define NRFX_SPI_ENABLED 0 +#endif +// NRFX_SPI0_ENABLED - Enable SPI0 instance + + +#ifndef NRFX_SPI0_ENABLED +#define NRFX_SPI0_ENABLED 0 +#endif + +// NRFX_SPI1_ENABLED - Enable SPI1 instance + + +#ifndef NRFX_SPI1_ENABLED +#define NRFX_SPI1_ENABLED 0 +#endif + +// NRFX_SPI_MISO_PULL_CFG - MISO pin pull configuration. + +// <0=> NRF_GPIO_PIN_NOPULL +// <1=> NRF_GPIO_PIN_PULLDOWN +// <3=> NRF_GPIO_PIN_PULLUP + +#ifndef NRFX_SPI_MISO_PULL_CFG +#define NRFX_SPI_MISO_PULL_CFG 1 +#endif + +// NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_SPI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SPI_CONFIG_LOG_ENABLED +#define NRFX_SPI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SPI_CONFIG_LOG_LEVEL +#define NRFX_SPI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_INFO_COLOR +#define NRFX_SPI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SPI_CONFIG_DEBUG_COLOR +#define NRFX_SPI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_SWI_ENABLED - nrfx_swi - SWI/EGU peripheral allocator +//========================================================== +#ifndef NRFX_SWI_ENABLED +#define NRFX_SWI_ENABLED 0 +#endif +// NRFX_EGU_ENABLED - Enable EGU support + + +#ifndef NRFX_EGU_ENABLED +#define NRFX_EGU_ENABLED 0 +#endif + +// NRFX_SWI0_DISABLED - Exclude SWI0 from being utilized by the driver + + +#ifndef NRFX_SWI0_DISABLED +#define NRFX_SWI0_DISABLED 0 +#endif + +// NRFX_SWI1_DISABLED - Exclude SWI1 from being utilized by the driver + + +#ifndef NRFX_SWI1_DISABLED +#define NRFX_SWI1_DISABLED 0 +#endif + +// NRFX_SWI2_DISABLED - Exclude SWI2 from being utilized by the driver + + +#ifndef NRFX_SWI2_DISABLED +#define NRFX_SWI2_DISABLED 0 +#endif + +// NRFX_SWI3_DISABLED - Exclude SWI3 from being utilized by the driver + + +#ifndef NRFX_SWI3_DISABLED +#define NRFX_SWI3_DISABLED 0 +#endif + +// NRFX_SWI4_DISABLED - Exclude SWI4 from being utilized by the driver + + +#ifndef NRFX_SWI4_DISABLED +#define NRFX_SWI4_DISABLED 0 +#endif + +// NRFX_SWI5_DISABLED - Exclude SWI5 from being utilized by the driver + + +#ifndef NRFX_SWI5_DISABLED +#define NRFX_SWI5_DISABLED 0 +#endif + +// NRFX_SWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_SWI_CONFIG_LOG_ENABLED +#define NRFX_SWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_SWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_SWI_CONFIG_LOG_LEVEL +#define NRFX_SWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_SWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SWI_CONFIG_INFO_COLOR +#define NRFX_SWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_SWI_CONFIG_DEBUG_COLOR +#define NRFX_SWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TIMER_ENABLED - nrfx_timer - TIMER periperal driver +//========================================================== +#ifndef NRFX_TIMER_ENABLED +#define NRFX_TIMER_ENABLED 0 +#endif +// NRFX_TIMER0_ENABLED - Enable TIMER0 instance + + +#ifndef NRFX_TIMER0_ENABLED +#define NRFX_TIMER0_ENABLED 0 +#endif + +// NRFX_TIMER1_ENABLED - Enable TIMER1 instance + + +#ifndef NRFX_TIMER1_ENABLED +#define NRFX_TIMER1_ENABLED 0 +#endif + +// NRFX_TIMER2_ENABLED - Enable TIMER2 instance + + +#ifndef NRFX_TIMER2_ENABLED +#define NRFX_TIMER2_ENABLED 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz +// <8=> 62.5 kHz +// <9=> 31.25 kHz + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TIMER_DEFAULT_CONFIG_FREQUENCY 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation + +// <0=> Timer +// <1=> Counter + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_MODE +#define NRFX_TIMER_DEFAULT_CONFIG_MODE 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width + +// <0=> 16 bit +// <1=> 8 bit +// <2=> 24 bit +// <3=> 32 bit + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH +#define NRFX_TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 +#endif + +// NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TIMER_CONFIG_LOG_ENABLED +#define NRFX_TIMER_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TIMER_CONFIG_LOG_LEVEL +#define NRFX_TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_INFO_COLOR +#define NRFX_TIMER_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TIMER_CONFIG_DEBUG_COLOR +#define NRFX_TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIM_ENABLED - nrfx_twim - TWIM peripheral driver +//========================================================== +#ifndef NRFX_TWIM_ENABLED +#define NRFX_TWIM_ENABLED 1 +#endif +// NRFX_TWIM0_ENABLED - Enable TWIM0 instance + + +#ifndef NRFX_TWIM0_ENABLED +#define NRFX_TWIM0_ENABLED 1 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWIM_DEFAULT_CONFIG_FREQUENCY 104857600 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWIM_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIM_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TWIM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIM_CONFIG_LOG_ENABLED +#define NRFX_TWIM_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIM_CONFIG_LOG_LEVEL +#define NRFX_TWIM_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_INFO_COLOR +#define NRFX_TWIM_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIM_CONFIG_DEBUG_COLOR +#define NRFX_TWIM_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWIS_ENABLED - nrfx_twis - TWIS peripheral driver +//========================================================== +#ifndef NRFX_TWIS_ENABLED +#define NRFX_TWIS_ENABLED 0 +#endif +// NRFX_TWIS0_ENABLED - Enable TWIS0 instance + + +#ifndef NRFX_TWIS0_ENABLED +#define NRFX_TWIS0_ENABLED 0 +#endif + +// NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once + + +// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. + +#ifndef NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define NRFX_TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +// NRFX_TWIS_NO_SYNC_MODE - Remove support for synchronous mode + + +// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. + +#ifndef NRFX_TWIS_NO_SYNC_MODE +#define NRFX_TWIS_NO_SYNC_MODE 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_ADDR0 - Address0 +#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR0 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR0 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_ADDR1 - Address1 +#ifndef NRFX_TWIS_DEFAULT_CONFIG_ADDR1 +#define NRFX_TWIS_DEFAULT_CONFIG_ADDR1 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SCL_PULL 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL +#define NRFX_TWIS_DEFAULT_CONFIG_SDA_PULL 0 +#endif + +// NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWIS_CONFIG_LOG_ENABLED +#define NRFX_TWIS_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWIS_CONFIG_LOG_LEVEL +#define NRFX_TWIS_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_INFO_COLOR +#define NRFX_TWIS_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWIS_CONFIG_DEBUG_COLOR +#define NRFX_TWIS_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_TWI_ENABLED - nrfx_twi - TWI peripheral driver +//========================================================== +#ifndef NRFX_TWI_ENABLED +#define NRFX_TWI_ENABLED 0 +#endif +// NRFX_TWI0_ENABLED - Enable TWI0 instance + + +#ifndef NRFX_TWI0_ENABLED +#define NRFX_TWI0_ENABLED 0 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef NRFX_TWI_DEFAULT_CONFIG_FREQUENCY +#define NRFX_TWI_DEFAULT_CONFIG_FREQUENCY 104857600 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define NRFX_TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_TWI_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_TWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_TWI_CONFIG_LOG_ENABLED +#define NRFX_TWI_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_TWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_TWI_CONFIG_LOG_LEVEL +#define NRFX_TWI_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_INFO_COLOR +#define NRFX_TWI_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_TWI_CONFIG_DEBUG_COLOR +#define NRFX_TWI_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UARTE_ENABLED - nrfx_uarte - UARTE peripheral driver +//========================================================== +#ifndef NRFX_UARTE_ENABLED +#define NRFX_UARTE_ENABLED 0 +#endif +// NRFX_UARTE0_ENABLED - Enable UARTE0 instance +#ifndef NRFX_UARTE0_ENABLED +#define NRFX_UARTE0_ENABLED 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_HWFC +#define NRFX_UARTE_DEFAULT_CONFIG_HWFC 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_PARITY +#define NRFX_UARTE_DEFAULT_CONFIG_PARITY 0 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <8388608=> 31250 baud +// <10289152=> 38400 baud +// <15007744=> 56000 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UARTE_DEFAULT_CONFIG_BAUDRATE 30801920 +#endif + +// NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_UARTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UARTE_CONFIG_LOG_ENABLED +#define NRFX_UARTE_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UARTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UARTE_CONFIG_LOG_LEVEL +#define NRFX_UARTE_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UARTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_INFO_COLOR +#define NRFX_UARTE_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UARTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UARTE_CONFIG_DEBUG_COLOR +#define NRFX_UARTE_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_UART_ENABLED - nrfx_uart - UART peripheral driver +//========================================================== +#ifndef NRFX_UART_ENABLED +#define NRFX_UART_ENABLED 0 +#endif +// NRFX_UART0_ENABLED - Enable UART0 instance +#ifndef NRFX_UART0_ENABLED +#define NRFX_UART0_ENABLED 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRFX_UART_DEFAULT_CONFIG_HWFC +#define NRFX_UART_DEFAULT_CONFIG_HWFC 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef NRFX_UART_DEFAULT_CONFIG_PARITY +#define NRFX_UART_DEFAULT_CONFIG_PARITY 0 +#endif + +// NRFX_UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3866624=> 14400 baud +// <5152768=> 19200 baud +// <7729152=> 28800 baud +// <8388608=> 31250 baud +// <10309632=> 38400 baud +// <15007744=> 56000 baud +// <15462400=> 57600 baud +// <20615168=> 76800 baud +// <30924800=> 115200 baud +// <61845504=> 230400 baud +// <67108864=> 250000 baud +// <123695104=> 460800 baud +// <247386112=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef NRFX_UART_DEFAULT_CONFIG_BAUDRATE +#define NRFX_UART_DEFAULT_CONFIG_BAUDRATE 30924800 +#endif + +// NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define NRFX_UART_DEFAULT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_UART_CONFIG_LOG_ENABLED +#define NRFX_UART_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_UART_CONFIG_LOG_LEVEL +#define NRFX_UART_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_INFO_COLOR +#define NRFX_UART_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_UART_CONFIG_DEBUG_COLOR +#define NRFX_UART_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// NRFX_WDT_ENABLED - nrfx_wdt - WDT peripheral driver +//========================================================== +#ifndef NRFX_WDT_ENABLED +#define NRFX_WDT_ENABLED 0 +#endif +// NRFX_WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode + +// <1=> Run in SLEEP, Pause in HALT +// <8=> Pause in SLEEP, Run in HALT +// <9=> Run in SLEEP and HALT +// <0=> Pause in SLEEP and HALT + +#ifndef NRFX_WDT_CONFIG_BEHAVIOUR +#define NRFX_WDT_CONFIG_BEHAVIOUR 1 +#endif + +// NRFX_WDT_CONFIG_RELOAD_VALUE - Reload value in ms <1-131072000> + + +#ifndef NRFX_WDT_CONFIG_RELOAD_VALUE +#define NRFX_WDT_CONFIG_RELOAD_VALUE 2000 +#endif + +// NRFX_WDT_CONFIG_NO_IRQ - Remove WDT IRQ handling from WDT driver + +// <0=> Include WDT IRQ handling +// <1=> Remove WDT IRQ handling + +#ifndef NRFX_WDT_CONFIG_NO_IRQ +#define NRFX_WDT_CONFIG_NO_IRQ 0 +#endif + +// NRFX_WDT_CONFIG_IRQ_PRIORITY - Interrupt priority + +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef NRFX_WDT_CONFIG_IRQ_PRIORITY +#define NRFX_WDT_CONFIG_IRQ_PRIORITY 6 +#endif + +// NRFX_WDT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef NRFX_WDT_CONFIG_LOG_ENABLED +#define NRFX_WDT_CONFIG_LOG_ENABLED 0 +#endif +// NRFX_WDT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRFX_WDT_CONFIG_LOG_LEVEL +#define NRFX_WDT_CONFIG_LOG_LEVEL 3 +#endif + +// NRFX_WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_INFO_COLOR +#define NRFX_WDT_CONFIG_INFO_COLOR 0 +#endif + +// NRFX_WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRFX_WDT_CONFIG_DEBUG_COLOR +#define NRFX_WDT_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// + +// + +// nRF_Libraries + +//========================================================== +// APP_GPIOTE_ENABLED - app_gpiote - GPIOTE events dispatcher + + +#ifndef APP_GPIOTE_ENABLED +#define APP_GPIOTE_ENABLED 0 +#endif + +// APP_PWM_ENABLED - app_pwm - PWM functionality + + +#ifndef APP_PWM_ENABLED +#define APP_PWM_ENABLED 0 +#endif + +// APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler +//========================================================== +#ifndef APP_SCHEDULER_ENABLED +#define APP_SCHEDULER_ENABLED 1 +#endif +// APP_SCHEDULER_WITH_PAUSE - Enabling pause feature + + +#ifndef APP_SCHEDULER_WITH_PAUSE +#define APP_SCHEDULER_WITH_PAUSE 0 +#endif + +// APP_SCHEDULER_WITH_PROFILER - Enabling scheduler profiling + + +#ifndef APP_SCHEDULER_WITH_PROFILER +#define APP_SCHEDULER_WITH_PROFILER 0 +#endif + +// + +// APP_SDCARD_ENABLED - app_sdcard - SD/MMC card support using SPI +//========================================================== +#ifndef APP_SDCARD_ENABLED +#define APP_SDCARD_ENABLED 0 +#endif +// APP_SDCARD_SPI_INSTANCE - SPI instance used + +// <0=> 0 +// <1=> 1 +// <2=> 2 + +#ifndef APP_SDCARD_SPI_INSTANCE +#define APP_SDCARD_SPI_INSTANCE 0 +#endif + +// APP_SDCARD_FREQ_INIT - SPI frequency + +// <33554432=> 125 kHz +// <67108864=> 250 kHz +// <134217728=> 500 kHz +// <268435456=> 1 MHz +// <536870912=> 2 MHz +// <1073741824=> 4 MHz +// <2147483648=> 8 MHz + +#ifndef APP_SDCARD_FREQ_INIT +#define APP_SDCARD_FREQ_INIT 67108864 +#endif + +// APP_SDCARD_FREQ_DATA - SPI frequency + +// <33554432=> 125 kHz +// <67108864=> 250 kHz +// <134217728=> 500 kHz +// <268435456=> 1 MHz +// <536870912=> 2 MHz +// <1073741824=> 4 MHz +// <2147483648=> 8 MHz + +#ifndef APP_SDCARD_FREQ_DATA +#define APP_SDCARD_FREQ_DATA 1073741824 +#endif + +// + +// APP_TIMER_ENABLED - app_timer - Application timer functionality +//========================================================== +#ifndef APP_TIMER_ENABLED +#define APP_TIMER_ENABLED 1 +#endif +// APP_TIMER_CONFIG_RTC_FREQUENCY - Configure RTC prescaler. + +// <0=> 32768 Hz +// <1=> 16384 Hz +// <3=> 8192 Hz +// <7=> 4096 Hz +// <15=> 2048 Hz +// <31=> 1024 Hz + +#ifndef APP_TIMER_CONFIG_RTC_FREQUENCY +#define APP_TIMER_CONFIG_RTC_FREQUENCY 1 +#endif + +// APP_TIMER_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef APP_TIMER_CONFIG_IRQ_PRIORITY +#define APP_TIMER_CONFIG_IRQ_PRIORITY 6 +#endif + +// APP_TIMER_CONFIG_OP_QUEUE_SIZE - Capacity of timer requests queue. +// Size of the queue depends on how many timers are used +// in the system, how often timers are started and overall +// system latency. If queue size is too small app_timer calls +// will fail. + +#ifndef APP_TIMER_CONFIG_OP_QUEUE_SIZE +#define APP_TIMER_CONFIG_OP_QUEUE_SIZE 10 +#endif + +// APP_TIMER_CONFIG_USE_SCHEDULER - Enable scheduling app_timer events to app_scheduler + + +#ifndef APP_TIMER_CONFIG_USE_SCHEDULER +#define APP_TIMER_CONFIG_USE_SCHEDULER 0 +#endif + +// APP_TIMER_KEEPS_RTC_ACTIVE - Enable RTC always on + + +// If option is enabled RTC is kept running even if there is no active timers. +// This option can be used when app_timer is used for timestamping. + +#ifndef APP_TIMER_KEEPS_RTC_ACTIVE +#define APP_TIMER_KEEPS_RTC_ACTIVE 0 +#endif + +// APP_TIMER_SAFE_WINDOW_MS - Maximum possible latency (in milliseconds) of handling app_timer event. +// Maximum possible timeout that can be set is reduced by safe window. +// Example: RTC frequency 16384 Hz, maximum possible timeout 1024 seconds - APP_TIMER_SAFE_WINDOW_MS. +// Since RTC is not stopped when processor is halted in debugging session, this value +// must cover it if debugging is needed. It is possible to halt processor for APP_TIMER_SAFE_WINDOW_MS +// without corrupting app_timer behavior. + +#ifndef APP_TIMER_SAFE_WINDOW_MS +#define APP_TIMER_SAFE_WINDOW_MS 300000 +#endif + + +// + +// APP_USBD_AUDIO_ENABLED - app_usbd_audio - USB AUDIO class + + +#ifndef APP_USBD_AUDIO_ENABLED +#define APP_USBD_AUDIO_ENABLED 0 +#endif + +// APP_USBD_ENABLED - app_usbd - USB Device library +//========================================================== +#ifndef APP_USBD_ENABLED +#define APP_USBD_ENABLED 0 +#endif +// APP_USBD_VID - Vendor ID. <0x0000-0xFFFF> + + +// Note: This value is not editable in Configuration Wizard. +// Vendor ID ordered from USB IF: http://www.usb.org/developers/vendor/ + +#ifndef APP_USBD_VID +#define APP_USBD_VID 0 +#endif + +// APP_USBD_PID - Product ID. <0x0000-0xFFFF> + + +// Note: This value is not editable in Configuration Wizard. +// Selected Product ID + +#ifndef APP_USBD_PID +#define APP_USBD_PID 0 +#endif + +// APP_USBD_DEVICE_VER_MAJOR - Major device version <0-99> + + +// Major device version, will be converted automatically to BCD notation. Use just decimal values. + +#ifndef APP_USBD_DEVICE_VER_MAJOR +#define APP_USBD_DEVICE_VER_MAJOR 1 +#endif + +// APP_USBD_DEVICE_VER_MINOR - Minor device version <0-9> + + +// Minor device version, will be converted automatically to BCD notation. Use just decimal values. + +#ifndef APP_USBD_DEVICE_VER_MINOR +#define APP_USBD_DEVICE_VER_MINOR 0 +#endif + +// APP_USBD_DEVICE_VER_SUB - Sub-minor device version <0-9> + + +// Sub-minor device version, will be converted automatically to BCD notation. Use just decimal values. + +#ifndef APP_USBD_DEVICE_VER_SUB +#define APP_USBD_DEVICE_VER_SUB 0 +#endif + +// APP_USBD_CONFIG_SELF_POWERED - Self-powered device, as opposed to bus-powered. + + +#ifndef APP_USBD_CONFIG_SELF_POWERED +#define APP_USBD_CONFIG_SELF_POWERED 1 +#endif + +// APP_USBD_CONFIG_MAX_POWER - MaxPower field in configuration descriptor in milliamps. <0-500> + + +#ifndef APP_USBD_CONFIG_MAX_POWER +#define APP_USBD_CONFIG_MAX_POWER 100 +#endif + +// APP_USBD_CONFIG_POWER_EVENTS_PROCESS - Process power events. + + +// Enable processing power events in USB event handler. + +#ifndef APP_USBD_CONFIG_POWER_EVENTS_PROCESS +#define APP_USBD_CONFIG_POWER_EVENTS_PROCESS 1 +#endif + +// APP_USBD_CONFIG_EVENT_QUEUE_ENABLE - Enable event queue. + +// This is the default configuration when all the events are placed into internal queue. +// Disable it when an external queue is used like app_scheduler or if you wish to process all events inside interrupts. +// Processing all events from the interrupt level adds requirement not to call any functions that modifies the USBD library state from the context higher than USB interrupt context. +// Functions that modify USBD state are functions for sleep, wakeup, start, stop, enable, and disable. +//========================================================== +#ifndef APP_USBD_CONFIG_EVENT_QUEUE_ENABLE +#define APP_USBD_CONFIG_EVENT_QUEUE_ENABLE 1 +#endif +// APP_USBD_CONFIG_EVENT_QUEUE_SIZE - The size of the event queue. <16-64> + + +// The size of the queue for the events that would be processed in the main loop. + +#ifndef APP_USBD_CONFIG_EVENT_QUEUE_SIZE +#define APP_USBD_CONFIG_EVENT_QUEUE_SIZE 32 +#endif + +// APP_USBD_CONFIG_SOF_HANDLING_MODE - Change SOF events handling mode. + + +// Normal queue - SOF events are pushed normally into the event queue. +// Compress queue - SOF events are counted and binded with other events or executed when the queue is empty. +// This prevents the queue from filling up with SOF events. +// Interrupt - SOF events are processed in interrupt. +// <0=> Normal queue +// <1=> Compress queue +// <2=> Interrupt + +#ifndef APP_USBD_CONFIG_SOF_HANDLING_MODE +#define APP_USBD_CONFIG_SOF_HANDLING_MODE 1 +#endif + +// + +// APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE - Provide a function that generates timestamps for logs based on the current SOF. + + +// The function app_usbd_sof_timestamp_get is implemented if the logger is enabled. +// Use it when initializing the logger. +// SOF processing is always enabled when this configuration parameter is active. +// Note: This option is configured outside of APP_USBD_CONFIG_LOG_ENABLED. +// This means that it works even if the logging in this very module is disabled. + +#ifndef APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE +#define APP_USBD_CONFIG_SOF_TIMESTAMP_PROVIDE 0 +#endif + +// APP_USBD_CONFIG_DESC_STRING_SIZE - Maximum size of the NULL-terminated string of the string descriptor. <31-254> + + +// 31 characters can be stored in the internal USB buffer used for transfers. +// Any value higher than 31 creates an additional buffer just for descriptor strings. + +#ifndef APP_USBD_CONFIG_DESC_STRING_SIZE +#define APP_USBD_CONFIG_DESC_STRING_SIZE 31 +#endif + +// APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED - Enable UTF8 conversion. + + +// Enable UTF8-encoded characters. In normal processing, only ASCII characters are available. + +#ifndef APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED +#define APP_USBD_CONFIG_DESC_STRING_UTF_ENABLED 0 +#endif + +// APP_USBD_STRINGS_LANGIDS - Supported languages identifiers. + +// Note: This value is not editable in Configuration Wizard. +// Comma-separated list of supported languages. +#ifndef APP_USBD_STRINGS_LANGIDS +#define APP_USBD_STRINGS_LANGIDS APP_USBD_LANG_AND_SUBLANG(APP_USBD_LANG_ENGLISH, APP_USBD_SUBLANG_ENGLISH_US) +#endif + +// APP_USBD_STRING_ID_MANUFACTURER - Define manufacturer string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_MANUFACTURER +#define APP_USBD_STRING_ID_MANUFACTURER 1 +#endif +// APP_USBD_STRINGS_MANUFACTURER_EXTERN - Define whether @ref APP_USBD_STRINGS_MANUFACTURER is created by macro or declared as a global variable. + + +#ifndef APP_USBD_STRINGS_MANUFACTURER_EXTERN +#define APP_USBD_STRINGS_MANUFACTURER_EXTERN 0 +#endif + +// APP_USBD_STRINGS_MANUFACTURER - String descriptor for the manufacturer name. + +// Note: This value is not editable in Configuration Wizard. +// Comma-separated list of manufacturer names for each defined language. +// Use @ref APP_USBD_STRING_DESC macro to create string descriptor from a NULL-terminated string. +// Use @ref APP_USBD_STRING_RAW8_DESC macro to create string descriptor from comma-separated uint8_t values. +// Use @ref APP_USBD_STRING_RAW16_DESC macro to create string descriptor from comma-separated uint16_t values. +// Alternatively, configure the macro to point to any internal variable pointer that already contains the descriptor. +// Setting string to NULL disables that string. +// The order of manufacturer names must be the same like in @ref APP_USBD_STRINGS_LANGIDS. +#ifndef APP_USBD_STRINGS_MANUFACTURER +#define APP_USBD_STRINGS_MANUFACTURER APP_USBD_STRING_DESC("Nordic Semiconductor") +#endif + +// + +// APP_USBD_STRING_ID_PRODUCT - Define product string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_PRODUCT +#define APP_USBD_STRING_ID_PRODUCT 2 +#endif +// APP_USBD_STRINGS_PRODUCT_EXTERN - Define whether @ref APP_USBD_STRINGS_PRODUCT is created by macro or declared as a global variable. + + +#ifndef APP_USBD_STRINGS_PRODUCT_EXTERN +#define APP_USBD_STRINGS_PRODUCT_EXTERN 0 +#endif + +// APP_USBD_STRINGS_PRODUCT - String descriptor for the product name. + +// Note: This value is not editable in Configuration Wizard. +// List of product names that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER. +#ifndef APP_USBD_STRINGS_PRODUCT +#define APP_USBD_STRINGS_PRODUCT APP_USBD_STRING_DESC("nRF52 USB Product") +#endif + +// + +// APP_USBD_STRING_ID_SERIAL - Define serial number string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_SERIAL +#define APP_USBD_STRING_ID_SERIAL 3 +#endif +// APP_USBD_STRING_SERIAL_EXTERN - Define whether @ref APP_USBD_STRING_SERIAL is created by macro or declared as a global variable. + + +#ifndef APP_USBD_STRING_SERIAL_EXTERN +#define APP_USBD_STRING_SERIAL_EXTERN 0 +#endif + +// APP_USBD_STRING_SERIAL - String descriptor for the serial number. + +// Note: This value is not editable in Configuration Wizard. +// Serial number that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER. +#ifndef APP_USBD_STRING_SERIAL +#define APP_USBD_STRING_SERIAL APP_USBD_STRING_DESC("000000000000") +#endif + +// + +// APP_USBD_STRING_ID_CONFIGURATION - Define configuration string ID. + +// Setting ID to 0 disables the string. +//========================================================== +#ifndef APP_USBD_STRING_ID_CONFIGURATION +#define APP_USBD_STRING_ID_CONFIGURATION 4 +#endif +// APP_USBD_STRING_CONFIGURATION_EXTERN - Define whether @ref APP_USBD_STRINGS_CONFIGURATION is created by macro or declared as global variable. + + +#ifndef APP_USBD_STRING_CONFIGURATION_EXTERN +#define APP_USBD_STRING_CONFIGURATION_EXTERN 0 +#endif + +// APP_USBD_STRINGS_CONFIGURATION - String descriptor for the device configuration. + +// Note: This value is not editable in Configuration Wizard. +// Configuration string that is defined the same way like in @ref APP_USBD_STRINGS_MANUFACTURER. +#ifndef APP_USBD_STRINGS_CONFIGURATION +#define APP_USBD_STRINGS_CONFIGURATION APP_USBD_STRING_DESC("Default configuration") +#endif + +// + +// APP_USBD_STRINGS_USER - Default values for user strings. + +// Note: This value is not editable in Configuration Wizard. +// This value stores all application specific user strings with the default initialization. +// The setup is done by X-macros. +// Expected macro parameters: +// @code +// X(mnemonic, [=str_idx], ...) +// @endcode +// - @c mnemonic: Mnemonic of the string descriptor that would be added to +// @ref app_usbd_string_desc_idx_t enumerator. +// - @c str_idx : String index value, can be set or left empty. +// For example, WinUSB driver requires descriptor to be present on 0xEE index. +// Then use X(USBD_STRING_WINUSB, =0xEE, (APP_USBD_STRING_DESC(...))) +// - @c ... : List of string descriptors for each defined language. +#ifndef APP_USBD_STRINGS_USER +#define APP_USBD_STRINGS_USER X(APP_USER_1, , APP_USBD_STRING_DESC("User 1")) +#endif + +// + +// APP_USBD_HID_ENABLED - app_usbd_hid - USB HID class +//========================================================== +#ifndef APP_USBD_HID_ENABLED +#define APP_USBD_HID_ENABLED 0 +#endif +// APP_USBD_HID_DEFAULT_IDLE_RATE - Default idle rate for HID class. <0-255> + + +// 0 means indefinite duration, any other value is multiplied by 4 milliseconds. Refer to Chapter 7.2.4 of HID 1.11 Specification. + +#ifndef APP_USBD_HID_DEFAULT_IDLE_RATE +#define APP_USBD_HID_DEFAULT_IDLE_RATE 0 +#endif + +// APP_USBD_HID_REPORT_IDLE_TABLE_SIZE - Size of idle rate table. <1-255> + + +// Must be higher than the highest report ID used. + +#ifndef APP_USBD_HID_REPORT_IDLE_TABLE_SIZE +#define APP_USBD_HID_REPORT_IDLE_TABLE_SIZE 4 +#endif + +// + +// APP_USBD_HID_GENERIC_ENABLED - app_usbd_hid_generic - USB HID generic + + +#ifndef APP_USBD_HID_GENERIC_ENABLED +#define APP_USBD_HID_GENERIC_ENABLED 0 +#endif + +// APP_USBD_HID_KBD_ENABLED - app_usbd_hid_kbd - USB HID keyboard + + +#ifndef APP_USBD_HID_KBD_ENABLED +#define APP_USBD_HID_KBD_ENABLED 0 +#endif + +// APP_USBD_HID_MOUSE_ENABLED - app_usbd_hid_mouse - USB HID mouse + + +#ifndef APP_USBD_HID_MOUSE_ENABLED +#define APP_USBD_HID_MOUSE_ENABLED 0 +#endif + +// APP_USBD_MSC_ENABLED - app_usbd_msc - USB MSC class + + +#ifndef APP_USBD_MSC_ENABLED +#define APP_USBD_MSC_ENABLED 0 +#endif + +// CRC16_ENABLED - crc16 - CRC16 calculation routines + + +#ifndef CRC16_ENABLED +#define CRC16_ENABLED 0 +#endif + +// CRC32_ENABLED - crc32 - CRC32 calculation routines + + +#ifndef CRC32_ENABLED +#define CRC32_ENABLED 0 +#endif + +// ECC_ENABLED - ecc - Elliptic Curve Cryptography Library + + +#ifndef ECC_ENABLED +#define ECC_ENABLED 0 +#endif + +// FDS_ENABLED - fds - Flash data storage module +//========================================================== +#ifndef FDS_ENABLED +#define FDS_ENABLED 0 +#endif +// Pages - Virtual page settings + +// Configure the number of virtual pages to use and their size. +//========================================================== +// FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. +// One of the virtual pages is reserved by the system for garbage collection. +// Therefore, the minimum is two virtual pages: one page to store data and one page to be used by the system for garbage collection. +// The total amount of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES * @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes. + +#ifndef FDS_VIRTUAL_PAGES +#define FDS_VIRTUAL_PAGES 3 +#endif + +// FDS_VIRTUAL_PAGE_SIZE - The size of a virtual flash page. + + +// Expressed in number of 4-byte words. +// By default, a virtual page is the same size as a physical page. +// The size of a virtual page must be a multiple of the size of a physical page. +// <1024=> 1024 +// <2048=> 2048 + +#ifndef FDS_VIRTUAL_PAGE_SIZE +#define FDS_VIRTUAL_PAGE_SIZE 1024 +#endif + +// FDS_VIRTUAL_PAGES_RESERVED - The number of virtual flash pages that are used by other modules. +// FDS module stores its data in the last pages of the flash memory. +// By setting this value, you can move flash end address used by the FDS. +// As a result the reserved space can be used by other modules. + +#ifndef FDS_VIRTUAL_PAGES_RESERVED +#define FDS_VIRTUAL_PAGES_RESERVED 0 +#endif + +// +//========================================================== + +// Backend - Backend configuration + +// Configure which nrf_fstorage backend is used by FDS to write to flash. +//========================================================== +// FDS_BACKEND - FDS flash backend. + + +// NRF_FSTORAGE_SD uses the nrf_fstorage_sd backend implementation using the SoftDevice API. Use this if you have a SoftDevice present. +// NRF_FSTORAGE_NVMC uses the nrf_fstorage_nvmc implementation. Use this setting if you don't use the SoftDevice. +// <1=> NRF_FSTORAGE_NVMC +// <2=> NRF_FSTORAGE_SD + +#ifndef FDS_BACKEND +#define FDS_BACKEND 2 +#endif + +// +//========================================================== + +// Queue - Queue settings + +//========================================================== +// FDS_OP_QUEUE_SIZE - Size of the internal queue. +// Increase this value if you frequently get synchronous FDS_ERR_NO_SPACE_IN_QUEUES errors. + +#ifndef FDS_OP_QUEUE_SIZE +#define FDS_OP_QUEUE_SIZE 4 +#endif + +// +//========================================================== + +// CRC - CRC functionality + +//========================================================== +// FDS_CRC_CHECK_ON_READ - Enable CRC checks. + +// Save a record's CRC when it is written to flash and check it when the record is opened. +// Records with an incorrect CRC can still be 'seen' by the user using FDS functions, but they cannot be opened. +// Additionally, they will not be garbage collected until they are deleted. +//========================================================== +#ifndef FDS_CRC_CHECK_ON_READ +#define FDS_CRC_CHECK_ON_READ 0 +#endif +// FDS_CRC_CHECK_ON_WRITE - Perform a CRC check on newly written records. + + +// Perform a CRC check on newly written records. +// This setting can be used to make sure that the record data was not altered while being written to flash. +// <1=> Enabled +// <0=> Disabled + +#ifndef FDS_CRC_CHECK_ON_WRITE +#define FDS_CRC_CHECK_ON_WRITE 0 +#endif + +// + +// +//========================================================== + +// Users - Number of users + +//========================================================== +// FDS_MAX_USERS - Maximum number of callbacks that can be registered. +#ifndef FDS_MAX_USERS +#define FDS_MAX_USERS 4 +#endif + +// +//========================================================== + +// + +// HARDFAULT_HANDLER_ENABLED - hardfault_default - HardFault default handler for debugging and release + + +#ifndef HARDFAULT_HANDLER_ENABLED +#define HARDFAULT_HANDLER_ENABLED 0 +#endif + +// HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI +//========================================================== +#ifndef HCI_MEM_POOL_ENABLED +#define HCI_MEM_POOL_ENABLED 0 +#endif +// HCI_TX_BUF_SIZE - TX buffer size in bytes. +#ifndef HCI_TX_BUF_SIZE +#define HCI_TX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_SIZE - RX buffer size in bytes. +#ifndef HCI_RX_BUF_SIZE +#define HCI_RX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. +#ifndef HCI_RX_BUF_QUEUE_SIZE +#define HCI_RX_BUF_QUEUE_SIZE 4 +#endif + +// + +// HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI +//========================================================== +#ifndef HCI_SLIP_ENABLED +#define HCI_SLIP_ENABLED 0 +#endif +// HCI_UART_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30801920=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 1000000 baud + +#ifndef HCI_UART_BAUDRATE +#define HCI_UART_BAUDRATE 30801920 +#endif + +// HCI_UART_FLOW_CONTROL - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef HCI_UART_FLOW_CONTROL +#define HCI_UART_FLOW_CONTROL 0 +#endif + +// HCI_UART_RX_PIN - UART RX pin +#ifndef HCI_UART_RX_PIN +#define HCI_UART_RX_PIN 31 +#endif + +// HCI_UART_TX_PIN - UART TX pin +#ifndef HCI_UART_TX_PIN +#define HCI_UART_TX_PIN 31 +#endif + +// HCI_UART_RTS_PIN - UART RTS pin +#ifndef HCI_UART_RTS_PIN +#define HCI_UART_RTS_PIN 31 +#endif + +// HCI_UART_CTS_PIN - UART CTS pin +#ifndef HCI_UART_CTS_PIN +#define HCI_UART_CTS_PIN 31 +#endif + +// + +// HCI_TRANSPORT_ENABLED - hci_transport - HCI transport +//========================================================== +#ifndef HCI_TRANSPORT_ENABLED +#define HCI_TRANSPORT_ENABLED 0 +#endif +// HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. +#ifndef HCI_MAX_PACKET_SIZE_IN_BITS +#define HCI_MAX_PACKET_SIZE_IN_BITS 8000 +#endif + +// + +// LED_SOFTBLINK_ENABLED - led_softblink - led_softblink module + + +#ifndef LED_SOFTBLINK_ENABLED +#define LED_SOFTBLINK_ENABLED 0 +#endif + +// LOW_POWER_PWM_ENABLED - low_power_pwm - low_power_pwm module + + +#ifndef LOW_POWER_PWM_ENABLED +#define LOW_POWER_PWM_ENABLED 0 +#endif + +// MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator +//========================================================== +#ifndef MEM_MANAGER_ENABLED +#define MEM_MANAGER_ENABLED 0 +#endif +// MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block. <0-255> + + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT +#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1 +#endif + +// MEMORY_MANAGER_SMALL_BLOCK_SIZE - Size of each memory blocks identified as 'small' block. +// Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE +#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block. <0-255> + + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT +#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_SIZE - Size of each memory blocks identified as 'medium' block. +// Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE +#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block. <0-255> + + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT +#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_SIZE - Size of each memory blocks identified as 'large' block. +// Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE +#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256 +#endif + +// MEMORY_MANAGER_XLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra large' block. <0-255> + + +#ifndef MEMORY_MANAGER_XLARGE_BLOCK_COUNT +#define MEMORY_MANAGER_XLARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra large' block. +// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XLARGE_BLOCK_SIZE +#define MEMORY_MANAGER_XLARGE_BLOCK_SIZE 1320 +#endif + +// MEMORY_MANAGER_XXLARGE_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra large' block. <0-255> + + +#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_COUNT +#define MEMORY_MANAGER_XXLARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XXLARGE_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra large' block. +// Size of each memory blocks identified as 'extra extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XXLARGE_BLOCK_SIZE +#define MEMORY_MANAGER_XXLARGE_BLOCK_SIZE 3444 +#endif + +// MEMORY_MANAGER_XSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra small' block. <0-255> + + +#ifndef MEMORY_MANAGER_XSMALL_BLOCK_COUNT +#define MEMORY_MANAGER_XSMALL_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra small' block. +// Size of each memory blocks identified as 'extra large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XSMALL_BLOCK_SIZE +#define MEMORY_MANAGER_XSMALL_BLOCK_SIZE 64 +#endif + +// MEMORY_MANAGER_XXSMALL_BLOCK_COUNT - Size of each memory blocks identified as 'extra extra small' block. <0-255> + + +#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_COUNT +#define MEMORY_MANAGER_XXSMALL_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_XXSMALL_BLOCK_SIZE - Size of each memory blocks identified as 'extra extra small' block. +// Size of each memory blocks identified as 'extra extra small' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_XXSMALL_BLOCK_SIZE +#define MEMORY_MANAGER_XXSMALL_BLOCK_SIZE 32 +#endif + +// MEM_MANAGER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef MEM_MANAGER_CONFIG_LOG_ENABLED +#define MEM_MANAGER_CONFIG_LOG_ENABLED 0 +#endif +// MEM_MANAGER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef MEM_MANAGER_CONFIG_LOG_LEVEL +#define MEM_MANAGER_CONFIG_LOG_LEVEL 3 +#endif + +// MEM_MANAGER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MEM_MANAGER_CONFIG_INFO_COLOR +#define MEM_MANAGER_CONFIG_INFO_COLOR 0 +#endif + +// MEM_MANAGER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef MEM_MANAGER_CONFIG_DEBUG_COLOR +#define MEM_MANAGER_CONFIG_DEBUG_COLOR 0 +#endif + +// + +// MEM_MANAGER_DISABLE_API_PARAM_CHECK - Disable API parameter checks in the module. + + +#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK +#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0 +#endif + +// + +// NRF_BALLOC_ENABLED - nrf_balloc - Block allocator module +//========================================================== +#ifndef NRF_BALLOC_ENABLED +#define NRF_BALLOC_ENABLED 1 +#endif +// NRF_BALLOC_CONFIG_DEBUG_ENABLED - Enables debug mode in the module. +//========================================================== +#ifndef NRF_BALLOC_CONFIG_DEBUG_ENABLED +#define NRF_BALLOC_CONFIG_DEBUG_ENABLED 0 +#endif +// NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS - Number of words used as head guard. <0-255> + + +#ifndef NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS +#define NRF_BALLOC_CONFIG_HEAD_GUARD_WORDS 1 +#endif + +// NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS - Number of words used as tail guard. <0-255> + + +#ifndef NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS +#define NRF_BALLOC_CONFIG_TAIL_GUARD_WORDS 1 +#endif + +// NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED - Enables basic checks in this module. + + +#ifndef NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED +#define NRF_BALLOC_CONFIG_BASIC_CHECKS_ENABLED 0 +#endif + +// NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED - Enables double memory free check in this module. + + +#ifndef NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED +#define NRF_BALLOC_CONFIG_DOUBLE_FREE_CHECK_ENABLED 0 +#endif + +// NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED - Enables free memory corruption check in this module. + + +#ifndef NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED +#define NRF_BALLOC_CONFIG_DATA_TRASHING_CHECK_ENABLED 0 +#endif + +// NRF_BALLOC_CLI_CMDS - Enable CLI commands specific to the module + + +#ifndef NRF_BALLOC_CLI_CMDS +#define NRF_BALLOC_CLI_CMDS 0 +#endif + +// + +// + +// NRF_CSENSE_ENABLED - nrf_csense - Capacitive sensor module +//========================================================== +#ifndef NRF_CSENSE_ENABLED +#define NRF_CSENSE_ENABLED 0 +#endif +// NRF_CSENSE_PAD_HYSTERESIS - Minimum value of change required to determine that a pad was touched. +#ifndef NRF_CSENSE_PAD_HYSTERESIS +#define NRF_CSENSE_PAD_HYSTERESIS 15 +#endif + +// NRF_CSENSE_PAD_DEVIATION - Minimum value measured on a pad required to take it into account while calculating the step. +#ifndef NRF_CSENSE_PAD_DEVIATION +#define NRF_CSENSE_PAD_DEVIATION 70 +#endif + +// NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on a pad required to take its value into account. +#ifndef NRF_CSENSE_MIN_PAD_VALUE +#define NRF_CSENSE_MIN_PAD_VALUE 20 +#endif + +// NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. +#ifndef NRF_CSENSE_MAX_PADS_NUMBER +#define NRF_CSENSE_MAX_PADS_NUMBER 20 +#endif + +// NRF_CSENSE_MAX_VALUE - Maximum normalized value obtained from measurement. +#ifndef NRF_CSENSE_MAX_VALUE +#define NRF_CSENSE_MAX_VALUE 1000 +#endif + +// NRF_CSENSE_OUTPUT_PIN - Output pin used by the low-level module. +// This is used when capacitive sensor does not use COMP. + +#ifndef NRF_CSENSE_OUTPUT_PIN +#define NRF_CSENSE_OUTPUT_PIN 26 +#endif + +// + +// NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor low-level module +//========================================================== +#ifndef NRF_DRV_CSENSE_ENABLED +#define NRF_DRV_CSENSE_ENABLED 0 +#endif +// USE_COMP - Use the comparator to implement the capacitive sensor driver. + +// Due to Anomaly 84, COMP I_SOURCE is not functional. It has too high a varation. +//========================================================== +#ifndef USE_COMP +#define USE_COMP 0 +#endif +// TIMER0_FOR_CSENSE - First TIMER instance used by the driver (not used on nRF51). +#ifndef TIMER0_FOR_CSENSE +#define TIMER0_FOR_CSENSE 1 +#endif + +// TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (not used on nRF51). +#ifndef TIMER1_FOR_CSENSE +#define TIMER1_FOR_CSENSE 2 +#endif + +// MEASUREMENT_PERIOD - Single measurement period. +// Time of a single measurement can be calculated as +// T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ). +// I_SOURCE, VUP, and VDOWN are values used to initialize COMP and C is the capacitance of the used pad. + +#ifndef MEASUREMENT_PERIOD +#define MEASUREMENT_PERIOD 20 +#endif + +// + +// + +// NRF_FSTORAGE_ENABLED - nrf_fstorage - Flash abstraction library +//========================================================== +#ifndef NRF_FSTORAGE_ENABLED +#define NRF_FSTORAGE_ENABLED 0 +#endif +// nrf_fstorage - Common settings + +// Common settings to all fstorage implementations +//========================================================== +// NRF_FSTORAGE_PARAM_CHECK_DISABLED - Disable user input validation + + +// If selected, use ASSERT to validate user input. +// This effectively removes user input validation in production code. +// Recommended setting: OFF, only enable this setting if size is a major concern. + +#ifndef NRF_FSTORAGE_PARAM_CHECK_DISABLED +#define NRF_FSTORAGE_PARAM_CHECK_DISABLED 0 +#endif + +// +//========================================================== + +// nrf_fstorage_sd - Implementation using the SoftDevice + +// Configuration options for the fstorage implementation using the SoftDevice +//========================================================== +// NRF_FSTORAGE_SD_QUEUE_SIZE - Size of the internal queue of operations +// Increase this value if API calls frequently return the error @ref NRF_ERROR_NO_MEM. + +#ifndef NRF_FSTORAGE_SD_QUEUE_SIZE +#define NRF_FSTORAGE_SD_QUEUE_SIZE 4 +#endif + +// NRF_FSTORAGE_SD_MAX_RETRIES - Maximum number of attempts at executing an operation when the SoftDevice is busy +// Increase this value if events frequently return the @ref NRF_ERROR_TIMEOUT error. +// The SoftDevice might fail to schedule flash access due to high BLE activity. + +#ifndef NRF_FSTORAGE_SD_MAX_RETRIES +#define NRF_FSTORAGE_SD_MAX_RETRIES 8 +#endif + +// NRF_FSTORAGE_SD_MAX_WRITE_SIZE - Maximum number of bytes to be written to flash in a single operation +// This value must be a multiple of four. +// Lowering this value can increase the chances of the SoftDevice being able to execute flash operations in between radio activity. +// This value is bound by the maximum number of bytes that can be written to flash in a single call to @ref sd_flash_write. +// That is 1024 bytes for nRF51 ICs and 4096 bytes for nRF52 ICs. + +#ifndef NRF_FSTORAGE_SD_MAX_WRITE_SIZE +#define NRF_FSTORAGE_SD_MAX_WRITE_SIZE 4096 +#endif + +// +//========================================================== + +// + +// NRF_GFX_ENABLED - nrf_gfx - GFX module + + +#ifndef NRF_GFX_ENABLED +#define NRF_GFX_ENABLED 0 +#endif + +// NRF_MEMOBJ_ENABLED - nrf_memobj - Linked memory allocator module + + +#ifndef NRF_MEMOBJ_ENABLED +#define NRF_MEMOBJ_ENABLED 1 +#endif + +// NRF_PWR_MGMT_ENABLED - nrf_pwr_mgmt - Power management module +//========================================================== +#ifndef NRF_PWR_MGMT_ENABLED +#define NRF_PWR_MGMT_ENABLED 0 +#endif +// NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED - Enables pin debug in the module. + +// Selected pin will be set when CPU is in sleep mode. +//========================================================== +#ifndef NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED +#define NRF_PWR_MGMT_CONFIG_DEBUG_PIN_ENABLED 0 +#endif +// NRF_PWR_MGMT_SLEEP_DEBUG_PIN - Pin number + +// <0=> 0 (P0.0) +// <1=> 1 (P0.1) +// <2=> 2 (P0.2) +// <3=> 3 (P0.3) +// <4=> 4 (P0.4) +// <5=> 5 (P0.5) +// <6=> 6 (P0.6) +// <7=> 7 (P0.7) +// <8=> 8 (P0.8) +// <9=> 9 (P0.9) +// <10=> 10 (P0.10) +// <11=> 11 (P0.11) +// <12=> 12 (P0.12) +// <13=> 13 (P0.13) +// <14=> 14 (P0.14) +// <15=> 15 (P0.15) +// <16=> 16 (P0.16) +// <17=> 17 (P0.17) +// <18=> 18 (P0.18) +// <19=> 19 (P0.19) +// <20=> 20 (P0.20) +// <21=> 21 (P0.21) +// <22=> 22 (P0.22) +// <23=> 23 (P0.23) +// <24=> 24 (P0.24) +// <25=> 25 (P0.25) +// <26=> 26 (P0.26) +// <27=> 27 (P0.27) +// <28=> 28 (P0.28) +// <29=> 29 (P0.29) +// <30=> 30 (P0.30) +// <31=> 31 (P0.31) +// <4294967295=> Not connected + +#ifndef NRF_PWR_MGMT_SLEEP_DEBUG_PIN +#define NRF_PWR_MGMT_SLEEP_DEBUG_PIN 31 +#endif + +// + +// NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED - Enables CPU usage monitor. + + +// Module will trace percentage of CPU usage in one second intervals. + +#ifndef NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED +#define NRF_PWR_MGMT_CONFIG_CPU_USAGE_MONITOR_ENABLED 0 +#endif + +// NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED - Enable standby timeout. +//========================================================== +#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED +#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_ENABLED 0 +#endif +// NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S - Standby timeout (in seconds). +// Shutdown procedure will begin no earlier than after this number of seconds. + +#ifndef NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S +#define NRF_PWR_MGMT_CONFIG_STANDBY_TIMEOUT_S 3 +#endif + +// + +// NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED - Enables FPU event cleaning. + + +#ifndef NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED +#define NRF_PWR_MGMT_CONFIG_FPU_SUPPORT_ENABLED 0 +#endif + +// NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY - Blocked shutdown procedure will be retried every second. + + +#ifndef NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY +#define NRF_PWR_MGMT_CONFIG_AUTO_SHUTDOWN_RETRY 0 +#endif + +// NRF_PWR_MGMT_CONFIG_USE_SCHEDULER - Module will use @ref app_scheduler. + + +#ifndef NRF_PWR_MGMT_CONFIG_USE_SCHEDULER +#define NRF_PWR_MGMT_CONFIG_USE_SCHEDULER 0 +#endif + +// NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT - The number of priorities for module handlers. +// The number of stages of the shutdown process. + +#ifndef NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT +#define NRF_PWR_MGMT_CONFIG_HANDLER_PRIORITY_COUNT 3 +#endif + +// + +// NRF_QUEUE_ENABLED - nrf_queue - Queue module +//========================================================== +#ifndef NRF_QUEUE_ENABLED +#define NRF_QUEUE_ENABLED 0 +#endif +// NRF_QUEUE_CLI_CMDS - Enable CLI commands specific to the module + + +#ifndef NRF_QUEUE_CLI_CMDS +#define NRF_QUEUE_CLI_CMDS 0 +#endif + +// + +// NRF_SECTION_ITER_ENABLED - nrf_section_iter - Section iterator + + +#ifndef NRF_SECTION_ITER_ENABLED +#define NRF_SECTION_ITER_ENABLED 1 +#endif + +// NRF_SORTLIST_ENABLED - nrf_sortlist - Sorted list + + +#ifndef NRF_SORTLIST_ENABLED +#define NRF_SORTLIST_ENABLED 1 +#endif + +// NRF_SPI_MNGR_ENABLED - nrf_spi_mngr - SPI transaction manager + + +#ifndef NRF_SPI_MNGR_ENABLED +#define NRF_SPI_MNGR_ENABLED 0 +#endif + +// NRF_STRERROR_ENABLED - nrf_strerror - Library for converting error code to string. + + +#ifndef NRF_STRERROR_ENABLED +#define NRF_STRERROR_ENABLED 1 +#endif + +// NRF_TWI_MNGR_ENABLED - nrf_twi_mngr - TWI transaction manager + + +#ifndef NRF_TWI_MNGR_ENABLED +#define NRF_TWI_MNGR_ENABLED 0 +#endif + +// SLIP_ENABLED - slip - SLIP encoding and decoding + + +#ifndef SLIP_ENABLED +#define SLIP_ENABLED 0 +#endif + +// TASK_MANAGER_ENABLED - task_manager - Task manager. +//========================================================== +#ifndef TASK_MANAGER_ENABLED +#define TASK_MANAGER_ENABLED 0 +#endif +// TASK_MANAGER_CLI_CMDS - Enable CLI commands specific to the module + + +#ifndef TASK_MANAGER_CLI_CMDS +#define TASK_MANAGER_CLI_CMDS 0 +#endif + +// TASK_MANAGER_CONFIG_MAX_TASKS - Maximum number of tasks which can be created +#ifndef TASK_MANAGER_CONFIG_MAX_TASKS +#define TASK_MANAGER_CONFIG_MAX_TASKS 2 +#endif + +// TASK_MANAGER_CONFIG_STACK_SIZE - Stack size for every task (power of 2) +#ifndef TASK_MANAGER_CONFIG_STACK_SIZE +#define TASK_MANAGER_CONFIG_STACK_SIZE 1024 +#endif + +// TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED - Enable stack profiling. + + +#ifndef TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED +#define TASK_MANAGER_CONFIG_STACK_PROFILER_ENABLED 1 +#endif + +// TASK_MANAGER_CONFIG_STACK_GUARD - Configures stack guard. + +// <0=> Disabled +// <4=> 32 bytes +// <5=> 64 bytes +// <6=> 128 bytes +// <7=> 256 bytes +// <8=> 512 bytes + +#ifndef TASK_MANAGER_CONFIG_STACK_GUARD +#define TASK_MANAGER_CONFIG_STACK_GUARD 7 +#endif + +// + +// app_button - buttons handling module + +//========================================================== +// BUTTON_ENABLED - Enables Button module + + +#ifndef BUTTON_ENABLED +#define BUTTON_ENABLED 0 +#endif + +// BUTTON_HIGH_ACCURACY_ENABLED - Enables GPIOTE high accuracy for buttons + + +#ifndef BUTTON_HIGH_ACCURACY_ENABLED +#define BUTTON_HIGH_ACCURACY_ENABLED 0 +#endif + +// +//========================================================== + +// app_usbd_cdc_acm - USB CDC ACM class + +//========================================================== +// APP_USBD_CDC_ACM_ENABLED - Enabling USBD CDC ACM Class library + + +#ifndef APP_USBD_CDC_ACM_ENABLED +#define APP_USBD_CDC_ACM_ENABLED 0 +#endif + +// APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE - Send ZLP on write with same size as endpoint + + +// If enabled, CDC ACM class will automatically send a zero length packet after transfer which has the same size as endpoint. +// This may limit throughput if a lot of binary data is sent, but in terminal mode operation it makes sure that the data is always displayed right after it is sent. + +#ifndef APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE +#define APP_USBD_CDC_ACM_ZLP_ON_EPSIZE_WRITE 1 +#endif + +// +//========================================================== + +// nrf_cli - Command line interface + +//========================================================== +// NRF_CLI_ENABLED - Enable/disable the CLI module. + + +#ifndef NRF_CLI_ENABLED +#define NRF_CLI_ENABLED 0 +#endif + +// NRF_CLI_ARGC_MAX - Maximum number of parameters passed to the command handler. +#ifndef NRF_CLI_ARGC_MAX +#define NRF_CLI_ARGC_MAX 12 +#endif + +// NRF_CLI_BUILD_IN_CMDS_ENABLED - CLI built-in commands. + + +#ifndef NRF_CLI_BUILD_IN_CMDS_ENABLED +#define NRF_CLI_BUILD_IN_CMDS_ENABLED 1 +#endif + +// NRF_CLI_CMD_BUFF_SIZE - Maximum buffer size for a single command. +#ifndef NRF_CLI_CMD_BUFF_SIZE +#define NRF_CLI_CMD_BUFF_SIZE 128 +#endif + +// NRF_CLI_ECHO_STATUS - CLI echo status. If set, echo is ON. + + +#ifndef NRF_CLI_ECHO_STATUS +#define NRF_CLI_ECHO_STATUS 1 +#endif + +// NRF_CLI_WILDCARD_ENABLED - Enable wildcard functionality for CLI commands. + + +#ifndef NRF_CLI_WILDCARD_ENABLED +#define NRF_CLI_WILDCARD_ENABLED 0 +#endif + +// NRF_CLI_METAKEYS_ENABLED - Enable additional control keys for CLI commands like ctrl+a, ctrl+e, ctrl+w, ctrl+u + + +#ifndef NRF_CLI_METAKEYS_ENABLED +#define NRF_CLI_METAKEYS_ENABLED 0 +#endif + +// NRF_CLI_PRINTF_BUFF_SIZE - Maximum print buffer size. +#ifndef NRF_CLI_PRINTF_BUFF_SIZE +#define NRF_CLI_PRINTF_BUFF_SIZE 23 +#endif + +// NRF_CLI_HISTORY_ENABLED - Enable CLI history mode. +//========================================================== +#ifndef NRF_CLI_HISTORY_ENABLED +#define NRF_CLI_HISTORY_ENABLED 1 +#endif +// NRF_CLI_HISTORY_ELEMENT_SIZE - Size of one memory object reserved for CLI history. +#ifndef NRF_CLI_HISTORY_ELEMENT_SIZE +#define NRF_CLI_HISTORY_ELEMENT_SIZE 32 +#endif + +// NRF_CLI_HISTORY_ELEMENT_COUNT - Number of history memory objects. +#ifndef NRF_CLI_HISTORY_ELEMENT_COUNT +#define NRF_CLI_HISTORY_ELEMENT_COUNT 8 +#endif + +// + +// NRF_CLI_VT100_COLORS_ENABLED - CLI VT100 colors. + + +#ifndef NRF_CLI_VT100_COLORS_ENABLED +#define NRF_CLI_VT100_COLORS_ENABLED 1 +#endif + +// NRF_CLI_STATISTICS_ENABLED - Enable CLI statistics. + + +#ifndef NRF_CLI_STATISTICS_ENABLED +#define NRF_CLI_STATISTICS_ENABLED 1 +#endif + +// NRF_CLI_LOG_BACKEND - Enable logger backend interface. + + +#ifndef NRF_CLI_LOG_BACKEND +#define NRF_CLI_LOG_BACKEND 1 +#endif + +// NRF_CLI_USES_TASK_MANAGER_ENABLED - Enable CLI to use task_manager + + +#ifndef NRF_CLI_USES_TASK_MANAGER_ENABLED +#define NRF_CLI_USES_TASK_MANAGER_ENABLED 0 +#endif + +// +//========================================================== + +// nrf_fprintf - fprintf function. + +//========================================================== +// NRF_FPRINTF_ENABLED - Enable/disable fprintf module. + + +#ifndef NRF_FPRINTF_ENABLED +#define NRF_FPRINTF_ENABLED 1 +#endif + +// NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED - For each printed LF, function will add CR. + + +#ifndef NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED +#define NRF_FPRINTF_FLAG_AUTOMATIC_CR_ON_LF_ENABLED 1 +#endif + +// NRF_FPRINTF_DOUBLE_ENABLED - Enable IEEE-754 double precision formatting. + + +#ifndef NRF_FPRINTF_DOUBLE_ENABLED +#define NRF_FPRINTF_DOUBLE_ENABLED 0 +#endif + +// +//========================================================== + +// nRF_Segger_RTT + +// These are needed to avoid errors caused by removing all nRF logging +#define NRF_LOG_ENABLED 0 +#define NRF_SORTLIST_CONFIG_LOG_ENABLED 0 + +// segger_rtt - SEGGER RTT +// SEGGER_RTT_CONFIG_BUFFER_SIZE_UP - Size of upstream buffer. +// Note that either @ref NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE +// or this value is actually used. It depends on which one is bigger. +#ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_UP +#define SEGGER_RTT_CONFIG_BUFFER_SIZE_UP 5000 +#endif +// SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS - Maximum number of upstream buffers. +#ifndef SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS +#define SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS 1 +#endif +// SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN - Size of downstream buffer. +#ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN +#define SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN 16 +#endif +// SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS - Maximum number of downstream buffers. +#ifndef SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS +#define SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS 0 +#endif +// SEGGER_RTT_CONFIG_DEFAULT_MODE - RTT behavior if the buffer is full. +// The following modes are supported: +// - SKIP - Do not block, output nothing. +// - TRIM - Do not block, output as much as fits. +// - BLOCK - Wait until there is space in the buffer. +// <0=> SKIP +// <1=> TRIM +// <2=> BLOCK_IF_FIFO_FULL +#ifndef SEGGER_RTT_CONFIG_DEFAULT_MODE +#define SEGGER_RTT_CONFIG_DEFAULT_MODE 1 +#endif +// +// + +// +//========================================================== + + +// <<< end of configuration section >>> +#endif //SDK_CONFIG_H +