From 8b0df5e7dcf9323866ae53b9d38e4d620883efd1 Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Sat, 3 Apr 2021 18:13:50 +0000 Subject: [PATCH] fix for chipsalliance/chisel3#1730 --- iocell/src/main/scala/barstools/iocell/chisel/IOCell.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/iocell/src/main/scala/barstools/iocell/chisel/IOCell.scala b/iocell/src/main/scala/barstools/iocell/chisel/IOCell.scala index d244d298..160f3430 100644 --- a/iocell/src/main/scala/barstools/iocell/chisel/IOCell.scala +++ b/iocell/src/main/scala/barstools/iocell/chisel/IOCell.scala @@ -141,7 +141,7 @@ object IOCell { * @param name An optional name or name prefix to use for naming IO cells * @return A Seq of all generated IO cell instances */ - val toSyncReset: (Reset) => Bool = _.toBool + val toSyncReset: (Reset) => Bool = _.asBool val toAsyncReset: (Reset) => AsyncReset = _.asAsyncReset def generateFromSignal[T <: Data, R <: Reset]( coreSignal: T,