From 2220115440b8f6ccd206e658f04b4bd9557eafd2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=9C=C3=A2wissy?= <1536771081@qq.com> Date: Tue, 14 Jun 2022 18:13:48 +0800 Subject: [PATCH] add selection of a & fix srt8 --- arithmetic/src/division/srt/SRT.scala | 36 +++- arithmetic/src/division/srt/SRTTable.scala | 2 +- arithmetic/src/division/srt/srt16/OTF.scala | 4 +- arithmetic/src/division/srt/srt16/SRT16.scala | 1 - arithmetic/src/division/srt/srt4/OTF.scala | 62 +++++-- arithmetic/src/division/srt/srt4/QDS.scala | 40 +++-- arithmetic/src/division/srt/srt4/SRT4.scala | 81 ++++++--- arithmetic/src/division/srt/srt8/OTF.scala | 117 ++++++++++--- arithmetic/src/division/srt/srt8/QDS.scala | 110 +++++++++--- arithmetic/src/division/srt/srt8/SRT8.scala | 163 ++++++++++++++---- arithmetic/src/utils/package.scala | 2 +- .../tests/src/division/srt/SRTSpec.scala | 4 +- .../tests/src/division/srt/SRTTest.scala | 18 +- 13 files changed, 483 insertions(+), 157 deletions(-) diff --git a/arithmetic/src/division/srt/SRT.scala b/arithmetic/src/division/srt/SRT.scala index dd1d961..539afb4 100644 --- a/arithmetic/src/division/srt/SRT.scala +++ b/arithmetic/src/division/srt/SRT.scala @@ -15,9 +15,35 @@ class SRT( dTruncateWidth: Int = 4, rTruncateWidth: Int = 4) extends Module { +// val x = (radixLog2, a, dTruncateWidth) +// val tips = x match { +// case (2,2,4) => require(rTruncateWidth >= 4, "rTruncateWidth need >= 4") +// case (2,2,5) => require(rTruncateWidth >= 4, "rTruncateWidth need >= 4") +// case (2,2,6) => require(rTruncateWidth >= 4, "rTruncateWidth need >= 4") +// +// case (3,4,6) => require(rTruncateWidth >= 7, "rTruncateWidth need >= 7") +// case (3,4,7) => require(rTruncateWidth >= 6, "rTruncateWidth need >= 6") +// +// case (3,5,5) => require(rTruncateWidth >= 5, "rTruncateWidth need >= 5") +// case (3,5,6) => require(rTruncateWidth >= 4, "rTruncateWidth need >= 4") +// +// case (3,6,4) => require(rTruncateWidth >= 6, "rTruncateWidth need >= 6") +// case (3,6,5) => require(rTruncateWidth >= 4, "rTruncateWidth need >= 4") +// +// case (3,7,4) => require(rTruncateWidth >= 4, "rTruncateWidth need >= 4") +// case (3,7,5) => require(rTruncateWidth >= 3, "rTruncateWidth need >= 3") +// +// case (4,2,4) => require(rTruncateWidth >= 4, "rTruncateWidth need >= 4") +// case (4,2,5) => require(rTruncateWidth >= 4, "rTruncateWidth need >= 4") +// case (4,2,6) => require(rTruncateWidth >= 4, "rTruncateWidth need >= 4") +// +// case _ => println("this srt is not supported") +// } + val input = IO(Flipped(DecoupledIO(new SRTInput(dividendWidth, dividerWidth, n)))) val output = IO(ValidIO(new SRTOutput(dividerWidth, dividendWidth))) - // select radix + +// select radix if (radixLog2 == 2) { // SRT4 val srt = Module(new SRT4(dividendWidth, dividerWidth, n, radixLog2, a, dTruncateWidth, rTruncateWidth)) srt.input <> input @@ -31,4 +57,12 @@ class SRT( srt.input <> input output <> srt.output } + +// val srt = radixLog2 match { +// case 2 => Module(new SRT4(dividendWidth, dividerWidth, n, radixLog2, a, dTruncateWidth, rTruncateWidth)) +// case 3 => Module(new SRT8(dividendWidth, dividerWidth, n, radixLog2, a, dTruncateWidth, rTruncateWidth)) +// case 4 => Module(new SRT16(dividendWidth, dividerWidth, n, radixLog2 >> 1, a, dTruncateWidth, rTruncateWidth)) +// } +// srt.input <> input +// output <> srt.output } diff --git a/arithmetic/src/division/srt/SRTTable.scala b/arithmetic/src/division/srt/SRTTable.scala index b76c3a0..da843da 100644 --- a/arithmetic/src/division/srt/SRTTable.scala +++ b/arithmetic/src/division/srt/SRTTable.scala @@ -87,7 +87,7 @@ case class SRTTable( } // TODO: select a Constant from each m, then offer the table to QDS. - // select rule: symmetry and draw a line parallel to the X-axis, how define the rule + // todo: ? select rule: symmetry and draw a line parallel to the X-axis, how define the rule lazy val tablesToQDS: Seq[Seq[Int]] = { (aMin.toInt to aMax.toInt).drop(1).map { k => k -> dSet.dropRight(1).map { d => diff --git a/arithmetic/src/division/srt/srt16/OTF.scala b/arithmetic/src/division/srt/srt16/OTF.scala index 1c17a8e..d9d6d8b 100644 --- a/arithmetic/src/division/srt/srt16/OTF.scala +++ b/arithmetic/src/division/srt/srt16/OTF.scala @@ -40,11 +40,11 @@ object OTF { )(quotient: UInt, quotientMinusOne: UInt, selectedQuotientOH: UInt - ): Seq[UInt] = { + ): Vec[UInt] = { val m = Module(new OTF(radixLog2, qWidth, ohWidth)) m.input.quotient := quotient m.input.quotientMinusOne := quotientMinusOne m.input.selectedQuotientOH := selectedQuotientOH - Seq(m.output.quotient, m.output.quotientMinusOne) + VecInit(m.output.quotient, m.output.quotientMinusOne) } } diff --git a/arithmetic/src/division/srt/srt16/SRT16.scala b/arithmetic/src/division/srt/srt16/SRT16.scala index 210ba49..7ea12f1 100644 --- a/arithmetic/src/division/srt/srt16/SRT16.scala +++ b/arithmetic/src/division/srt/srt16/SRT16.scala @@ -76,7 +76,6 @@ class SRT16( val csa5 = addition.csa.c32(VecInit(csaIn1, csaIn2, dividerMap(4).head(csa0InWidth))) // 2 // qds - val tables: Seq[Seq[Int]] = SRTTable(1 << radixLog2, a, dTruncateWidth, rTruncateWidth).tablesToQDS val partialDivider: UInt = dividerNext.head(dTruncateWidth)(dTruncateWidth - 2, 0) val qdsOH0: UInt = diff --git a/arithmetic/src/division/srt/srt4/OTF.scala b/arithmetic/src/division/srt/srt4/OTF.scala index ffe3830..f89106a 100644 --- a/arithmetic/src/division/srt/srt4/OTF.scala +++ b/arithmetic/src/division/srt/srt4/OTF.scala @@ -4,29 +4,52 @@ import division.srt._ import chisel3._ import chisel3.util.Mux1H -class OTF(radixLog2: Int, qWidth: Int, ohWidth: Int) extends Module { +class OTF(radixLog2: Int, qWidth: Int, ohWidth: Int, a: Int) extends Module { val input = IO(Input(new OTFInput(qWidth, ohWidth))) val output = IO(Output(new OTFOutput(qWidth))) val radix: Int = 1 << radixLog2 // datapath // q_j+1 in this circle, only for srt4 - val qNext: UInt = Mux1H( - Seq( - input.selectedQuotientOH(0) -> "b110".U, - input.selectedQuotientOH(1) -> "b111".U, - input.selectedQuotientOH(2) -> "b000".U, - input.selectedQuotientOH(3) -> "b001".U, - input.selectedQuotientOH(4) -> "b010".U - ) - ) - // val cShiftQ: Bool = qNext >= 0.U // val cShiftQM: Bool = qNext <= 0.U - val cShiftQ: Bool = input.selectedQuotientOH(ohWidth - 1, ohWidth / 2).orR - val cShiftQM: Bool = input.selectedQuotientOH(ohWidth / 2, 0).orR - val qIn: UInt = Mux(cShiftQ, qNext, radix.U + qNext)(radixLog2 - 1, 0) - val qmIn: UInt = Mux(!cShiftQM, qNext - 1.U, (radix - 1).U + qNext)(radixLog2 - 1, 0) + val qNext: UInt = Wire(UInt(3.W)) + val cShiftQ, cShiftQM = Wire(Bool()) + + if (a == 2) { + qNext := Mux1H( + Seq( + input.selectedQuotientOH(0) -> "b110".U, //-2 + input.selectedQuotientOH(1) -> "b111".U, //-1 + input.selectedQuotientOH(2) -> "b000".U, // 0 + input.selectedQuotientOH(3) -> "b001".U, // 1 + input.selectedQuotientOH(4) -> "b010".U // 2 + ) + ) + cShiftQ := input.selectedQuotientOH(ohWidth - 1, ohWidth / 2).orR + cShiftQM := input.selectedQuotientOH(ohWidth / 2, 0).orR + } else if (a == 3) { + qNext := Mux1H( + Seq( + input.selectedQuotientOH(0) -> "b111".U, //-1 + input.selectedQuotientOH(1) -> "b000".U, // 0 + input.selectedQuotientOH(2) -> "b001".U // 1 + ) + ) + Mux1H( + Seq( + input.selectedQuotientOH(3) -> "b110".U, // -2 + input.selectedQuotientOH(4) -> "b000".U, // 0 + input.selectedQuotientOH(5) -> "b010".U // 2 + ) + ) + cShiftQ := input.selectedQuotientOH(5) || + (input.selectedQuotientOH(4) && input.selectedQuotientOH(2, 1).orR) + cShiftQM := input.selectedQuotientOH(3) || + (input.selectedQuotientOH(4) && input.selectedQuotientOH(1, 0).orR) + } + + val qIn: UInt = Mux(cShiftQ, qNext, radix.U + qNext)(radixLog2 - 1, 0) + val qmIn: UInt = Mux(!cShiftQM, qNext - 1.U, (radix - 1).U + qNext)(radixLog2 - 1, 0) output.quotient := Mux(cShiftQ, input.quotient, input.quotientMinusOne)(qWidth - radixLog2, 0) ## qIn output.quotientMinusOne := Mux(!cShiftQM, input.quotient, input.quotientMinusOne)(qWidth - radixLog2, 0) ## qmIn @@ -36,15 +59,16 @@ object OTF { def apply( radixLog2: Int, qWidth: Int, - ohWidth: Int + ohWidth: Int, + a: Int )(quotient: UInt, quotientMinusOne: UInt, selectedQuotientOH: UInt - ): Seq[UInt] = { - val m = Module(new OTF(radixLog2, qWidth, ohWidth)) + ): Vec[UInt] = { + val m = Module(new OTF(radixLog2, qWidth, ohWidth, a)) m.input.quotient := quotient m.input.quotientMinusOne := quotientMinusOne m.input.selectedQuotientOH := selectedQuotientOH - Seq(m.output.quotient, m.output.quotientMinusOne) + VecInit(m.output.quotient, m.output.quotientMinusOne) } } diff --git a/arithmetic/src/division/srt/srt4/QDS.scala b/arithmetic/src/division/srt/srt4/QDS.scala index 8897761..fa40757 100644 --- a/arithmetic/src/division/srt/srt4/QDS.scala +++ b/arithmetic/src/division/srt/srt4/QDS.scala @@ -7,7 +7,7 @@ import chisel3.util.BitPat.bitPatToUInt import chisel3.util.experimental.decode.TruthTable import utils.{extend, sIntToBitPat} -class QDS(rWidth: Int, ohWidth: Int, partialDividerWidth: Int, tables: Seq[Seq[Int]]) extends Module { +class QDS(rWidth: Int, ohWidth: Int, partialDividerWidth: Int, tables: Seq[Seq[Int]], a: Int) extends Module { // IO val input = IO(Input(new QDSInput(rWidth, partialDividerWidth))) val output = IO(Output(new QDSOutput(ohWidth))) @@ -54,15 +54,30 @@ class QDS(rWidth: Int, ohWidth: Int, partialDividerWidth: Int, tables: Seq[Seq[I // decoder or findFirstOne here, prefer decoder, the decoder only for srt4 output.selectedQuotientOH := chisel3.util.experimental.decode.decoder( selectPoints, - TruthTable( - Seq( - BitPat("b???0") -> BitPat("b10000"), //2 - BitPat("b??01") -> BitPat("b01000"), //1 - BitPat("b?011") -> BitPat("b00100"), //0 - BitPat("b0111") -> BitPat("b00010") //-1 - ), - BitPat("b00001") //-2 - ) + a match { + case 2 => + TruthTable( + Seq( + BitPat("b???0") -> BitPat("b10000"), //2 + BitPat("b??01") -> BitPat("b01000"), //1 + BitPat("b?011") -> BitPat("b00100"), //0 + BitPat("b0111") -> BitPat("b00010") //-1 + ), + BitPat("b00001") //-2 + ) + case 3 => + TruthTable( + Seq( // 2 0 -2 1 0 -1 + BitPat("b??_???0") -> BitPat("b100_100"), //3 = 2 + 1 + BitPat("b??_??01") -> BitPat("b100_010"), //2 = 2 + 0 + BitPat("b??_?011") -> BitPat("b010_100"), //1 = 0 + 1 + BitPat("b??_0111") -> BitPat("b010_010"), //0 = 0 + 0 + BitPat("b?0_1111") -> BitPat("b010_001"), //-1 = 0 + -1 + BitPat("b01_1111") -> BitPat("b001_010") //-2 = -2 + 0 + ), + BitPat("b001_001") //-3 = -2 + -1 + ) + } ) } @@ -71,12 +86,13 @@ object QDS { rWidth: Int, ohWidth: Int, partialDividerWidth: Int, - tables: Seq[Seq[Int]] + tables: Seq[Seq[Int]], + a: Int )(partialReminderSum: UInt, partialReminderCarry: UInt, partialDivider: UInt ): UInt = { - val m = Module(new QDS(rWidth, ohWidth, partialDividerWidth, tables)) + val m = Module(new QDS(rWidth, ohWidth, partialDividerWidth, tables, a)) m.input.partialReminderSum := partialReminderSum m.input.partialReminderCarry := partialReminderCarry m.input.partialDivider := partialDivider diff --git a/arithmetic/src/division/srt/srt4/SRT4.scala b/arithmetic/src/division/srt/srt4/SRT4.scala index 4111a27..f10dfaa 100644 --- a/arithmetic/src/division/srt/srt4/SRT4.scala +++ b/arithmetic/src/division/srt/srt4/SRT4.scala @@ -5,6 +5,7 @@ import addition.csa.CarrySaveAdder import addition.csa.common.CSACompressor3_2 import chisel3._ import chisel3.util._ +import spire.math import utils.leftShift /** SRT4 @@ -26,11 +27,8 @@ class SRT4( dTruncateWidth: Int = 4, rTruncateWidth: Int = 4) extends Module { - - val xLen: Int = dividendWidth + radixLog2 + 1 - val wLen: Int = xLen + radixLog2 - val ohWidth: Int = 2 * a + 1 - + val xLen: Int = dividendWidth + radixLog2 + 1 + val wLen: Int = xLen + radixLog2 // IO val input = IO(Flipped(DecoupledIO(new SRTInput(dividendWidth, dividerWidth, n)))) val output = IO(ValidIO(new SRTOutput(dividerWidth, dividendWidth))) @@ -41,9 +39,8 @@ class SRT4( val counterNext = Wire(UInt(log2Ceil(n).W)) // Control - // sign of select quotient, true -> negative, false -> positive // sign of Cycle, true -> (counter === 0.U) - val qdsSign, isLastCycle, enable: Bool = Wire(Bool()) + val isLastCycle, enable: Bool = Wire(Bool()) // State // because we need a CSA to minimize the critical path @@ -68,41 +65,77 @@ class SRT4( output.bits.reminder := Mux(needCorrect, remainderCorrect, remainderNoCorrect)(wLen - 4, radixLog2) output.bits.quotient := Mux(needCorrect, quotientMinusOne, quotient) - // qds val rWidth: Int = 1 + radixLog2 + rTruncateWidth val tables: Seq[Seq[Int]] = SRTTable(1 << radixLog2, a, dTruncateWidth, rTruncateWidth).tablesToQDS + val ohWidth: Int = a match { + case 2 => 2 * a + 1 + case 3 => 6 + } + //qds val selectedQuotientOH: UInt = - QDS(rWidth, ohWidth, dTruncateWidth - 1, tables)( + QDS(rWidth, ohWidth, dTruncateWidth - 1, tables, a)( leftShift(partialReminderSum, radixLog2).head(rWidth), leftShift(partialReminderCarry, radixLog2).head(rWidth), dividerNext.head(dTruncateWidth)(dTruncateWidth - 2, 0) //.1********* -> 1*** -> *** ) - qdsSign := selectedQuotientOH(ohWidth - 1, ohWidth / 2 + 1).orR + // On-The-Fly conversion + val otf = OTF(radixLog2, n, ohWidth, a)(quotient, quotientMinusOne, selectedQuotientOH) - // csa for SRT4 -> CSA32 - val csa = Module(new CarrySaveAdder(CSACompressor3_2, xLen)) - csa.in(0) := leftShift(partialReminderSum, radixLog2).head(wLen - radixLog2) - csa.in(1) := leftShift(partialReminderCarry, radixLog2).head(wLen - radixLog2 - 1) ## qdsSign - csa.in(2) := - Mux1H( - selectedQuotientOH, - //this is for SRT4, for SRT8 or SRT16, this should be changed - VecInit((-2 to 2).map { + val csa: Vec[UInt] = + if (a == 2) { // a == 2 + //csa + val dividerMap = VecInit((-2 to 2).map { case -2 => divider << 1 case -1 => divider case 0 => 0.U case 1 => Fill(1 + radixLog2, 1.U(1.W)) ## ~divider case 2 => Fill(radixLog2, 1.U(1.W)) ## ~(divider << 1) }) - ) + val qdsSign = selectedQuotientOH(ohWidth - 1, ohWidth / 2 + 1).orR + addition.csa.c32( + VecInit( + leftShift(partialReminderSum, radixLog2).head(wLen - radixLog2), + leftShift(partialReminderCarry, radixLog2).head(wLen - radixLog2 - 1) ## qdsSign, + Mux1H(selectedQuotientOH, dividerMap) + ) + ) + } else { // a==3 + val qHigh = selectedQuotientOH(5, 3) + val qLow = selectedQuotientOH(2, 0) + val qds0Sign = qHigh.head(1) + val qds1Sign = qLow.head(1) - // On-The-Fly conversion - val otf = OTF(radixLog2, n, ohWidth)(quotient, quotientMinusOne, selectedQuotientOH) + // csa + val dividerHMap = VecInit((-1 to 1).map { + case -1 => divider << 1 // -2 + case 0 => 0.U // 0 + case 1 => Fill(radixLog2, 1.U(1.W)) ## ~(divider << 1) // 2 + }) + val dividerLMap = VecInit((-1 to 1).map { + case -1 => divider // -1 + case 0 => 0.U // 0 + case 1 => Fill(1 + radixLog2, 1.U(1.W)) ## ~divider // 1 + }) + val csa0 = addition.csa.c32( + VecInit( + leftShift(partialReminderSum, radixLog2).head(wLen - radixLog2), + leftShift(partialReminderCarry, radixLog2).head(wLen - radixLog2 - 1) ## qds0Sign, + Mux1H(qHigh, dividerHMap) + ) + ) + addition.csa.c32( + VecInit( + csa0(1).head(wLen - radixLog2), + leftShift(csa0(0), 1).head(wLen - radixLog2 - 1) ## qds1Sign, + Mux1H(qLow, dividerLMap) + ) + ) + } dividerNext := Mux(input.fire, input.bits.divider, divider) counterNext := Mux(input.fire, input.bits.counter, counter - 1.U) quotientNext := Mux(input.fire, 0.U, otf(0)) quotientMinusOneNext := Mux(input.fire, 0.U, otf(1)) - partialReminderSumNext := Mux(input.fire, input.bits.dividend, csa.out(1) << radixLog2) - partialReminderCarryNext := Mux(input.fire, 0.U, csa.out(0) << 1 + radixLog2) + partialReminderSumNext := Mux(input.fire, input.bits.dividend, csa(1) << radixLog2) + partialReminderCarryNext := Mux(input.fire, 0.U, csa(0) << 1 + radixLog2) } diff --git a/arithmetic/src/division/srt/srt8/OTF.scala b/arithmetic/src/division/srt/srt8/OTF.scala index cefff67..640a67f 100644 --- a/arithmetic/src/division/srt/srt8/OTF.scala +++ b/arithmetic/src/division/srt/srt8/OTF.scala @@ -4,37 +4,101 @@ import division.srt._ import chisel3._ import chisel3.util.Mux1H -class OTF(radixLog2: Int, qWidth: Int, ohWidth: Int) extends Module { +class OTF(radixLog2: Int, qWidth: Int, ohWidth: Int, a: Int) extends Module { val input = IO(Input(new OTFInput(qWidth, ohWidth))) val output = IO(Output(new OTFOutput(qWidth))) val radix: Int = 1 << radixLog2 // datapath - // q_j+1 in this circle, only for srt8(a = 7) - val qNext: UInt = Mux1H( - Seq( - input.selectedQuotientOH(0) -> "b11110".U, // -2 - input.selectedQuotientOH(1) -> "b11111".U, // -1 - input.selectedQuotientOH(2) -> "b00000".U, // 0 - input.selectedQuotientOH(3) -> "b00001".U, // 1 - input.selectedQuotientOH(4) -> "b00010".U // 2 - ) - ) + Mux1H( - Seq( - input.selectedQuotientOH(5) -> "b11000".U, // -8 - input.selectedQuotientOH(6) -> "b11100".U, // -4 - input.selectedQuotientOH(7) -> "b00000".U, // 0 - input.selectedQuotientOH(8) -> "b00100".U, // 4 - input.selectedQuotientOH(9) -> "b01000".U // 8 - ) - ) - + // q_j+1 in this circle // val cShiftQ: Bool = qNext >= 0.U // val cShiftQM: Bool = qNext <= 0.U - val cShiftQ: Bool = input.selectedQuotientOH(9, 8).orR || + val qNext: UInt = Wire(UInt(5.W)) + val cShiftQ, cShiftQM: Bool = Wire(Bool()) + + if (a == 7) { + qNext := Mux1H( + Seq( + input.selectedQuotientOH(0) -> "b11110".U, // -2 + input.selectedQuotientOH(1) -> "b11111".U, // -1 + input.selectedQuotientOH(2) -> "b00000".U, // 0 + input.selectedQuotientOH(3) -> "b00001".U, // 1 + input.selectedQuotientOH(4) -> "b00010".U // 2 + ) + ) + Mux1H( + Seq( + input.selectedQuotientOH(5) -> "b11000".U, // -8 + input.selectedQuotientOH(6) -> "b11100".U, // -4 + input.selectedQuotientOH(7) -> "b00000".U, // 0 + input.selectedQuotientOH(8) -> "b00100".U, // 4 + input.selectedQuotientOH(9) -> "b01000".U // 8 + ) + ) + cShiftQ := input.selectedQuotientOH(9, 8).orR || (input.selectedQuotientOH(7) && input.selectedQuotientOH(4, 2).orR) - val cShiftQM: Bool = input.selectedQuotientOH(6, 5).orR || + cShiftQM := input.selectedQuotientOH(6, 5).orR || (input.selectedQuotientOH(7) && input.selectedQuotientOH(2, 0).orR) + } else if (a == 6) { + qNext := Mux1H( + Seq( + input.selectedQuotientOH(0) -> "b11110".U, // -2 + input.selectedQuotientOH(1) -> "b11111".U, // -1 + input.selectedQuotientOH(2) -> "b00000".U, // 0 + input.selectedQuotientOH(3) -> "b00001".U, // 1 + input.selectedQuotientOH(4) -> "b00010".U // 2 + ) + ) + Mux1H( + Seq( + input.selectedQuotientOH(5) -> "b11100".U, // -4 + input.selectedQuotientOH(6) -> "b00000".U, // 0 + input.selectedQuotientOH(7) -> "b00100".U // 4 + ) + ) + cShiftQ := input.selectedQuotientOH(7) || + (input.selectedQuotientOH(6) && input.selectedQuotientOH(4, 2).orR) + cShiftQM := input.selectedQuotientOH(5) || + (input.selectedQuotientOH(6) && input.selectedQuotientOH(2, 0).orR) + } else if (a == 5) { + qNext := Mux1H( + Seq( + input.selectedQuotientOH(0) -> "b11110".U, // -2 + input.selectedQuotientOH(1) -> "b11111".U, // -1 + input.selectedQuotientOH(2) -> "b00000".U, // 0 + input.selectedQuotientOH(3) -> "b00001".U, // 1 + input.selectedQuotientOH(4) -> "b00010".U // 2 + ) + ) + Mux1H( + Seq( + input.selectedQuotientOH(5) -> "b11100".U, // -4 + input.selectedQuotientOH(6) -> "b00000".U, // 0 + input.selectedQuotientOH(7) -> "b00100".U // 4 + ) + ) + cShiftQ := input.selectedQuotientOH(7) || + (input.selectedQuotientOH(6) && input.selectedQuotientOH(4, 2).orR) + cShiftQM := input.selectedQuotientOH(5) || + (input.selectedQuotientOH(6) && input.selectedQuotientOH(2, 0).orR) + } else if (a == 4) { + qNext := Mux1H( + Seq( + input.selectedQuotientOH(0) -> "b11110".U, // -2 + input.selectedQuotientOH(1) -> "b11111".U, // -1 + input.selectedQuotientOH(2) -> "b00000".U, // 0 + input.selectedQuotientOH(3) -> "b00001".U, // 1 + input.selectedQuotientOH(4) -> "b00010".U // 2 + ) + ) + Mux1H( + Seq( + input.selectedQuotientOH(5) -> "b11110".U, // -2 + input.selectedQuotientOH(6) -> "b00000".U, // 0 + input.selectedQuotientOH(7) -> "b00010".U // 2 + ) + ) + cShiftQ := input.selectedQuotientOH(7) || + (input.selectedQuotientOH(6) && input.selectedQuotientOH(3, 2).orR) + cShiftQM := input.selectedQuotientOH(5) || + (input.selectedQuotientOH(6) && input.selectedQuotientOH(2, 1).orR) + } val qIn: UInt = Mux(cShiftQ, qNext, radix.U + qNext)(radixLog2 - 1, 0) val qmIn: UInt = Mux(!cShiftQM, qNext - 1.U, (radix - 1).U + qNext)(radixLog2 - 1, 0) @@ -47,15 +111,16 @@ object OTF { def apply( radixLog2: Int, qWidth: Int, - ohWidth: Int + ohWidth: Int, + a: Int )(quotient: UInt, quotientMinusOne: UInt, selectedQuotientOH: UInt - ): Seq[UInt] = { - val m = Module(new OTF(radixLog2, qWidth, ohWidth)) + ): Vec[UInt] = { + val m = Module(new OTF(radixLog2, qWidth, ohWidth, a)) m.input.quotient := quotient m.input.quotientMinusOne := quotientMinusOne m.input.selectedQuotientOH := selectedQuotientOH - Seq(m.output.quotient, m.output.quotientMinusOne) + VecInit(m.output.quotient, m.output.quotientMinusOne) } } diff --git a/arithmetic/src/division/srt/srt8/QDS.scala b/arithmetic/src/division/srt/srt8/QDS.scala index c306db6..e9adc83 100644 --- a/arithmetic/src/division/srt/srt8/QDS.scala +++ b/arithmetic/src/division/srt/srt8/QDS.scala @@ -7,7 +7,7 @@ import chisel3.util.BitPat.bitPatToUInt import chisel3.util.experimental.decode.TruthTable import utils.{extend, sIntToBitPat} -class QDS(rWidth: Int, ohWidth: Int, partialDividerWidth: Int, tables: Seq[Seq[Int]]) extends Module { +class QDS(rWidth: Int, ohWidth: Int, partialDividerWidth: Int, tables: Seq[Seq[Int]], a: Int) extends Module { // IO val input = IO(Input(new QDSInput(rWidth, partialDividerWidth))) val output = IO(Output(new QDSOutput(ohWidth))) @@ -29,28 +29,91 @@ class QDS(rWidth: Int, ohWidth: Int, partialDividerWidth: Int, tables: Seq[Seq[I + extend(mk, adderWidth).asUInt).head(1) }).asUInt - // decoder or findFirstOne here, prefer decoder, the decoder only for srt8(a = 7) output.selectedQuotientOH := chisel3.util.experimental.decode.decoder( selectPoints, - TruthTable( - Seq( // 8 4 0 -4 -8__2 1 0 -1 -2 - BitPat("b??_????_????_???0") -> BitPat("b10000_00010"), // 7 = +8 + (-1) - BitPat("b??_????_????_??01") -> BitPat("b01000_10000"), // 6 = +4 + (+2) - BitPat("b??_????_????_?011") -> BitPat("b01000_01000"), // 5 = +4 + (+1) - BitPat("b??_????_????_0111") -> BitPat("b01000_00100"), // 4 = +4 + ( 0) - BitPat("b??_????_???0_1111") -> BitPat("b01000_00010"), // 3 = +4 + (-1) - BitPat("b??_????_??01_1111") -> BitPat("b00100_10000"), // 2 = 0 + (+2) - BitPat("b??_????_?011_1111") -> BitPat("b00100_01000"), // 1 = 0 + (+1) - BitPat("b??_????_0111_1111") -> BitPat("b00100_00100"), // 0 = 0 + ( 0) - BitPat("b??_???0_1111_1111") -> BitPat("b00100_00010"), //-1 = 0 + (-1) - BitPat("b??_??01_1111_1111") -> BitPat("b00100_00001"), //-2 = 0 + (-2) - BitPat("b??_?011_1111_1111") -> BitPat("b00010_01000"), //-3 = -4 + ( 1) - BitPat("b??_0111_1111_1111") -> BitPat("b00010_00100"), //-4 = -4 + ( 0) - BitPat("b?0_1111_1111_1111") -> BitPat("b00010_00010"), //-5 = -4 + (-1) - BitPat("b01_1111_1111_1111") -> BitPat("b00010_00001") //-6 = -4 + (-2) - ), - BitPat("b00001_01000") //-7 = -8 + (+1) - ) + a match { + case 7 => + TruthTable( + Seq( // 8 4 0 -4 -8__2 1 0 -1 -2 + BitPat("b??_????_????_???0") -> BitPat("b10000_00010"), // 7 = +8 + (-1) + BitPat("b??_????_????_??01") -> BitPat("b01000_10000"), // 6 = +4 + (+2) + BitPat("b??_????_????_?011") -> BitPat("b01000_01000"), // 5 = +4 + (+1) + BitPat("b??_????_????_0111") -> BitPat("b01000_00100"), // 4 = +4 + ( 0) + BitPat("b??_????_???0_1111") -> BitPat("b01000_00010"), // 3 = +4 + (-1) + BitPat("b??_????_??01_1111") -> BitPat("b00100_10000"), // 2 = 0 + (+2) + BitPat("b??_????_?011_1111") -> BitPat("b00100_01000"), // 1 = 0 + (+1) + BitPat("b??_????_0111_1111") -> BitPat("b00100_00100"), // 0 = 0 + ( 0) + BitPat("b??_???0_1111_1111") -> BitPat("b00100_00010"), //-1 = 0 + (-1) + BitPat("b??_??01_1111_1111") -> BitPat("b00100_00001"), //-2 = 0 + (-2) + BitPat("b??_?011_1111_1111") -> BitPat("b00010_01000"), //-3 = -4 + ( 1) + BitPat("b??_0111_1111_1111") -> BitPat("b00010_00100"), //-4 = -4 + ( 0) + BitPat("b?0_1111_1111_1111") -> BitPat("b00010_00010"), //-5 = -4 + (-1) + BitPat("b01_1111_1111_1111") -> BitPat("b00010_00001") // -6 = -4 + (-2) + ), + BitPat("b00001_01000") //-7 = -8 + (+1) + ) + case 6 => + TruthTable( + Seq( // 4 0 -4__2 1 0 -1 -2 + BitPat("b????_????_???0") -> BitPat("b100_10000"), // 6 = +4 + (+2) + BitPat("b????_????_??01") -> BitPat("b100_01000"), // 5 = +4 + (+1) + BitPat("b????_????_?011") -> BitPat("b100_00100"), // 4 = +4 + ( 0) + BitPat("b????_????_0111") -> BitPat("b100_00010"), // 3 = +4 + (-1) + BitPat("b????_???0_1111") -> BitPat("b010_10000"), // 2 = 0 + (+2) + BitPat("b????_??01_1111") -> BitPat("b010_01000"), // 1 = 0 + (+1) + BitPat("b????_?011_1111") -> BitPat("b010_00100"), // 0 = 0 + ( 0) + BitPat("b????_0111_1111") -> BitPat("b010_00010"), //-1 = 0 + (-1) + BitPat("b???0_1111_1111") -> BitPat("b010_00001"), //-2 = 0 + (-2) + BitPat("b??01_1111_1111") -> BitPat("b001_01000"), //-3 = -4 + ( 1) + BitPat("b?011_1111_1111") -> BitPat("b001_00100"), //-4 = -4 + ( 0) + BitPat("b0111_1111_1111") -> BitPat("b001_00010") // -5 = -4 + (-1) + ), + BitPat("b001_00001") //-6 = -4 + (-2) + ) + case 5 => + TruthTable( + Seq( // 4 0 -4__2 1 0 -1 -2 + BitPat("b??_????_???0") -> BitPat("b100_01000"), // 5 = +4 + (+1) + BitPat("b??_????_??01") -> BitPat("b100_00100"), // 4 = +4 + ( 0) + BitPat("b??_????_?011") -> BitPat("b100_00010"), // 3 = +4 + (-1) + BitPat("b??_????_0111") -> BitPat("b010_10000"), // 2 = 0 + (+2) + BitPat("b??_???0_1111") -> BitPat("b010_01000"), // 1 = 0 + (+1) + BitPat("b??_??01_1111") -> BitPat("b010_00100"), // 0 = 0 + ( 0) + BitPat("b??_?011_1111") -> BitPat("b010_00010"), //-1 = 0 + (-1) + BitPat("b??_0111_1111") -> BitPat("b010_00001"), //-2 = 0 + (-2) + BitPat("b?0_1111_1111") -> BitPat("b001_01000"), //-3 = -4 + ( 1) + BitPat("b01_1111_1111") -> BitPat("b001_00100") // -4 = -4 + ( 0) + ), + BitPat("b001_00010") //-5 = -4 + (-1) + ) + case 4 => + TruthTable( + Seq( // 2 0 -2__2 1 0 -1 -2 + BitPat("b????_???0") -> BitPat("b100_10000"), // 4 = +2 + ( 2) + BitPat("b????_??01") -> BitPat("b100_01000"), // 3 = +2 + ( 1) + BitPat("b????_?011") -> BitPat("b100_00100"), // 2 = 2 + ( 0) + BitPat("b????_0111") -> BitPat("b010_01000"), // 1 = 0 + (+1) + BitPat("b???0_1111") -> BitPat("b010_00100"), // 0 = 0 + ( 0) + BitPat("b??01_1111") -> BitPat("b010_00010"), //-1 = 0 + (-1) + BitPat("b?011_1111") -> BitPat("b001_00100"), //-2 = -2 + ( 0) + BitPat("b0111_1111") -> BitPat("b001_00010") // -3 = -2 + (-1) + ), + BitPat("b001_00001") //-4 = -2 + (-2) + ) + // TruthTable( + // Seq( // 4 0 -4__2 1 0 -1 -2 + // BitPat("b????_???0") -> BitPat("b100_00100"), // 4 = +4 + ( 0) + // BitPat("b????_??01") -> BitPat("b100_00010"), // 3 = +4 + (-1) + // BitPat("b????_?011") -> BitPat("b010_10000"), // 2 = 0 + (+2) + // BitPat("b????_0111") -> BitPat("b010_01000"), // 1 = 0 + (+1) + // BitPat("b???0_1111") -> BitPat("b010_00100"), // 0 = 0 + ( 0) + // BitPat("b??01_1111") -> BitPat("b010_00010"), //-1 = 0 + (-1) + // BitPat("b?011_1111") -> BitPat("b010_00001"), //-2 = 0 + (-2) + // BitPat("b0111_1111") -> BitPat("b001_01000") //-3 = -4 + ( 1) + // ), + // BitPat("b001_00100") //-4 = -4 + ( 0) + // ) + } ) } @@ -59,12 +122,13 @@ object QDS { rWidth: Int, ohWidth: Int, partialDividerWidth: Int, - tables: Seq[Seq[Int]] + tables: Seq[Seq[Int]], + a: Int )(partialReminderSum: UInt, partialReminderCarry: UInt, partialDivider: UInt ): UInt = { - val m = Module(new QDS(rWidth, ohWidth, partialDividerWidth, tables)) + val m = Module(new QDS(rWidth, ohWidth, partialDividerWidth, tables, a)) m.input.partialReminderSum := partialReminderSum m.input.partialReminderCarry := partialReminderCarry m.input.partialDivider := partialDivider diff --git a/arithmetic/src/division/srt/srt8/SRT8.scala b/arithmetic/src/division/srt/srt8/SRT8.scala index a120a9b..f45196d 100644 --- a/arithmetic/src/division/srt/srt8/SRT8.scala +++ b/arithmetic/src/division/srt/srt8/SRT8.scala @@ -27,9 +27,8 @@ class SRT8( rTruncateWidth: Int = 4) extends Module { - val xLen: Int = dividendWidth + radixLog2 + 1 - val wLen: Int = xLen + radixLog2 - val ohWidth: Int = 10 + val xLen: Int = dividendWidth + radixLog2 + 1 + val wLen: Int = xLen + radixLog2 // IO val input = IO(Flipped(DecoupledIO(new SRTInput(dividendWidth, dividerWidth, n)))) @@ -43,7 +42,7 @@ class SRT8( // Control // sign of select quotient, true -> negative, false -> positive // sign of Cycle, true -> (counter === 0.U) - val qdsSign0, qdsSign1, isLastCycle, enable: Bool = Wire(Bool()) + val isLastCycle, enable: Bool = Wire(Bool()) // State // because we need a CSA to minimize the critical path @@ -68,58 +67,150 @@ class SRT8( output.bits.reminder := Mux(needCorrect, remainderCorrect, remainderNoCorrect)(wLen - 5, radixLog2) output.bits.quotient := Mux(needCorrect, quotientMinusOne, quotient) - // qds val rWidth: Int = 1 + radixLog2 + rTruncateWidth val tables: Seq[Seq[Int]] = SRTTable(1 << radixLog2, a, dTruncateWidth, rTruncateWidth).tablesToQDS + + val ohWidth: Int = a match { + case 7 => 10 + case 6 => 8 + case 5 => 8 + case 4 => 8 + } + // qds val selectedQuotientOH: UInt = - QDS(rWidth, ohWidth, dTruncateWidth - 1, tables)( + QDS(rWidth, ohWidth, dTruncateWidth - 1, tables, a)( leftShift(partialReminderSum, radixLog2).head(rWidth), leftShift(partialReminderCarry, radixLog2).head(rWidth), dividerNext.head(dTruncateWidth)(dTruncateWidth - 2, 0) //.1********* -> 1*** -> *** ) + // On-The-Fly conversion + val otf = OTF(radixLog2, n, ohWidth, a)(quotient, quotientMinusOne, selectedQuotientOH) - qdsSign0 := selectedQuotientOH(9, 8).orR - qdsSign1 := selectedQuotientOH(4, 3).orR - - val qHigh: UInt = selectedQuotientOH(9, 5) - val qLow: UInt = selectedQuotientOH(4, 0) - // csa for SRT8 -> CSA32+CSA32 - val dividerMap0 = VecInit((-2 to 2).map { - case -2 => divider << 3 // -8 - case -1 => divider << 2 // -4 - case 0 => 0.U // 0 - case 1 => Fill(2, 1.U(1.W)) ## ~(divider << 2) // 4 - case 2 => Fill(1, 1.U(1.W)) ## ~(divider << 3) // 8 - }) - val dividerMap1 = VecInit((-2 to 2).map { + val dividerLMap = VecInit((-2 to 2).map { case -2 => divider << 1 // -2 case -1 => divider // -1 case 0 => 0.U // 0 case 1 => Fill(1 + radixLog2, 1.U(1.W)) ## ~divider // 1 case 2 => Fill(radixLog2, 1.U(1.W)) ## ~(divider << 1) // 2 }) - val csa0 = addition.csa.c32( - VecInit( - leftShift(partialReminderSum, radixLog2).head(wLen - radixLog2), - leftShift(partialReminderCarry, radixLog2).head(wLen - radixLog2 - 1) ## qdsSign0, - Mux1H(qHigh, dividerMap0) + + if (a == 7) { + val qHigh: UInt = selectedQuotientOH(9, 5) + val qLow: UInt = selectedQuotientOH(4, 0) + val qdsSign0: Bool = qHigh.head(2).orR + val qdsSign1: Bool = qLow.head(2).orR + // csa for SRT8 -> CSA32+CSA32 + val dividerHMap = VecInit((-2 to 2).map { + case -2 => divider << 3 // -8 + case -1 => divider << 2 // -4 + case 0 => 0.U // 0 + case 1 => Fill(2, 1.U(1.W)) ## ~(divider << 2) // 4 + case 2 => Fill(1, 1.U(1.W)) ## ~(divider << 3) // 8 + }) + val csa0 = addition.csa.c32( + VecInit( + leftShift(partialReminderSum, radixLog2).head(wLen - radixLog2), + leftShift(partialReminderCarry, radixLog2).head(wLen - radixLog2 - 1) ## qdsSign0, + Mux1H(qHigh, dividerHMap) + ) ) - ) - val csa1 = addition.csa.c32( - VecInit( - csa0(1).head(wLen - radixLog2), - leftShift(csa0(0), 1).head(wLen - radixLog2 - 1) ## qdsSign1, - Mux1H(qLow, dividerMap1) + val csa1 = addition.csa.c32( + VecInit( + csa0(1).head(wLen - radixLog2), + leftShift(csa0(0), 1).head(wLen - radixLog2 - 1) ## qdsSign1, + Mux1H(qLow, dividerLMap) + ) ) - ) + partialReminderSumNext := Mux(input.fire, input.bits.dividend, csa1(1) << radixLog2) + partialReminderCarryNext := Mux(input.fire, 0.U, csa1(0) << 1 + radixLog2) + } else if (a == 6) { + val qHigh: UInt = selectedQuotientOH(7, 5) + val qLow: UInt = selectedQuotientOH(4, 0) + val qdsSign0: Bool = qHigh.head(1).asBool + val qdsSign1: Bool = qLow.head(2).orR - // On-The-Fly conversion - val otf = OTF(radixLog2, n, ohWidth)(quotient, quotientMinusOne, selectedQuotientOH) + // csa for SRT8 -> CSA32+CSA32 + val dividerHMap = VecInit((-1 to 1).map { + case -1 => divider << 2 // -4 + case 0 => 0.U // 0 + case 1 => Fill(2, 1.U(1.W)) ## ~(divider << 2) // 4 + }) + val csa0 = addition.csa.c32( + VecInit( + leftShift(partialReminderSum, radixLog2).head(wLen - radixLog2), + leftShift(partialReminderCarry, radixLog2).head(wLen - radixLog2 - 1) ## qdsSign0, + Mux1H(qHigh, dividerHMap) + ) + ) + val csa1 = addition.csa.c32( + VecInit( + csa0(1).head(wLen - radixLog2), + leftShift(csa0(0), 1).head(wLen - radixLog2 - 1) ## qdsSign1, + Mux1H(qLow, dividerLMap) + ) + ) + partialReminderSumNext := Mux(input.fire, input.bits.dividend, csa1(1) << radixLog2) + partialReminderCarryNext := Mux(input.fire, 0.U, csa1(0) << 1 + radixLog2) + } else if (a == 5) { + val qHigh: UInt = selectedQuotientOH(7, 5) + val qLow: UInt = selectedQuotientOH(4, 0) + val qdsSign0: Bool = qHigh.head(1).asBool + val qdsSign1: Bool = qLow.head(2).orR + + // csa for SRT8 -> CSA32+CSA32 + val dividerHMap = VecInit((-1 to 1).map { + case -1 => divider << 2 // -4 + case 0 => 0.U // 0 + case 1 => Fill(2, 1.U(1.W)) ## ~(divider << 2) // 4 + }) + val csa0 = addition.csa.c32( + VecInit( + leftShift(partialReminderSum, radixLog2).head(wLen - radixLog2), + leftShift(partialReminderCarry, radixLog2).head(wLen - radixLog2 - 1) ## qdsSign0, + Mux1H(qHigh, dividerHMap) + ) + ) + val csa1 = addition.csa.c32( + VecInit( + csa0(1).head(wLen - radixLog2), + leftShift(csa0(0), 1).head(wLen - radixLog2 - 1) ## qdsSign1, + Mux1H(qLow, dividerLMap) + ) + ) + partialReminderSumNext := Mux(input.fire, input.bits.dividend, csa1(1) << radixLog2) + partialReminderCarryNext := Mux(input.fire, 0.U, csa1(0) << 1 + radixLog2) + } else if (a == 4) { + val qHigh: UInt = selectedQuotientOH(7, 5) + val qLow: UInt = selectedQuotientOH(4, 0) + val qdsSign0: Bool = qHigh.head(1).asBool + val qdsSign1: Bool = qLow.head(2).orR + + // csa for SRT8 -> CSA32+CSA32 + val dividerHMap = VecInit((-1 to 1).map { + case -1 => divider << 1 // -2 + case 0 => 0.U // 0 + case 1 => Fill(radixLog2, 1.U(1.W)) ## ~(divider << 1) // 2 + }) + val csa0 = addition.csa.c32( + VecInit( + leftShift(partialReminderSum, radixLog2).head(wLen - radixLog2), + leftShift(partialReminderCarry, radixLog2).head(wLen - radixLog2 - 1) ## qdsSign0, + Mux1H(qHigh, dividerHMap) + ) + ) + val csa1 = addition.csa.c32( + VecInit( + csa0(1).head(wLen - radixLog2), + leftShift(csa0(0), 1).head(wLen - radixLog2 - 1) ## qdsSign1, + Mux1H(qLow, dividerLMap) + ) + ) + partialReminderSumNext := Mux(input.fire, input.bits.dividend, csa1(1) << radixLog2) + partialReminderCarryNext := Mux(input.fire, 0.U, csa1(0) << 1 + radixLog2) + } dividerNext := Mux(input.fire, input.bits.divider, divider) counterNext := Mux(input.fire, input.bits.counter, counter - 1.U) quotientNext := Mux(input.fire, 0.U, otf(0)) quotientMinusOneNext := Mux(input.fire, 0.U, otf(1)) - partialReminderSumNext := Mux(input.fire, input.bits.dividend, csa1(1) << radixLog2) - partialReminderCarryNext := Mux(input.fire, 0.U, csa1(0) << 1 + radixLog2) } diff --git a/arithmetic/src/utils/package.scala b/arithmetic/src/utils/package.scala index b3e3d73..2edf1ab 100644 --- a/arithmetic/src/utils/package.scala +++ b/arithmetic/src/utils/package.scala @@ -55,7 +55,7 @@ package object utils { else BitPat((x + (1 << w)).U(w.W)) } - + // left shift and keep the width of Bits def leftShift(x: Bits, n: Int): UInt = { val length: Int = x.getWidth diff --git a/arithmetic/tests/src/division/srt/SRTSpec.scala b/arithmetic/tests/src/division/srt/SRTSpec.scala index 4309e09..2d9c960 100644 --- a/arithmetic/tests/src/division/srt/SRTSpec.scala +++ b/arithmetic/tests/src/division/srt/SRTSpec.scala @@ -9,10 +9,10 @@ import utils.extend object SRTSpec extends TestSuite{ override def tests: Tests = Tests { test("SRT should draw PD") { - val srt = SRTTable(4,2,4,4) + val srt = SRTTable(8,5,5,5) // println(srt.tables) // println(srt.tablesToQDS) - srt.dumpGraph(srt.pd, os.root / "tmp" / "srt4-2-4-4.png") + srt.dumpGraph(srt.pd, os.root / "tmp" / "srt8-5-5-5.png") } } } diff --git a/arithmetic/tests/src/division/srt/SRTTest.scala b/arithmetic/tests/src/division/srt/SRTTest.scala index 588f44e..5c73846 100644 --- a/arithmetic/tests/src/division/srt/SRTTest.scala +++ b/arithmetic/tests/src/division/srt/SRTTest.scala @@ -46,12 +46,12 @@ object SRTTest extends TestSuite with ChiselUtestTester { val remainder: BigInt = dividend % divider val leftShiftWidthDividend: Int = zeroHeadDividend - guardWidth val leftShiftWidthDivider: Int = zeroHeadDivider - // println("dividend = %8x, dividend = %d ".format(dividend, dividend)) - // println("divider = %8x, divider = %d".format(divider, divider)) - // println("zeroHeadDividend = %d, dividend << zeroHeadDividend = %d".format(zeroHeadDividend, dividend << leftShiftWidthDividend)) - // println("zeroHeadDivider = %d, divider << zeroHeadDivider = %d".format(zeroHeadDivider, divider << leftShiftWidthDivider)) - // println("quotient = %d, remainder = %d".format(quotient, remainder)) - // println("counter = %d, needComputerWidth = %d".format(counter, needComputerWidth)) +// println("dividend = %8x, dividend = %d ".format(dividend, dividend)) +// println("divider = %8x, divider = %d".format(divider, divider)) +// println("zeroHeadDividend = %d, dividend << zeroHeadDividend = %d".format(zeroHeadDividend, dividend << leftShiftWidthDividend)) +// println("zeroHeadDivider = %d, divider << zeroHeadDivider = %d".format(zeroHeadDivider, divider << leftShiftWidthDivider)) +// println("quotient = %d, remainder = %d".format(quotient, remainder)) +// println("counter = %d, needComputerWidth = %d".format(counter, needComputerWidth)) // test testCircuit(new SRT(n, n, n, radixLog2, a, dTruncateWidth, rTruncateWidth), Seq(chiseltest.internal.NoThreadingAnnotation, @@ -69,7 +69,7 @@ object SRTTest extends TestSuite with ChiselUtestTester { if (dut.output.valid.peek().litValue == 1) { flag = true println(dut.output.bits.quotient.peek().litValue) - println(dut.output.bits.reminder.peek().litValue) + println(dut.output.bits.reminder.peek().litValue >> zeroHeadDivider) utest.assert(dut.output.bits.quotient.peek().litValue == quotient) utest.assert(dut.output.bits.reminder.peek().litValue >> zeroHeadDivider == remainder) } @@ -79,9 +79,9 @@ object SRTTest extends TestSuite with ChiselUtestTester { dut.clock.step(scala.util.Random.nextInt(5)) } } - testcase(64) +// testcase(64) for( i <- 1 to 50){ - testcase(64,3,7,4) + testcase(n = 64, radixLog2 = 3, a = 7, dTruncateWidth = 4, rTruncateWidth = 4) } } }