From 2fcb7247f5ef874b7fdbcddf09d756816c872671 Mon Sep 17 00:00:00 2001 From: Liang Zhong Date: Tue, 17 Dec 2024 14:38:09 +0800 Subject: [PATCH 1/2] tl321x_retention: add config for packet buffer optimization optimize the packet buffer to save iram space Signed-off-by: Liang Zhong --- config/telink/chip-module/Kconfig.defaults | 12 ++++- ...nericThreadStackManagerImpl_OpenThread.hpp | 12 +++++ src/platform/telink/BLEManagerImpl.cpp | 7 ++- src/platform/telink/SystemPlatformConfig.h | 9 ++++ src/system/SystemPacketBuffer.cpp | 52 +++++++++++++++++++ src/system/SystemPacketBuffer.h | 4 ++ 6 files changed, 94 insertions(+), 2 deletions(-) diff --git a/config/telink/chip-module/Kconfig.defaults b/config/telink/chip-module/Kconfig.defaults index b094f5752d725b..fc8355d902dce1 100644 --- a/config/telink/chip-module/Kconfig.defaults +++ b/config/telink/chip-module/Kconfig.defaults @@ -84,7 +84,7 @@ config HEAP_MEM_POOL_SIZE # need to enlarge to 21000 , to pass TC_RR_1.1 config COMMON_LIBC_MALLOC_ARENA_SIZE - default 21000 if SOC_RISCV_TELINK_TL321X || SOC_SERIES_RISCV_TELINK_B9X_RETENTION + default 12288 if SOC_RISCV_TELINK_TL321X || SOC_SERIES_RISCV_TELINK_B9X_RETENTION default 12288 config NET_IPV6_MLD @@ -329,6 +329,16 @@ config OPENTHREAD_CSMABACKOFF_OPTIMIZATION default n if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION default n +config ZEPHYR_NETBUFFER_OPTIMIZATION + bool "move the net buffer from iram to dram" + default y if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION + default n + +config CHIP_PACKETBUFFER_OPTIMIZATION + bool "move the packet buffer from iram to dram" + default y if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION + default n + config OPENTHREAD_THREAD_STACK_SIZE default 2400 if PM || SOC_RISCV_TELINK_TL321X diff --git a/src/platform/OpenThread/GenericThreadStackManagerImpl_OpenThread.hpp b/src/platform/OpenThread/GenericThreadStackManagerImpl_OpenThread.hpp index f15e22252d6ab9..26898ae1a4d1a9 100644 --- a/src/platform/OpenThread/GenericThreadStackManagerImpl_OpenThread.hpp +++ b/src/platform/OpenThread/GenericThreadStackManagerImpl_OpenThread.hpp @@ -65,6 +65,11 @@ extern "C" void otSysProcessDrivers(otInstance * aInstance); #if CHIP_DEVICE_CONFIG_THREAD_ENABLE_CLI extern "C" void otAppCliInit(otInstance * aInstance); #endif +#if defined(CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION) && CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION +extern "C" { +extern char packetBufferThreadFlag; +} +#endif /* CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ namespace chip { namespace DeviceLayer { @@ -371,6 +376,13 @@ bool GenericThreadStackManagerImpl_OpenThread::_IsThreadAttached() Impl()->LockThreadStack(); curRole = otThreadGetDeviceRole(mOTInst); Impl()->UnlockThreadStack(); +#if defined(CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION) && CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION + if((curRole != OT_DEVICE_ROLE_DISABLED && curRole != OT_DEVICE_ROLE_DETACHED)) + { + if(packetBufferThreadFlag==0) + packetBufferThreadFlag = 1; + } +#endif /* CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ return (curRole != OT_DEVICE_ROLE_DISABLED && curRole != OT_DEVICE_ROLE_DETACHED); } diff --git a/src/platform/telink/BLEManagerImpl.cpp b/src/platform/telink/BLEManagerImpl.cpp index 819d2614ce349d..24fdbc5088d6cf 100644 --- a/src/platform/telink/BLEManagerImpl.cpp +++ b/src/platform/telink/BLEManagerImpl.cpp @@ -47,6 +47,9 @@ extern "C" { extern __attribute__((noinline)) void telink_bt_blc_mac_init(uint8_t * bt_mac); +#if defined(CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION) && CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION +extern char packetBufferBLEFlag; +#endif /* CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ } #if defined(CONFIG_PM) && !defined(CONFIG_CHIP_ENABLE_PM_DURING_BLE) @@ -951,7 +954,9 @@ void BLEManagerImpl::SwitchToIeee802154(void) // Deinit BLE bt_disable(); mBLERadioInitialized = false; - +#if defined(CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION) && CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION + packetBufferBLEFlag = 1; +#endif /* CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ #if defined(CONFIG_PM) && !defined(CONFIG_CHIP_ENABLE_PM_DURING_BLE) pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES); #endif diff --git a/src/platform/telink/SystemPlatformConfig.h b/src/platform/telink/SystemPlatformConfig.h index 9f77a54b223169..dfc560911d8cc6 100644 --- a/src/platform/telink/SystemPlatformConfig.h +++ b/src/platform/telink/SystemPlatformConfig.h @@ -45,8 +45,13 @@ struct ChipDeviceEvent; #endif // CHIP_SYSTEM_CONFIG_USE_POSIX_TIME_FUNCTS #if defined(CONFIG_SOC_RISCV_TELINK_TL321X) || defined(CONFIG_SOC_SERIES_RISCV_TELINK_B9X_RETENTION) +#if defined(CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION) && CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION +#define CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_HEAP 0 +#define CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_POOL 1 +#else /* !CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ #define CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_HEAP 1 #define CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_POOL 0 +#endif /* CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ #define CHIP_SYSTEM_CONFIG_POOL_USE_HEAP 1 #define CHIP_SYSTEM_CONFIG_PACKETBUFFER_CAPACITY_MAX 1280 #endif @@ -56,7 +61,11 @@ struct ChipDeviceEvent; // Reduce packet buffer pool size (default 15) to reduce ram consumption #if defined CONFIG_PM || defined CONFIG_SOC_RISCV_TELINK_TL321X +#if defined(CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION) && CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION +#define CHIP_SYSTEM_CONFIG_PACKETBUFFER_POOL_SIZE 6 +#else /* !CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ #define CHIP_SYSTEM_CONFIG_PACKETBUFFER_POOL_SIZE 0 +#endif /* CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ #else #define CHIP_SYSTEM_CONFIG_PACKETBUFFER_POOL_SIZE 8 #endif diff --git a/src/system/SystemPacketBuffer.cpp b/src/system/SystemPacketBuffer.cpp index f644d1a23eb323..4416eeb46896f0 100644 --- a/src/system/SystemPacketBuffer.cpp +++ b/src/system/SystemPacketBuffer.cpp @@ -43,6 +43,17 @@ #include #include #include +#if defined(CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION) && CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION +extern "C" +{ + char packetBufferBLEFlag=0; + char packetBufferThreadFlag=0; + extern unsigned int _RAMCODE_BLE_VMA_START; + extern unsigned int _RAMCODE_BLE_LMA_START; + +} +#endif /* CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ + #if CHIP_SYSTEM_CONFIG_USE_LWIP #include @@ -66,7 +77,12 @@ namespace System { // Pool allocation for PacketBuffer objects. // +#if defined(CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION) && CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION +PacketBuffer::BufferPoolElement * PacketBuffer::sFreeRetentionList; +__attribute__((section(".bss"))) PacketBuffer::BufferPoolElement PacketBuffer::sBufferPool[CHIP_SYSTEM_CONFIG_PACKETBUFFER_POOL_SIZE]; +#else /* !CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ PacketBuffer::BufferPoolElement PacketBuffer::sBufferPool[CHIP_SYSTEM_CONFIG_PACKETBUFFER_POOL_SIZE]; +#endif /* CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ PacketBuffer * PacketBuffer::sFreeList = PacketBuffer::BuildFreeList(); @@ -104,6 +120,27 @@ PacketBuffer * PacketBuffer::BuildFreeList() return static_cast(lHead); } +#if defined(CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION) && CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION +PacketBuffer * PacketBuffer::BuildRetentionFreeList() +{ + pbuf * lHead = nullptr; + + for (int i = 0; i < CHIP_SYSTEM_CONFIG_PACKETBUFFER_POOL_SIZE; i++) + { + pbuf * lCursor = &sFreeRetentionList[i].Header; + lCursor->next = lHead; + lCursor->ref = 0; + lHead = lCursor; + } + +#if !CHIP_SYSTEM_CONFIG_NO_LOCKING + Mutex::Init(sBufferPoolMutex); +#endif // !CHIP_SYSTEM_CONFIG_NO_LOCKING + + return static_cast(lHead); +} +#endif /* CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ + #elif CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_HEAP // // Heap allocation for PacketBuffer objects. @@ -510,6 +547,21 @@ void PacketBuffer::AddRef() PacketBufferHandle PacketBufferHandle::New(size_t aAvailableSize, uint16_t aReservedSize) { +#if defined(CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION) && CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION + if(packetBufferBLEFlag==1) + { + packetBufferBLEFlag = 0; + packetBufferThreadFlag = 2; + PacketBuffer::sFreeRetentionList = (PacketBuffer::BufferPoolElement *)&_RAMCODE_BLE_VMA_START; + PacketBuffer::sFreeList = PacketBuffer::BuildRetentionFreeList(); + } + else if(packetBufferThreadFlag==1) + { + packetBufferThreadFlag = 2; + PacketBuffer::sFreeRetentionList = (PacketBuffer::BufferPoolElement *)&_RAMCODE_BLE_VMA_START; + PacketBuffer::sFreeList = PacketBuffer::BuildRetentionFreeList(); + } +#endif /* CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ // Sanity check for kStructureSize to ensure that it matches the PacketBuffer size. static_assert(PacketBuffer::kStructureSize == sizeof(PacketBuffer), "PacketBuffer size mismatch"); // Setting a static upper bound on kStructureSize to ensure the summation of all the sizes does not overflow. diff --git a/src/system/SystemPacketBuffer.h b/src/system/SystemPacketBuffer.h index 8fd73b9c352754..979fe1a9b7565c 100644 --- a/src/system/SystemPacketBuffer.h +++ b/src/system/SystemPacketBuffer.h @@ -385,6 +385,10 @@ class DLL_EXPORT PacketBuffer : private pbuf static BufferPoolElement sBufferPool[CHIP_SYSTEM_CONFIG_PACKETBUFFER_POOL_SIZE]; static PacketBuffer * sFreeList; static PacketBuffer * BuildFreeList(); +#if defined(CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION) && CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION + static BufferPoolElement * sFreeRetentionList; + static PacketBuffer * BuildRetentionFreeList(); +#endif /* CONFIG_CHIP_PACKETBUFFER_OPTIMIZATION */ #endif // CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_POOL || defined(DOXYGEN) #if CHIP_SYSTEM_PACKETBUFFER_HAS_CHECK From 9e19a5e34c1d6a32f18f11561220a35bdcd79681 Mon Sep 17 00:00:00 2001 From: Liang Zhong Date: Thu, 26 Dec 2024 19:24:43 +0800 Subject: [PATCH 2/2] tlx3218x: add some config about pm add tlx 802154 and backoff config Signed-off-by: Liang Zhong --- config/telink/chip-module/Kconfig.defaults | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/config/telink/chip-module/Kconfig.defaults b/config/telink/chip-module/Kconfig.defaults index fc8355d902dce1..006c700e351057 100644 --- a/config/telink/chip-module/Kconfig.defaults +++ b/config/telink/chip-module/Kconfig.defaults @@ -84,7 +84,7 @@ config HEAP_MEM_POOL_SIZE # need to enlarge to 21000 , to pass TC_RR_1.1 config COMMON_LIBC_MALLOC_ARENA_SIZE - default 12288 if SOC_RISCV_TELINK_TL321X || SOC_SERIES_RISCV_TELINK_B9X_RETENTION + default 14288 if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION default 12288 config NET_IPV6_MLD @@ -326,7 +326,7 @@ config CHIP_ENABLE_ICD_SUPPORT config OPENTHREAD_CSMABACKOFF_OPTIMIZATION bool "Skip the first backoff during sending data request" depends on CHIP_ENABLE_ICD_SUPPORT - default n if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION + default y if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION default n config ZEPHYR_NETBUFFER_OPTIMIZATION @@ -339,6 +339,14 @@ config CHIP_PACKETBUFFER_OPTIMIZATION default y if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION default n +config IEEE802154_TLX_OPTIMIZATION + bool "optimize the rf performance for tlx" + default y if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION + default n + help + optimize the rf performance for tlx. + + config OPENTHREAD_THREAD_STACK_SIZE default 2400 if PM || SOC_RISCV_TELINK_TL321X