diff --git a/.github/workflows/chef.yaml b/.github/workflows/chef.yaml
index c6fd67c62dcfb4..a84444113d349d 100644
--- a/.github/workflows/chef.yaml
+++ b/.github/workflows/chef.yaml
@@ -111,7 +111,7 @@ jobs:
                 platform: telink
             - name: Update Zephyr to specific revision (for developers purpose)
               shell: bash
-              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py origin/develop_tlx802154_optimization"
+              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py origin/develop_customer"
             - name: CI Examples Telink
               shell: bash
               run: |
diff --git a/.github/workflows/examples-telink.yaml b/.github/workflows/examples-telink.yaml
index bc3934455bece4..19447d7dca5e3c 100644
--- a/.github/workflows/examples-telink.yaml
+++ b/.github/workflows/examples-telink.yaml
@@ -58,7 +58,7 @@ jobs:
                 gh-context: ${{ toJson(github) }}
 
             - name: Update Zephyr to specific revision (for developers purpose)
-              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py origin/develop_tlx802154_optimization"
+              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py origin/develop_customer"
 
             - name: Build example Telink (B92 retention) Air Quality Sensor App
               # Run test for master and s07641069 PRs
diff --git a/config/telink/chip-module/Kconfig.defaults b/config/telink/chip-module/Kconfig.defaults
index eb154c40bf0c8d..207a39793f521d 100644
--- a/config/telink/chip-module/Kconfig.defaults
+++ b/config/telink/chip-module/Kconfig.defaults
@@ -84,7 +84,8 @@ config HEAP_MEM_POOL_SIZE
 
 # need to enlarge to 21000 , to pass TC_RR_1.1
 config COMMON_LIBC_MALLOC_ARENA_SIZE
-    default 14336 if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION
+    default 14336 if SOC_SERIES_RISCV_TELINK_B9X_RETENTION
+    default 13824 if SOC_RISCV_TELINK_TL321X && SOC_SERIES_RISCV_TELINK_TLX_RETENTION
     default 12288
 
 config NET_IPV6_MLD
@@ -330,11 +331,11 @@ config OPENTHREAD_CSMABACKOFF_OPTIMIZATION
 	default n
 
 config ZEPHYR_NETBUFFER_OPTIMIZATION
-	bool "Move the net buffer from iram to dram"
+	bool "Place net buffer in DLM instead of ILM"
 	default y if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION
 	default n
 	help
-	  This option enables the net buffer from iram to dram.
+	  This option enables storing the net buffer in DLM rather than ILM.
 
 config IEEE802154_TLX_OPTIMIZATION
 	bool "optimize the rf performance for tlx"
diff --git a/src/platform/telink/SystemPlatformConfig.h b/src/platform/telink/SystemPlatformConfig.h
index 5d50e2d4fa30c5..156f7c148464a8 100644
--- a/src/platform/telink/SystemPlatformConfig.h
+++ b/src/platform/telink/SystemPlatformConfig.h
@@ -56,7 +56,7 @@ struct ChipDeviceEvent;
 #endif
 
 #if defined CONFIG_SOC_RISCV_TELINK_TL321X
-#define CHIP_SYSTEM_CONFIG_PACKETBUFFER_CAPACITY_MAX 1100
+#define CHIP_SYSTEM_CONFIG_PACKETBUFFER_CAPACITY_MAX 1024
 #elif defined CONFIG_SOC_SERIES_RISCV_TELINK_B9X_RETENTION
 #define CHIP_SYSTEM_CONFIG_PACKETBUFFER_CAPACITY_MAX 1280
 #endif