diff --git a/.github/workflows/chef.yaml b/.github/workflows/chef.yaml
index a673479c22e195..c6fd67c62dcfb4 100644
--- a/.github/workflows/chef.yaml
+++ b/.github/workflows/chef.yaml
@@ -111,7 +111,7 @@ jobs:
                 platform: telink
             - name: Update Zephyr to specific revision (for developers purpose)
               shell: bash
-              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py 3108dced67ee46d7b00a0abb3d7155e32c2b7c6f"
+              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py origin/develop_tlx802154_optimization"
             - name: CI Examples Telink
               shell: bash
               run: |
diff --git a/.github/workflows/examples-telink.yaml b/.github/workflows/examples-telink.yaml
index 1a778dcc2f7d02..bc3934455bece4 100644
--- a/.github/workflows/examples-telink.yaml
+++ b/.github/workflows/examples-telink.yaml
@@ -58,7 +58,7 @@ jobs:
                 gh-context: ${{ toJson(github) }}
 
             - name: Update Zephyr to specific revision (for developers purpose)
-              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py 3108dced67ee46d7b00a0abb3d7155e32c2b7c6f"
+              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py origin/develop_tlx802154_optimization"
 
             - name: Build example Telink (B92 retention) Air Quality Sensor App
               # Run test for master and s07641069 PRs
diff --git a/config/telink/chip-module/Kconfig.defaults b/config/telink/chip-module/Kconfig.defaults
index b094f5752d725b..eb154c40bf0c8d 100644
--- a/config/telink/chip-module/Kconfig.defaults
+++ b/config/telink/chip-module/Kconfig.defaults
@@ -84,7 +84,7 @@ config HEAP_MEM_POOL_SIZE
 
 # need to enlarge to 21000 , to pass TC_RR_1.1
 config COMMON_LIBC_MALLOC_ARENA_SIZE
-    default 21000 if SOC_RISCV_TELINK_TL321X || SOC_SERIES_RISCV_TELINK_B9X_RETENTION
+    default 14336 if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION
     default 12288
 
 config NET_IPV6_MLD
@@ -324,10 +324,24 @@ config CHIP_ENABLE_ICD_SUPPORT
 
 
 config OPENTHREAD_CSMABACKOFF_OPTIMIZATION
-    bool "Skip the first backoff during sending data request"
-    depends on CHIP_ENABLE_ICD_SUPPORT
-    default n if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION
-    default n
+	bool "Skip the first backoff during sending data request"
+	depends on CHIP_ENABLE_ICD_SUPPORT
+	default y if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION
+	default n
+
+config ZEPHYR_NETBUFFER_OPTIMIZATION
+	bool "Move the net buffer from iram to dram"
+	default y if SOC_SERIES_RISCV_TELINK_TLX_RETENTION || SOC_SERIES_RISCV_TELINK_B9X_RETENTION
+	default n
+	help
+	  This option enables the net buffer from iram to dram.
+
+config IEEE802154_TLX_OPTIMIZATION
+	bool "optimize the rf performance for tlx"
+	default y if SOC_SERIES_RISCV_TELINK_TLX_RETENTION
+	default n
+	help
+	  optimize the rf performance for tlx.
 
 config OPENTHREAD_THREAD_STACK_SIZE
     default 2400 if PM || SOC_RISCV_TELINK_TL321X
diff --git a/src/platform/OpenThread/GenericThreadStackManagerImpl_OpenThread.hpp b/src/platform/OpenThread/GenericThreadStackManagerImpl_OpenThread.hpp
index f15e22252d6ab9..dc3b0ed908c248 100644
--- a/src/platform/OpenThread/GenericThreadStackManagerImpl_OpenThread.hpp
+++ b/src/platform/OpenThread/GenericThreadStackManagerImpl_OpenThread.hpp
@@ -66,6 +66,10 @@ extern "C" void otSysProcessDrivers(otInstance * aInstance);
 extern "C" void otAppCliInit(otInstance * aInstance);
 #endif
 
+#if defined CONFIG_IEEE802154_TLX_OPTIMIZATION && CONFIG_IEEE802154_TLX_OPTIMIZATION
+bool isThreadCommissioned = false;
+#endif /* CONFIG_IEEE802154_TLX_OPTIMIZATION */
+
 namespace chip {
 namespace DeviceLayer {
 namespace Internal {
@@ -372,6 +376,14 @@ bool GenericThreadStackManagerImpl_OpenThread<ImplClass>::_IsThreadAttached()
     curRole = otThreadGetDeviceRole(mOTInst);
     Impl()->UnlockThreadStack();
 
+#if defined CONFIG_IEEE802154_TLX_OPTIMIZATION && CONFIG_IEEE802154_TLX_OPTIMIZATION
+    if ((curRole != OT_DEVICE_ROLE_DISABLED && curRole != OT_DEVICE_ROLE_DETACHED))
+    {
+        if (isThreadCommissioned == false)
+            isThreadCommissioned = true;
+    }
+#endif /* CONFIG_IEEE802154_TLX_OPTIMIZATION */
+
     return (curRole != OT_DEVICE_ROLE_DISABLED && curRole != OT_DEVICE_ROLE_DETACHED);
 }
 
diff --git a/src/platform/telink/SystemPlatformConfig.h b/src/platform/telink/SystemPlatformConfig.h
index 9f77a54b223169..5d50e2d4fa30c5 100644
--- a/src/platform/telink/SystemPlatformConfig.h
+++ b/src/platform/telink/SystemPlatformConfig.h
@@ -44,10 +44,20 @@ struct ChipDeviceEvent;
 #define CHIP_SYSTEM_CONFIG_PLATFORM_PROVIDES_TIME 1
 #endif // CHIP_SYSTEM_CONFIG_USE_POSIX_TIME_FUNCTS
 
-#if defined(CONFIG_SOC_RISCV_TELINK_TL321X) || defined(CONFIG_SOC_SERIES_RISCV_TELINK_B9X_RETENTION)
+#if defined CONFIG_SOC_RISCV_TELINK_TL321X || defined CONFIG_SOC_SERIES_RISCV_TELINK_B9X_RETENTION
+#if defined CONFIG_IEEE802154_TLX_OPTIMIZATION && CONFIG_IEEE802154_TLX_OPTIMIZATION
+#define CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_HEAP 0
+#define CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_POOL 1
+#else /* !CONFIG_IEEE802154_TLX_OPTIMIZATION */
 #define CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_HEAP 1
 #define CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_POOL 0
+#endif /* CONFIG_IEEE802154_TLX_OPTIMIZATION */
 #define CHIP_SYSTEM_CONFIG_POOL_USE_HEAP 1
+#endif
+
+#if defined CONFIG_SOC_RISCV_TELINK_TL321X
+#define CHIP_SYSTEM_CONFIG_PACKETBUFFER_CAPACITY_MAX 1100
+#elif defined CONFIG_SOC_SERIES_RISCV_TELINK_B9X_RETENTION
 #define CHIP_SYSTEM_CONFIG_PACKETBUFFER_CAPACITY_MAX 1280
 #endif
 
@@ -56,7 +66,11 @@ struct ChipDeviceEvent;
 
 // Reduce packet buffer pool size (default 15) to reduce ram consumption
 #if defined CONFIG_PM || defined CONFIG_SOC_RISCV_TELINK_TL321X
+#if defined CONFIG_IEEE802154_TLX_OPTIMIZATION && CONFIG_IEEE802154_TLX_OPTIMIZATION
+#define CHIP_SYSTEM_CONFIG_PACKETBUFFER_POOL_SIZE 6
+#else /* !CONFIG_IEEE802154_TLX_OPTIMIZATION */
 #define CHIP_SYSTEM_CONFIG_PACKETBUFFER_POOL_SIZE 0
+#endif /* CONFIG_IEEE802154_TLX_OPTIMIZATION */
 #else
 #define CHIP_SYSTEM_CONFIG_PACKETBUFFER_POOL_SIZE 8
 #endif