diff --git a/src/addr.rs b/src/addr.rs
index 09ec65328..46852c081 100644
--- a/src/addr.rs
+++ b/src/addr.rs
@@ -281,23 +281,6 @@ impl AddAssign<u64> for VirtAddr {
     }
 }
 
-#[cfg(target_pointer_width = "64")]
-impl Add<usize> for VirtAddr {
-    type Output = Self;
-    #[inline]
-    fn add(self, rhs: usize) -> Self::Output {
-        self + rhs as u64
-    }
-}
-
-#[cfg(target_pointer_width = "64")]
-impl AddAssign<usize> for VirtAddr {
-    #[inline]
-    fn add_assign(&mut self, rhs: usize) {
-        self.add_assign(rhs as u64)
-    }
-}
-
 impl Sub<u64> for VirtAddr {
     type Output = Self;
     #[inline]
@@ -313,23 +296,6 @@ impl SubAssign<u64> for VirtAddr {
     }
 }
 
-#[cfg(target_pointer_width = "64")]
-impl Sub<usize> for VirtAddr {
-    type Output = Self;
-    #[inline]
-    fn sub(self, rhs: usize) -> Self::Output {
-        self - rhs as u64
-    }
-}
-
-#[cfg(target_pointer_width = "64")]
-impl SubAssign<usize> for VirtAddr {
-    #[inline]
-    fn sub_assign(&mut self, rhs: usize) {
-        self.sub_assign(rhs as u64)
-    }
-}
-
 impl Sub<VirtAddr> for VirtAddr {
     type Output = u64;
     #[inline]
@@ -564,23 +530,6 @@ impl AddAssign<u64> for PhysAddr {
     }
 }
 
-#[cfg(target_pointer_width = "64")]
-impl Add<usize> for PhysAddr {
-    type Output = Self;
-    #[inline]
-    fn add(self, rhs: usize) -> Self::Output {
-        self + rhs as u64
-    }
-}
-
-#[cfg(target_pointer_width = "64")]
-impl AddAssign<usize> for PhysAddr {
-    #[inline]
-    fn add_assign(&mut self, rhs: usize) {
-        self.add_assign(rhs as u64)
-    }
-}
-
 impl Sub<u64> for PhysAddr {
     type Output = Self;
     #[inline]
@@ -596,23 +545,6 @@ impl SubAssign<u64> for PhysAddr {
     }
 }
 
-#[cfg(target_pointer_width = "64")]
-impl Sub<usize> for PhysAddr {
-    type Output = Self;
-    #[inline]
-    fn sub(self, rhs: usize) -> Self::Output {
-        self - rhs as u64
-    }
-}
-
-#[cfg(target_pointer_width = "64")]
-impl SubAssign<usize> for PhysAddr {
-    #[inline]
-    fn sub_assign(&mut self, rhs: usize) {
-        self.sub_assign(rhs as u64)
-    }
-}
-
 impl Sub<PhysAddr> for PhysAddr {
     type Output = u64;
     #[inline]