diff --git a/Cargo.lock b/Cargo.lock index d3c6054f4da37..d659e0c19a8f0 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -2564,10 +2564,6 @@ dependencies = [ "syntax_pos 0.0.0", ] -[[package]] -name = "rustc_platform_intrinsics" -version = "0.0.0" - [[package]] name = "rustc_plugin" version = "0.0.0" @@ -2678,7 +2674,6 @@ dependencies = [ "rustc 0.0.0", "rustc_data_structures 0.0.0", "rustc_errors 0.0.0", - "rustc_platform_intrinsics 0.0.0", "rustc_target 0.0.0", "smallvec 0.6.7 (registry+https://github.com/rust-lang/crates.io-index)", "syntax 0.0.0", diff --git a/src/etc/platform-intrinsics/aarch64.json b/src/etc/platform-intrinsics/aarch64.json deleted file mode 100644 index c8cda4077b790..0000000000000 --- a/src/etc/platform-intrinsics/aarch64.json +++ /dev/null @@ -1,592 +0,0 @@ -{ - "platform": "aarch64_v", - "intrinsic_prefix": "", - "llvm_prefix": "llvm.aarch64.neon.", - "number_info": { - "signed": { - "kind": "s", - "data_type": { "pattern": "s{bitwidth}" } - }, - "unsigned": { - "kind": "u", - "data_type": { "pattern": "u{bitwidth}" } - }, - "float": { - "kind": "f", - "data_type": { "pattern": "f{bitwidth}" } - } - }, - "width_info": { - "64": { "width": "" }, - "128": { "width": "q" } - }, - "intrinsics": [ - { - "intrinsic": "hadd{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "{0.kind}hadd.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "rhadd{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "{0.kind}rhadd.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "qadd{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "{0.kind}qadd.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "uqadd_{0.data_type}", - "width": [128], - "llvm": "suqadd.{0.llvm_name}", - "ret": "s(8-64)", - "args": ["0", "0u"] - }, - { - "intrinsic": "sqadd_{0.data_type}", - "width": [128], - "llvm": "usqadd.{0.llvm_name}", - "ret": "u(8-64)", - "args": ["0", "0s"] - }, - { - "intrinsic": "raddhn_{1.data_type}", - "width": [64], - "llvm": "raddhn.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0w", "0w"] - }, - { - "intrinsic": "fmulx{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "fmulx.{0.llvm_name}", - "ret": "f(32-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "fma{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "!llvm.fma.{0.llvm_name}", - "ret": "f(32-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "qdmulh{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "sqdmulh.{0.llvm_name}", - "ret": "s(16-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "qrdmulh{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "sqrdmulh.{0.llvm_name}", - "ret": "s(16-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "mull_{1.data_type}", - "width": [128], - "llvm": "{0.kind}mull.{0.llvm_name}", - "ret": "i(16-64)", - "args": ["0n", "0n"] - }, - { - "intrinsic": "qdmull{0.width}_{1.data_type}", - "width": [128], - "llvm": "sqdmull.{0.llvm_name}", - "ret": "s(16-32)", - "args": ["0n", "0n"] - }, - { - "intrinsic": "hsub{0.width}_{1.data_type}", - "width": [64, 128], - "llvm": "{0.kind}hsub.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "qsub{0.width}_{1.data_type}", - "width": [64, 128], - "llvm": "{0.kind}qsub.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "rsubhn_{1.data_type}", - "width": [64], - "llvm": "rsubhn.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0w", "0w"] - }, - { - "intrinsic": "abd{0.width}_{1.data_type}", - "width": [64, 128], - "llvm": "{0.kind}abd.{0.llvm_name}", - "ret": ["i(8-32)","f(32-64)"], - "args": ["0", "0"] - }, - { - "intrinsic": "max{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "{0.kind}max.{0.llvm_name}", - "ret": ["i(8-32)","f(32-64)"], - "args": ["0", "0"] - }, - { - "intrinsic": "min{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "{0.kind}min.{0.llvm_name}", - "ret": ["i(8-32)","f(32-64)"], - "args": ["0", "0"] - }, - { - "intrinsic": "maxnm{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "{0.kind}maxnm.{0.llvm_name}", - "ret": "f(32-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "minnm{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "{0.kind}minnm.{0.llvm_name}", - "ret": "f(32-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "shl{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "{0.kind}shl.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0s"] - }, - { - "intrinsic": "qshl{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "{0.kind}qshl.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0s"] - }, - { - "intrinsic": "rshl{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "{0.kind}rshl.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0s"] - }, - { - "intrinsic": "qrshl{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "{0.kind}qrshl.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0s"] - }, - { - "intrinsic": "qshrun_n_{1.data_type}", - "width": [64], - "llvm": "sqshrun.{0.llvm_name}", - "ret": "s(8-32)", - "args": ["0w", "U32"] - }, - { - "intrinsic": "qrshrun_n_{1.data_type}", - "width": [64], - "llvm": "sqrshrun.{0.llvm_name}", - "ret": "s(8-32)", - "args": ["0w", "U32"] - }, - { - "intrinsic": "qshrn_n_{1.data_type}", - "width": [64], - "llvm": "{0.kind}qshrn.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0w", "U32"] - }, - { - "intrinsic": "rshrn_n_{1.data_type}", - "width": [64], - "llvm": "rshrn.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0w", "U32"] - }, - { - "intrinsic": "qrshrn_n_{1.data_type}", - "width": [64], - "llvm": "{0.kind}qrshrn.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0w", "U32"] - }, - { - "intrinsic": "sri{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "vsri.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "sli{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "vsli.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "vqmovn_{1.data_type}", - "width": [64], - "llvm": "{0.kind}qxtn.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0w"] - }, - { - "intrinsic": "abs{0.width}_{0.data_type}", - "width": [64,128], - "llvm": "abs.{0.llvm_name}", - "ret": "s(8-64)", - "args": ["0"] - }, - { - "intrinsic": "abs{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "!llvm.fabs.{0.llvm_name}", - "ret": "f(32-64)", - "args": ["0"] - }, - { - "intrinsic": "qabs{0.width}_{0.data_type}", - "width": [64,128], - "llvm": "sqabs.{0.llvm_name}", - "ret": "s(8-64)", - "args": ["0"] - }, - { - "intrinsic": "qneg{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "sqneg.{0.llvm_name}", - "ret": "s(8-64)", - "args": ["0"] - }, - { - "intrinsic": "clz{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "!llvm.ctlz.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0"] - }, - { - "intrinsic": "cls{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "cls.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0"] - }, - { - "intrinsic": "cnt{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "!llvm.ctpop.{0.llvm_name}", - "ret": "i8", - "args": ["0"] - }, - { - "intrinsic": "recpe{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "{0.kind}recpe.{0.llvm_name}", - "ret": ["u32","f(32-64)"], - "args": ["0"] - }, - { - "intrinsic": "recps{0.width}_{0.data_type}", - "width": [64,128], - "llvm": "frecps.{0.llvm_name}", - "ret": "f(32-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "sqrt{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "!llvm.sqrt.{0.llvm_name}", - "ret": "f(32-64)", - "args": ["0"] - }, - { - "intrinsic": "rsqrte{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "{0.kind}rsqrte.{0.llvm_name}", - "ret": ["u32","f(32-64)"], - "args": ["0"] - }, - { - "intrinsic": "rsqrts{0.width}_{0.data_type}", - "width": [64,128], - "llvm": "frsqrts.{0.llvm_name}", - "ret": "f(32-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "rbit{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "rbit.{0.llvm_name}", - "ret": "i8", - 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"args": ["0", "(0x128,0x128,0x128,0x128)f", "0u"] - } - ] -} diff --git a/src/etc/platform-intrinsics/arm.json b/src/etc/platform-intrinsics/arm.json deleted file mode 100644 index d008320713c3b..0000000000000 --- a/src/etc/platform-intrinsics/arm.json +++ /dev/null @@ -1,396 +0,0 @@ -{ - "platform": "arm_v", - "intrinsic_prefix": "", - "llvm_prefix": "llvm.arm.neon.v", - "number_info": { - "signed": { - "kind": "s", - "data_type": { "pattern": "s{bitwidth}" } - }, - "unsigned": { - "kind": "u", - "data_type": { "pattern": "u{bitwidth}" } - }, - "float": { - "kind": "f", - "data_type": { "pattern": "f{bitwidth}" } - } - }, - "width_info": { - "64": { "width": "" }, - "128": { "width": "q" } - }, - "intrinsics": [ - { - "intrinsic": "hadd{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "hadd{0.kind}.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "rhadd{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "rhadd{0.kind}.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "qadd{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "qadd{0.kind}.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "raddhn_{1.data_type}", - "width": [64], - "llvm": "raddhn.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0w", "0w"] - }, - { - "intrinsic": "fma{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "!llvm.fma.{0.llvm_name}", - "ret": "f32", - "args": ["0", "0"] - }, - { - "intrinsic": "qdmulh{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "sqdmulh.{0.llvm_name}", - "ret": "s(16-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "qrdmulh{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "sqrdmulh.{0.llvm_name}", - "ret": "s(16-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "mull_{1.data_type}", - "width": [128], - "llvm": "mull{0.kind}.{0.llvm_name}", - "ret": "i(16-64)", - "args": ["0n", "0n"] - }, - { - "intrinsic": "qdmull{0.width}_{1.data_type}", - "width": [128], - "llvm": "sqdmull.{0.llvm_name}", - "ret": "s(16-32)", - "args": ["0n", "0n"] - }, - { - "intrinsic": "hsub{0.width}_{1.data_type}", - "width": [64, 128], - "llvm": "hsub{0.kind}.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "qsub{0.width}_{1.data_type}", - "width": [64, 128], - "llvm": "qsub{0.kind}.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "rsubhn_{1.data_type}", - "width": [64], - "llvm": "rsubhn.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0w", "0w"] - }, - { - "intrinsic": "abd{0.width}_{1.data_type}", - "width": [64, 128], - "llvm": "abd{0.kind}.{0.llvm_name}", - "ret": ["i(8-32)","f32"], - "args": ["0", "0"] - }, - { - "intrinsic": "max{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "max{0.kind}.{0.llvm_name}", - "ret": ["i(8-32)","f32"], - "args": ["0", "0"] - }, - { - "intrinsic": "min{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "min{0.kind}.{0.llvm_name}", - "ret": ["i(8-32)","f32"], - "args": ["0", "0"] - }, - { - "intrinsic": "shl{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "shl{0.kind}.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0s"] - }, - { - "intrinsic": "qshl{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "qshl{0.kind}.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0s"] - }, - { - "intrinsic": "rshl{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "rshl{0.kind}.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0s"] - }, - { - "intrinsic": "qrshl{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "qrshl{0.kind}.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0s"] - }, - { - "intrinsic": "qshrun_n_{1.data_type}", - "width": [64], - "llvm": "sqshrun.{0.llvm_name}", - "ret": "s(8-32)", - "args": ["0w", "U32"] - }, - { - "intrinsic": "qrshrun_n_{1.data_type}", - "width": [64], - "llvm": "sqrshrun.{0.llvm_name}", - "ret": "s(8-32)", - "args": ["0w", "U32"] - }, - { - "intrinsic": "qshrn_n_{1.data_type}", - "width": [64], - "llvm": "qshrn{0.kind}.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0w", "U32"] - }, - { - "intrinsic": "rshrn_n_{1.data_type}", - "width": [64], - "llvm": "rshrn.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0w", "U32"] - }, - { - "intrinsic": "qrshrn_n_{1.data_type}", - "width": [64], - "llvm": "qrshrn{0.kind}.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0w", "U32"] - }, - { - "intrinsic": "sri{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "vsri.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "sli{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "vsli.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "vqmovn_{1.data_type}", - "width": [64], - "llvm": "qxtn{0.kind}.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0w"] - }, - { - "intrinsic": "abs{0.width}_{0.data_type}", - "width": [64,128], - "llvm": "abs.{0.llvm_name}", - "ret": "s(8-32)", - "args": ["0"] - }, - { - "intrinsic": "abs{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "!llvm.fabs.{0.llvm_name}", - "ret": "f32", - "args": ["0"] - }, - { - "intrinsic": "qabs{0.width}_{0.data_type}", - "width": [64,128], - "llvm": "sqabs.{0.llvm_name}", - "ret": "s(8-32)", - "args": ["0"] - }, - { - "intrinsic": "qneg{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "sqneg.{0.llvm_name}", - "ret": "s(8-32)", - "args": ["0"] - }, - { - "intrinsic": "clz{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "!llvm.ctlz.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0"] - }, - { - "intrinsic": "cls{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "cls.{0.llvm_name}", - "ret": "i(8-32)", - "args": ["0"] - }, - { - "intrinsic": "cnt{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "!llvm.ctpop.{0.llvm_name}", - "ret": "i8", - "args": ["0"] - }, - { - "intrinsic": "recpe{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "recpe.{0.llvm_name}", - "ret": ["u32","f32"], - "args": ["0"] - }, - { - "intrinsic": "recps{0.width}_{0.data_type}", - "width": [64,128], - "llvm": "frecps.{0.llvm_name}", - "ret": "f32", - "args": ["0", "0"] - }, - { - "intrinsic": "sqrt{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "!llvm.sqrt.{0.llvm_name}", - "ret": "f32", - "args": ["0"] - }, - { - "intrinsic": "rsqrte{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "rsqrte.{0.llvm_name}", - "ret": ["u32","f32"], - "args": ["0"] - }, - { - "intrinsic": "rsqrts{0.width}_{0.data_type}", - "width": [64,128], - "llvm": "rsqrts.{0.llvm_name}", - "ret": "f32", - "args": ["0", "0"] - }, - { - "intrinsic": "bsl{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "bsl.{0.llvm_name}", - "ret": "i(8-64)", - "args": ["0u", "0"] - }, - { - "intrinsic": "padd{0.width}_{0.data_type}", - "width": [64], - "llvm": "padd.{0.llvm_name}", - "ret": ["i(8-32)","f32"], - "args": ["0", "0"] - }, - { - "intrinsic": "paddl{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "paddl{0.kind}.{0.llvm_name}.{1.llvm_name}", - "ret": "i(16-64)", - "args": ["0dn"] - }, - { - "intrinsic": "padal{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "padal{0.kind}.{0.llvm_name}.{1.llvm_name}", - "ret": "i(16-64)", - "args": ["0", "0dn"] - }, - { - "intrinsic": "pmax{0.width}_{0.data_type}", - "width": [64], - "llvm": "pmax{0.kind}.{0.llvm_name}", - "ret": ["i(8-32)","f32"], - "args": ["0", "0"] - }, - { - "intrinsic": "pmin{0.width}_{0.data_type}", - "width": [64, 128], - "llvm": "pmin{0.kind}.{0.llvm_name}", - "ret": ["i(8-32)","f32"], - "args": ["0", "0"] - }, - { - "intrinsic": "tbl1_{0.data_type}", - "width": [64], - "llvm": "tbl1", - "ret": "i8", - "args": ["0", "0u"] - }, - { - "intrinsic": "tbx1_{0.data_type}", - "width": [64], - "llvm": "tbx1", - "ret": "i8", - "args": ["0", "0", "0u"] - }, - { - "intrinsic": "tbl2_{0.data_type}", - "width": [64], - "llvm": "tbl2", - "ret": "i8", - "args": ["(0,0)f", "0u"] - }, - { - "intrinsic": "tbx2_{0.data_type}", - "width": [64], - "llvm": "tbx2", - "ret": "i8", - "args": ["(0,0)f", "0u"] - }, - { - "intrinsic": "tbl3_{0.data_type}", - "width": [64], - "llvm": "tbl3", - "ret": "i8", - "args": ["(0,0,0)f", "0u"] - }, - { - "intrinsic": "tbx3_{0.data_type}", - "width": [64], - "llvm": "tbx3", - "ret": "i8", - "args": ["0", "(0,0,0)f", "0u"] - }, - { - "intrinsic": "tbl4_{0.data_type}", - "width": [64], - "llvm": "tbl4", - "ret": "i8", - "args": ["(0,0,0,0)f", "0u"] - }, - { - "intrinsic": "tbx4_{0.data_type}", - "width": [64], - "llvm": "tbx4", - "ret": "i8", - "args": ["0", "(0,0,0,0)f", "0u"] - } - ] -} diff --git a/src/etc/platform-intrinsics/generator.py b/src/etc/platform-intrinsics/generator.py deleted file mode 100644 index fa97131f695f9..0000000000000 --- a/src/etc/platform-intrinsics/generator.py +++ /dev/null @@ -1,854 +0,0 @@ -from __future__ import division, print_function -import json -import argparse -import sys -import re -import textwrap -import itertools - -SPEC = re.compile( - r'^(?:(?PV)|(?P[iusfIUSF])(?:\((?P\d+)-(?P\d+)\)|' - r'(?P\d+)(:?/(?P\d+))?)' - r'|(?P\d+))(?P\.\d+)?(?P[vShdnwusfDMCNW]*)(?Px\d+)?' - r'(?:(?PPm|Pc)(?P/.*)?|(?P->.*))?$' -) - -class PlatformInfo(object): - def __init__(self, json): - self._platform = json['platform'] - - def platform_prefix(self): - return self._platform - -class IntrinsicSet(object): - def __init__(self, platform, json): - self._llvm_prefix = json['llvm_prefix'] - self._type_info = json['number_info'] - self._intrinsics = json['intrinsics'] - self._widths = json['width_info'] - self._platform = platform - self._intrinsic_prefix = json['intrinsic_prefix'] - - def intrinsics(self): - for raw in self._intrinsics: - yield GenericIntrinsic(self, - raw['intrinsic'], raw['width'], raw['llvm'], - raw['ret'], raw['args']) - - def platform(self): - return self._platform - - def intrinsic_prefix(self): - return self._intrinsic_prefix - - def llvm_prefix(self): - return self._llvm_prefix - - def width_info(self, bitwidth): - return self._widths[str(bitwidth)] - - def number_type_info(self, value): - data = self._type_info[value.__class__.__name__.lower()] - bitwidth = value.bitwidth() - def lookup(raw): - if not isinstance(raw, dict): - return raw - - try: - return raw[str(bitwidth)] - except KeyError: - return raw['pattern'].format(bitwidth = bitwidth) - - return PlatformTypeInfo(value.llvm_name(), - {k: lookup(v) for k, v in data.items()}) - -class PlatformTypeInfo(object): - def __init__(self, llvm_name, properties, elems = None): - if elems is None: - self.properties = properties - self.llvm_name = llvm_name - else: - assert properties is None and llvm_name is None - self.properties = {} - self.elems = elems - - def __repr__(self): - return ''.format(self.llvm_name, self.properties) - - def __getattr__(self, name): - return self.properties[name] - - def __getitem__(self, idx): - return self.elems[idx] - - def vectorize(self, length, width_info): - props = self.properties.copy() - props.update(width_info) - return PlatformTypeInfo('v{}{}'.format(length, self.llvm_name), props) - - def pointer(self, llvm_elem): - name = self.llvm_name if llvm_elem is None else llvm_elem.llvm_name - return PlatformTypeInfo('p0{}'.format(name), self.properties) - -BITWIDTH_POINTER = '' - -class Type(object): - def __init__(self, bitwidth): - self._bitwidth = bitwidth - - def bitwidth(self): - return self._bitwidth - - def modify(self, spec, width, previous): - raise NotImplementedError() - - def __ne__(self, other): - return not (self == other) - -class Void(Type): - def __init__(self): - Type.__init__(self, 0) - - @staticmethod - def compiler_ctor(): - return '::VOID' - - def compiler_ctor_ref(self): - return '&' + self.compiler_ctor() - - @staticmethod - def rust_name(): - return '()' - - @staticmethod - def type_info(platform_info): - return None - - def __eq__(self, other): - return isinstance(other, Void) - -class Number(Type): - def __init__(self, bitwidth): - Type.__init__(self, bitwidth) - - def modify(self, spec, width, previous): - if spec == 'u': - return Unsigned(self.bitwidth()) - elif spec == 's': - return Signed(self.bitwidth()) - elif spec == 'f': - return Float(self.bitwidth()) - elif spec == 'w': - return self.__class__(self.bitwidth() * 2) - elif spec == 'n': - return self.__class__(self.bitwidth() // 2) - elif spec == 'v': - return Vector(self, width // self.bitwidth()) - else: - raise ValueError('unknown modification spec {}', spec) - - def type_info(self, platform_info): - return platform_info.number_type_info(self) - - def __eq__(self, other): - # print(self, other) - return self.__class__ == other.__class__ and self.bitwidth() == other.bitwidth() - -class Signed(Number): - def __init__(self, bitwidth, llvm_bitwidth = None): - Number.__init__(self, bitwidth) - self._llvm_bitwidth = llvm_bitwidth - - - def compiler_ctor(self): - if self._llvm_bitwidth is None: - return '::I{}'.format(self.bitwidth()) - else: - return '::I{}_{}'.format(self.bitwidth(), self._llvm_bitwidth) - - def compiler_ctor_ref(self): - return '&' + self.compiler_ctor() - - def llvm_name(self): - bw = self._llvm_bitwidth or self.bitwidth() - return 'i{}'.format(bw) - - def rust_name(self): - return 'i{}'.format(self.bitwidth()) - -class Unsigned(Number): - def __init__(self, bitwidth, llvm_bitwidth = None): - Number.__init__(self, bitwidth) - self._llvm_bitwidth = llvm_bitwidth - - def compiler_ctor(self): - if self._llvm_bitwidth is None: - return '::U{}'.format(self.bitwidth()) - else: - return '::U{}_{}'.format(self.bitwidth(), self._llvm_bitwidth) - - def compiler_ctor_ref(self): - return '&' + self.compiler_ctor() - - def llvm_name(self): - bw = self._llvm_bitwidth or self.bitwidth() - return 'i{}'.format(bw) - - def rust_name(self): - return 'u{}'.format(self.bitwidth()) - -class Float(Number): - def __init__(self, bitwidth): - assert bitwidth in (32, 64) - Number.__init__(self, bitwidth) - - def compiler_ctor(self): - return '::F{}'.format(self.bitwidth()) - - def compiler_ctor_ref(self): - return '&' + self.compiler_ctor() - - def llvm_name(self): - return 'f{}'.format(self.bitwidth()) - - def rust_name(self): - return 'f{}'.format(self.bitwidth()) - -class Vector(Type): - def __init__(self, elem, length, bitcast = None): - assert isinstance(elem, Type) and not isinstance(elem, Vector) - Type.__init__(self, - elem.bitwidth() * length) - self._length = length - self._elem = elem - assert bitcast is None or (isinstance(bitcast, Vector) and - bitcast._bitcast is None and - bitcast._elem.bitwidth() == elem.bitwidth()) - if bitcast is not None and bitcast._elem != elem: - self._bitcast = bitcast._elem - else: - self._bitcast = None - - def modify(self, spec, width, previous): - if spec == 'S': - return self._elem - elif spec == 'h': - return Vector(self._elem, self._length // 2) - elif spec == 'd': - return Vector(self._elem, self._length * 2) - elif spec == 'N': - elem = self._elem.__class__(self._elem.bitwidth() // 2) - return Vector(elem, self._length * 2) - elif spec == 'W': - elem = self._elem.__class__(self._elem.bitwidth() * 2) - return Vector(elem, self._length // 2) - elif spec.startswith('x'): - new_bitwidth = int(spec[1:]) - return Vector(self._elem, new_bitwidth // self._elem.bitwidth()) - elif spec.startswith('->'): - bitcast_to = TypeSpec(spec[2:]) - choices = list(bitcast_to.enumerate(width, previous)) - assert len(choices) == 1 - bitcast_to = choices[0] - return Vector(self._elem, self._length, bitcast_to) - else: - return Vector(self._elem.modify(spec, width, previous), self._length) - - def compiler_ctor(self): - if self._bitcast is None: - return '{}x{}'.format(self._elem.compiler_ctor(), - self._length) - else: - return '{}x{}_{}'.format(self._elem.compiler_ctor(), - self._length, - self._bitcast.compiler_ctor() - .replace('::', '')) - - def compiler_ctor_ref(self): - return '&' + self.compiler_ctor() - - def rust_name(self): - return '{}x{}'.format(self._elem.rust_name(), self._length) - - def type_info(self, platform_info): - elem_info = self._elem.type_info(platform_info) - return elem_info.vectorize(self._length, - platform_info.width_info(self.bitwidth())) - - def __eq__(self, other): - return isinstance(other, Vector) and self._length == other._length and \ - self._elem == other._elem and self._bitcast == other._bitcast - -class Pointer(Type): - def __init__(self, elem, llvm_elem, const): - self._elem = elem - self._llvm_elem = llvm_elem - self._const = const - Type.__init__(self, BITWIDTH_POINTER) - - def modify(self, spec, width, previous): - if spec == 'D': - return self._elem - elif spec == 'M': - return Pointer(self._elem, self._llvm_elem, False) - elif spec == 'C': - return Pointer(self._elem, self._llvm_elem, True) - else: - return Pointer(self._elem.modify(spec, width, previous), self._llvm_elem, self._const) - - def compiler_ctor(self): - if self._llvm_elem is None: - llvm_elem = 'None' - else: - llvm_elem = 'Some({})'.format(self._llvm_elem.compiler_ctor_ref()) - return 'Type::Pointer({}, {}, {})'.format(self._elem.compiler_ctor_ref(), - llvm_elem, - 'true' if self._const else 'false') - - def compiler_ctor_ref(self): - return "{{ static PTR: Type = {}; &PTR }}".format(self.compiler_ctor()) - - - def rust_name(self): - return '*{} {}'.format('const' if self._const else 'mut', - self._elem.rust_name()) - - def type_info(self, platform_info): - if self._llvm_elem is None: - llvm_elem = None - else: - llvm_elem = self._llvm_elem.type_info(platform_info) - return self._elem.type_info(platform_info).pointer(llvm_elem) - - def __eq__(self, other): - return isinstance(other, Pointer) and self._const == other._const \ - and self._elem == other._elem and self._llvm_elem == other._llvm_elem - -class Aggregate(Type): - def __init__(self, flatten, elems): - self._flatten = flatten - self._elems = elems - Type.__init__(self, sum(elem.bitwidth() for elem in elems)) - - def __repr__(self): - return ''.format(self._elems) - - def modify(self, spec, width, previous): - if spec.startswith('.'): - num = int(spec[1:]) - return self._elems[num] - else: - print(spec) - raise NotImplementedError() - - def compiler_ctor(self): - parts = "{{ static PARTS: [&'static Type; {}] = [{}]; &PARTS }}" - elems = ', '.join(elem.compiler_ctor_ref() for elem in self._elems) - parts = parts.format(len(self._elems), elems) - return 'Type::Aggregate({}, {})'.format('true' if self._flatten else 'false', - parts) - - def compiler_ctor_ref(self): - return "{{ static AGG: Type = {}; &AGG }}".format(self.compiler_ctor()) - - def rust_name(self): - return '({})'.format(', '.join(elem.rust_name() for elem in self._elems)) - - def type_info(self, platform_info): - return PlatformTypeInfo(None, None, [elem.type_info(platform_info) for elem in self._elems]) - - def __eq__(self, other): - return isinstance(other, Aggregate) and self._flatten == other._flatten and \ - self._elems == other._elems - - -TYPE_ID_LOOKUP = {'i': [Signed, Unsigned], - 's': [Signed], - 'u': [Unsigned], - 'f': [Float]} - -def ptrify(match, elem, width, previous): - ptr = match.group('pointer') - if ptr is None: - return elem - else: - llvm_ptr = match.group('llvm_pointer') - if llvm_ptr is None: - llvm_elem = None - else: - assert llvm_ptr.startswith('/') - options = list(TypeSpec(llvm_ptr[1:]).enumerate(width, previous)) - assert len(options) == 1 - llvm_elem = options[0] - assert ptr in ('Pc', 'Pm') - return Pointer(elem, llvm_elem, ptr == 'Pc') - -class TypeSpec(object): - def __init__(self, spec): - if not isinstance(spec, list): - spec = [spec] - - self.spec = spec - - def enumerate(self, width, previous): - for spec in self.spec: - match = SPEC.match(spec) - if match is not None: - id = match.group('id') - reference = match.group('reference') - - modifiers = [] - index = match.group('index') - if index is not None: - modifiers.append(index) - modifiers += list(match.group('modifiers') or '') - force = match.group('force_width') - if force is not None: - modifiers.append(force) - bitcast = match.group('bitcast') - if bitcast is not None: - modifiers.append(bitcast) - - if match.group('void') is not None: - assert spec == 'V' - yield Void() - elif id is not None: - is_vector = id.islower() - type_ctors = TYPE_ID_LOOKUP[id.lower()] - - start = match.group('start') - if start is not None: - end = match.group('end') - llvm_width = None - else: - start = end = match.group('width') - llvm_width = match.group('llvm_width') - start = int(start) - end = int(end) - - bitwidth = start - while bitwidth <= end: - for ctor in type_ctors: - if llvm_width is not None: - assert not is_vector - llvm_width = int(llvm_width) - assert llvm_width < bitwidth - scalar = ctor(bitwidth, llvm_width) - else: - scalar = ctor(bitwidth) - - if is_vector: - elem = Vector(scalar, width // bitwidth) - else: - assert bitcast is None - elem = scalar - - for x in modifiers: - elem = elem.modify(x, width, previous) - yield ptrify(match, elem, width, previous) - bitwidth *= 2 - elif reference is not None: - reference = int(reference) - assert reference < len(previous), \ - 'referring to argument {}, but only {} are known'.format(reference, - len(previous)) - ret = previous[reference] - for x in modifiers: - ret = ret.modify(x, width, previous) - yield ptrify(match, ret, width, previous) - else: - assert False, 'matched `{}`, but didn\'t understand it?'.format(spec) - elif spec.startswith('('): - if spec.endswith(')'): - true_spec = spec[1:-1] - flatten = False - elif spec.endswith(')f'): - true_spec = spec[1:-2] - flatten = True - else: - assert False, 'found unclosed aggregate `{}`'.format(spec) - - for elems in itertools.product(*(TypeSpec(subspec).enumerate(width, previous) - for subspec in true_spec.split(','))): - yield Aggregate(flatten, elems) - elif spec.startswith('['): - if spec.endswith(']'): - true_spec = spec[1:-1] - flatten = False - elif spec.endswith(']f'): - true_spec = spec[1:-2] - flatten = True - else: - assert False, 'found unclosed aggregate `{}`'.format(spec) - elem_spec, count = true_spec.split(';') - - count = int(count) - for elem in TypeSpec(elem_spec).enumerate(width, previous): - yield Aggregate(flatten, [elem] * count) - else: - assert False, 'Failed to parse `{}`'.format(spec) - -class GenericIntrinsic(object): - def __init__(self, platform, intrinsic, widths, llvm_name, ret, args): - self._platform = platform - self.intrinsic = intrinsic - self.widths = map(int, widths) - self.llvm_name = llvm_name - self.ret = TypeSpec(ret) - self.args = list(map(TypeSpec, args)) - - def monomorphise(self): - for width in self.widths: - # must be a power of two - assert width & (width - 1) == 0 - def recur(processed, untouched): - if not untouched: - ret = processed[0] - args = processed[1:] - yield MonomorphicIntrinsic(self._platform, self.intrinsic, width, - self.llvm_name, - ret, args) - else: - raw_arg = untouched[0] - rest = untouched[1:] - for arg in raw_arg.enumerate(width, processed): - for intr in recur(processed + [arg], rest): - yield intr - - for x in recur([], [self.ret] + self.args): - yield x - -class MonomorphicIntrinsic(object): - def __init__(self, platform, intrinsic, width, llvm_name, ret, args): - self._platform = platform - self._intrinsic = intrinsic - self._width = '' if width == 64 else 'q' - self._llvm_name = llvm_name - self._ret_raw = ret - self._ret = ret.type_info(platform) - self._args_raw = args - self._args = [arg.type_info(platform) for arg in args] - - def llvm_name(self): - if self._llvm_name.startswith('!'): - return self._llvm_name[1:].format(self._ret, *self._args) - else: - return self._platform.llvm_prefix() + self._llvm_name.format(self._ret, *self._args) - - def intrinsic_suffix(self): - return self._intrinsic.format(self._ret, - *self._args, - width = self._width) - - def platform_prefix(self): - return self._platform.platform().platform_prefix() - - def intrinsic_set_name(self): - return self._platform.intrinsic_prefix() - - def intrinsic_name(self): - return self._platform.intrinsic_prefix() + self.intrinsic_suffix() - - def compiler_args(self): - return ', '.join(arg.compiler_ctor_ref() for arg in self._args_raw) - - def compiler_ret(self): - return self._ret_raw.compiler_ctor_ref() - - def compiler_signature(self): - return '({}) -> {}'.format(self.compiler_args(), self.compiler_ret()) - - def intrinsic_signature(self): - names = 'xyzwabcdef' - return '({}) -> {}'.format(', '.join('{}: {}'.format(name, arg.rust_name()) - for name, arg in zip(names, self._args_raw)), - self._ret_raw.rust_name()) - -def parse_args(): - parser = argparse.ArgumentParser( - formatter_class = argparse.RawDescriptionHelpFormatter, - description = 'Render an intrinsic definition JSON to various formats.', - epilog = textwrap.dedent('''\ - Quick How-To: - - There are two operating modes: single file and multiple files. - - For example, ARM is specified as a single file. To generate the - compiler-definitions for ARM just pass the script the "arm.json" file: - - python generator.py --format compiler-defs arm.json - - The X86 architecture is specified as multiple files (for the different - instruction sets that x86 supports). To generate the compiler - definitions one needs to pass the script a "platform information file" - (with the -i flag) next to the files of the different instruction sets. - For example, to generate the X86 compiler-definitions for SSE4.2, just: - - python generator.py --format compiler-defs -i x86/info.json sse42.json - - And to generate the compiler-definitions for SSE4.1 and SSE4.2, just: - - python generator.py --format compiler-defs -i x86/info.json sse41.json sse42.json - - An intrinsic definition consists of a map with fields: - - intrinsic: pattern for the name(s) of the vendor's C intrinsic(s) - - llvm: pattern for the name(s) of the internal llvm intrinsic(s) - - width: a vector of vector bit-widths the pattern works with - - ret: type specifier for the return value - - arguments: vector of type specifiers for arguments - - The width and types describe a range of possible intrinsics, - and these are fed back into the intrinsic and llvm patterns to - create the appropriate definitions. - - ## Type specifier grammar - - ``` - type := core_type modifier* suffix? - - core_type := void | vector | scalar | aggregate | reference - - modifier := 'v' | 'h' | 'd' | 'n' | 'w' | 'u' | 's' | - 'x' number | '.' number - suffix := pointer | bitcast - pointer := 'Pm' llvm_pointer? | 'Pc' llvm_pointer? - llvm_pointer := '/' type - bitcast := '->' type - - void := 'V' - - vector := vector_elem width | - vector_elem := 'i' | 'u' | 's' | 'f' - - scalar := scalar_type number llvm_width? - scalar_type := 'U' | 'S' | 'F' - llvm_width := '/' number - - aggregate := '(' (type),* ')' 'f'? | '[' type ';' number ']' 'f'? - - reference := number - - width = number | '(' number '-' number ')' - - number = [0-9]+ - ``` - - ## Void - - The `V` type corresponds to `void` in LLVM (`()` in - Rust). It's likely to only work in return position. - - ## Vectors - - The vector grammar is a pattern describing many possibilities - for arguments/return value. The `vector_elem` describes the - types of elements to use, and the `width` describes the (range - of) widths for those elements, which are then placed into a - vector with the `width` bitwidth. E.g. if an intrinsic has a - `width` that includes 128, and the return value is `i(8-32)`, - then some instantiation of that intrinsic will be `u8x16`, - `u32x4`, `i32x4`, etc. - - ### Elements - - - i: integer, both signed and unsigned - - u: unsigned integer - - s: signed integer - - f: float - - ## Scalars - - Similar to vectors, but these describe a single concrete type, - not a range. The number is the bitwidth. The optional - `llvm_width` is the bitwidth of the integer that should be - passed to LLVM (by truncating the Rust argument): this only - works with scalar integers and the LLVM width must be smaller - than the Rust width. - - ### Types - - - U: unsigned integer - - S: signed integer - - F: float - - ## Aggregates - - An aggregate is a collection of multiple types; a tuple in - Rust terms, or an unnamed struct in LLVM. The `f` modifiers - forces the tuple to be flattened in the LLVM - intrinsic. E.g. if `llvm.foo` takes `(F32,S32)`: - - - no `f` corresponds to `declare ... @llvm.foo({float, i32})`. - - having an `f` corresponds to `declare ... @llvm.foo(float, i32)`. - - The `[type;number]` form is a just shorter way to write - `(...)`, except avoids doing a cartesian product of generic - types, e.g. `[S32;2]` is the same as `(S32, S32)`, while - `[I32;2]` is describing just the two types `(S32,S32)` and - `(U32,U32)` (i.e. doesn't include `(S32,U32)`, `(U32,S32)` as - `(I32,I32)` would). - - (Currently aggregates can not contain other aggregates.) - - ## References - - A reference uses the type of another argument, with possible - modifications. The number refers to the type to use, starting - with 0 == return value, 1 == first argument, 2 == second - argument, etc. - - ## Affixes - - The `modifier` and `suffix` adaptors change the precise - representation. - - ### Modifiers - - - 'v': put a scalar into a vector of the current width (u32 -> u32x4, when width == 128) - - 'S': get the scalar element of a vector (u32x4 -> u32) - - 'h': half the length of the vector (u32x4 -> u32x2) - - 'd': double the length of the vector (u32x2 -> u32x4) - - 'n': narrow the element of the vector (u32x4 -> u16x4) - - 'w': widen the element of the vector (u16x4 -> u32x4) - - 'N': half the length of the vector element (u32x4 -> u16x8) - - 'W': double the length of the vector element (u16x8 -> u32x4) - - 'u': force a number (vector or scalar) to be unsigned int (f32x4 -> u32x4) - - 's': force a number (vector or scalar) to be signed int (u32x4 -> i32x4) - - 'f': force a number (vector or scalar) to be float (u32x4 -> f32x4) - - 'x' number: force the type to be a vector of bitwidth `number`. - - '.' number: get the `number`th element of an aggregate - - 'D': dereference a pointer (*mut u32 -> u32) - - 'C': make a pointer const (*mut u32 -> *const u32) - - 'M': make a pointer mut (*const u32 -> *mut u32) - - ### Pointers - - Pointers can be created of any type by appending a `P*` - suffix. The `m` vs. `c` chooses mut vs. const. e.g. `S32Pm` - corresponds to `*mut i32`, and `i32Pc` corresponds (with width - 128) to `*const i8x16`, `*const u32x4`, etc. - - The type after the `/` (optional) represents the type used - internally to LLVM, e.g. `S32pm/S8` is exposed as `*mut i32` - in Rust, but is `i8*` in LLVM. (This defaults to the main - type). - - ### Bitcast - - The `'->' type` bitcast suffix will cause the value to be - bitcast to the right-hand type when calling the intrinsic, - e.g. `s32->f32` will expose the intrinsic as `i32x4` at the - Rust level, but will cast that vector to `f32x4` when calling - the LLVM intrinsic. - ''')) - parser.add_argument('--format', choices=FORMATS, required=True, - help = 'Output format.') - parser.add_argument('-o', '--out', type=argparse.FileType('w'), default=sys.stdout, - help = 'File to output to (default stdout).') - parser.add_argument('-i', '--info', type=argparse.FileType('r'), - help = 'File containing platform specific information to merge into ' - 'the input files\' header.') - parser.add_argument('in_', metavar="FILE", type=argparse.FileType('r'), nargs='+', - help = 'JSON files to load') - return parser.parse_args() - - -class ExternBlock(object): - def __init__(self): - pass - - @staticmethod - def open(platform): - return 'extern "platform-intrinsic" {' - - @staticmethod - def render(mono): - return ' fn {}{}{};'.format(mono.platform_prefix(), - mono.intrinsic_name(), - mono.intrinsic_signature()) - - @staticmethod - def close(): - return '}' - -class CompilerDefs(object): - def __init__(self): - pass - - @staticmethod - def open(platform): - return '''\ -// DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py -// ignore-tidy-linelength - -#![allow(unused_imports)] - -use {{Intrinsic, Type}}; -use IntrinsicDef::Named; - -pub fn find(name: &str) -> Option {{ - if !name.starts_with("{0}") {{ return None }} - Some(match &name["{0}".len()..] {{'''.format(platform.platform_prefix()) - - @staticmethod - def render(mono): - return '''\ - "{}" => Intrinsic {{ - inputs: {{ static INPUTS: [&'static Type; {}] = [{}]; &INPUTS }}, - output: {}, - definition: Named("{}") - }},'''.format(mono.intrinsic_set_name() + mono.intrinsic_suffix(), - len(mono._args_raw), - mono.compiler_args(), - mono.compiler_ret(), - mono.llvm_name()) - - @staticmethod - def close(): - return '''\ - _ => return None, - }) -}''' - -FORMATS = { - 'extern-block': ExternBlock(), - 'compiler-defs': CompilerDefs(), -} - - -def main(): - args = parse_args() - ins = args.in_ - out = args.out - out_format = FORMATS[args.format] - info = args.info - one_file_no_info = False - if len(ins) > 1 and info is None: - print('error: cannot have multiple inputs without an info header.', file=sys.stderr) - sys.exit(1) - - elif info is None: - info = ins[0] - one_file_no_info = True - info_json = json.load(info) - platform = PlatformInfo(info_json) - - print(out_format.open(platform), file=out) - - for in_ in ins: - - if one_file_no_info: - data = info_json - else: - data = json.load(in_) - data.update(info_json) - - intrinsics = IntrinsicSet(platform, data) - for intr in intrinsics.intrinsics(): - for mono in intr.monomorphise(): - print(out_format.render(mono), file=out) - - print(out_format.close(), file=out) - -if __name__ == '__main__': - main() diff --git a/src/etc/platform-intrinsics/hexagon/hvx_v60.json b/src/etc/platform-intrinsics/hexagon/hvx_v60.json deleted file mode 100644 index a1897e6bf6100..0000000000000 --- a/src/etc/platform-intrinsics/hexagon/hvx_v60.json +++ /dev/null @@ -1,1326 +0,0 @@ -{ - "platform": "Q6_", - "intrinsic_prefix": "", - "llvm_prefix": "llvm.hexagon.V6.", - "number_info": { - "signed": { - "kind": "s", - "data_type": { "8": "b", "16": "h", "32": "w" }, - "data_type_plain": { "8": "b", "16": "h", "32": "w" } - }, - "unsigned": { - "kind": "u", - "data_type": { "8": "ub", "16": "uh", "32": "uw" }, - "data_type_plain": { "8": "b", "16": "h", "32": "w" } - }, - "float": { - "kind": "f", - "data_type": { "8": "b", "16": "h", "32": "w" }, - "data_type_plain": { "8": "b", "16": "h", "32": "w" } - } - }, - "width_info": { - "64": { "width_b": "64", "width_suffix": "" }, - "128": { "width_b": "128", "width_suffix": ".128B" }, - "512": { "width_b": "64", "width_suffix": "" }, - "1024": { "widthd_b": "64", "width_b": "128", "width_suffix": ".128B", "widthd_suffix": "" }, - "2048": { "widthd_b": "128", "widthd_suffix": ".128B" } - }, - "intrinsics": [ - { - "intrinsic": "R_vextract{1.width_b}", - "width": [512, 1024], - "llvm": "extractw{1.width_suffix}", - "ret": "U32", - "args": ["u32", "U32"] - }, - { - "intrinsic": "V_lo{0.width_b}", - "width": [512, 1024], - "llvm": "lo{0.width_suffix}", - "ret": "u32", - "args": ["0d"] - }, - { - "intrinsic": "V_hi{0.width_b}", - "width": [512, 1024], - "llvm": "hi{0.width_suffix}", - "ret": "u32", - "args": ["0d"] - }, - { - "intrinsic": "V_vsplat_R{0.width_b}", - "width": [512, 1024], - "llvm": "lvsplat{1.data_type}{0.width_suffix}", - "ret": "u32", - "args": ["0S"] - }, - { - "intrinsic": "Q_and_QQ{0.width_b}", - "width": [64, 128], - "llvm": "pred.and{0.width_suffix}", - "ret": "u32", - "args": ["0", "0"] - }, - { - "intrinsic": "Q_not_Q{0.width_b}", - "width": [64, 128], - "llvm": "pred.not{0.width_suffix}", - "ret": "u32", - "args": ["0"] - }, - { - "intrinsic": "Q_or_QQ{0.width_b}", - "width": [64, 128], - "llvm": "pred.or{0.width_suffix}", - "ret": "u32", - "args": ["0", "0"] - }, - { - "intrinsic": "Q_xor_QQ{0.width_b}", - "width": [64, 128], - "llvm": "pred.xor{0.width_suffix}", - "ret": "u32", - "args": ["0", "0"] - }, - { - "intrinsic": "V{0.data_type}_vabsdiff_V{1.data_type}V{2.data_type}{0.width_b}", - "width": [512, 1024], - "llvm": "vabsdiff{1.data_type}{0.width_suffix}", - "ret": "u(8-16)", - "args": ["0", "0"] - }, - { - "intrinsic": "V{0.data_type}_vabsdiff_V{1.data_type}V{2.data_type}{0.width_b}", - "width": [512, 1024], - "llvm": "vabsdiff{1.data_type}{0.width_suffix}", - "ret": "u(16-32)", - "args": ["0s", "0s"] - }, - { - "intrinsic": "V{0.data_type}_vabs_V{1.data_type}{0.width_b}", - "width": [512, 1024], - "llvm": "vabs{1.data_type}{0.width_suffix}", - "ret": "s(16-32)", - "args": ["0"] - }, - { - "intrinsic": "V{0.data_type}_vabs_V{1.data_type}_sat{0.width_b}", - "width": [512, 1024], - "llvm": "vabs{1.data_type}.sat{0.width_suffix}", - "ret": "s(16-32)", - "args": ["0"] - }, - { - "intrinsic": "V{0.data_type}_vadd_V{1.data_type}V{2.data_type}{0.width_b}", - "width": [512, 1024], - "llvm": "vadd{0.data_type}{0.width_suffix}", - "ret": "s(8-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "V{0.data_type}_vadd_V{1.data_type}V{2.data_type}_sat{0.width_b}", - "width": [512, 1024], - "llvm": "vadd{0.data_type}sat{0.width_suffix}", - "ret": "s(16-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "V{0.data_type}_vadd_V{1.data_type}V{2.data_type}_sat{0.width_b}", - "width": [512, 1024], - "llvm": "vadd{0.data_type}sat{0.width_suffix}", - "ret": "u(8-16)", - "args": ["0", "0"] - }, - { - "intrinsic": "W{0.data_type}_vadd_W{1.data_type}W{2.data_type}{0.widthd_b}", - "width": [512, 1024], - "llvm": "vadd{0.data_type}.dv{0.widthd_suffix}", - "ret": "s(8-32)d", - "args": ["0", "0"] - }, - { - "intrinsic": "W{0.data_type}_vadd_W{1.data_type}W{2.data_type}_sat{0.widthd_b}", - "width": [512, 1024], - "llvm": "vadd{0.data_type}sat.dv{0.widthd_suffix}", - "ret": "s(16-32)d", - "args": ["0", "0"] - }, - { - "intrinsic": "W{0.data_type}_vadd_W{1.data_type}W{2.data_type}_sat{0.widthd_b}", - "width": [512, 1024], - "llvm": "vadd{0.data_type}sat.dv{0.widthd_suffix}", - "ret": "u(8-16)d", - "args": ["0", "0"] - }, - { - "intrinsic": "V_valign_VVR{0.width_b}", - "width": [512, 1024], - "llvm": "valignb{0.width_suffix}", - "ret": "u8", - "args": ["0", "0", "U32"] - }, - { - "intrinsic": "V_valign_VVI{0.width_b}", - "width": [512, 1024], - "llvm": "valignbi{0.width_suffix}", - "ret": "u8", - "args": ["0", "0", "U32"] - }, - { - "intrinsic": "V_vlalign_VVR{0.width_b}", - "width": [512, 1024], - "llvm": "vlalignb{0.width_suffix}", - "ret": "u8", - "args": ["0", "0", "U32"] - }, - { - "intrinsic": "V_vlalign_VVI{0.width_b}", - "width": [512, 1024], - "llvm": "vlalignbi{0.width_suffix}", - "ret": "u8", - "args": ["0", "0", "U32"] - }, - { - "intrinsic": "V_vand_VV{0.width_b}", - "width": [512, 1024], - "llvm": "vand{0.width_suffix}", - "ret": "u16", - "args": ["0", "0"] - }, - { - "intrinsic": "V_vand_QR{0.width_b}", - "width": [512, 1024], - "llvm": "vandqrt{0.width_suffix}", - "ret": "u8", - "args": ["u32hhh", "U32"] - }, - { - "intrinsic": "V_vandor_VQR{0.width_b}", - "width": [512, 1024], - "llvm": "vandqrt.acc{0.width_suffix}", - "ret": "u8", - "args": ["0", "u32hhh", "U32"] - }, - { - "intrinsic": "Q_vand_VR{0.width_b}", - "width": [512, 1024], - "llvm": "vandvrt{0.width_suffix}", - "ret": "u32hhh", - "args": ["u8", "U32"] - }, - { - "intrinsic": "Q_vandor_QVR{0.width_b}", - "width": [512, 1024], - "llvm": "vandvrt{0.width_suffix}", - "ret": "u32hhh", - "args": ["0", "u8", "U32"] - }, - { - "intrinsic": "V{0.data_type}_vasl_V{1.data_type}R{0.width_b}", - "width": [512, 1024], - "llvm": "vasl{0.data_type}{0.width_suffix}", - "ret": "s(16-32)", - "args": ["0", "U32"] - }, - { - "intrinsic": "V{0.data_type}_vasl_V{1.data_type}V{2.data_type}{0.width_b}", - "width": [512, 1024], - "llvm": "vasl{0.data_type}v{0.width_suffix}", - "ret": "s(16-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "V{0.data_type}_vaslacc_V{1.data_type}V{2.data_type}R{0.width_b}", - "width": [512, 1024], - "llvm": "vasl{0.data_type}.acc{0.width_suffix}", - "ret": "s32", - "args": ["0", "0", "U32"] - }, - { - "intrinsic": "V{0.data_type}_vasr_V{1.data_type}R{0.width_b}", - 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"ret": "u16", - "args": ["0", "0"] - } - ] -} diff --git a/src/etc/platform-intrinsics/nvptx/cuda.json b/src/etc/platform-intrinsics/nvptx/cuda.json deleted file mode 100644 index 1beaaeb5d8718..0000000000000 --- a/src/etc/platform-intrinsics/nvptx/cuda.json +++ /dev/null @@ -1,13 +0,0 @@ -{ - "intrinsic_prefix": "_", - "llvm_prefix": "llvm.cuda.", - "intrinsics": [ - { - "intrinsic": "syncthreads", - "width": ["0"], - "llvm": "syncthreads", - "ret": "V", - "args": [] - } - ] -} diff --git a/src/etc/platform-intrinsics/nvptx/info.json b/src/etc/platform-intrinsics/nvptx/info.json deleted file mode 100644 index 80332c54e0414..0000000000000 --- a/src/etc/platform-intrinsics/nvptx/info.json +++ /dev/null @@ -1,7 +0,0 @@ -{ - "platform": "nvptx", - "number_info": { - "signed": {} - }, - "width_info": {} -} diff --git a/src/etc/platform-intrinsics/nvptx/sreg.json b/src/etc/platform-intrinsics/nvptx/sreg.json deleted file mode 100644 index 33d97f2694699..0000000000000 --- a/src/etc/platform-intrinsics/nvptx/sreg.json +++ /dev/null @@ -1,90 +0,0 @@ -{ - "intrinsic_prefix": "_", - "llvm_prefix": "llvm.nvvm.read.ptx.sreg.", - "intrinsics": [ - { - "intrinsic": "block_dim_x", - "width": ["0"], - "llvm": "ntid.x", - "ret": "S32", - "args": [] - }, - { - "intrinsic": "block_dim_y", - "width": ["0"], - "llvm": "ntid.y", - "ret": "S32", - "args": [] - }, - { - "intrinsic": "block_dim_z", - "width": ["0"], - "llvm": "ntid.z", - "ret": "S32", - "args": [] - }, - { - "intrinsic": "block_idx_x", - "width": ["0"], - "llvm": "ctaid.x", - "ret": "S32", - "args": [] - }, - { - "intrinsic": "block_idx_y", - "width": ["0"], - "llvm": "ctaid.y", - "ret": "S32", - "args": [] - }, - { - "intrinsic": "block_idx_z", - "width": ["0"], - "llvm": "ctaid.z", - "ret": "S32", - "args": [] - }, - { - "intrinsic": "grid_dim_x", - "width": ["0"], - "llvm": "nctaid.x", - "ret": "S32", - "args": [] - }, - { - "intrinsic": "grid_dim_y", - "width": ["0"], - "llvm": "nctaid.y", - "ret": "S32", - "args": [] - }, - { - "intrinsic": "grid_dim_z", - "width": ["0"], - "llvm": "nctaid.z", - "ret": "S32", - "args": [] - }, - { - "intrinsic": "thread_idx_x", - "width": ["0"], - "llvm": "tid.x", - "ret": "S32", - "args": [] - }, - { - "intrinsic": "thread_idx_y", - "width": ["0"], - "llvm": "tid.y", - "ret": "S32", - "args": [] - }, - { - "intrinsic": "thread_idx_z", - "width": ["0"], - "llvm": "tid.z", - "ret": "S32", - "args": [] - } - ] -} diff --git a/src/etc/platform-intrinsics/powerpc.json b/src/etc/platform-intrinsics/powerpc.json deleted file mode 100644 index acb6813887c5c..0000000000000 --- a/src/etc/platform-intrinsics/powerpc.json +++ /dev/null @@ -1,294 +0,0 @@ -{ - "platform": "powerpc", - "intrinsic_prefix": "_vec_", - "llvm_prefix": "llvm.ppc.altivec.", - "number_info": { - "unsigned": { - "kind" : "u", - "data_type_short": { "8": "b", "16": "h", "32": "w", "64": "d" } - }, - "signed": { - "kind" : "s", - "data_type_short": { "8": "b", "16": "h", "32": "w", "64": "d" } - }, - "float": {} - }, - "width_info": { - "128": { "width": "" } - }, - "intrinsics": [ - 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"ret": "f32", - "args": ["0"] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/avx.json b/src/etc/platform-intrinsics/x86/avx.json deleted file mode 100644 index 1f41e2ecf3e6d..0000000000000 --- a/src/etc/platform-intrinsics/x86/avx.json +++ /dev/null @@ -1,272 +0,0 @@ -{ - "intrinsic_prefix": "_mm", - "llvm_prefix": "llvm.x86.avx.", - "intrinsics": [ - { - "intrinsic": "256_addsub_{0.data_type}", - "width": [256], - "llvm": "addsub.{0.data_type}.256", - "ret": "f(32-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "256_blendv_{0.data_type}", - "width": [256], - "llvm": "blendv.{0.data_type}.256", - "ret": "f(32-64)", - "args": ["0", "0", "0"] - }, - { - "intrinsic": "256_broadcast_{0.data_type}", - "width": [256], - "llvm": "vbroadcastf128.{0.data_type}.256", - "ret": "f(32-64)", - "args": ["s8SPc"] - }, - { - "intrinsic": "256_cmp_{0.data_type}", - "width": [256], - "llvm": "cmp.{1.data_type}.256", - "ret": "f(32-64)", - "args": ["0", "0", "s8S"] - }, - { - "intrinsic": "256_cvtepi32_pd", - "width": [256], - "llvm": "cvtdq2.pd.256", - "ret": "f64", - "args": ["s32h"] - }, - { - "intrinsic": "256_cvtepi32_ps", - "width": [256], - "llvm": "cvtdq2.ps.256", - "ret": "f32", - "args": ["s32"] - }, - { - "intrinsic": "256_cvtpd_epi32", - "width": [256], - "llvm": "cvt.pd2dq.256", - "ret": "s32h", - "args": ["f64"] - }, - { - "intrinsic": "256_cvtpd_ps", - "width": [256], - "llvm": "cvt.pd2.ps.256", - "ret": "f32h", - "args": ["f64"] - }, - { - "intrinsic": "256_cvtps_epi32", - "width": [256], - "llvm": "cvt.ps2dq.256", - "ret": "s32", - "args": ["f32"] - }, - { - "intrinsic": "256_cvtps_pd", - "width": [256], - "llvm": "cvt.ps2.pd.256", - "ret": "f64", - "args": ["f32h"] - }, - { - "intrinsic": "256_cvttpd_epi32", - "width": [256], - "llvm": "cvtt.pd2dq.256", - "ret": "s32h", - "args": ["f64"] - }, - { - "intrinsic": "256_cvttps_epi32", - "width": [256], - "llvm": "cvtt.ps2dq.256", - "ret": "s32", - "args": ["f32"] - }, - { - "intrinsic": "256_dp_ps", - "width": [256], - "llvm": "dp.ps.256", - "ret": "f32", - "args": ["0", "0", "S32/8"] - }, - { - "intrinsic": "256_hadd_{0.data_type}", - "width": [256], - "llvm": "hadd.{0.data_type}.256", - "ret": "f(32-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "256_hsub_{0.data_type}", - "width": [256], - "llvm": "hsub.{0.data_type}.256", - "ret": "f(32-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "256_max_{0.data_type}", - "width": [256], - "llvm": "max.{0.data_type}.256", - "ret": "f(32-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "{0.width_mm}_maskload_{0.data_type}", - "width": [128, 256], - "llvm": "maskload.{0.data_type_short}{0.width_suffix}", - "ret": ["f(32-64)"], - "args": ["0SPc/S8", "0s->0"] - }, - { - "intrinsic": "{3.width_mm}_maskstore_{3.data_type}", - "width": [128, 256], - "llvm": "maskstore.{3.data_type_short}{3.width_suffix}", - "ret": "V", - "args": ["F(32-64)Pm/S8", "1Dsv->1Dv", "1Dv"] - }, - { - "intrinsic": "256_min_{0.data_type}", - "width": [256], - "llvm": "min.{0.data_type}.256", - "ret": "f(32-64)", - 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"width": [128, 256], - "llvm": "vtestz.ps{1.width_suffix}", - "ret": "S32", - "args": ["f32", "f32"] - }, - { - "intrinsic": "{1.width_mm}_testz_pd", - "width": [128, 256], - "llvm": "vtestz.pd{1.width_suffix}", - "ret": "S32", - "args": ["f64", "f64"] - }, - { - "intrinsic": "256_testz_si256", - "width": [256], - "llvm": "ptestz.256", - "ret": "S32", - "args": ["u64", "u64"] - }, - { - "intrinsic": "256_zeroall", - "width": [256], - "llvm": "vzeroall", - "ret": "V", - "args": [] - }, - { - "intrinsic": "256_zeroupper", - "width": [256], - "llvm": "vzeroupper", - "ret": "V", - "args": [] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/avx2.json b/src/etc/platform-intrinsics/x86/avx2.json deleted file mode 100644 index dc055b583c568..0000000000000 --- a/src/etc/platform-intrinsics/x86/avx2.json +++ /dev/null @@ -1,202 +0,0 @@ -{ - "intrinsic_prefix": "_mm", - "llvm_prefix": "llvm.x86.avx2.", - "intrinsics": [ - { - "intrinsic": "256_abs_{0.data_type}", - "width": [256], - "llvm": "pabs.{0.data_type_short}", - "ret": "s(8-32)", - "args": ["0"] - }, - { - "intrinsic": "256_adds_{0.data_type}", - "width": [256], - "llvm": "padd{0.kind_short}s.{0.data_type_short}", - "ret": "i(8-16)", - "args": ["0", "0"] - }, - { - "intrinsic": "256_avg_{0.data_type}", - "width": [256], - "llvm": "pavg.{0.data_type_short}", - "ret": "u(8-16)", - "args": ["0", "0"] - }, - { - "intrinsic": "256_hadd_{0.data_type}", - "width": [256], - "llvm": "phadd.{0.data_type_short}", - "ret": "s(16-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "256_hadds_epi16", - "width": [256], - "llvm": "phadd.sw", - "ret": "s16", - "args": ["0", "0"] - }, - { - "intrinsic": "256_hsub_{0.data_type}", - "width": [256], - "llvm": "phsub.{0.data_type_short}", - "ret": "s(16-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "256_hsubs_epi16", - "width": [256], - "llvm": "phsub.sw", - "ret": "s16", - "args": ["0", "0"] - }, - { - "intrinsic": "256_madd_epi16", - "width": [256], - "llvm": "pmadd.wd", - "ret": "s32", - "args": ["s16", "s16"] - }, - { - "intrinsic": "256_maddubs_epi16", - "width": [256], - "llvm": "pmadd.ub.sw", - "ret": "s16", - "args": ["s8", "s8"] - }, - { - "intrinsic": "{0.width_mm}_mask_i32gather_{0.data_type}", - "width": [128, 256], - "llvm": "gather.d.{0.data_type_short}{0.width_suffix}", - "ret": ["s32", "f32"], - "args": ["0", "0SPc/S8", "s32", "0s->0", "S32/8"] - }, - { - "intrinsic": "{0.width_mm}_mask_i32gather_{0.data_type}", - "width": [128, 256], - "llvm": "gather.d.{0.data_type_short}{0.width_suffix}", - "ret": ["s64", "f64"], - "args": ["0", "0SPc/S8", "s32x128", "0s->0", "S32/8"] - }, - { - "intrinsic": "{3.width_mm}_mask_i64gather_{0.data_type}", - "width": [128, 256], - "llvm": "gather.q.{0.data_type_short}{0.width_suffix}", - "ret": ["s32x128", "f32x128"], - "args": ["0", "0SPc/S8", "s64", "0s->0", "S32/8"] - }, - { - "intrinsic": "{0.width_mm}_mask_i64gather_{0.data_type}", - "width": [128, 256], - "llvm": "gather.q.{0.data_type_short}{0.width_suffix}", - "ret": ["s64", "f64"], - "args": ["0", "0SPc/S8", "s64", "0s->0", "S32/8"] - }, - { - "intrinsic": "{0.width_mm}_maskload_{0.data_type}", - "width": [128, 256], - "llvm": "maskload.{0.data_type_short}{0.width_suffix}", - "ret": ["s(32-64)"], - "args": ["0Pc/S8", "0"] - }, - { - "intrinsic": "{2.width_mm}_maskstore_{2.data_type}", - "width": [128, 256], - "llvm": "maskstore.{2.data_type_short}{2.width_suffix}", - "ret": "V", - "args": ["S(32-64)Pm/S8", "1Dv", "2"] - }, - { - "intrinsic": "256_max_{0.data_type}", - "width": [256], - "llvm": "pmax{0.kind}.{0.data_type_short}", - "ret": "i(8-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "256_min_{0.data_type}", - "width": [256], - "llvm": "pmin{0.kind}.{0.data_type_short}", - "ret": "i(8-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "256_movemask_epi8", - "width": [256], - "llvm": "pmovmskb", - "ret": "S32", - "args": ["s8"] - }, - { - "intrinsic": "256_mpsadbw_epu8", - "width": [256], - "llvm": "mpsadbw", - "ret": "u16", - "args": ["u8", "u8", "S32/8"] - }, - { - "intrinsic": "256_mul_{0.data_type}", - "width": [256], - "llvm": "pmul{0.data_type_short}.dq", - "ret": "i64", - "args": ["0dn", "0dn"] - }, - { - "intrinsic": "256_mulhi_{0.data_type}", - "width": [256], - "llvm": "pmulh{0.data_type_short}.w", - "ret": "i16", - "args": ["0", "0"] - }, - { - "intrinsic": "256_mulhrs_epi16", - "width": [256], - "llvm": "pmul.hr.sw", - "ret": "s16", - "args": ["0", "0"] - }, - { - "intrinsic": "256_pack{0.kind_short}s_{1.data_type}", - "width": [256], - "llvm": "pack{0.kind}s{1.data_type_short}{0.data_type_short}", - "ret": "i(8-16)", - "args": ["0hws", "0hws"] - }, - { - "intrinsic": "256_permutevar8x32_{0.data_type}", - "width": [256], - "llvm": "perm{0.data_type_short}", - "ret": ["s32", "f32"], - "args": ["0", "0s"] - }, - { - "intrinsic": "256_sad_epu8", - "width": [256], - "llvm": "psad.bw", - "ret": "u64", - "args": ["0", "0"] - }, - { - "intrinsic": "256_shuffle_epi8", - "width": [256], - "llvm": "pshuf.b", - "ret": "s8", - "args": ["0", "0"] - }, - { - "intrinsic": "256_sign_{0.data_type}", - "width": [256], - "llvm": "psign.{0.data_type_short}", - "ret": "s(8-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "256_subs_{0.data_type}", - "width": [256], - "llvm": "psub{0.kind_short}s.{0.data_type_short}", - "ret": "i(8-16)", - "args": ["0", "0"] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/bmi.json b/src/etc/platform-intrinsics/x86/bmi.json deleted file mode 100644 index 24e2cbcf8aad1..0000000000000 --- a/src/etc/platform-intrinsics/x86/bmi.json +++ /dev/null @@ -1,13 +0,0 @@ -{ - "intrinsic_prefix": "_bmi", - "llvm_prefix": "llvm.x86.bmi.", - "intrinsics": [ - { - "intrinsic": "_bextr_{0.bitwidth}", - "width": ["0"], - "llvm": "bextr.{0.bitwidth}", - "ret": "S(32-64)u", - "args": ["0", "0"] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/bmi2.json b/src/etc/platform-intrinsics/x86/bmi2.json deleted file mode 100644 index f5a0db5ef51da..0000000000000 --- a/src/etc/platform-intrinsics/x86/bmi2.json +++ /dev/null @@ -1,27 +0,0 @@ -{ - "intrinsic_prefix": "_bmi2", - "llvm_prefix": "llvm.x86.bmi.", - "intrinsics": [ - { - "intrinsic": "_bzhi_{0.bitwidth}", - "width": ["0"], - "llvm": "bzhi.{0.bitwidth}", - "ret": "S(32-64)u", - "args": ["0", "0"] - }, - { - "intrinsic": "_pdep_{0.bitwidth}", - "width": ["0"], - "llvm": "pdep.{0.bitwidth}", - "ret": "S(32-64)u", - "args": ["0", "0"] - }, - { - "intrinsic": "_pext_{0.bitwidth}", - "width": ["0"], - "llvm": "pext.{0.bitwidth}", - "ret": "S(32-64)u", - "args": ["0", "0"] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/fma.json b/src/etc/platform-intrinsics/x86/fma.json deleted file mode 100644 index dcc26cd501c9b..0000000000000 --- a/src/etc/platform-intrinsics/x86/fma.json +++ /dev/null @@ -1,48 +0,0 @@ -{ - "intrinsic_prefix": "_mm", - "llvm_prefix": "llvm.x86.fma.", - "intrinsics": [ - { - "intrinsic": "{0.width_mm}_fmadd_{0.data_type}", - "width": [128, 256], - "llvm": "vfmadd.{0.data_type_short}{0.width_suffix}", - "ret": "f(32-64)", - "args": ["0", "0", "0"] - }, - { - "intrinsic": "{0.width_mm}_fmaddsub_{0.data_type}", - "width": [128, 256], - "llvm": "vfmaddsub.{0.data_type_short}{0.width_suffix}", - "ret": "f(32-64)", - "args": ["0", "0", "0"] - }, - { - "intrinsic": "{0.width_mm}_fmsub_{0.data_type}", - "width": [128, 256], - "llvm": "vfmsub.{0.data_type_short}{0.width_suffix}", - "ret": "f(32-64)", - "args": ["0", "0", "0"] - }, - { - "intrinsic": "{0.width_mm}_fmsubadd_{0.data_type}", - "width": [128, 256], - "llvm": "vfmsubadd.{0.data_type_short}{0.width_suffix}", - "ret": "f(32-64)", - "args": ["0", "0", "0"] - }, - { - "intrinsic": "{0.width_mm}_fnmadd_{0.data_type}", - "width": [128, 256], - "llvm": "vfnmadd.{0.data_type_short}{0.width_suffix}", - "ret": "f(32-64)", - "args": ["0", "0", "0"] - }, - { - "intrinsic": "{0.width_mm}_fnmsub_{0.data_type}", - "width": [128, 256], - "llvm": "vfnmsub.{0.data_type_short}{0.width_suffix}", - "ret": "f(32-64)", - "args": ["0", "0", "0"] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/info.json b/src/etc/platform-intrinsics/x86/info.json deleted file mode 100644 index 8e90b8579c49e..0000000000000 --- a/src/etc/platform-intrinsics/x86/info.json +++ /dev/null @@ -1,32 +0,0 @@ -{ - "platform": "x86", - "number_info": { - "signed": { - "kind": "s", - "kind_short": "", - "data_type": { "pattern": "epi{bitwidth}" }, - "bitwidth": { "pattern": "{bitwidth}" }, - "data_type_short": { "8": "b", "16": "w", "32": "d", "64": "q" } - }, - "unsigned": { - "kind": "u", - "kind_short": "u", - "data_type": { "pattern": "epu{bitwidth}" }, - "bitwidth": { "pattern": "{bitwidth}" }, - "data_type_short": { "8": "b", "16": "w", "32": "d", "64": "q" } - }, - "float": { - "kind": "f", - "data_type": { "32": "ps", "64": "pd" }, - "bitwidth": { "pattern": "{bitwidth}" }, - "data_type_short": { "32": "ps", "64": "pd" } - } - }, - "width_info": { - "32": { "width_mm": "32", "width_suffix": "" }, - "64": { "width_mm": "64", "width_suffix": "" }, - "128": { "width_mm": "", "width_suffix": "" }, - "256": { "width_mm": "256", "width_suffix": ".256" }, - "512": { "width_mm": "512", "width_suffix": ".512" } - } -} diff --git a/src/etc/platform-intrinsics/x86/rdrand.json b/src/etc/platform-intrinsics/x86/rdrand.json deleted file mode 100644 index fa2feb4224b9f..0000000000000 --- a/src/etc/platform-intrinsics/x86/rdrand.json +++ /dev/null @@ -1,27 +0,0 @@ -{ - "intrinsic_prefix": "_rdrand", - "llvm_prefix": "llvm.x86.rdrand.", - "intrinsics": [ - { - "intrinsic": "16_step", - "width": ["0"], - "llvm": "16", - "ret": "(U16,S32)", - "args": [] - }, - { - "intrinsic": "32_step", - "width": ["0"], - "llvm": "32", - "ret": "(U32,S32)", - "args": [] - }, - { - "intrinsic": "64_step", - "width": ["0"], - "llvm": "64", - "ret": "(U64,S32)", - "args": [] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/rdseed.json b/src/etc/platform-intrinsics/x86/rdseed.json deleted file mode 100644 index 7be64b583e0ac..0000000000000 --- a/src/etc/platform-intrinsics/x86/rdseed.json +++ /dev/null @@ -1,27 +0,0 @@ -{ - "intrinsic_prefix": "_rdseed", - "llvm_prefix": "llvm.x86.rdseed.", - "intrinsics": [ - { - "intrinsic": "16_step", - "width": ["0"], - "llvm": "16", - "ret": "(U16,S32)", - "args": [] - }, - { - "intrinsic": "32_step", - "width": ["0"], - "llvm": "32", - "ret": "(U32,S32)", - "args": [] - }, - { - "intrinsic": "64_step", - "width": ["0"], - "llvm": "64", - "ret": "(U64,S32)", - "args": [] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/sse.json b/src/etc/platform-intrinsics/x86/sse.json deleted file mode 100644 index d8eef8a3514ae..0000000000000 --- a/src/etc/platform-intrinsics/x86/sse.json +++ /dev/null @@ -1,55 +0,0 @@ -{ - "intrinsic_prefix": "_mm", - "llvm_prefix": "llvm.x86.sse.", - "intrinsics": [ - { - "intrinsic": "_movemask_ps", - "width": [128], - "llvm": "movmsk.ps", - "ret": "S32", - "args": ["f32"] - }, - { - "intrinsic": "_max_ps", - "width": [128], - "llvm": "max.ps", - "ret": "f32", - "args": ["0", "0"] - }, - { - "intrinsic": "_min_ps", - "width": [128], - "llvm": "min.ps", - "ret": "f32", - "args": ["0", "0"] - }, - { - "intrinsic": "_rsqrt_ps", - "width": [128], - "llvm": "rsqrt.ps", - "ret": "f32", - "args": ["0"] - }, - { - "intrinsic": "_rcp_ps", - "width": [128], - "llvm": "rcp.ps", - "ret": "f32", - "args": ["0"] - }, - { - "intrinsic": "_sqrt_ps", - "width": [128], - "llvm": "!llvm.sqrt.v4f32", - "ret": "f32", - "args": ["0"] - }, - { - "intrinsic": "_storeu_ps", - "width": [128], - "llvm": "storeu.ps", - "ret": "V", - "args": ["F32Pm/S8", "f32"] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/sse2.json b/src/etc/platform-intrinsics/x86/sse2.json deleted file mode 100644 index 4d6317d80a57e..0000000000000 --- a/src/etc/platform-intrinsics/x86/sse2.json +++ /dev/null @@ -1,160 +0,0 @@ -{ - "intrinsic_prefix": "_mm", - "llvm_prefix": "llvm.x86.sse2.", - "intrinsics": [ - { - "intrinsic": "_adds_{0.data_type}", - "width": [128], - "llvm": "padd{0.kind_short}s.{0.data_type_short}", - "ret": "i(8-16)", - "args": ["0", "0"] - }, - { - "intrinsic": "_avg_{0.data_type}", - "width": [128], - "llvm": "pavg.{0.data_type_short}", - "ret": "u(8-16)", - "args": ["0", "0"] - }, - { - "intrinsic": "_lfence", - "width": [128], - "llvm": "lfence", - "ret": "V", - "args": [] - }, - { - "intrinsic": "_madd_epi16", - "width": [128], - "llvm": "pmadd.wd", - "ret": "s32", - "args": ["s16", "s16"] - }, - { - "intrinsic": "_maskmoveu_si128", - "width": [128], - "llvm": "maskmov.dqu", - "ret": "V", - "args": ["u8", "u8", "U8Pm"] - }, - { - "intrinsic": "_max_{0.data_type}", - "width": [128], - "llvm": "pmax{0.kind}.{0.data_type_short}", - "ret": ["s16", "u8"], - "args": ["0", "0"] - }, - { - "intrinsic": "_max_pd", - "width": [128], - "llvm": "max.pd", - "ret": "f64", - "args": ["0", "0"] - }, - { - "intrinsic": "_mfence", - "width": [128], - "llvm": "fence", - "ret": "V", - "args": [] - }, - { - "intrinsic": "_min_{0.data_type}", - "width": [128], - "llvm": "pmin{0.kind}.{0.data_type_short}", - "ret": ["s16", "u8"], - "args": ["0", "0"] - }, - { - "intrinsic": "_min_pd", - "width": [128], - "llvm": "min.pd", - "ret": "f64", - "args": ["0", "0"] - }, - { - "intrinsic": "_movemask_pd", - "width": [128], - "llvm": "movmsk.pd", - "ret": "S32", - "args": ["f64"] - }, - { - "intrinsic": "_movemask_epi8", - "width": [128], - "llvm": "pmovmskb.128", - "ret": "S32", - "args": ["s8"] - }, - { - "intrinsic": "_mul_epu32", - "width": [128], - "llvm": "pmulu.dq", - "ret": "u64", - "args": ["0dn", "0dn"] - }, - { - "intrinsic": "_mulhi_{0.data_type}", - "width": [128], - "llvm": "pmulh{0.kind_short}.w", - "ret": "i16", - "args": ["0", "0"] - }, - { - "intrinsic": "_packs_{1.data_type}", - "width": [128], - "llvm": "packss{1.data_type_short}{0.data_type_short}.128", - "ret": "s(8-16)", - "args": ["0hw", "0hw"] - }, - { - "intrinsic": "_packus_epi16", - "width": [128], - "llvm": "packuswb.128", - "ret": "u8", - "args": ["s16", "s16"] - }, - { - "intrinsic": "_sad_epu8", - "width": [128], - "llvm": "psad.bw", - "ret": "u64", - "args": ["u8", "u8"] - }, - { - "intrinsic": "_sfence", - "width": [128], - "llvm": "sfence", - "ret": "V", - "args": [] - }, - { - "intrinsic": "_sqrt_pd", - "width": [128], - "llvm": "!llvm.sqrt.v2f64", - "ret": "f64", - "args": ["0"] - }, - { - "intrinsic": "_storeu_pd", - "width": [128], - "llvm": "storeu.pd", - "ret": "V", - "args": ["F64Pm/U8", "f64"] - }, - { - "intrinsic": "_storeu_si128", - "width": [128], - "llvm": "storeu.dq", - "ret": "V", - "args": ["u8Pm/U8", "u8"] - }, - { - "intrinsic": "_subs_{0.data_type}", - "width": [128], - "llvm": "psub{0.kind_short}s.{0.data_type_short}", - "ret": "i(8-16)", - "args": ["0", "0"] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/sse3.json b/src/etc/platform-intrinsics/x86/sse3.json deleted file mode 100644 index 119bf208f7e34..0000000000000 --- a/src/etc/platform-intrinsics/x86/sse3.json +++ /dev/null @@ -1,34 +0,0 @@ -{ - "intrinsic_prefix": "_mm", - "llvm_prefix": "llvm.x86.sse3.", - "intrinsics": [ - { - "intrinsic": "_addsub_{0.data_type}", - "width": [128], - "llvm": "addsub.{0.data_type}", - "ret": "f(32-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "_hadd_{0.data_type}", - "width": [128], - "llvm": "hadd.{0.data_type}", - "ret": "f(32-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "_hsub_{0.data_type}", - "width": [128], - "llvm": "hsub.{0.data_type}", - "ret": "f(32-64)", - "args": ["0", "0"] - }, - { - "intrinsic": "_lddqu_si128", - "width": [128], - "llvm": "ldu.dq", - "ret": "u8", - "args": ["0Pc/S8"] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/sse41.json b/src/etc/platform-intrinsics/x86/sse41.json deleted file mode 100644 index b499637e0d3c6..0000000000000 --- a/src/etc/platform-intrinsics/x86/sse41.json +++ /dev/null @@ -1,76 +0,0 @@ -{ - "intrinsic_prefix": "_mm", - "llvm_prefix": "llvm.x86.sse41.", - "intrinsics": [ - { - "intrinsic": "_dp_{0.data_type}", - "width": [128], - "llvm": "dp{0.data_type}", - "ret": "f(32-64)", - "args": ["0", "0", "S32/8"] - }, - { - "intrinsic": "_max_{0.data_type}", - "width": [128], - "llvm": "pmax{0.kind}{0.data_type_short}", - "ret": ["s8", "u16", "i32"], - "args": ["0", "0"] - }, - { - "intrinsic": "_min_{0.data_type}", - "width": [128], - "llvm": "pmin{0.kind}{0.data_type_short}", - "ret": ["s8", "u16", "i32"], - "args": ["0", "0"] - }, - { - "intrinsic": "_minpos_epu16", - "width": [128], - "llvm": "phminposuw", - "ret": "u16", - "args": ["0"] - }, - { - "intrinsic": "_mpsadbw_epu8", - "width": [128], - "llvm": "mpsadbw", - "ret": "u16", - "args": ["u8", "u8", "S32/8"] - }, - { - "intrinsic": "_mul_epi32", - "width": [128], - "llvm": "pmuldq", - "ret": "s64", - "args": ["s32", "s32"] - }, - { - "intrinsic": "_packus_epi32", - "width": [128], - "llvm": "packusdw", - "ret": "u16", - "args": ["s32", "s32"] - }, - { - "intrinsic": "_testc_si128", - "width": [128], - "llvm": "ptestc", - "ret": "S32", - "args": ["u64", "u64"] - }, - { - "intrinsic": "_testnzc_si128", - "width": [128], - "llvm": "ptestnzc", - "ret": "S32", - "args": ["u64", "u64"] - }, - { - "intrinsic": "_testz_si128", - "width": [128], - "llvm": "ptestz", - "ret": "S32", - "args": ["u64", "u64"] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/sse42.json b/src/etc/platform-intrinsics/x86/sse42.json deleted file mode 100644 index fdee9c8a6671b..0000000000000 --- a/src/etc/platform-intrinsics/x86/sse42.json +++ /dev/null @@ -1,104 +0,0 @@ -{ - "intrinsic_prefix": "_mm", - "llvm_prefix": "llvm.x86.sse42.", - "intrinsics": [ - { - "intrinsic": "_cmpestra", - "width": [128], - "llvm": "pcmpestria128", - "ret": "S32", - "args": ["s8", "S32", "s8", "S32", "S32/8"] - }, - { - "intrinsic": "_cmpestrc", - "width": [128], - "llvm": "pcmpestric128", - "ret": "S32", - "args": ["s8", "S32", "s8", "S32", "S32/8"] - }, - { - "intrinsic": "_cmpestri", - "width": [128], - "llvm": "pcmpestri128", - "ret": "S32", - "args": ["s8", "S32", "s8", "S32", "S32/8"] - }, - { - "intrinsic": "_cmpestrm", - "width": [128], - "llvm": "pcmpestrm128", - "ret": "s8", - "args": ["s8", "S32", "s8", "S32", "S32/8"] - }, - { - "intrinsic": "_cmpestro", - "width": [128], - "llvm": "pcmpestrio128", - "ret": "S32", - "args": ["s8", "S32", "s8", "S32", "S32/8"] - }, - { - "intrinsic": "_cmpestrs", - "width": [128], - "llvm": "pcmpestris128", - "ret": "S32", - "args": ["s8", "S32", "s8", "S32", "S32/8"] - }, - { - "intrinsic": "_cmpestrz", - "width": [128], - "llvm": "pcmpestriz128", - "ret": "S32", - "args": ["s8", "S32", "s8", "S32", "S32/8"] - }, - { - "intrinsic": "_cmpistra", - "width": [128], - "llvm": "pcmpistria128", - "ret": "S32", - "args": ["s8", "s8", "S32/8"] - }, - { - "intrinsic": "_cmpistrc", - "width": [128], - "llvm": "pcmpistric128", - "ret": "S32", - "args": ["s8", "s8", "S32/8"] - }, - { - "intrinsic": "_cmpistri", - "width": [128], - "llvm": "pcmpistri128", - "ret": "S32", - "args": ["s8", "s8", "S32/8"] - }, - { - "intrinsic": "_cmpistrm", - "width": [128], - "llvm": "pcmpistrm128", - "ret": "s8", - "args": ["s8", "s8", "S32/8"] - }, - { - "intrinsic": "_cmpistro", - "width": [128], - "llvm": "pcmpistrio128", - "ret": "S32", - "args": ["s8", "s8", "S32/8"] - }, - { - "intrinsic": "_cmpistrs", - "width": [128], - "llvm": "pcmpistris128", - "ret": "S32", - "args": ["s8", "s8", "S32/8"] - }, - { - "intrinsic": "_cmpistrz", - "width": [128], - "llvm": "pcmpistriz128", - "ret": "S32", - "args": ["s8", "s8", "S32/8"] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/ssse3.json b/src/etc/platform-intrinsics/x86/ssse3.json deleted file mode 100644 index 5a5617957b3e5..0000000000000 --- a/src/etc/platform-intrinsics/x86/ssse3.json +++ /dev/null @@ -1,69 +0,0 @@ -{ - "intrinsic_prefix": "_mm", - "llvm_prefix": "llvm.x86.ssse3.", - "intrinsics": [ - { - "intrinsic": "_abs_{0.data_type}", - "width": [128], - "llvm": "pabs.{0.data_type_short}.128", - "ret": "s(8-32)", - "args": ["0"] - }, - { - "intrinsic": "_hadd_{0.data_type}", - "width": [128], - "llvm": "phadd.{0.data_type_short}.128", - "ret": "s(16-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "_hadds_epi16", - "width": [128], - "llvm": "phadd.sw.128", - "ret": "s16", - "args": ["0", "0"] - }, - { - "intrinsic": "_hsub_{0.data_type}", - "width": [128], - "llvm": "phsub.{0.data_type_short}.128", - "ret": "s(16-32)", - "args": ["0", "0"] - }, - { - "intrinsic": "_hsubs_epi16", - "width": [128], - "llvm": "phsub.sw.128", - "ret": "s16", - "args": ["0", "0"] - }, - { - "intrinsic": "_maddubs_epi16", - "width": [128], - "llvm": "pmadd.ub.sw.128", - "ret": "s16", - "args": ["u8", "s8"] - }, - { - "intrinsic": "_mulhrs_epi16", - "width": [128], - "llvm": "pmul.hr.sw.128", - "ret": "s16", - "args": ["s16", "s16"] - }, - { - "intrinsic": "_shuffle_epi8", - "width": [128], - "llvm": "pshuf.b.128", - "ret": "s8", - "args": ["s8", "s8"] - }, - { - "intrinsic": "_sign_{0.data_type}", - "width": [128], - "llvm": "psign.{0.data_type_short}.128", - "ret": "s(8-32)", - "args": ["0", "0"] - } - ] -} diff --git a/src/etc/platform-intrinsics/x86/tbm.json b/src/etc/platform-intrinsics/x86/tbm.json deleted file mode 100644 index d1322cd60c4cf..0000000000000 --- a/src/etc/platform-intrinsics/x86/tbm.json +++ /dev/null @@ -1,13 +0,0 @@ -{ - "intrinsic_prefix": "_tbm", - "llvm_prefix": "llvm.x86.tbm.", - "intrinsics": [ - { - "intrinsic": "_bextri_u{0.bitwidth}", - "width": ["0"], - "llvm": "bextri.u{0.bitwidth}", - "ret": "S(32-64)u", - "args": ["0", "0"] - } - ] -} diff --git a/src/librustc_codegen_llvm/intrinsic.rs b/src/librustc_codegen_llvm/intrinsic.rs index f5680b295477a..eeb6a64164e9c 100644 --- a/src/librustc_codegen_llvm/intrinsic.rs +++ b/src/librustc_codegen_llvm/intrinsic.rs @@ -1,7 +1,6 @@ #![allow(non_upper_case_globals)] use attributes; -use intrinsics::{self, Intrinsic}; use llvm; use llvm_util; use abi::{Abi, FnType, LlvmType, PassMode}; @@ -658,142 +657,7 @@ impl IntrinsicCallMethods<'tcx> for Builder<'a, 'll, 'tcx> { return; } - _ => { - let intr = match Intrinsic::find(&name) { - Some(intr) => intr, - None => bug!("unknown intrinsic '{}'", name), - }; - fn one(x: Vec) -> T { - assert_eq!(x.len(), 1); - x.into_iter().next().unwrap() - } - fn ty_to_type<'ll>( - cx: &CodegenCx<'ll, '_>, - t: &intrinsics::Type - ) -> Vec<&'ll Type> { - use intrinsics::Type::*; - match *t { - Void => vec![cx.type_void()], - Integer(_signed, _width, llvm_width) => { - vec![cx.type_ix( llvm_width as u64)] - } - Float(x) => { - match x { - 32 => vec![cx.type_f32()], - 64 => vec![cx.type_f64()], - _ => bug!() - } - } - Pointer(ref t, ref llvm_elem, _const) => { - let t = llvm_elem.as_ref().unwrap_or(t); - let elem = one(ty_to_type(cx, t)); - vec![cx.type_ptr_to(elem)] - } - Vector(ref t, ref llvm_elem, length) => { - let t = llvm_elem.as_ref().unwrap_or(t); - let elem = one(ty_to_type(cx, t)); - vec![cx.type_vector(elem, length as u64)] - } - Aggregate(false, ref contents) => { - let elems = contents.iter() - .map(|t| one(ty_to_type(cx, t))) - .collect::>(); - vec![cx.type_struct( &elems, false)] - } - Aggregate(true, ref contents) => { - contents.iter() - .flat_map(|t| ty_to_type(cx, t)) - .collect() - } - } - } - - // This allows an argument list like `foo, (bar, baz), - // qux` to be converted into `foo, bar, baz, qux`, integer - // arguments to be truncated as needed and pointers to be - // cast. - fn modify_as_needed<'ll, 'tcx>( - bx: &mut Builder<'_, 'll, 'tcx>, - t: &intrinsics::Type, - arg: &OperandRef<'tcx, &'ll Value>, - ) -> Vec<&'ll Value> { - match *t { - intrinsics::Type::Aggregate(true, ref contents) => { - // We found a tuple that needs squishing! So - // run over the tuple and load each field. - // - // This assumes the type is "simple", i.e., no - // destructors, and the contents are SIMD - // etc. - assert!(!bx.type_needs_drop(arg.layout.ty)); - let (ptr, align) = match arg.val { - OperandValue::Ref(ptr, None, align) => (ptr, align), - _ => bug!() - }; - let arg = PlaceRef::new_sized(ptr, arg.layout, align); - (0..contents.len()).map(|i| { - let field = arg.project_field(bx, i); - bx.load_operand(field).immediate() - }).collect() - } - intrinsics::Type::Pointer(_, Some(ref llvm_elem), _) => { - let llvm_elem = one(ty_to_type(bx, llvm_elem)); - vec![bx.pointercast(arg.immediate(), bx.type_ptr_to(llvm_elem))] - } - intrinsics::Type::Vector(_, Some(ref llvm_elem), length) => { - let llvm_elem = one(ty_to_type(bx, llvm_elem)); - vec![ - bx.bitcast(arg.immediate(), - bx.type_vector(llvm_elem, length as u64)) - ] - } - intrinsics::Type::Integer(_, width, llvm_width) if width != llvm_width => { - // the LLVM intrinsic uses a smaller integer - // size than the C intrinsic's signature, so - // we have to trim it down here. - vec![bx.trunc(arg.immediate(), bx.type_ix(llvm_width as u64))] - } - _ => vec![arg.immediate()], - } - } - - - let inputs = intr.inputs.iter() - .flat_map(|t| ty_to_type(self, t)) - .collect::>(); - - let outputs = one(ty_to_type(self, &intr.output)); - - let llargs: Vec<_> = intr.inputs.iter().zip(args).flat_map(|(t, arg)| { - modify_as_needed(self, t, arg) - }).collect(); - assert_eq!(inputs.len(), llargs.len()); - - let val = match intr.definition { - intrinsics::IntrinsicDef::Named(name) => { - let f = self.declare_cfn( - name, - self.type_func(&inputs, outputs), - ); - self.call(f, &llargs, None) - } - }; - - match *intr.output { - intrinsics::Type::Aggregate(flatten, ref elems) => { - // the output is a tuple so we need to munge it properly - assert!(!flatten); - - for i in 0..elems.len() { - let dest = result.project_field(self, i); - let val = self.extract_value(val, i as u64); - self.store(val, dest.llval, dest.align); - } - return; - } - _ => val, - } - } + _ => bug!("unknown intrinsic '{}'", name), }; if !fn_ty.ret.is_ignore() { diff --git a/src/librustc_codegen_llvm/lib.rs b/src/librustc_codegen_llvm/lib.rs index 3205348fde33c..272f34b0b3f16 100644 --- a/src/librustc_codegen_llvm/lib.rs +++ b/src/librustc_codegen_llvm/lib.rs @@ -43,7 +43,6 @@ extern crate rustc_target; extern crate rustc_demangle; extern crate rustc_incremental; extern crate rustc_llvm; -extern crate rustc_platform_intrinsics as intrinsics; extern crate rustc_codegen_utils; extern crate rustc_codegen_ssa; extern crate rustc_fs_util; diff --git a/src/librustc_platform_intrinsics/Cargo.toml b/src/librustc_platform_intrinsics/Cargo.toml deleted file mode 100644 index 92f37f974efdc..0000000000000 --- a/src/librustc_platform_intrinsics/Cargo.toml +++ /dev/null @@ -1,9 +0,0 @@ -[package] -authors = ["The Rust Project Developers"] -name = "rustc_platform_intrinsics" -version = "0.0.0" - -[lib] -name = "rustc_platform_intrinsics" -path = "lib.rs" -crate-type = ["dylib"] diff --git a/src/librustc_platform_intrinsics/aarch64.rs b/src/librustc_platform_intrinsics/aarch64.rs deleted file mode 100644 index 833a312ae63a4..0000000000000 --- a/src/librustc_platform_intrinsics/aarch64.rs +++ /dev/null @@ -1,3404 +0,0 @@ -// DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py -// ignore-tidy-linelength - -#![allow(unused_imports)] - -use {Intrinsic, Type}; -use IntrinsicDef::Named; - -pub fn find(name: &str) -> Option { - if !name.starts_with("aarch64_v") { return None } - Some(match &name["aarch64_v".len()..] { - "hadd_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.shadd.v8i8") - }, - "hadd_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.uhadd.v8i8") - }, - "hadd_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.shadd.v4i16") - }, - "hadd_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.uhadd.v4i16") - }, - "hadd_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.shadd.v2i32") - }, - "hadd_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.uhadd.v2i32") - }, - "haddq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.shadd.v16i8") - }, - "haddq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.uhadd.v16i8") - }, - "haddq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.shadd.v8i16") - }, - "haddq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.uhadd.v8i16") - }, - "haddq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.shadd.v4i32") - }, - "haddq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.uhadd.v4i32") - }, - "rhadd_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.srhadd.v8i8") - }, - "rhadd_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.urhadd.v8i8") - }, - "rhadd_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.srhadd.v4i16") - }, - "rhadd_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.urhadd.v4i16") - }, - "rhadd_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.srhadd.v2i32") - }, - "rhadd_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.urhadd.v2i32") - }, - "rhaddq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.srhadd.v16i8") - }, - "rhaddq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.urhadd.v16i8") - }, - "rhaddq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.srhadd.v8i16") - }, - "rhaddq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.urhadd.v8i16") - }, - "rhaddq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.srhadd.v4i32") - }, - "rhaddq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.urhadd.v4i32") - }, - "qadd_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sqadd.v8i8") - }, - "qadd_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.uqadd.v8i8") - }, - "qadd_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sqadd.v4i16") - }, - "qadd_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.uqadd.v4i16") - }, - "qadd_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sqadd.v2i32") - }, - "qadd_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.uqadd.v2i32") - }, - "qadd_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.aarch64.neon.sqadd.v1i64") - }, - "qadd_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.aarch64.neon.uqadd.v1i64") - }, - "qaddq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.sqadd.v16i8") - }, - "qaddq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.uqadd.v16i8") - }, - "qaddq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.sqadd.v8i16") - }, - "qaddq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.uqadd.v8i16") - }, - "qaddq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.sqadd.v4i32") - }, - "qaddq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.uqadd.v4i32") - }, - "qaddq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.sqadd.v2i64") - }, - "qaddq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.uqadd.v2i64") - }, - "uqadd_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::U8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.suqadd.v16i8") - }, - "uqadd_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.suqadd.v8i16") - }, - "uqadd_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.suqadd.v4i32") - }, - "uqadd_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.suqadd.v2i64") - }, - "sqadd_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.usqadd.v16i8") - }, - "sqadd_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.usqadd.v8i16") - }, - "sqadd_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.usqadd.v4i32") - }, - "sqadd_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.usqadd.v2i64") - }, - "raddhn_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.raddhn.v8i8") - }, - "raddhn_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.raddhn.v8i8") - }, - "raddhn_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.raddhn.v4i16") - }, - "raddhn_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.raddhn.v4i16") - }, - "raddhn_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.raddhn.v2i32") - }, - "raddhn_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.raddhn.v2i32") - }, - "fmulx_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.fmulx.v2f32") - }, - "fmulx_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }, - output: &::F64x1, - definition: Named("llvm.aarch64.neon.fmulx.v1f64") - }, - "fmulxq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.fmulx.v4f32") - }, - "fmulxq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.fmulx.v2f64") - }, - "fma_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.fma.v2f32") - }, - "fma_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }, - output: &::F64x1, - definition: Named("llvm.fma.v1f64") - }, - "fmaq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.fma.v4f32") - }, - "fmaq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.fma.v2f64") - }, - "qdmulh_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sqdmulh.v4i16") - }, - "qdmulh_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sqdmulh.v2i32") - }, - "qdmulhq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.sqdmulh.v8i16") - }, - "qdmulhq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.sqdmulh.v4i32") - }, - "qrdmulh_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sqrdmulh.v4i16") - }, - "qrdmulh_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sqrdmulh.v2i32") - }, - "qrdmulhq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.sqrdmulh.v8i16") - }, - "qrdmulhq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.sqrdmulh.v4i32") - }, - "mull_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.smull.v8i16") - }, - "mull_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.umull.v8i16") - }, - "mull_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.smull.v4i32") - }, - "mull_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.umull.v4i32") - }, - "mull_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.smull.v2i64") - }, - "mull_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.umull.v2i64") - }, - "qdmullq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.sqdmull.v8i16") - }, - "qdmullq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.sqdmull.v4i32") - }, - "hsub_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.shsub.v8i8") - }, - "hsub_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.uhsub.v8i8") - }, - "hsub_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.shsub.v4i16") - }, - "hsub_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.uhsub.v4i16") - }, - "hsub_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.shsub.v2i32") - }, - "hsub_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.uhsub.v2i32") - }, - "hsubq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.shsub.v16i8") - }, - "hsubq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.uhsub.v16i8") - }, - "hsubq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.shsub.v8i16") - }, - "hsubq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.uhsub.v8i16") - }, - "hsubq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.shsub.v4i32") - }, - "hsubq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.uhsub.v4i32") - }, - "qsub_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sqsub.v8i8") - }, - "qsub_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.uqsub.v8i8") - }, - "qsub_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sqsub.v4i16") - }, - "qsub_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.uqsub.v4i16") - }, - "qsub_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sqsub.v2i32") - }, - "qsub_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.uqsub.v2i32") - }, - "qsub_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.aarch64.neon.sqsub.v1i64") - }, - "qsub_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.aarch64.neon.uqsub.v1i64") - }, - "qsubq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.sqsub.v16i8") - }, - "qsubq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.uqsub.v16i8") - }, - "qsubq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.sqsub.v8i16") - }, - "qsubq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.uqsub.v8i16") - }, - "qsubq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.sqsub.v4i32") - }, - "qsubq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.uqsub.v4i32") - }, - "qsubq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.sqsub.v2i64") - }, - "qsubq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.uqsub.v2i64") - }, - "rsubhn_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.rsubhn.v8i8") - }, - "rsubhn_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.rsubhn.v8i8") - }, - "rsubhn_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.rsubhn.v4i16") - }, - "rsubhn_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.rsubhn.v4i16") - }, - "rsubhn_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.rsubhn.v2i32") - }, - "rsubhn_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.rsubhn.v2i32") - }, - "abd_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sabd.v8i8") - }, - "abd_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.uabd.v8i8") - }, - "abd_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sabd.v4i16") - }, - "abd_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.uabd.v4i16") - }, - "abd_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sabd.v2i32") - }, - "abd_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.uabd.v2i32") - }, - "abd_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.fabd.v2f32") - }, - "abd_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }, - output: &::F64x1, - definition: Named("llvm.aarch64.neon.fabd.v1f64") - }, - "abdq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.sabd.v16i8") - }, - "abdq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.uabd.v16i8") - }, - "abdq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.sabd.v8i16") - }, - "abdq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.uabd.v8i16") - }, - "abdq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.sabd.v4i32") - }, - "abdq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.uabd.v4i32") - }, - "abdq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.fabd.v4f32") - }, - "abdq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.fabd.v2f64") - }, - "max_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.smax.v8i8") - }, - "max_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.umax.v8i8") - }, - "max_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.smax.v4i16") - }, - "max_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.umax.v4i16") - }, - "max_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.smax.v2i32") - }, - "max_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.umax.v2i32") - }, - "max_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.fmax.v2f32") - }, - "max_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }, - output: &::F64x1, - definition: Named("llvm.aarch64.neon.fmax.v1f64") - }, - "maxq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.smax.v16i8") - }, - "maxq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.umax.v16i8") - }, - "maxq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.smax.v8i16") - }, - "maxq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.umax.v8i16") - }, - "maxq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.smax.v4i32") - }, - "maxq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.umax.v4i32") - }, - "maxq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.fmax.v4f32") - }, - "maxq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.fmax.v2f64") - }, - "min_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.smin.v8i8") - }, - "min_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.umin.v8i8") - }, - "min_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.smin.v4i16") - }, - "min_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.umin.v4i16") - }, - "min_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.smin.v2i32") - }, - "min_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.umin.v2i32") - }, - "min_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.fmin.v2f32") - }, - "min_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }, - output: &::F64x1, - definition: Named("llvm.aarch64.neon.fmin.v1f64") - }, - "minq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.smin.v16i8") - }, - "minq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.umin.v16i8") - }, - "minq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.smin.v8i16") - }, - "minq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.umin.v8i16") - }, - "minq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.smin.v4i32") - }, - "minq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.umin.v4i32") - }, - "minq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.fmin.v4f32") - }, - "minq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.fmin.v2f64") - }, - "maxnm_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.fmaxnm.v2f32") - }, - "maxnm_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }, - output: &::F64x1, - definition: Named("llvm.aarch64.neon.fmaxnm.v1f64") - }, - "maxnmq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.fmaxnm.v4f32") - }, - "maxnmq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.fmaxnm.v2f64") - }, - "minnm_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.fminnm.v2f32") - }, - "minnm_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }, - output: &::F64x1, - definition: Named("llvm.aarch64.neon.fminnm.v1f64") - }, - "minnmq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.fminnm.v4f32") - }, - "minnmq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.fminnm.v2f64") - }, - "shl_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sshl.v8i8") - }, - "shl_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.ushl.v8i8") - }, - "shl_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sshl.v4i16") - }, - "shl_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.ushl.v4i16") - }, - "shl_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sshl.v2i32") - }, - "shl_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.ushl.v2i32") - }, - "shl_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.aarch64.neon.sshl.v1i64") - }, - "shl_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.aarch64.neon.ushl.v1i64") - }, - "shlq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.sshl.v16i8") - }, - "shlq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.ushl.v16i8") - }, - "shlq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.sshl.v8i16") - }, - "shlq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.ushl.v8i16") - }, - "shlq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.sshl.v4i32") - }, - "shlq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.ushl.v4i32") - }, - "shlq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.sshl.v2i64") - }, - "shlq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.ushl.v2i64") - }, - "qshl_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sqshl.v8i8") - }, - "qshl_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.uqshl.v8i8") - }, - "qshl_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sqshl.v4i16") - }, - "qshl_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.uqshl.v4i16") - }, - "qshl_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sqshl.v2i32") - }, - "qshl_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.uqshl.v2i32") - }, - "qshl_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.aarch64.neon.sqshl.v1i64") - }, - "qshl_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.aarch64.neon.uqshl.v1i64") - }, - "qshlq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.sqshl.v16i8") - }, - "qshlq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.uqshl.v16i8") - }, - "qshlq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.sqshl.v8i16") - }, - "qshlq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.uqshl.v8i16") - }, - "qshlq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.sqshl.v4i32") - }, - "qshlq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.uqshl.v4i32") - }, - "qshlq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.sqshl.v2i64") - }, - "qshlq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.uqshl.v2i64") - }, - "rshl_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.srshl.v8i8") - }, - "rshl_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.urshl.v8i8") - }, - "rshl_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.srshl.v4i16") - }, - "rshl_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.urshl.v4i16") - }, - "rshl_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.srshl.v2i32") - }, - "rshl_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.urshl.v2i32") - }, - "rshl_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.aarch64.neon.srshl.v1i64") - }, - "rshl_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.aarch64.neon.urshl.v1i64") - }, - "rshlq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.srshl.v16i8") - }, - "rshlq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.urshl.v16i8") - }, - "rshlq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.srshl.v8i16") - }, - "rshlq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.urshl.v8i16") - }, - "rshlq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.srshl.v4i32") - }, - "rshlq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.urshl.v4i32") - }, - "rshlq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.srshl.v2i64") - }, - "rshlq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.urshl.v2i64") - }, - "qrshl_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sqrshl.v8i8") - }, - "qrshl_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.uqrshl.v8i8") - }, - "qrshl_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sqrshl.v4i16") - }, - "qrshl_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.uqrshl.v4i16") - }, - "qrshl_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sqrshl.v2i32") - }, - "qrshl_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.uqrshl.v2i32") - }, - "qrshl_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.aarch64.neon.sqrshl.v1i64") - }, - "qrshl_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.aarch64.neon.uqrshl.v1i64") - }, - "qrshlq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.sqrshl.v16i8") - }, - "qrshlq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.uqrshl.v16i8") - }, - "qrshlq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.sqrshl.v8i16") - }, - "qrshlq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.uqrshl.v8i16") - }, - "qrshlq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.sqrshl.v4i32") - }, - "qrshlq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.uqrshl.v4i32") - }, - "qrshlq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.sqrshl.v2i64") - }, - "qrshlq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.uqrshl.v2i64") - }, - "qshrun_n_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sqshrun.v8i8") - }, - "qshrun_n_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sqshrun.v4i16") - }, - "qshrun_n_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sqshrun.v2i32") - }, - "qrshrun_n_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sqrshrun.v8i8") - }, - "qrshrun_n_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sqrshrun.v4i16") - }, - "qrshrun_n_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sqrshrun.v2i32") - }, - "qshrn_n_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sqshrn.v8i8") - }, - "qshrn_n_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.uqshrn.v8i8") - }, - "qshrn_n_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sqshrn.v4i16") - }, - "qshrn_n_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.uqshrn.v4i16") - }, - "qshrn_n_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sqshrn.v2i32") - }, - "qshrn_n_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.uqshrn.v2i32") - }, - "rshrn_n_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.rshrn.v8i8") - }, - "rshrn_n_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.rshrn.v8i8") - }, - "rshrn_n_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.rshrn.v4i16") - }, - "rshrn_n_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.rshrn.v4i16") - }, - "rshrn_n_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.rshrn.v2i32") - }, - "rshrn_n_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.rshrn.v2i32") - }, - "qrshrn_n_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sqrshrn.v8i8") - }, - "qrshrn_n_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.uqrshrn.v8i8") - }, - "qrshrn_n_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sqrshrn.v4i16") - }, - "qrshrn_n_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.uqrshrn.v4i16") - }, - "qrshrn_n_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sqrshrn.v2i32") - }, - "qrshrn_n_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.uqrshrn.v2i32") - }, - "sri_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.vsri.v8i8") - }, - "sri_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.vsri.v8i8") - }, - "sri_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.vsri.v4i16") - }, - "sri_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.vsri.v4i16") - }, - "sri_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.vsri.v2i32") - }, - "sri_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.vsri.v2i32") - }, - "sri_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.aarch64.neon.vsri.v1i64") - }, - "sri_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.aarch64.neon.vsri.v1i64") - }, - "sriq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.vsri.v16i8") - }, - "sriq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.vsri.v16i8") - }, - "sriq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.vsri.v8i16") - }, - "sriq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.vsri.v8i16") - }, - "sriq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.vsri.v4i32") - }, - "sriq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.vsri.v4i32") - }, - "sriq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.vsri.v2i64") - }, - "sriq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.vsri.v2i64") - }, - "sli_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.vsli.v8i8") - }, - "sli_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.vsli.v8i8") - }, - "sli_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.vsli.v4i16") - }, - "sli_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.vsli.v4i16") - }, - "sli_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.vsli.v2i32") - }, - "sli_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.vsli.v2i32") - }, - "sli_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.aarch64.neon.vsli.v1i64") - }, - "sli_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.aarch64.neon.vsli.v1i64") - }, - "sliq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.vsli.v16i8") - }, - "sliq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.vsli.v16i8") - }, - "sliq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.vsli.v8i16") - }, - "sliq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.vsli.v8i16") - }, - "sliq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.vsli.v4i32") - }, - "sliq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.vsli.v4i32") - }, - "sliq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.vsli.v2i64") - }, - "sliq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.vsli.v2i64") - }, - "vqmovn_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sqxtn.v8i8") - }, - "vqmovn_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.uqxtn.v8i8") - }, - "vqmovn_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sqxtn.v4i16") - }, - "vqmovn_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.uqxtn.v4i16") - }, - "vqmovn_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sqxtn.v2i32") - }, - "vqmovn_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U64x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.uqxtn.v2i32") - }, - "abs_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.abs.v8i8") - }, - "abs_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.abs.v4i16") - }, - "abs_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.abs.v2i32") - }, - "abs_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.aarch64.neon.abs.v1i64") - }, - "absq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.abs.v16i8") - }, - "absq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.abs.v8i16") - }, - "absq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.abs.v4i32") - }, - "absq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.abs.v2i64") - }, - "abs_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.fabs.v2f32") - }, - "abs_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS }, - output: &::F64x1, - definition: Named("llvm.fabs.v1f64") - }, - "absq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.fabs.v4f32") - }, - "absq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.fabs.v2f64") - }, - "qabs_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sqabs.v8i8") - }, - "qabs_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sqabs.v4i16") - }, - "qabs_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sqabs.v2i32") - }, - "qabs_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.aarch64.neon.sqabs.v1i64") - }, - "qabsq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.sqabs.v16i8") - }, - "qabsq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.sqabs.v8i16") - }, - "qabsq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.sqabs.v4i32") - }, - "qabsq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.sqabs.v2i64") - }, - "qneg_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sqneg.v8i8") - }, - "qneg_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sqneg.v4i16") - }, - "qneg_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sqneg.v2i32") - }, - "qneg_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.aarch64.neon.sqneg.v1i64") - }, - "qnegq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.sqneg.v16i8") - }, - "qnegq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.sqneg.v8i16") - }, - "qnegq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.sqneg.v4i32") - }, - "qnegq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.sqneg.v2i64") - }, - "clz_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.ctlz.v8i8") - }, - "clz_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.ctlz.v8i8") - }, - "clz_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.ctlz.v4i16") - }, - "clz_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.ctlz.v4i16") - }, - "clz_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.ctlz.v2i32") - }, - "clz_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.ctlz.v2i32") - }, - "clzq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.ctlz.v16i8") - }, - "clzq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.ctlz.v16i8") - }, - "clzq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ctlz.v8i16") - }, - "clzq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.ctlz.v8i16") - }, - "clzq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ctlz.v4i32") - }, - "clzq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ctlz.v4i32") - }, - "cls_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.cls.v8i8") - }, - "cls_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.cls.v8i8") - }, - "cls_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.cls.v4i16") - }, - "cls_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.cls.v4i16") - }, - "cls_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.cls.v2i32") - }, - "cls_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.cls.v2i32") - }, - "clsq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.cls.v16i8") - }, - "clsq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.cls.v16i8") - }, - "clsq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.cls.v8i16") - }, - "clsq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.cls.v8i16") - }, - "clsq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.cls.v4i32") - }, - "clsq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.cls.v4i32") - }, - "cnt_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.ctpop.v8i8") - }, - "cnt_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.ctpop.v8i8") - }, - "cntq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.ctpop.v16i8") - }, - "cntq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.ctpop.v16i8") - }, - "recpe_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.urecpe.v2i32") - }, - "recpe_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.frecpe.v2f32") - }, - "recpe_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS }, - output: &::F64x1, - definition: Named("llvm.aarch64.neon.frecpe.v1f64") - }, - "recpeq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.urecpe.v4i32") - }, - "recpeq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.frecpe.v4f32") - }, - "recpeq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.frecpe.v2f64") - }, - "recps_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.frecps.v2f32") - }, - "recps_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }, - output: &::F64x1, - definition: Named("llvm.aarch64.neon.frecps.v1f64") - }, - "recpsq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.frecps.v4f32") - }, - "recpsq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.frecps.v2f64") - }, - "sqrt_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.sqrt.v2f32") - }, - "sqrt_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS }, - output: &::F64x1, - definition: Named("llvm.sqrt.v1f64") - }, - "sqrtq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.sqrt.v4f32") - }, - "sqrtq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.sqrt.v2f64") - }, - "rsqrte_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.ursqrte.v2i32") - }, - "rsqrte_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.frsqrte.v2f32") - }, - "rsqrte_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x1]; &INPUTS }, - output: &::F64x1, - definition: Named("llvm.aarch64.neon.frsqrte.v1f64") - }, - "rsqrteq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.ursqrte.v4i32") - }, - "rsqrteq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.frsqrte.v4f32") - }, - "rsqrteq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.frsqrte.v2f64") - }, - "rsqrts_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.frsqrts.v2f32") - }, - "rsqrts_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &INPUTS }, - output: &::F64x1, - definition: Named("llvm.aarch64.neon.frsqrts.v1f64") - }, - "rsqrtsq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.frsqrts.v4f32") - }, - "rsqrtsq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.frsqrts.v2f64") - }, - "rbit_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.rbit.v8i8") - }, - "rbit_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.rbit.v8i8") - }, - "rbitq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.rbit.v16i8") - }, - "rbitq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.rbit.v16i8") - }, - "ld2_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x8), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v8i8.p0v8i8") - }, - "ld2_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x8), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v8i8.p0v8i8") - }, - "ld2_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v4i16.p0v4i16") - }, - "ld2_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v4i16.p0v4i16") - }, - "ld2_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v2i32.p0v2i32") - }, - "ld2_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v2i32.p0v2i32") - }, - "ld2_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x1), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v1i64.p0v1i64") - }, - "ld2_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x1), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v1i64.p0v1i64") - }, - "ld2_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v2f32.p0v2f32") - }, - "ld2_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x1), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v1f64.p0v1f64") - }, - "ld2q_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x16), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v16i8.p0v16i8") - }, - "ld2q_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x16), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v16i8.p0v16i8") - }, - "ld2q_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x8), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v8i16.p0v8i16") - }, - "ld2q_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x8), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v8i16.p0v8i16") - }, - "ld2q_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v4i32.p0v4i32") - }, - "ld2q_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v4i32.p0v4i32") - }, - "ld2q_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v2i64.p0v2i64") - }, - "ld2q_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v2i64.p0v2i64") - }, - "ld2q_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v4f32.p0v4f32") - }, - "ld2q_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v2f64.p0v2f64") - }, - "ld3_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x8), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v8i8.p0v8i8") - }, - "ld3_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x8), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v8i8.p0v8i8") - }, - "ld3_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x4, &::I16x4, &::I16x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v4i16.p0v4i16") - }, - "ld3_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x4, &::U16x4, &::U16x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v4i16.p0v4i16") - }, - "ld3_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x2, &::I32x2, &::I32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v2i32.p0v2i32") - }, - "ld3_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x2, &::U32x2, &::U32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v2i32.p0v2i32") - }, - "ld3_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x1), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x1, &::I64x1, &::I64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v1i64.p0v1i64") - }, - "ld3_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x1), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x1, &::U64x1, &::U64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v1i64.p0v1i64") - }, - "ld3_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x2, &::F32x2, &::F32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v2f32.p0v2f32") - }, - "ld3_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x1), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x1, &::F64x1, &::F64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v1f64.p0v1f64") - }, - "ld3q_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x16), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v16i8.p0v16i8") - }, - "ld3q_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x16), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v16i8.p0v16i8") - }, - "ld3q_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x8), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I16x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v8i16.p0v8i16") - }, - "ld3q_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x8), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x8, &::U16x8, &::U16x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v8i16.p0v8i16") - }, - "ld3q_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x4, &::I32x4, &::I32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v4i32.p0v4i32") - }, - "ld3q_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x4, &::U32x4, &::U32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v4i32.p0v4i32") - }, - "ld3q_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x2, &::I64x2, &::I64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v2i64.p0v2i64") - }, - "ld3q_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x2, &::U64x2, &::U64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v2i64.p0v2i64") - }, - "ld3q_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v4f32.p0v4f32") - }, - "ld3q_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v2f64.p0v2f64") - }, - "ld4_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x8), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v8i8.p0v8i8") - }, - "ld4_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x8), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v8i8.p0v8i8") - }, - "ld4_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x4, &::I16x4, &::I16x4, &::I16x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v4i16.p0v4i16") - }, - "ld4_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x4, &::U16x4, &::U16x4, &::U16x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v4i16.p0v4i16") - }, - "ld4_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x2, &::I32x2, &::I32x2, &::I32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v2i32.p0v2i32") - }, - "ld4_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x2, &::U32x2, &::U32x2, &::U32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v2i32.p0v2i32") - }, - "ld4_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x1), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x1, &::I64x1, &::I64x1, &::I64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v1i64.p0v1i64") - }, - "ld4_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x1), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x1, &::U64x1, &::U64x1, &::U64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v1i64.p0v1i64") - }, - "ld4_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x2, &::F32x2, &::F32x2, &::F32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v2f32.p0v2f32") - }, - "ld4_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x1), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x1, &::F64x1, &::F64x1, &::F64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v1f64.p0v1f64") - }, - "ld4q_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, Some(&::I8x16), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v16i8.p0v16i8") - }, - "ld4q_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, Some(&::U8x16), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v16i8.p0v16i8") - }, - "ld4q_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, Some(&::I16x8), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x8, &::I16x8, &::I16x8, &::I16x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v8i16.p0v8i16") - }, - "ld4q_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, Some(&::U16x8), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x8, &::U16x8, &::U16x8, &::U16x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v8i16.p0v8i16") - }, - "ld4q_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I32x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x4, &::I32x4, &::I32x4, &::I32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v4i32.p0v4i32") - }, - "ld4q_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, Some(&::U32x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x4, &::U32x4, &::U32x4, &::U32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v4i32.p0v4i32") - }, - "ld4q_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I64x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x2, &::I64x2, &::I64x2, &::I64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v2i64.p0v2i64") - }, - "ld4q_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, Some(&::U64x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x2, &::U64x2, &::U64x2, &::U64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v2i64.p0v2i64") - }, - "ld4q_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::F32x4), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x4, &::F32x4, &::F32x4, &::F32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v4f32.p0v4f32") - }, - "ld4q_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::F64x2), true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x2, &::F64x2, &::F64x2, &::F64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v2f64.p0v2f64") - }, - "ld2_dup_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v8i8.p0i8") - }, - "ld2_dup_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v8i8.p0i8") - }, - "ld2_dup_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v4i16.p0i16") - }, - "ld2_dup_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v4i16.p0i16") - }, - "ld2_dup_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v2i32.p0i32") - }, - "ld2_dup_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v2i32.p0i32") - }, - "ld2_dup_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v1i64.p0i64") - }, - "ld2_dup_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v1i64.p0i64") - }, - "ld2_dup_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v2f32.p0f32") - }, - "ld2_dup_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x1, &::F64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v1f64.p0f64") - }, - "ld2q_dup_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v16i8.p0i8") - }, - "ld2q_dup_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v16i8.p0i8") - }, - "ld2q_dup_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v8i16.p0i16") - }, - "ld2q_dup_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v8i16.p0i16") - }, - "ld2q_dup_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v4i32.p0i32") - }, - "ld2q_dup_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v4i32.p0i32") - }, - "ld2q_dup_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v2i64.p0i64") - }, - "ld2q_dup_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v2i64.p0i64") - }, - "ld2q_dup_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v4f32.p0f32") - }, - "ld2q_dup_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld2.v2f64.p0f64") - }, - "ld3_dup_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v8i8.p0i8") - }, - "ld3_dup_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v8i8.p0i8") - }, - "ld3_dup_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x4, &::I16x4, &::I16x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v4i16.p0i16") - }, - "ld3_dup_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x4, &::U16x4, &::U16x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v4i16.p0i16") - }, - "ld3_dup_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x2, &::I32x2, &::I32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v2i32.p0i32") - }, - "ld3_dup_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x2, &::U32x2, &::U32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v2i32.p0i32") - }, - "ld3_dup_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x1, &::I64x1, &::I64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v1i64.p0i64") - }, - "ld3_dup_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x1, &::U64x1, &::U64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v1i64.p0i64") - }, - "ld3_dup_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x2, &::F32x2, &::F32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v2f32.p0f32") - }, - "ld3_dup_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x1, &::F64x1, &::F64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v1f64.p0f64") - }, - "ld3q_dup_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v16i8.p0i8") - }, - "ld3q_dup_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v16i8.p0i8") - }, - "ld3q_dup_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I16x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v8i16.p0i16") - }, - "ld3q_dup_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U16x8, &::U16x8, &::U16x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v8i16.p0i16") - }, - "ld3q_dup_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I32x4, &::I32x4, &::I32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v4i32.p0i32") - }, - "ld3q_dup_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U32x4, &::U32x4, &::U32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v4i32.p0i32") - }, - "ld3q_dup_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::I64x2, &::I64x2, &::I64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v2i64.p0i64") - }, - "ld3q_dup_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::U64x2, &::U64x2, &::U64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v2i64.p0i64") - }, - "ld3q_dup_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v4f32.p0f32") - }, - "ld3q_dup_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld3.v2f64.p0f64") - }, - "ld4_dup_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v8i8.p0i8") - }, - "ld4_dup_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v8i8.p0i8") - }, - "ld4_dup_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x4, &::I16x4, &::I16x4, &::I16x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v4i16.p0i16") - }, - "ld4_dup_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x4, &::U16x4, &::U16x4, &::U16x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v4i16.p0i16") - }, - "ld4_dup_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x2, &::I32x2, &::I32x2, &::I32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v2i32.p0i32") - }, - "ld4_dup_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x2, &::U32x2, &::U32x2, &::U32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v2i32.p0i32") - }, - "ld4_dup_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x1, &::I64x1, &::I64x1, &::I64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v1i64.p0i64") - }, - "ld4_dup_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x1, &::U64x1, &::U64x1, &::U64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v1i64.p0i64") - }, - "ld4_dup_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x2, &::F32x2, &::F32x2, &::F32x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v2f32.p0f32") - }, - "ld4_dup_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x1, &::F64x1, &::F64x1, &::F64x1]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v1f64.p0f64") - }, - "ld4q_dup_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v16i8.p0i8") - }, - "ld4q_dup_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v16i8.p0i8") - }, - "ld4q_dup_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I16, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I16x8, &::I16x8, &::I16x8, &::I16x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v8i16.p0i16") - }, - "ld4q_dup_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U16, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U16x8, &::U16x8, &::U16x8, &::U16x8]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v8i16.p0i16") - }, - "ld4q_dup_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I32x4, &::I32x4, &::I32x4, &::I32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v4i32.p0i32") - }, - "ld4q_dup_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U32x4, &::U32x4, &::U32x4, &::U32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v4i32.p0i32") - }, - "ld4q_dup_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::I64x2, &::I64x2, &::I64x2, &::I64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v2i64.p0i64") - }, - "ld4q_dup_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::U64x2, &::U64x2, &::U64x2, &::U64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v2i64.p0i64") - }, - "ld4q_dup_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F32, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F32x4, &::F32x4, &::F32x4, &::F32x4]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v4f32.p0f32") - }, - "ld4q_dup_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::F64, None, true); &PTR }]; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 4] = [&::F64x2, &::F64x2, &::F64x2, &::F64x2]; &PARTS }); &AGG }, - definition: Named("llvm.aarch64.neon.ld4.v2f64.p0f64") - }, - "padd_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.addp.v8i8") - }, - "padd_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.addp.v8i8") - }, - "padd_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.addp.v4i16") - }, - "padd_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.addp.v4i16") - }, - "padd_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.addp.v2i32") - }, - "padd_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.addp.v2i32") - }, - "padd_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.addp.v2f32") - }, - "paddq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.addp.v16i8") - }, - "paddq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.addp.v16i8") - }, - "paddq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.addp.v8i16") - }, - "paddq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.addp.v8i16") - }, - "paddq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.addp.v4i32") - }, - "paddq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.addp.v4i32") - }, - "paddq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.addp.v4f32") - }, - "paddq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.addp.v2i64") - }, - "paddq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.addp.v2i64") - }, - "paddq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.addp.v2f64") - }, - "paddl_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.saddlp.v4i16.v8i8") - }, - "paddl_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.uaddlp.v4i16.v8i8") - }, - "paddl_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.saddlp.v2i32.v4i16") - }, - "paddl_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.uaddlp.v2i32.v4i16") - }, - "paddl_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.aarch64.neon.saddlp.v1i64.v2i32") - }, - "paddl_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.aarch64.neon.uaddlp.v1i64.v2i32") - }, - "paddlq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.saddlp.v8i16.v16i8") - }, - "paddlq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.uaddlp.v8i16.v16i8") - }, - "paddlq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.saddlp.v4i32.v8i16") - }, - "paddlq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.uaddlp.v4i32.v8i16") - }, - "paddlq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.saddlp.v2i64.v4i32") - }, - "paddlq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.uaddlp.v2i64.v4i32") - }, - "pmax_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.smaxp.v8i8") - }, - "pmax_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.umaxp.v8i8") - }, - "pmax_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.smaxp.v4i16") - }, - "pmax_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.umaxp.v4i16") - }, - "pmax_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.smaxp.v2i32") - }, - "pmax_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.umaxp.v2i32") - }, - "pmax_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.fmaxp.v2f32") - }, - "pmaxq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.smaxp.v16i8") - }, - "pmaxq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.umaxp.v16i8") - }, - "pmaxq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.smaxp.v8i16") - }, - "pmaxq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.umaxp.v8i16") - }, - "pmaxq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.smaxp.v4i32") - }, - "pmaxq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.umaxp.v4i32") - }, - "pmaxq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.fmaxp.v4f32") - }, - "pmaxq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.smaxp.v2i64") - }, - "pmaxq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.umaxp.v2i64") - }, - "pmaxq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.fmaxp.v2f64") - }, - "pmin_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.sminp.v8i8") - }, - "pmin_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.uminp.v8i8") - }, - "pmin_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.sminp.v4i16") - }, - "pmin_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.uminp.v4i16") - }, - "pmin_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.sminp.v2i32") - }, - "pmin_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.uminp.v2i32") - }, - "pmin_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.fminp.v2f32") - }, - "pminq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.sminp.v16i8") - }, - "pminq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.uminp.v16i8") - }, - "pminq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.sminp.v8i16") - }, - "pminq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.uminp.v8i16") - }, - "pminq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.sminp.v4i32") - }, - "pminq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.uminp.v4i32") - }, - "pminq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.fminp.v4f32") - }, - "pminq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.sminp.v2i64") - }, - "pminq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.uminp.v2i64") - }, - "pminq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.fminp.v2f64") - }, - "pmaxnm_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.smaxnmp.v8i8") - }, - "pmaxnm_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.umaxnmp.v8i8") - }, - "pmaxnm_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.aarch64.neon.smaxnmp.v4i16") - }, - "pmaxnm_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.aarch64.neon.umaxnmp.v4i16") - }, - "pmaxnm_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.aarch64.neon.smaxnmp.v2i32") - }, - "pmaxnm_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.aarch64.neon.umaxnmp.v2i32") - }, - "pmaxnm_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.fmaxnmp.v2f32") - }, - "pmaxnmq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.smaxnmp.v16i8") - }, - "pmaxnmq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.umaxnmp.v16i8") - }, - "pmaxnmq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.aarch64.neon.smaxnmp.v8i16") - }, - "pmaxnmq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.aarch64.neon.umaxnmp.v8i16") - }, - "pmaxnmq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.aarch64.neon.smaxnmp.v4i32") - }, - "pmaxnmq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.aarch64.neon.umaxnmp.v4i32") - }, - "pmaxnmq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.fmaxnmp.v4f32") - }, - "pmaxnmq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.aarch64.neon.smaxnmp.v2i64") - }, - "pmaxnmq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.aarch64.neon.umaxnmp.v2i64") - }, - "pmaxnmq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.fmaxnmp.v2f64") - }, - "pminnm_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.aarch64.neon.fminnmp.v2f32") - }, - "pminnmq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.aarch64.neon.fminnmp.v4f32") - }, - "pminnmq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.aarch64.neon.fminnmp.v2f64") - }, - "addv_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8, - definition: Named("llvm.aarch64.neon.saddv.i8.v8i8") - }, - "addv_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }, - output: &::U8, - definition: Named("llvm.aarch64.neon.uaddv.i8.v8i8") - }, - "addv_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I16, - definition: Named("llvm.aarch64.neon.saddv.i16.v4i16") - }, - "addv_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }, - output: &::U16, - definition: Named("llvm.aarch64.neon.uaddv.i16.v4i16") - }, - "addv_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I32, - definition: Named("llvm.aarch64.neon.saddv.i32.v2i32") - }, - "addv_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U32, - definition: Named("llvm.aarch64.neon.uaddv.i32.v2i32") - }, - "addv_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }, - output: &::F32, - definition: Named("llvm.aarch64.neon.faddv.f32.v2f32") - }, - "addvq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8, - definition: Named("llvm.aarch64.neon.saddv.i8.v16i8") - }, - "addvq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }, - output: &::U8, - definition: Named("llvm.aarch64.neon.uaddv.i8.v16i8") - }, - "addvq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16, - definition: Named("llvm.aarch64.neon.saddv.i16.v8i16") - }, - "addvq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }, - output: &::U16, - definition: Named("llvm.aarch64.neon.uaddv.i16.v8i16") - }, - "addvq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.aarch64.neon.saddv.i32.v4i32") - }, - "addvq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U32, - definition: Named("llvm.aarch64.neon.uaddv.i32.v4i32") - }, - "addvq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32, - definition: Named("llvm.aarch64.neon.faddv.f32.v4f32") - }, - "addvq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS }, - output: &::I64, - definition: Named("llvm.aarch64.neon.saddv.i64.v2i64") - }, - "addvq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U64x2]; &INPUTS }, - output: &::U64, - definition: Named("llvm.aarch64.neon.uaddv.i64.v2i64") - }, - "addvq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }, - output: &::F64, - definition: Named("llvm.aarch64.neon.faddv.f64.v2f64") - }, - "addlv_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I16, - definition: Named("llvm.aarch64.neon.saddlv.i16.v8i8") - }, - "addlv_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }, - output: &::U16, - definition: Named("llvm.aarch64.neon.uaddlv.i16.v8i8") - }, - "addlv_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.aarch64.neon.saddlv.i32.v4i16") - }, - "addlv_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }, - output: &::U32, - definition: Named("llvm.aarch64.neon.uaddlv.i32.v4i16") - }, - "addlv_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I64, - definition: Named("llvm.aarch64.neon.saddlv.i64.v2i32") - }, - "addlv_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U64, - definition: Named("llvm.aarch64.neon.uaddlv.i64.v2i32") - }, - "addlvq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I16, - definition: Named("llvm.aarch64.neon.saddlv.i16.v16i8") - }, - "addlvq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }, - output: &::U16, - definition: Named("llvm.aarch64.neon.uaddlv.i16.v16i8") - }, - "addlvq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.aarch64.neon.saddlv.i32.v8i16") - }, - "addlvq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }, - output: &::U32, - definition: Named("llvm.aarch64.neon.uaddlv.i32.v8i16") - }, - "addlvq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I64, - definition: Named("llvm.aarch64.neon.saddlv.i64.v4i32") - }, - "addlvq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U64, - definition: Named("llvm.aarch64.neon.uaddlv.i64.v4i32") - }, - "maxv_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8, - definition: Named("llvm.aarch64.neon.smaxv.i8.v8i8") - }, - "maxv_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }, - output: &::U8, - definition: Named("llvm.aarch64.neon.umaxv.i8.v8i8") - }, - "maxv_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I16, - definition: Named("llvm.aarch64.neon.smaxv.i16.v4i16") - }, - "maxv_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }, - output: &::U16, - definition: Named("llvm.aarch64.neon.umaxv.i16.v4i16") - }, - "maxv_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I32, - definition: Named("llvm.aarch64.neon.smaxv.i32.v2i32") - }, - "maxv_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U32, - definition: Named("llvm.aarch64.neon.umaxv.i32.v2i32") - }, - "maxv_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }, - output: &::F32, - definition: Named("llvm.aarch64.neon.fmaxv.f32.v2f32") - }, - "maxvq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8, - definition: Named("llvm.aarch64.neon.smaxv.i8.v16i8") - }, - "maxvq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }, - output: &::U8, - definition: Named("llvm.aarch64.neon.umaxv.i8.v16i8") - }, - "maxvq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16, - definition: Named("llvm.aarch64.neon.smaxv.i16.v8i16") - }, - "maxvq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }, - output: &::U16, - definition: Named("llvm.aarch64.neon.umaxv.i16.v8i16") - }, - "maxvq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.aarch64.neon.smaxv.i32.v4i32") - }, - "maxvq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U32, - definition: Named("llvm.aarch64.neon.umaxv.i32.v4i32") - }, - "maxvq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32, - definition: Named("llvm.aarch64.neon.fmaxv.f32.v4f32") - }, - "maxvq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }, - output: &::F64, - definition: Named("llvm.aarch64.neon.fmaxv.f64.v2f64") - }, - "minv_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8, - definition: Named("llvm.aarch64.neon.sminv.i8.v8i8") - }, - "minv_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }, - output: &::U8, - definition: Named("llvm.aarch64.neon.uminv.i8.v8i8") - }, - "minv_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I16, - definition: Named("llvm.aarch64.neon.sminv.i16.v4i16") - }, - "minv_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }, - output: &::U16, - definition: Named("llvm.aarch64.neon.uminv.i16.v4i16") - }, - "minv_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I32, - definition: Named("llvm.aarch64.neon.sminv.i32.v2i32") - }, - "minv_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U32, - definition: Named("llvm.aarch64.neon.uminv.i32.v2i32") - }, - "minv_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }, - output: &::F32, - definition: Named("llvm.aarch64.neon.fminv.f32.v2f32") - }, - "minvq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8, - definition: Named("llvm.aarch64.neon.sminv.i8.v16i8") - }, - "minvq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }, - output: &::U8, - definition: Named("llvm.aarch64.neon.uminv.i8.v16i8") - }, - "minvq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16, - definition: Named("llvm.aarch64.neon.sminv.i16.v8i16") - }, - "minvq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }, - output: &::U16, - definition: Named("llvm.aarch64.neon.uminv.i16.v8i16") - }, - "minvq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.aarch64.neon.sminv.i32.v4i32") - }, - "minvq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U32, - definition: Named("llvm.aarch64.neon.uminv.i32.v4i32") - }, - "minvq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32, - definition: Named("llvm.aarch64.neon.fminv.f32.v4f32") - }, - "minvq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }, - output: &::F64, - definition: Named("llvm.aarch64.neon.fminv.f64.v2f64") - }, - "maxnmv_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }, - output: &::F32, - definition: Named("llvm.aarch64.neon.fmaxnmv.f32.v2f32") - }, - "maxnmvq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32, - definition: Named("llvm.aarch64.neon.fmaxnmv.f32.v4f32") - }, - "maxnmvq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }, - output: &::F64, - definition: Named("llvm.aarch64.neon.fmaxnmv.f64.v2f64") - }, - "minnmv_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }, - output: &::F32, - definition: Named("llvm.aarch64.neon.fminnmv.f32.v2f32") - }, - "minnmvq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32, - definition: Named("llvm.aarch64.neon.fminnmv.f32.v4f32") - }, - "minnmvq_f64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }, - output: &::F64, - definition: Named("llvm.aarch64.neon.fminnmv.f64.v2f64") - }, - "qtbl1_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.tbl1.v8i8") - }, - "qtbl1_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.tbl1.v8i8") - }, - "qtbl1q_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::U8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.tbl1.v16i8") - }, - "qtbl1q_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.tbl1.v16i8") - }, - "qtbx1_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, &::I8x16, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.tbx1.v8i8") - }, - "qtbx1_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, &::U8x16, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.tbx1.v8i8") - }, - "qtbx1q_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::U8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.tbx1.v16i8") - }, - "qtbx1q_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.tbx1.v16i8") - }, - "qtbl2_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.tbl2.v8i8") - }, - "qtbl2_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.tbl2.v8i8") - }, - "qtbl2q_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.tbl2.v16i8") - }, - "qtbl2q_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.tbl2.v16i8") - }, - "qtbx2_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.tbx2.v8i8") - }, - "qtbx2_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.tbx2.v8i8") - }, - "qtbx2q_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.tbx2.v16i8") - }, - "qtbx2q_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.tbx2.v16i8") - }, - "qtbl3_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.tbl3.v8i8") - }, - "qtbl3_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.tbl3.v8i8") - }, - "qtbl3q_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.tbl3.v16i8") - }, - "qtbl3q_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.tbl3.v16i8") - }, - "qtbx3_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.tbx3.v8i8") - }, - "qtbx3_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.tbx3.v8i8") - }, - "qtbx3q_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.tbx3.v16i8") - }, - "qtbx3q_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.tbx3.v16i8") - }, - "qtbl4_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.tbl4.v8i8") - }, - "qtbl4_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.tbl4.v8i8") - }, - "qtbl4q_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.tbl4.v16i8") - }, - "qtbl4q_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.tbl4.v16i8") - }, - "qtbx4_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.aarch64.neon.tbx4.v8i8") - }, - "qtbx4_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.aarch64.neon.tbx4.v8i8") - }, - "qtbx4q_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x16, &::I8x16, &::I8x16, &::I8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.aarch64.neon.tbx4.v16i8") - }, - "qtbx4q_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x16, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x16, &::U8x16, &::U8x16, &::U8x16]; &PARTS }); &AGG }, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.aarch64.neon.tbx4.v16i8") - }, - _ => return None, - }) -} diff --git a/src/librustc_platform_intrinsics/arm.rs b/src/librustc_platform_intrinsics/arm.rs deleted file mode 100644 index 2d19293b13295..0000000000000 --- a/src/librustc_platform_intrinsics/arm.rs +++ /dev/null @@ -1,2074 +0,0 @@ -// DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py -// ignore-tidy-linelength - -#![allow(unused_imports)] - -use {Intrinsic, Type}; -use IntrinsicDef::Named; - -pub fn find(name: &str) -> Option { - if !name.starts_with("arm_v") { return None } - Some(match &name["arm_v".len()..] { - "hadd_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vhadds.v8i8") - }, - "hadd_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vhaddu.v8i8") - }, - "hadd_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vhadds.v4i16") - }, - "hadd_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vhaddu.v4i16") - }, - "hadd_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vhadds.v2i32") - }, - "hadd_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vhaddu.v2i32") - }, - "haddq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vhadds.v16i8") - }, - "haddq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vhaddu.v16i8") - }, - "haddq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vhadds.v8i16") - }, - "haddq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vhaddu.v8i16") - }, - "haddq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vhadds.v4i32") - }, - "haddq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vhaddu.v4i32") - }, - "rhadd_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vrhadds.v8i8") - }, - "rhadd_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vrhaddu.v8i8") - }, - "rhadd_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vrhadds.v4i16") - }, - "rhadd_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vrhaddu.v4i16") - }, - "rhadd_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vrhadds.v2i32") - }, - "rhadd_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vrhaddu.v2i32") - }, - "rhaddq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vrhadds.v16i8") - }, - "rhaddq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vrhaddu.v16i8") - }, - "rhaddq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vrhadds.v8i16") - }, - "rhaddq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vrhaddu.v8i16") - }, - "rhaddq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vrhadds.v4i32") - }, - "rhaddq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vrhaddu.v4i32") - }, - "qadd_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vqadds.v8i8") - }, - "qadd_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vqaddu.v8i8") - }, - "qadd_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vqadds.v4i16") - }, - "qadd_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vqaddu.v4i16") - }, - "qadd_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vqadds.v2i32") - }, - "qadd_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vqaddu.v2i32") - }, - "qadd_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.arm.neon.vqadds.v1i64") - }, - "qadd_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.arm.neon.vqaddu.v1i64") - }, - "qaddq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vqadds.v16i8") - }, - "qaddq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vqaddu.v16i8") - }, - "qaddq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vqadds.v8i16") - }, - "qaddq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vqaddu.v8i16") - }, - "qaddq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vqadds.v4i32") - }, - "qaddq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vqaddu.v4i32") - }, - "qaddq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.arm.neon.vqadds.v2i64") - }, - "qaddq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.arm.neon.vqaddu.v2i64") - }, - "raddhn_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vraddhn.v8i8") - }, - "raddhn_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vraddhn.v8i8") - }, - "raddhn_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vraddhn.v4i16") - }, - "raddhn_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vraddhn.v4i16") - }, - "raddhn_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vraddhn.v2i32") - }, - "raddhn_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vraddhn.v2i32") - }, - "fma_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.fma.v2f32") - }, - "fmaq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.fma.v4f32") - }, - "qdmulh_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vsqdmulh.v4i16") - }, - "qdmulh_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vsqdmulh.v2i32") - }, - "qdmulhq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vsqdmulh.v8i16") - }, - "qdmulhq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vsqdmulh.v4i32") - }, - "qrdmulh_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vsqrdmulh.v4i16") - }, - "qrdmulh_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vsqrdmulh.v2i32") - }, - "qrdmulhq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vsqrdmulh.v8i16") - }, - "qrdmulhq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vsqrdmulh.v4i32") - }, - "mull_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vmulls.v8i16") - }, - "mull_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vmullu.v8i16") - }, - "mull_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vmulls.v4i32") - }, - "mull_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vmullu.v4i32") - }, - "mull_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.arm.neon.vmulls.v2i64") - }, - "mull_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.arm.neon.vmullu.v2i64") - }, - "qdmullq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vsqdmull.v8i16") - }, - "qdmullq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vsqdmull.v4i32") - }, - "hsub_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vhsubs.v8i8") - }, - "hsub_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vhsubu.v8i8") - }, - "hsub_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vhsubs.v4i16") - }, - "hsub_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vhsubu.v4i16") - }, - "hsub_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vhsubs.v2i32") - }, - "hsub_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vhsubu.v2i32") - }, - "hsubq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vhsubs.v16i8") - }, - "hsubq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vhsubu.v16i8") - }, - "hsubq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vhsubs.v8i16") - }, - "hsubq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vhsubu.v8i16") - }, - "hsubq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vhsubs.v4i32") - }, - "hsubq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vhsubu.v4i32") - }, - "qsub_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vqsubs.v8i8") - }, - "qsub_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vqsubu.v8i8") - }, - "qsub_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vqsubs.v4i16") - }, - "qsub_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vqsubu.v4i16") - }, - "qsub_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vqsubs.v2i32") - }, - "qsub_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vqsubu.v2i32") - }, - "qsub_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.arm.neon.vqsubs.v1i64") - }, - "qsub_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.arm.neon.vqsubu.v1i64") - }, - "qsubq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vqsubs.v16i8") - }, - "qsubq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vqsubu.v16i8") - }, - "qsubq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vqsubs.v8i16") - }, - "qsubq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vqsubu.v8i16") - }, - "qsubq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vqsubs.v4i32") - }, - "qsubq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vqsubu.v4i32") - }, - "qsubq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.arm.neon.vqsubs.v2i64") - }, - "qsubq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.arm.neon.vqsubu.v2i64") - }, - "rsubhn_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vrsubhn.v8i8") - }, - "rsubhn_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vrsubhn.v8i8") - }, - "rsubhn_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vrsubhn.v4i16") - }, - "rsubhn_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vrsubhn.v4i16") - }, - "rsubhn_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vrsubhn.v2i32") - }, - "rsubhn_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vrsubhn.v2i32") - }, - "abd_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vabds.v8i8") - }, - "abd_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vabdu.v8i8") - }, - "abd_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vabds.v4i16") - }, - "abd_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vabdu.v4i16") - }, - "abd_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vabds.v2i32") - }, - "abd_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vabdu.v2i32") - }, - "abd_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.arm.neon.vabdf.v2f32") - }, - "abdq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vabds.v16i8") - }, - "abdq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vabdu.v16i8") - }, - "abdq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vabds.v8i16") - }, - "abdq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vabdu.v8i16") - }, - "abdq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vabds.v4i32") - }, - "abdq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vabdu.v4i32") - }, - "abdq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.arm.neon.vabdf.v4f32") - }, - "max_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vmaxs.v8i8") - }, - "max_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vmaxu.v8i8") - }, - "max_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vmaxs.v4i16") - }, - "max_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vmaxu.v4i16") - }, - "max_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vmaxs.v2i32") - }, - "max_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vmaxu.v2i32") - }, - "max_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.arm.neon.vmaxf.v2f32") - }, - "maxq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vmaxs.v16i8") - }, - "maxq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vmaxu.v16i8") - }, - "maxq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vmaxs.v8i16") - }, - "maxq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vmaxu.v8i16") - }, - "maxq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vmaxs.v4i32") - }, - "maxq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vmaxu.v4i32") - }, - "maxq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.arm.neon.vmaxf.v4f32") - }, - "min_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vmins.v8i8") - }, - "min_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vminu.v8i8") - }, - "min_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vmins.v4i16") - }, - "min_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vminu.v4i16") - }, - "min_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vmins.v2i32") - }, - "min_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vminu.v2i32") - }, - "min_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.arm.neon.vminf.v2f32") - }, - "minq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vmins.v16i8") - }, - "minq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vminu.v16i8") - }, - "minq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vmins.v8i16") - }, - "minq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vminu.v8i16") - }, - "minq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vmins.v4i32") - }, - "minq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vminu.v4i32") - }, - "minq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.arm.neon.vminf.v4f32") - }, - "shl_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vshls.v8i8") - }, - "shl_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vshlu.v8i8") - }, - "shl_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vshls.v4i16") - }, - "shl_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vshlu.v4i16") - }, - "shl_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vshls.v2i32") - }, - "shl_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vshlu.v2i32") - }, - "shl_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.arm.neon.vshls.v1i64") - }, - "shl_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.arm.neon.vshlu.v1i64") - }, - "shlq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vshls.v16i8") - }, - "shlq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vshlu.v16i8") - }, - "shlq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vshls.v8i16") - }, - "shlq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vshlu.v8i16") - }, - "shlq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vshls.v4i32") - }, - "shlq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vshlu.v4i32") - }, - "shlq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.arm.neon.vshls.v2i64") - }, - "shlq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.arm.neon.vshlu.v2i64") - }, - "qshl_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vqshls.v8i8") - }, - "qshl_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vqshlu.v8i8") - }, - "qshl_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vqshls.v4i16") - }, - "qshl_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vqshlu.v4i16") - }, - "qshl_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vqshls.v2i32") - }, - "qshl_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vqshlu.v2i32") - }, - "qshl_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.arm.neon.vqshls.v1i64") - }, - "qshl_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.arm.neon.vqshlu.v1i64") - }, - "qshlq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vqshls.v16i8") - }, - "qshlq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vqshlu.v16i8") - }, - "qshlq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vqshls.v8i16") - }, - "qshlq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vqshlu.v8i16") - }, - "qshlq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vqshls.v4i32") - }, - "qshlq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vqshlu.v4i32") - }, - "qshlq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.arm.neon.vqshls.v2i64") - }, - "qshlq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.arm.neon.vqshlu.v2i64") - }, - "rshl_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vrshls.v8i8") - }, - "rshl_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vrshlu.v8i8") - }, - "rshl_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vrshls.v4i16") - }, - "rshl_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vrshlu.v4i16") - }, - "rshl_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vrshls.v2i32") - }, - "rshl_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vrshlu.v2i32") - }, - "rshl_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.arm.neon.vrshls.v1i64") - }, - "rshl_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.arm.neon.vrshlu.v1i64") - }, - "rshlq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vrshls.v16i8") - }, - "rshlq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vrshlu.v16i8") - }, - "rshlq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vrshls.v8i16") - }, - "rshlq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vrshlu.v8i16") - }, - "rshlq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vrshls.v4i32") - }, - "rshlq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vrshlu.v4i32") - }, - "rshlq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.arm.neon.vrshls.v2i64") - }, - "rshlq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.arm.neon.vrshlu.v2i64") - }, - "qrshl_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vqrshls.v8i8") - }, - "qrshl_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vqrshlu.v8i8") - }, - "qrshl_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vqrshls.v4i16") - }, - "qrshl_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vqrshlu.v4i16") - }, - "qrshl_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vqrshls.v2i32") - }, - "qrshl_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vqrshlu.v2i32") - }, - "qrshl_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.arm.neon.vqrshls.v1i64") - }, - "qrshl_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.arm.neon.vqrshlu.v1i64") - }, - "qrshlq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vqrshls.v16i8") - }, - "qrshlq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vqrshlu.v16i8") - }, - "qrshlq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vqrshls.v8i16") - }, - "qrshlq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vqrshlu.v8i16") - }, - "qrshlq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vqrshls.v4i32") - }, - "qrshlq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vqrshlu.v4i32") - }, - "qrshlq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.arm.neon.vqrshls.v2i64") - }, - "qrshlq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.arm.neon.vqrshlu.v2i64") - }, - "qshrun_n_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vsqshrun.v8i8") - }, - "qshrun_n_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vsqshrun.v4i16") - }, - "qshrun_n_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vsqshrun.v2i32") - }, - "qrshrun_n_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vsqrshrun.v8i8") - }, - "qrshrun_n_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vsqrshrun.v4i16") - }, - "qrshrun_n_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vsqrshrun.v2i32") - }, - "qshrn_n_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vqshrns.v8i8") - }, - "qshrn_n_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vqshrnu.v8i8") - }, - "qshrn_n_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vqshrns.v4i16") - }, - "qshrn_n_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vqshrnu.v4i16") - }, - "qshrn_n_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vqshrns.v2i32") - }, - "qshrn_n_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vqshrnu.v2i32") - }, - "rshrn_n_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vrshrn.v8i8") - }, - "rshrn_n_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vrshrn.v8i8") - }, - "rshrn_n_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vrshrn.v4i16") - }, - "rshrn_n_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vrshrn.v4i16") - }, - "rshrn_n_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vrshrn.v2i32") - }, - "rshrn_n_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vrshrn.v2i32") - }, - "qrshrn_n_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::U32]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vqrshrns.v8i8") - }, - "qrshrn_n_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U32]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vqrshrnu.v8i8") - }, - "qrshrn_n_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::U32]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vqrshrns.v4i16") - }, - "qrshrn_n_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vqrshrnu.v4i16") - }, - "qrshrn_n_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::U32]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vqrshrns.v2i32") - }, - "qrshrn_n_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vqrshrnu.v2i32") - }, - "sri_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vvsri.v8i8") - }, - "sri_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vvsri.v8i8") - }, - "sri_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vvsri.v4i16") - }, - "sri_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vvsri.v4i16") - }, - "sri_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vvsri.v2i32") - }, - "sri_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vvsri.v2i32") - }, - "sri_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.arm.neon.vvsri.v1i64") - }, - "sri_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.arm.neon.vvsri.v1i64") - }, - "sriq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vvsri.v16i8") - }, - "sriq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vvsri.v16i8") - }, - "sriq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vvsri.v8i16") - }, - "sriq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vvsri.v8i16") - }, - "sriq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vvsri.v4i32") - }, - "sriq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vvsri.v4i32") - }, - "sriq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.arm.neon.vvsri.v2i64") - }, - "sriq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.arm.neon.vvsri.v2i64") - }, - "sli_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vvsli.v8i8") - }, - "sli_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vvsli.v8i8") - }, - "sli_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vvsli.v4i16") - }, - "sli_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vvsli.v4i16") - }, - "sli_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vvsli.v2i32") - }, - "sli_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vvsli.v2i32") - }, - "sli_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.arm.neon.vvsli.v1i64") - }, - "sli_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.arm.neon.vvsli.v1i64") - }, - "sliq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vvsli.v16i8") - }, - "sliq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vvsli.v16i8") - }, - "sliq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vvsli.v8i16") - }, - "sliq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vvsli.v8i16") - }, - "sliq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vvsli.v4i32") - }, - "sliq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vvsli.v4i32") - }, - "sliq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.arm.neon.vvsli.v2i64") - }, - "sliq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.arm.neon.vvsli.v2i64") - }, - "vqmovn_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vqxtns.v8i8") - }, - "vqmovn_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vqxtnu.v8i8") - }, - "vqmovn_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vqxtns.v4i16") - }, - "vqmovn_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vqxtnu.v4i16") - }, - "vqmovn_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I64x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vqxtns.v2i32") - }, - "vqmovn_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U64x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vqxtnu.v2i32") - }, - "abs_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vabs.v8i8") - }, - "abs_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vabs.v4i16") - }, - "abs_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vabs.v2i32") - }, - "absq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vabs.v16i8") - }, - "absq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vabs.v8i16") - }, - "absq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vabs.v4i32") - }, - "abs_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.fabs.v2f32") - }, - "absq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.fabs.v4f32") - }, - "qabs_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vsqabs.v8i8") - }, - "qabs_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vsqabs.v4i16") - }, - "qabs_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vsqabs.v2i32") - }, - "qabsq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vsqabs.v16i8") - }, - "qabsq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vsqabs.v8i16") - }, - "qabsq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vsqabs.v4i32") - }, - "qneg_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vsqneg.v8i8") - }, - "qneg_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vsqneg.v4i16") - }, - "qneg_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vsqneg.v2i32") - }, - "qnegq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vsqneg.v16i8") - }, - "qnegq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vsqneg.v8i16") - }, - "qnegq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vsqneg.v4i32") - }, - "clz_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.ctlz.v8i8") - }, - "clz_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.ctlz.v8i8") - }, - "clz_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.ctlz.v4i16") - }, - "clz_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.ctlz.v4i16") - }, - "clz_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.ctlz.v2i32") - }, - "clz_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.ctlz.v2i32") - }, - "clzq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.ctlz.v16i8") - }, - "clzq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.ctlz.v16i8") - }, - "clzq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ctlz.v8i16") - }, - "clzq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.ctlz.v8i16") - }, - "clzq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ctlz.v4i32") - }, - "clzq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ctlz.v4i32") - }, - "cls_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vcls.v8i8") - }, - "cls_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vcls.v8i8") - }, - "cls_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vcls.v4i16") - }, - "cls_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vcls.v4i16") - }, - "cls_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vcls.v2i32") - }, - "cls_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vcls.v2i32") - }, - "clsq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vcls.v16i8") - }, - "clsq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vcls.v16i8") - }, - "clsq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vcls.v8i16") - }, - "clsq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vcls.v8i16") - }, - "clsq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vcls.v4i32") - }, - "clsq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vcls.v4i32") - }, - "cnt_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.ctpop.v8i8") - }, - "cnt_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.ctpop.v8i8") - }, - "cntq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.ctpop.v16i8") - }, - "cntq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.ctpop.v16i8") - }, - "recpe_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vrecpe.v2i32") - }, - "recpe_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.arm.neon.vrecpe.v2f32") - }, - "recpeq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vrecpe.v4i32") - }, - "recpeq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.arm.neon.vrecpe.v4f32") - }, - "recps_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.arm.neon.vfrecps.v2f32") - }, - "recpsq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.arm.neon.vfrecps.v4f32") - }, - "sqrt_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.sqrt.v2f32") - }, - "sqrtq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.sqrt.v4f32") - }, - "rsqrte_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vrsqrte.v2i32") - }, - "rsqrte_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.arm.neon.vrsqrte.v2f32") - }, - "rsqrteq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vrsqrte.v4i32") - }, - "rsqrteq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.arm.neon.vrsqrte.v4f32") - }, - "rsqrts_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.arm.neon.vrsqrts.v2f32") - }, - "rsqrtsq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.arm.neon.vrsqrts.v4f32") - }, - "bsl_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vbsl.v8i8") - }, - "bsl_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vbsl.v8i8") - }, - "bsl_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vbsl.v4i16") - }, - "bsl_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vbsl.v4i16") - }, - "bsl_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vbsl.v2i32") - }, - "bsl_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vbsl.v2i32") - }, - "bsl_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::I64x1]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.arm.neon.vbsl.v1i64") - }, - "bsl_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U64x1]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.arm.neon.vbsl.v1i64") - }, - "bslq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vbsl.v16i8") - }, - "bslq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vbsl.v16i8") - }, - "bslq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vbsl.v8i16") - }, - "bslq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vbsl.v8i16") - }, - "bslq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vbsl.v4i32") - }, - "bslq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vbsl.v4i32") - }, - "bslq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.arm.neon.vbsl.v2i64") - }, - "bslq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.arm.neon.vbsl.v2i64") - }, - "padd_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vpadd.v8i8") - }, - "padd_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vpadd.v8i8") - }, - "padd_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vpadd.v4i16") - }, - "padd_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vpadd.v4i16") - }, - "padd_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vpadd.v2i32") - }, - "padd_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vpadd.v2i32") - }, - "padd_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.arm.neon.vpadd.v2f32") - }, - "paddl_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x8]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vpaddls.v4i16.v8i8") - }, - "paddl_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x8]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vpaddlu.v4i16.v8i8") - }, - "paddl_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x4]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vpaddls.v2i32.v4i16") - }, - "paddl_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x4]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vpaddlu.v2i32.v4i16") - }, - "paddl_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x2]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.arm.neon.vpaddls.v1i64.v2i32") - }, - "paddl_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.arm.neon.vpaddlu.v1i64.v2i32") - }, - "paddlq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vpaddls.v8i16.v16i8") - }, - "paddlq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x16]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vpaddlu.v8i16.v16i8") - }, - "paddlq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vpaddls.v4i32.v8i16") - }, - "paddlq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vpaddlu.v4i32.v8i16") - }, - "paddlq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.arm.neon.vpaddls.v2i64.v4i32") - }, - "paddlq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.arm.neon.vpaddlu.v2i64.v4i32") - }, - "padal_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I8x8]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vpadals.v4i16.v4i16") - }, - "padal_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U8x8]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vpadalu.v4i16.v4i16") - }, - "padal_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I16x4]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vpadals.v2i32.v2i32") - }, - "padal_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U16x4]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vpadalu.v2i32.v2i32") - }, - "padal_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x1, &::I32x2]; &INPUTS }, - output: &::I64x1, - definition: Named("llvm.arm.neon.vpadals.v1i64.v1i64") - }, - "padal_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x1, &::U32x2]; &INPUTS }, - output: &::U64x1, - definition: Named("llvm.arm.neon.vpadalu.v1i64.v1i64") - }, - "padalq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I8x16]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vpadals.v8i16.v8i16") - }, - "padalq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U8x16]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vpadalu.v8i16.v8i16") - }, - "padalq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I16x8]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vpadals.v4i32.v4i32") - }, - "padalq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U16x8]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vpadalu.v4i32.v4i32") - }, - "padalq_s64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I64x2, &::I32x4]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.arm.neon.vpadals.v2i64.v2i64") - }, - "padalq_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U32x4]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.arm.neon.vpadalu.v2i64.v2i64") - }, - "pmax_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vpmaxs.v8i8") - }, - "pmax_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vpmaxu.v8i8") - }, - "pmax_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vpmaxs.v4i16") - }, - "pmax_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vpmaxu.v4i16") - }, - "pmax_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vpmaxs.v2i32") - }, - "pmax_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vpmaxu.v2i32") - }, - "pmax_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.arm.neon.vpmaxf.v2f32") - }, - "pmin_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vpmins.v8i8") - }, - "pmin_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vpminu.v8i8") - }, - "pmin_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x4, &::I16x4]; &INPUTS }, - output: &::I16x4, - definition: Named("llvm.arm.neon.vpmins.v4i16") - }, - "pmin_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x4, &::U16x4]; &INPUTS }, - output: &::U16x4, - definition: Named("llvm.arm.neon.vpminu.v4i16") - }, - "pmin_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x2, &::I32x2]; &INPUTS }, - output: &::I32x2, - definition: Named("llvm.arm.neon.vpmins.v2i32") - }, - "pmin_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.arm.neon.vpminu.v2i32") - }, - "pmin_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x2, &::F32x2]; &INPUTS }, - output: &::F32x2, - definition: Named("llvm.arm.neon.vpminf.v2f32") - }, - "pminq_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.arm.neon.vpmins.v16i8") - }, - "pminq_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.arm.neon.vpminu.v16i8") - }, - "pminq_s16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.arm.neon.vpmins.v8i16") - }, - "pminq_u16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.arm.neon.vpminu.v8i16") - }, - "pminq_s32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.arm.neon.vpmins.v4i32") - }, - "pminq_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.arm.neon.vpminu.v4i32") - }, - "pminq_f32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.arm.neon.vpminf.v4f32") - }, - "tbl1_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x8, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vtbl1") - }, - "tbl1_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vtbl1") - }, - "tbx1_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vtbx1") - }, - "tbx1_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vtbx1") - }, - "tbl2_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vtbl2") - }, - "tbl2_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vtbl2") - }, - "tbx2_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vtbx2") - }, - "tbx2_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 2] = [&::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vtbx2") - }, - "tbl3_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vtbl3") - }, - "tbl3_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vtbl3") - }, - "tbx3_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vtbx3") - }, - "tbx3_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 3] = [&::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vtbx3") - }, - "tbl4_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vtbl4") - }, - "tbl4_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vtbl4") - }, - "tbx4_s8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::I8x8, &::I8x8, &::I8x8, &::I8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::I8x8, - definition: Named("llvm.arm.neon.vtbx4") - }, - "tbx4_u8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x8, { static AGG: Type = Type::Aggregate(true, { static PARTS: [&'static Type; 4] = [&::U8x8, &::U8x8, &::U8x8, &::U8x8]; &PARTS }); &AGG }, &::U8x8]; &INPUTS }, - output: &::U8x8, - definition: Named("llvm.arm.neon.vtbx4") - }, - _ => return None, - }) -} diff --git a/src/librustc_platform_intrinsics/hexagon.rs b/src/librustc_platform_intrinsics/hexagon.rs deleted file mode 100644 index fd0f3a46b39cd..0000000000000 --- a/src/librustc_platform_intrinsics/hexagon.rs +++ /dev/null @@ -1,2924 +0,0 @@ -// DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py -// ignore-tidy-linelength - -#![allow(unused_imports)] - -use {Intrinsic, Type}; -use IntrinsicDef::Named; - -pub fn find(name: &str) -> Option { - if !name.starts_with("Q6_") { return None } - Some(match &name["Q6_".len()..] { - "R_vextract64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x16, &::U32]; &INPUTS }, - output: &::U32, - definition: Named("llvm.hexagon.V6.extractw") - }, - "R_vextract128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x32, &::U32]; &INPUTS }, - output: &::U32, - definition: Named("llvm.hexagon.V6.extractw.128B") - }, - "V_lo64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x32]; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.lo") - }, - "V_lo128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x64]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.lo.128B") - }, - "V_hi64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x32]; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.hi") - }, - "V_hi128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x64]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.hi.128B") - }, - "V_vsplat_R64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32]; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.lvsplatuw") - }, - "V_vsplat_R128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.lvsplatuw.128B") - }, - "Q_and_QQ64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.pred.and") - }, - "Q_and_QQ128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.pred.and.128B") - }, - "Q_not_Q64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.pred.not") - }, - "Q_not_Q128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.pred.not.128B") - }, - "Q_or_QQ64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.pred.or") - }, - "Q_or_QQ128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.pred.or.128B") - }, - "Q_xor_QQ64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32x2]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.pred.xor") - }, - "Q_xor_QQ128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.pred.xor.128B") - }, - "Vub_vabsdiff_VubVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vabsdiffub") - }, - "Vuh_vabsdiff_VuhVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vabsdiffuh") - }, - "Vub_vabsdiff_VubVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vabsdiffub.128B") - }, - "Vuh_vabsdiff_VuhVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vabsdiffuh.128B") - }, - "Vuh_vabsdiff_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vabsdiffh") - }, - "Vuw_vabsdiff_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.vabsdiffw") - }, - "Vuh_vabsdiff_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vabsdiffh.128B") - }, - "Vuw_vabsdiff_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vabsdiffw.128B") - }, - "Vh_vabs_Vh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vabsh") - }, - "Vw_vabs_Vw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vabsw") - }, - "Vh_vabs_Vh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vabsh.128B") - }, - "Vw_vabs_Vw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vabsw.128B") - }, - "Vh_vabs_Vh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vabsh.sat") - }, - "Vw_vabs_Vw_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vabsw.sat") - }, - "Vh_vabs_Vh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vabsh.sat.128B") - }, - "Vw_vabs_Vw_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vabsw.sat.128B") - }, - "Vb_vadd_VbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vaddb") - }, - "Vh_vadd_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vaddh") - }, - "Vw_vadd_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vaddw") - }, - "Vb_vadd_VbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vaddb.128B") - }, - "Vh_vadd_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vaddh.128B") - }, - "Vw_vadd_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vaddw.128B") - }, - "Vh_vadd_VhVh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vaddhsat") - }, - "Vw_vadd_VwVw_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vaddwsat") - }, - "Vh_vadd_VhVh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vaddhsat.128B") - }, - "Vw_vadd_VwVw_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vaddwsat.128B") - }, - "Vub_vadd_VubVub_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vaddubsat") - }, - "Vuh_vadd_VuhVuh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vadduhsat") - }, - "Vub_vadd_VubVub_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vaddubsat.128B") - }, - "Vuh_vadd_VuhVuh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vadduhsat.128B") - }, - "Wb_vadd_WbWb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vaddb.dv") - }, - "Wh_vadd_WhWh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vaddh.dv") - }, - "Ww_vadd_WwWw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vaddw.dv") - }, - "Wb_vadd_WbWb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x256, &::I8x256]; &INPUTS }, - output: &::I8x256, - definition: Named("llvm.hexagon.V6.vaddb.dv.128B") - }, - "Wh_vadd_WhWh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::I16x128]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vaddh.dv.128B") - }, - "Ww_vadd_WwWw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x64, &::I32x64]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vaddw.dv.128B") - }, - "Wh_vadd_WhWh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vaddhsat.dv") - }, - "Ww_vadd_WwWw_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vaddwsat.dv") - }, - "Wh_vadd_WhWh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::I16x128]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vaddhsat.dv.128B") - }, - "Ww_vadd_WwWw_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x64, &::I32x64]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vaddwsat.dv.128B") - }, - "Wub_vadd_WubWub_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vaddubsat.dv") - }, - "Wuh_vadd_WuhWuh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vadduhsat.dv") - }, - "Wub_vadd_WubWub_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U8x256]; &INPUTS }, - output: &::U8x256, - definition: Named("llvm.hexagon.V6.vaddubsat.dv.128B") - }, - "Wuh_vadd_WuhWuh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x128, &::U16x128]; &INPUTS }, - output: &::U16x128, - definition: Named("llvm.hexagon.V6.vadduhsat.dv.128B") - }, - "V_valign_VVR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U8x64, &::U32]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.valignb") - }, - "V_valign_VVR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U8x128, &::U32]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.valignb.128B") - }, - "V_valign_VVI64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U8x64, &::U32]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.valignbi") - }, - "V_valign_VVI128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U8x128, &::U32]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.valignbi.128B") - }, - "V_vlalign_VVR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U8x64, &::U32]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vlalignb") - }, - "V_vlalign_VVR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U8x128, &::U32]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vlalignb.128B") - }, - "V_vlalign_VVI64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U8x64, &::U32]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vlalignbi") - }, - "V_vlalign_VVI128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U8x128, &::U32]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vlalignbi.128B") - }, - "V_vand_VV64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vand") - }, - "V_vand_VV128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vand.128B") - }, - "V_vand_QR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x2, &::U32]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vandqrt") - }, - "V_vand_QR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vandqrt.128B") - }, - "V_vandor_VQR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U32x2, &::U32]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vandqrt.acc") - }, - "V_vandor_VQR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U32x4, &::U32]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vandqrt.acc.128B") - }, - "Q_vand_VR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vandvrt") - }, - "Q_vand_VR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vandvrt.128B") - }, - "Q_vandor_QVR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U8x64, &::U32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vandvrt") - }, - "Q_vandor_QVR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U8x128, &::U32]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vandvrt.128B") - }, - "Vh_vasl_VhR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vaslh") - }, - "Vw_vasl_VwR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vaslw") - }, - "Vh_vasl_VhR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vaslh.128B") - }, - "Vw_vasl_VwR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vaslw.128B") - }, - "Vh_vasl_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vaslhv") - }, - "Vw_vasl_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vaslwv") - }, - "Vh_vasl_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vaslhv.128B") - }, - "Vw_vasl_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vaslwv.128B") - }, - "Vw_vaslacc_VwVwR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vaslw.acc") - }, - "Vw_vaslacc_VwVwR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vaslw.acc.128B") - }, - "Vh_vasr_VhR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vasrh") - }, - "Vw_vasr_VwR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vasrw") - }, - "Vh_vasr_VhR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vasrh.128B") - }, - "Vw_vasr_VwR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vasrw.128B") - }, - "Vh_vasr_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vasrhv") - }, - "Vw_vasr_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vasrwv") - }, - "Vh_vasr_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vasrhv.128B") - }, - "Vw_vasr_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vasrwv.128B") - }, - "Vw_vasracc_VwVwR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vasrw.acc") - }, - "Vw_vasracc_VwVwR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vasrw.acc.128B") - }, - "Vh_vasr_VwVwR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vasrhw") - }, - "Vh_vasr_VwVwR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vasrhw.128B") - }, - "Vb_vasr_VhVhR_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::I16x32, &::U32]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vasrhbsat") - }, - "Vub_vasr_VhVhR_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::I16x32, &::U32]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vasrhbsat") - }, - "Vh_vasr_VwVwR_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vasrwhsat") - }, - "Vuh_vasr_VwVwR_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vasrwhsat") - }, - "Vb_vasr_VhVhR_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I16x64, &::U32]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vasrhbsat.128B") - }, - "Vub_vasr_VhVhR_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I16x64, &::U32]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vasrhbsat.128B") - }, - "Vh_vasr_VwVwR_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vasrwhsat.128B") - }, - "Vuh_vasr_VwVwR_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vasrwhsat.128B") - }, - "Vb_vasr_VhVhR_rnd_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::I16x32, &::U32]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vasrhbrndsat") - }, - "Vub_vasr_VhVhR_rnd_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::I16x32, &::U32]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vasrhbrndsat") - }, - "Vh_vasr_VwVwR_rnd_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vasrwhrndsat") - }, - "Vuh_vasr_VwVwR_rnd_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vasrwhrndsat") - }, - "Vb_vasr_VhVhR_rnd_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I16x64, &::U32]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vasrhbrndsat.128B") - }, - "Vub_vasr_VhVhR_rnd_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I16x64, &::U32]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vasrhbrndsat.128B") - }, - "Vh_vasr_VwVwR_rnd_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vasrwhrndsat.128B") - }, - "Vuh_vasr_VwVwR_rnd_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vasrwhrndsat.128B") - }, - "V_equals_V64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x16]; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.vassign") - }, - "V_equals_V128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vassign.128B") - }, - "W_equals_W64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vassignp") - }, - "W_equals_W128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x64]; &INPUTS }, - output: &::U32x64, - definition: Named("llvm.hexagon.V6.vassignp.128B") - }, - "Vh_vavg_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vavgh") - }, - "Vw_vavg_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vavgw") - }, - "Vh_vavg_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vavgh.128B") - }, - "Vw_vavg_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vavgw.128B") - }, - "Vub_vavg_VubVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vavgub") - }, - "Vuh_vavg_VuhVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vavguh") - }, - "Vub_vavg_VubVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vavgub.128B") - }, - "Vuh_vavg_VuhVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vavguh.128B") - }, - "Vh_vavg_VhVh_rnd64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vavgrndh") - }, - "Vw_vavg_VwVw_rnd64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vavgrndw") - }, - "Vh_vavg_VhVh_rnd128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vavgrndh.128B") - }, - "Vw_vavg_VwVw_rnd128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vavgrndw.128B") - }, - "Vub_vavg_VubVub_rnd64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vavgrndub") - }, - "Vuh_vavg_VuhVuh_rnd64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vavgrnduh") - }, - "Vub_vavg_VubVub_rnd128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vavgrndub.128B") - }, - "Vuh_vavg_VuhVuh_rnd128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vavgrnduh.128B") - }, - "Vuh_vcl0_Vuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vcl0h") - }, - "Vuw_vcl0_Vuw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x16]; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.vcl0w") - }, - "Vuh_vcl0_Vuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vcl0h.128B") - }, - "Vuw_vcl0_Vuw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U32x32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vcl0w.128B") - }, - "W_vcombine_VV64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vcombine") - }, - "W_vcombine_VV128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x256, - definition: Named("llvm.hexagon.V6.vcombine.128B") - }, - "V_vzero64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.vd0") - }, - "V_vzero128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vd0.128B") - }, - "Vb_vdeal_Vb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x64]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vdealb") - }, - "Vh_vdeal_Vh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vdealh") - }, - "Vb_vdeal_Vb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vdealb.128B") - }, - "Vh_vdeal_Vh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vdealh.128B") - }, - "Vb_vdeale_VbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vdealb4w") - }, - "Vb_vdeale_VbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vdealb4w.128B") - }, - "W_vdeal_VVR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U8x64, &::U32]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vdealvdd") - }, - "W_vdeal_VVR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U8x128, &::U32]; &INPUTS }, - output: &::U8x256, - definition: Named("llvm.hexagon.V6.vdealvdd.128B") - }, - "V_vdelta_VV64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vdelta") - }, - "V_vdelta_VV128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vdelta.128B") - }, - "Vh_vdmpy_VubRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vdmpybus") - }, - "Vh_vdmpy_VubRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vdmpybus.128B") - }, - "Vh_vdmpyacc_VhVubRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::U8x64, &::U32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vdmpybus.acc") - }, - "Vh_vdmpyacc_VhVubRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::U8x128, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vdmpybus.acc.128B") - }, - "Wh_vdmpy_WubRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vdmpybus.dv") - }, - "Wh_vdmpy_WubRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U32]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vdmpybus.dv.128B") - }, - "Wh_vdmpyacc_WhWubRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::U8x128, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vdmpybus.dv.acc") - }, - "Wh_vdmpyacc_WhWubRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::U8x256, &::U32]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vdmpybus.dv.acc.128B") - }, - "Vw_vdmpy_VhRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vdmpyhb") - }, - "Vw_vdmpy_VhRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhb.128B") - }, - "Vw_vdmpyacc_VwVhRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I16x32, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vdmpyhb.acc") - }, - "Vw_vdmpyacc_VwVhRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhb.acc.128B") - }, - "Ww_vdmpy_WhRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhb.dv") - }, - "Ww_vdmpy_WhRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::U32]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vdmpyhb.dv.128B") - }, - "Ww_vdmpyacc_WwWhRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhb.dv.acc") - }, - "Ww_vdmpyacc_WwWhRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::I16x128, &::U32]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vdmpyhb.dv.acc.128B") - }, - "Vw_vdmpy_WwRh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vdmpyhisat") - }, - "Vw_vdmpy_WwRh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhisat.128B") - }, - "Vw_vdmpy_VhRh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vdmpyhsat") - }, - "Vw_vdmpy_VhRh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhsat.128B") - }, - "Vw_vdmpy_WhRuh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vdmpyhsuisat") - }, - "Vw_vdmpy_WhRuh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhsuisat.128B") - }, - "Vw_vdmpy_VhRuh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vdmpyhsusat") - }, - "Vw_vdmpy_VhRuh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhsusat.128B") - }, - "Vw_vdmpy_VhVh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vdmpyhvsat") - }, - "Vw_vdmpy_VhVh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhvsat.128B") - }, - "Vw_vdmpyacc_VwWwRh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x32, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vdmpyhisat_acc") - }, - "Vw_vdmpyacc_VwWwRh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhisat_acc.128B") - }, - "Wuw_vdsad_WuhRuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vdsaduh") - }, - "Wuw_vdsad_WuhRuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x128, &::U32]; &INPUTS }, - output: &::U32x64, - definition: Named("llvm.hexagon.V6.vdsaduh.128B") - }, - "Wuw_vdsadacc_WuwWuhRuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U16x64, &::U32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vdsaduh.acc") - }, - "Wuw_vdsadacc_WuwWuhRuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x64, &::U16x128, &::U32]; &INPUTS }, - output: &::U32x64, - definition: Named("llvm.hexagon.V6.vdsaduh.acc.128B") - }, - "Vw_vdmpyacc_VwVhRh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I16x32, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vdmpyhsat_acc") - }, - "Vw_vdmpyacc_VwVhRh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhsat_acc.128B") - }, - "Vw_vdmpyacc_VwWhRuh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I16x64, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vdmpyhsuisat_acc") - }, - "Vw_vdmpyacc_VwWhRuh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x128, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhsuisat_acc.128B") - }, - "Vw_vdmpyacc_VwVhRuh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I16x32, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vdmpyhsusat_acc") - }, - "Vw_vdmpyacc_VwVhRuh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhsusat_acc.128B") - }, - "Vw_vdmpyacc_VwVhVh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I16x32, &::I16x32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vdmpyhvsat_acc") - }, - "Vw_vdmpyacc_VwVhVh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::I16x64]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vdmpyhvsat_acc.128B") - }, - "Q_vcmp_eq_VbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.veqb") - }, - "Q_vcmp_eq_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.veqh") - }, - "Q_vcmp_eq_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.veqw") - }, - "Q_vcmp_eq_VbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.veqb.128B") - }, - "Q_vcmp_eq_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.veqh.128B") - }, - "Q_vcmp_eq_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.veqw.128B") - }, - "Q_vcmp_eqand_QVbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.veqb.and") - }, - "Q_vcmp_eqand_QVhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.veqh.and") - }, - "Q_vcmp_eqand_QVwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.veqw.and") - }, - "Q_vcmp_eqand_QVbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.veqb.and.128B") - }, - "Q_vcmp_eqand_QVhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.veqh.and.128B") - }, - "Q_vcmp_eqand_QVwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.veqw.and.128B") - }, - "Q_vcmp_eqor_QVbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.veqb.or") - }, - "Q_vcmp_eqor_QVhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.veqh.or") - }, - "Q_vcmp_eqor_QVwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.veqw.or") - }, - "Q_vcmp_eqor_QVbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.veqb.or.128B") - }, - "Q_vcmp_eqor_QVhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.veqh.or.128B") - }, - "Q_vcmp_eqor_QVwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.veqw.or.128B") - }, - "Q_vcmp_eqxacc_QVbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.veqb.xor") - }, - "Q_vcmp_eqxacc_QVhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.veqh.xor") - }, - "Q_vcmp_eqxacc_QVwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.veqw.xor") - }, - "Q_vcmp_eqxacc_QVbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.veqb.xor.128B") - }, - "Q_vcmp_eqxacc_QVhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.veqh.xor.128B") - }, - "Q_vcmp_eqxacc_QVwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.veqw.xor.128B") - }, - "Q_vcmp_gt_VbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtb") - }, - "Q_vcmp_gt_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgth") - }, - "Q_vcmp_gt_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtw") - }, - "Q_vcmp_gt_VbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtb.128B") - }, - "Q_vcmp_gt_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgth.128B") - }, - "Q_vcmp_gt_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtw.128B") - }, - "Q_vcmp_gt_VubVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtub") - }, - "Q_vcmp_gt_VuhVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtuh") - }, - "Q_vcmp_gt_VubVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtub.128B") - }, - "Q_vcmp_gt_VuhVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtuh.128B") - }, - "Q_vcmp_gtand_QVbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtb.and") - }, - "Q_vcmp_gtand_QVhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgth.and") - }, - "Q_vcmp_gtand_QVwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtw.and") - }, - "Q_vcmp_gtand_QVbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtb.and.128B") - }, - "Q_vcmp_gtand_QVhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgth.and.128B") - }, - "Q_vcmp_gtand_QVwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtw.and.128B") - }, - "Q_vcmp_gtand_QVubVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U8x64, &::U8x64]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtub.and") - }, - "Q_vcmp_gtand_QVuhVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U16x32, &::U16x32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtuh.and") - }, - "Q_vcmp_gtand_QVubVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U8x128, &::U8x128]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtub.and.128B") - }, - "Q_vcmp_gtand_QVuhVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U16x64, &::U16x64]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtuh.and.128B") - }, - "Q_vcmp_gtor_QVbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtb.or") - }, - "Q_vcmp_gtor_QVhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgth.or") - }, - "Q_vcmp_gtor_QVwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtw.or") - }, - "Q_vcmp_gtor_QVbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtb.or.128B") - }, - "Q_vcmp_gtor_QVhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgth.or.128B") - }, - "Q_vcmp_gtor_QVwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtw.or.128B") - }, - "Q_vcmp_gtor_QVubVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U8x64, &::U8x64]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtub.or") - }, - "Q_vcmp_gtor_QVuhVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U16x32, &::U16x32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtuh.or") - }, - "Q_vcmp_gtor_QVubVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U8x128, &::U8x128]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtub.or.128B") - }, - "Q_vcmp_gtor_QVuhVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U16x64, &::U16x64]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtuh.or.128B") - }, - "Q_vcmp_gtxacc_QVbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtb.xor") - }, - "Q_vcmp_gtxacc_QVhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgth.xor") - }, - "Q_vcmp_gtxacc_QVwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtw.xor") - }, - "Q_vcmp_gtxacc_QVbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtb.xor.128B") - }, - "Q_vcmp_gtxacc_QVhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgth.xor.128B") - }, - "Q_vcmp_gtxacc_QVwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtw.xor.128B") - }, - "Q_vcmp_gtxacc_QVubVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U8x64, &::U8x64]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtub.xor") - }, - "Q_vcmp_gtxacc_QVuhVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U16x32, &::U16x32]; &INPUTS }, - output: &::U32x2, - definition: Named("llvm.hexagon.V6.vgtuh.xor") - }, - "Q_vcmp_gtxacc_QVubVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U8x128, &::U8x128]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtub.xor.128B") - }, - "Q_vcmp_gtxacc_QVuhVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U16x64, &::U16x64]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.hexagon.V6.vgtuh.xor.128B") - }, - "Vw_vinsert_VwR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vinsertwr") - }, - "Vw_vinsert_VwR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vinsertwr.128B") - }, - "Vuh_vlsr_VuhR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vlsrh") - }, - "Vuw_vlsr_VuwR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x16, &::U32]; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.vlsrw") - }, - "Vuh_vlsr_VuhR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U32]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vlsrh.128B") - }, - "Vuw_vlsr_VuwR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x32, &::U32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vlsrw.128B") - }, - "Vh_vlsr_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vlsrhv") - }, - "Vw_vlsr_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vlsrwv") - }, - "Vh_vlsr_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vlsrhv.128B") - }, - "Vw_vlsr_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vlsrwv.128B") - }, - "Vb_vlut32_VbVbR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x64, &::I8x64, &::U32]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vlutvvb") - }, - "Vb_vlut32_VbVbR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x128, &::I8x128, &::U32]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vlutvvb.128B") - }, - "Wh_vlut16_VbVhR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x64, &::I16x32, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vlutvwh") - }, - "Wh_vlut16_VbVhR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x128, &::I16x64, &::U32]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vlutvwh.128B") - }, - "Vb_vlut32or_VbVbVbR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 4] = [&::I8x64, &::I8x64, &::I8x64, &::U32]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vlutvvb.oracc") - }, - "Vb_vlut32or_VbVbVbR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 4] = [&::I8x128, &::I8x128, &::I8x128, &::U32]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vlutvvb.oracc.128B") - }, - "Wh_vlut16or_WhVbVhR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 4] = [&::I16x64, &::I8x64, &::I16x32, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vlutvwh.oracc") - }, - "Wh_vlut16or_WhVbVhR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 4] = [&::I16x128, &::I8x128, &::I16x64, &::U32]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vlutvwh.oracc.128B") - }, - "Vh_vmax_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vmaxh") - }, - "Vw_vmax_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmaxw") - }, - "Vh_vmax_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmaxh.128B") - }, - "Vw_vmax_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmaxw.128B") - }, - "Vub_vmax_VubVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vmaxub") - }, - "Vuh_vmax_VuhVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vmaxuh") - }, - "Vub_vmax_VubVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vmaxub.128B") - }, - "Vuh_vmax_VuhVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vmaxuh.128B") - }, - "Vh_vmin_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vminh") - }, - "Vw_vmin_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vminw") - }, - "Vh_vmin_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vminh.128B") - }, - "Vw_vmin_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vminw.128B") - }, - "Vub_vmin_VubVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vminub") - }, - "Vuh_vmin_VuhVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vminuh") - }, - "Vub_vmin_VubVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vminub.128B") - }, - "Vuh_vmin_VuhVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vminuh.128B") - }, - "Wh_vmpa_WubRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpabus") - }, - "Wh_vmpa_WubRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U32]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vmpabus.128B") - }, - "Wh_vmpaacc_WhWubRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::U8x128, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpabus.acc") - }, - "Wh_vmpaacc_WhWubRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::U8x256, &::U32]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vmpabus.acc.128B") - }, - "Wh_vmpa_WubWb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::I8x128]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpabusv") - }, - "Wh_vmpa_WubWub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpabuuv") - }, - "Wh_vmpa_WubWb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::I8x256]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vmpabusv.128B") - }, - "Wh_vmpa_WubWub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U8x256]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vmpabuuv.128B") - }, - "Ww_vmpa_WhRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpahb") - }, - "Ww_vmpa_WhRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::U32]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vmpahb.128B") - }, - "Ww_vmpaacc_WwWhRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpahb.acc") - }, - "Ww_vmpaacc_WwWhRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::I16x128, &::U32]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vmpahb.acc.128B") - }, - "Wh_vmpy_VbVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::U8x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpybus") - }, - "Ww_vmpy_VhVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U16x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyhus") - }, - "Wh_vmpy_VbVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::U8x128]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vmpybus.128B") - }, - "Ww_vmpy_VhVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U16x64]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vmpyhus.128B") - }, - "Wh_vmpyacc_WhVbVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I8x64, &::U8x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpybus.acc") - }, - "Ww_vmpyacc_WwVhVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x32, &::U16x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyhus.acc") - }, - "Wh_vmpyacc_WhVbVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::I8x128, &::U8x128]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vmpybus.acc.128B") - }, - "Ww_vmpyacc_WwVhVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::I16x64, &::U16x64]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vmpyhus.acc.128B") - }, - "Wh_vmpy_VubVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::I8x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpybusv") - }, - "Wh_vmpy_VubVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::I8x128]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vmpybusv.128B") - }, - "Wh_vmpyacc_WhVubVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::U8x64, &::I8x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpybusv.acc") - }, - "Wh_vmpyacc_WhVubVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::U8x128, &::I8x128]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vmpybusv.acc.128B") - }, - "Wh_vmpy_VbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpybv") - }, - "Wuh_vmpy_VubVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vmpyubv") - }, - "Ww_vmpy_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyhv") - }, - "Wuw_vmpy_VuhVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vmpyuhv") - }, - "Wh_vmpy_VbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vmpybv.128B") - }, - "Wuh_vmpy_VubVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U16x128, - definition: Named("llvm.hexagon.V6.vmpyubv.128B") - }, - "Ww_vmpy_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vmpyhv.128B") - }, - "Wuw_vmpy_VuhVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U32x64, - definition: Named("llvm.hexagon.V6.vmpyuhv.128B") - }, - "Wh_vmpyacc_WhVbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I8x64, &::I8x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpybv.acc") - }, - "Wuh_vmpyacc_WuhVubVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U16x64, &::U8x64, &::U8x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vmpyubv.acc") - }, - "Ww_vmpyacc_WwVhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x32, &::I16x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyhv.acc") - }, - "Wuw_vmpyacc_WuwVuhVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U16x32, &::U16x32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vmpyuhv.acc") - }, - "Wh_vmpyacc_WhVbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::I8x128, &::I8x128]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vmpybv.acc.128B") - }, - "Wuh_vmpyacc_WuhVubVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U16x128, &::U8x128, &::U8x128]; &INPUTS }, - output: &::U16x128, - definition: Named("llvm.hexagon.V6.vmpyubv.acc.128B") - }, - "Ww_vmpyacc_WwVhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::I16x64, &::I16x64]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vmpyhv.acc.128B") - }, - "Wuw_vmpyacc_WuwVuhVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x64, &::U16x64, &::U16x64]; &INPUTS }, - output: &::U32x64, - definition: Named("llvm.hexagon.V6.vmpyuhv.acc.128B") - }, - "Vw_vmpye_VwVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U16x32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyewuh") - }, - "Vw_vmpye_VwVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U16x64]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyewuh.128B") - }, - "Ww_vmpy_VhRh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyh") - }, - "Wuw_vmpy_VuhRuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vmpyuh") - }, - "Ww_vmpy_VhRh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vmpyh.128B") - }, - "Wuw_vmpy_VuhRuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U32]; &INPUTS }, - output: &::U32x64, - definition: Named("llvm.hexagon.V6.vmpyuh.128B") - }, - "Ww_vmpyacc_WwVhRh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x32, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyhsat.acc") - }, - "Ww_vmpyacc_WwVhRh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::I16x64, &::U32]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vmpyhsat.acc.128B") - }, - "Vw_vmpy_VhRh_s1_rnd_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyhsrs") - }, - "Vw_vmpy_VhRh_s1_rnd_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyhsrs.128B") - }, - "Vw_vmpy_VhRh_s1_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyhss") - }, - "Vw_vmpy_VhRh_s1_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyhss.128B") - }, - "Vh_vmpy_VhVh_s1_rnd_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vmpyhvsrs") - }, - "Vh_vmpy_VhVh_s1_rnd_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpyhvsrs.128B") - }, - "Vw_vmpyieo_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyieoh") - }, - "Vw_vmpyieo_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyieoh.128B") - }, - "Vw_vmpyieacc_VwVwVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::I16x32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyiewh.acc") - }, - "Vw_vmpyieacc_VwVwVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U16x32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyiewuh.acc") - }, - "Vw_vmpyieacc_VwVwVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::I16x64]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyiewh.acc.128B") - }, - "Vw_vmpyieacc_VwVwVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U16x64]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyiewuh.acc.128B") - }, - "Vw_vmpyie_VwVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U16x32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyiewuh") - }, - "Vw_vmpyie_VwVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U16x64]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyiewuh.128B") - }, - "Vh_vmpyi_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vmpyih") - }, - "Vh_vmpyi_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpyih.128B") - }, - "Vh_vmpyiacc_VhVhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vmpyih.acc") - }, - "Vh_vmpyiacc_VhVhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpyih.acc.128B") - }, - "Vh_vmpyi_VhRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::U32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vmpyihb") - }, - "Vw_vmpyi_VwRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyiwb") - }, - "Vh_vmpyi_VhRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpyihb.128B") - }, - "Vw_vmpyi_VwRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyiwb.128B") - }, - "Vh_vmpyiacc_VhVhRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x32, &::I16x32, &::U32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vmpyihb.acc") - }, - "Vw_vmpyiacc_VwVwRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyiwb.acc") - }, - "Vh_vmpyiacc_VhVhRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I16x64, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vmpyihb.acc.128B") - }, - "Vw_vmpyiacc_VwVwRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyiwb.acc.128B") - }, - "Vw_vmpyi_VwRh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyiwh") - }, - "Vw_vmpyi_VwRh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyiwh.128B") - }, - "Vw_vmpyiacc_VwVwRh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyiwh.acc") - }, - "Vw_vmpyiacc_VwVwRh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyiwh.acc.128B") - }, - "Vw_vmpyi_VwRub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyiwub") - }, - "Vw_vmpyi_VwRub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyiwub.128B") - }, - "Vw_vmpyiacc_VwVwRub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I32x16, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyiwub.acc") - }, - "Vw_vmpyiacc_VwVwRub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I32x32, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyiwub.acc.128B") - }, - "Vw_vmpyo_VwVh_s1_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I16x32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyowh") - }, - "Vw_vmpyo_VwVh_s1_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I16x64]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyowh.128B") - }, - "Vw_vmpyo_VwVh_s1_rnd_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I16x32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyowh.rnd") - }, - "Vw_vmpyo_VwVh_s1_rnd_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I16x64]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyowh.rnd.128B") - }, - "Vw_vmpyo_VwVh_s1_rnd_sat_shift64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I16x32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyowh.rnd.sacc") - }, - "Vw_vmpyo_VwVh_s1_rnd_sat_shift128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I16x64]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyowh.rnd.sacc.128B") - }, - "Vw_vmpyo_VwVh_s1_sat_shift64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I16x32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyowh.sacc") - }, - "Vw_vmpyo_VwVh_s1_sat_shift128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I16x64]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyowh.sacc.128B") - }, - "Vw_vmpyio_VwVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I16x32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vmpyiowh") - }, - "Vw_vmpyio_VwVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I16x64]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vmpyiowh.128B") - }, - "Wuh_vmpy_VubRub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U32]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vmpyub") - }, - "Wuh_vmpy_VubRub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS }, - output: &::U16x128, - definition: Named("llvm.hexagon.V6.vmpyub.128B") - }, - "Wuh_vmpyacc_WuhVubRub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U16x64, &::U8x64, &::U32]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vmpyub.acc") - }, - "Wuw_vmpyacc_WuwVuhRuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U16x32, &::U32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vmpyuh.acc") - }, - "Wuh_vmpyacc_WuhVubRub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U16x128, &::U8x128, &::U32]; &INPUTS }, - output: &::U16x128, - definition: Named("llvm.hexagon.V6.vmpyub.acc.128B") - }, - "Wuw_vmpyacc_WuwVuhRuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x64, &::U16x64, &::U32]; &INPUTS }, - output: &::U32x64, - definition: Named("llvm.hexagon.V6.vmpyuh.acc.128B") - }, - "Vuw_vmux_QVV64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U32x16, &::U32x16]; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.vmux") - }, - "Vuw_vmux_QVV128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U32x32, &::U32x32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vmux.128B") - }, - "Vh_vnavg_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vnavgh") - }, - "Vuh_vnavg_VuhVuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vnavguh") - }, - "Vw_vnavg_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vnavgw") - }, - "Vuw_vnavg_VuwVuw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x16, &::U32x16]; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.vnavguw") - }, - "Vh_vnavg_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vnavgh.128B") - }, - "Vuh_vnavg_VuhVuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vnavguh.128B") - }, - "Vw_vnavg_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vnavgw.128B") - }, - "Vuw_vnavg_VuwVuw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x32, &::U32x32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vnavguw.128B") - }, - "Vub_vnavg_VubVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vnavgub") - }, - "Vub_vnavg_VubVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vnavgub.128B") - }, - "Vh_vnormamt_Vh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vnormamth") - }, - "Vw_vnormamt_Vw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vnormamtw") - }, - "Vh_vnormamt_Vh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vnormamth.128B") - }, - "Vw_vnormamt_Vw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vnormamtw.128B") - }, - "V_vnot_VV64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vnot") - }, - "V_vnot_VV128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vnot.128B") - }, - "V_vor_VV64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vor") - }, - "V_vor_VV128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vor.128B") - }, - "Vb_vpacke_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vpackhe") - }, - "Vh_vpacke_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vpackwe") - }, - "Vb_vpacke_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vpackhe.128B") - }, - "Vh_vpacke_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vpackwe.128B") - }, - "Vb_vpacko_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vpackho") - }, - "Vh_vpacko_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vpackwo") - }, - "Vb_vpacko_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vpackho.128B") - }, - "Vh_vpacko_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vpackwo.128B") - }, - "Vb_vpack_VhVh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vpackhb.sat") - }, - "Vub_vpack_VhVh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vpackhub.sat") - }, - "Vh_vpack_VwVw_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vpackwh.sat") - }, - "Vuh_vpack_VwVw_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vpackwuh.sat") - }, - "Vb_vpack_VhVh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vpackhb.sat.128B") - }, - "Vub_vpack_VhVh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vpackhub.sat.128B") - }, - "Vh_vpack_VwVw_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vpackwh.sat.128B") - }, - "Vuh_vpack_VwVw_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vpackwuh.sat.128B") - }, - "Vh_vpopcount_Vh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vpopcounth") - }, - "Vh_vpopcount_Vh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vpopcounth.128B") - }, - "V_vrdelta_VV64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vrdelta") - }, - "V_vrdelta_VV128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vrdelta.128B") - }, - "Vw_vrmpy_VubRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vrmpybus") - }, - "Vw_vrmpy_VubRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vrmpybus.128B") - }, - "Vw_vrmpyacc_VwVubRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::U8x64, &::U32]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vrmpybus.acc") - }, - "Vw_vrmpyacc_VwVubRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::U8x128, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vrmpybus.acc.128B") - }, - "Ww_vrmpy_WubRbI64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vrmpybusi") - }, - "Ww_vrmpy_WubRbI128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U32]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vrmpybusi.128B") - }, - "Ww_vrmpyacc_WwWubRbI64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::U8x128, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vrmpybusi.acc") - }, - "Ww_vrmpyacc_WwWubRbI128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::U8x256, &::U32]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vrmpybusi.acc.128B") - }, - "Vw_vrmpy_VubVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::I8x64]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vrmpybusv") - }, - "Vw_vrmpy_VubVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::I8x128]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vrmpybusv.128B") - }, - "Vw_vrmpyacc_VwVubVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::U8x64, &::I8x64]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vrmpybusv.acc") - }, - "Vw_vrmpyacc_VwVubVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::U8x128, &::I8x128]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vrmpybusv.acc.128B") - }, - "Vw_vrmpy_VbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vrmpybv") - }, - "Vuw_vrmpy_VubVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.vrmpyubv") - }, - "Vw_vrmpy_VbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vrmpybv.128B") - }, - "Vuw_vrmpy_VubVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vrmpyubv.128B") - }, - "Vw_vrmpyacc_VwVbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x16, &::I8x64, &::I8x64]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vrmpywv.acc") - }, - "Vuw_vrmpyacc_VuwVubVub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x16, &::U8x64, &::U8x64]; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.vrmpyuwv.acc") - }, - "Vw_vrmpyacc_VwVbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I8x128, &::I8x128]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vrmpywv.acc.128B") - }, - "Vuw_vrmpyacc_VuwVubVub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U8x128, &::U8x128]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vrmpyuwv.acc.128B") - }, - "Vuw_vrmpy_VubRub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U32]; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.vrmpyub") - }, - "Vuw_vrmpy_VubRub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vrmpyub.128B") - }, - "Vuw_vrmpyacc_VuwVubRub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x16, &::U8x64, &::U32]; &INPUTS }, - output: &::U32x16, - definition: Named("llvm.hexagon.V6.vrmpyub.acc") - }, - "Vuw_vrmpyacc_VuwVubRub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U8x128, &::U32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vrmpyub.acc.128B") - }, - "Wuw_vrmpy_WubRubI64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vrmpyubi") - }, - "Wuw_vrmpy_WubRubI128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U32]; &INPUTS }, - output: &::U32x64, - definition: Named("llvm.hexagon.V6.vrmpyubi.128B") - }, - "Wuw_vrmpyacc_WuwWubRubI64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U8x128, &::U32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vrmpyubi.acc") - }, - "Wuw_vrmpyacc_WuwWubRubI128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x64, &::U8x256, &::U32]; &INPUTS }, - output: &::U32x64, - definition: Named("llvm.hexagon.V6.vrmpyubi.acc.128B") - }, - "V_vror_VR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U32]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vror") - }, - "V_vror_VR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vror.128B") - }, - "Vb_vround_VhVh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vroundhb") - }, - "Vub_vround_VhVh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vroundhub") - }, - "Vh_vround_VwVw_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vroundwh") - }, - "Vuh_vround_VwVw_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vroundwuh") - }, - "Vb_vround_VhVh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vroundhb.128B") - }, - "Vub_vround_VhVh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vroundhub.128B") - }, - "Vh_vround_VwVw_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vroundwh.128B") - }, - "Vuh_vround_VwVw_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vroundwuh.128B") - }, - "Wuw_vrsad_WubRubI64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vrsadubi") - }, - "Wuw_vrsad_WubRubI128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U32]; &INPUTS }, - output: &::U32x64, - definition: Named("llvm.hexagon.V6.vrsadubi.128B") - }, - "Wuw_vrsadacc_WuwWubRubI64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x32, &::U8x128, &::U32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vrsadubi.acc") - }, - "Wuw_vrsadacc_WuwWubRubI128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x64, &::U8x256, &::U32]; &INPUTS }, - output: &::U32x64, - definition: Named("llvm.hexagon.V6.vrsadubi.acc.128B") - }, - "Vub_vsat_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vsathub") - }, - "Vub_vsat_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vsathub.128B") - }, - "Vh_vsat_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vsatwh") - }, - "Vh_vsat_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vsatwh.128B") - }, - "Wh_vsxt_Vb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vsb") - }, - "Ww_vsxt_Vh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vsh") - }, - "Wh_vsxt_Vb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x128]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vsb.128B") - }, - "Ww_vsxt_Vh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vsh.128B") - }, - "Wuh_vzxt_Vub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vzb") - }, - "Wuw_vzxt_Vuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vzh") - }, - "Wuh_vzxt_Vub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x128]; &INPUTS }, - output: &::U16x128, - definition: Named("llvm.hexagon.V6.vzb.128B") - }, - "Wuw_vzxt_Vuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x64]; &INPUTS }, - output: &::U32x64, - definition: Named("llvm.hexagon.V6.vzh.128B") - }, - "Vb_condacc_QVbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vaddbq") - }, - "Vh_condacc_QVhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vaddhq") - }, - "Vw_condacc_QVwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vaddwq") - }, - "Vb_condacc_QVbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vaddbq.128B") - }, - "Vh_condacc_QVhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vaddhq.128B") - }, - "Vw_condacc_QVwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vaddwq.128B") - }, - "Vb_condacc_QnVbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vaddbnq") - }, - "Vh_condacc_QnVhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vaddhnq") - }, - "Vw_condacc_QnVwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vaddwnq") - }, - "Vb_condacc_QnVbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vaddbnq.128B") - }, - "Vh_condacc_QnVhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vaddhnq.128B") - }, - "Vw_condacc_QnVwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vaddwnq.128B") - }, - "Vb_condnac_QVbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vsubbq") - }, - "Vh_condnac_QVhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vsubhq") - }, - "Vw_condnac_QVwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vsubwq") - }, - "Vb_condnac_QVbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vsubbq.128B") - }, - "Vh_condnac_QVhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vsubhq.128B") - }, - "Vw_condnac_QVwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vsubwq.128B") - }, - "Vb_condnac_QnVbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I8x64, &::I8x64]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vsubbnq") - }, - "Vh_condnac_QnVhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vsubhnq") - }, - "Vw_condnac_QnVwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vsubwnq") - }, - "Vb_condnac_QnVbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I8x128, &::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vsubbnq.128B") - }, - "Vh_condnac_QnVhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vsubhnq.128B") - }, - "Vw_condnac_QnVwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vsubwnq.128B") - }, - "Vh_vshuffe_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vshufeh") - }, - "Vh_vshuffe_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vshufeh.128B") - }, - "Vh_vshuffo_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vshufoh") - }, - "Vh_vshuffo_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vshufoh.128B") - }, - "Vb_vshuff_Vb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x64]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vshuffb") - }, - "Vh_vshuff_Vh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vshuffh") - }, - "Vb_vshuff_Vb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vshuffb.128B") - }, - "Vh_vshuff_Vh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vshuffh.128B") - }, - "Vb_vshuffe_VbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vshuffeb") - }, - "Vb_vshuffe_VbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vshuffeb.128B") - }, - "Vb_vshuffo_VbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vshuffob") - }, - "Vb_vshuffo_VbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vshuffob.128B") - }, - "Vb_vshuffoe_VbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vshuffoeb") - }, - "Vh_vshuffoe_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vshuffoeh") - }, - "Vb_vshuffoe_VbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vshuffoeb.128B") - }, - "Vh_vshuffoe_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vshuffoeh.128B") - }, - "W_vshuff_VVR64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x64, &::U8x64, &::U32]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vshufvvd") - }, - "W_vshuff_VVR128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x128, &::U8x128, &::U32]; &INPUTS }, - output: &::U8x256, - definition: Named("llvm.hexagon.V6.vshufvvd.128B") - }, - "Vb_vsub_VbVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x64, &::I8x64]; &INPUTS }, - output: &::I8x64, - definition: Named("llvm.hexagon.V6.vsubb") - }, - "Vh_vsub_VhVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vsubh") - }, - "Vw_vsub_VwVw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vsubw") - }, - "Vb_vsub_VbVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vsubb.128B") - }, - "Vh_vsub_VhVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vsubh.128B") - }, - "Vw_vsub_VwVw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vsubw.128B") - }, - "Vh_vsub_VhVh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x32, &::I16x32]; &INPUTS }, - output: &::I16x32, - definition: Named("llvm.hexagon.V6.vsubhsat") - }, - "Vw_vsub_VwVw_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x16, &::I32x16]; &INPUTS }, - output: &::I32x16, - definition: Named("llvm.hexagon.V6.vsubwsat") - }, - "Vh_vsub_VhVh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vsubhsat.128B") - }, - "Vw_vsub_VwVw_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vsubwsat.128B") - }, - "Vub_vsub_VubVub_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x64, &::U8x64]; &INPUTS }, - output: &::U8x64, - definition: Named("llvm.hexagon.V6.vsububsat") - }, - "Vuh_vsub_VuhVuh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vsubuhsat") - }, - "Vub_vsub_VubVub_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vsububsat.128B") - }, - "Vuh_vsub_VuhVuh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vsubuhsat.128B") - }, - "Wb_vsub_WbWb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::I8x128]; &INPUTS }, - output: &::I8x128, - definition: Named("llvm.hexagon.V6.vsubb.dv") - }, - "Wh_vsub_WhWh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vsubh.dv") - }, - "Ww_vsub_WwWw64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vsubw.dv") - }, - "Wb_vsub_WbWb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x256, &::I8x256]; &INPUTS }, - output: &::I8x256, - definition: Named("llvm.hexagon.V6.vsubb.dv.128B") - }, - "Wh_vsub_WhWh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::I16x128]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vsubh.dv.128B") - }, - "Ww_vsub_WwWw128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x64, &::I32x64]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vsubw.dv.128B") - }, - "Wh_vsub_WhWh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I16x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vsubhsat.dv") - }, - "Ww_vsub_WwWw_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I32x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vsubwsat.dv") - }, - "Wh_vsub_WhWh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::I16x128]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vsubhsat.dv.128B") - }, - "Ww_vsub_WwWw_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x64, &::I32x64]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vsubwsat.dv.128B") - }, - "Wub_vsub_WubWub_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vsububsat.dv") - }, - "Wuh_vsub_WuhWuh_sat64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vsubuhsat.dv") - }, - "Wub_vsub_WubWub_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U8x256]; &INPUTS }, - output: &::U8x256, - definition: Named("llvm.hexagon.V6.vsububsat.dv.128B") - }, - "Wuh_vsub_WuhWuh_sat128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x128, &::U16x128]; &INPUTS }, - output: &::U16x128, - definition: Named("llvm.hexagon.V6.vsubuhsat.dv.128B") - }, - "W_vswap_QVV64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x2, &::U8x64, &::U8x64]; &INPUTS }, - output: &::U8x128, - definition: Named("llvm.hexagon.V6.vswap") - }, - "W_vswap_QVV128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U32x4, &::U8x128, &::U8x128]; &INPUTS }, - output: &::U8x256, - definition: Named("llvm.hexagon.V6.vswap.128B") - }, - "Wh_vtmpy_WbRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x128, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vtmpyb") - }, - "Wh_vtmpy_WbRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x256, &::U32]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vtmpyb.128B") - }, - "Wh_vtmpyacc_WhWbRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::I8x128, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vtmpyb.acc") - }, - "Wh_vtmpyacc_WhWbRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::I8x256, &::U32]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vtmpyb.acc.128B") - }, - "Wh_vtmpy_WubRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x128, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vtmpybus") - }, - "Wh_vtmpy_WubRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x256, &::U32]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vtmpybus.128B") - }, - "Wh_vtmpyacc_WhWubRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x64, &::U8x128, &::U32]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vtmpybus.acc") - }, - "Wh_vtmpyacc_WhWubRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x128, &::U8x256, &::U32]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vtmpybus.acc.128B") - }, - "Ww_vtmpy_WhRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vtmpyhb") - }, - "Ww_vtmpy_WhRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::U32]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vtmpyhb.128B") - }, - "Wh_vunpack_Vb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vunpackb") - }, - "Wuh_vunpack_Vub64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vunpackub") - }, - "Ww_vunpack_Vh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vunpackh") - }, - "Wuw_vunpack_Vuh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x32]; &INPUTS }, - output: &::U32x32, - definition: Named("llvm.hexagon.V6.vunpackuh") - }, - "Wh_vunpack_Vb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x128]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vunpackb.128B") - }, - "Wuh_vunpack_Vub128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U8x128]; &INPUTS }, - output: &::U16x128, - definition: Named("llvm.hexagon.V6.vunpackub.128B") - }, - "Ww_vunpack_Vh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x64]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vunpackh.128B") - }, - "Wuw_vunpack_Vuh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x64]; &INPUTS }, - output: &::U32x64, - definition: Named("llvm.hexagon.V6.vunpackuh.128B") - }, - "Wh_vunpackoor_WhVb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x64, &::I8x64]; &INPUTS }, - output: &::I16x64, - definition: Named("llvm.hexagon.V6.vunpackob") - }, - "Ww_vunpackoor_WwVh64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x32, &::I16x32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vunpackoh") - }, - "Wh_vunpackoor_WhVb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x128, &::I8x128]; &INPUTS }, - output: &::I16x128, - definition: Named("llvm.hexagon.V6.vunpackob.128B") - }, - "Ww_vunpackoor_WwVh128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x64, &::I16x64]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vunpackoh.128B") - }, - "Ww_vtmpyacc_WwWhRb64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x32, &::I16x64, &::U32]; &INPUTS }, - output: &::I32x32, - definition: Named("llvm.hexagon.V6.vtmpyhb.acc") - }, - "Ww_vtmpyacc_WwWhRb128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x64, &::I16x128, &::U32]; &INPUTS }, - output: &::I32x64, - definition: Named("llvm.hexagon.V6.vtmpyhb.acc.128B") - }, - "V_vxor_VV64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x32, &::U16x32]; &INPUTS }, - output: &::U16x32, - definition: Named("llvm.hexagon.V6.vxor") - }, - "V_vxor_VV128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x64, &::U16x64]; &INPUTS }, - output: &::U16x64, - definition: Named("llvm.hexagon.V6.vxor.128B") - }, - _ => return None, - }) -} diff --git a/src/librustc_platform_intrinsics/lib.rs b/src/librustc_platform_intrinsics/lib.rs deleted file mode 100644 index 9fbf168a118f7..0000000000000 --- a/src/librustc_platform_intrinsics/lib.rs +++ /dev/null @@ -1,124 +0,0 @@ -#![allow(nonstandard_style)] - -#![feature(nll)] - -pub struct Intrinsic { - pub inputs: &'static [&'static Type], - pub output: &'static Type, - - pub definition: IntrinsicDef, -} - -#[derive(Clone, Hash, Eq, PartialEq)] -pub enum Type { - Void, - Integer(/* signed */ bool, u8, /* llvm width */ u8), - Float(u8), - Pointer(&'static Type, Option<&'static Type>, /* const */ bool), - Vector(&'static Type, Option<&'static Type>, u16), - Aggregate(bool, &'static [&'static Type]), -} - -pub enum IntrinsicDef { - Named(&'static str), -} - -static I8: Type = Type::Integer(true, 8, 8); -static I16: Type = Type::Integer(true, 16, 16); -static I32: Type = Type::Integer(true, 32, 32); -static I64: Type = Type::Integer(true, 64, 64); -static U8: Type = Type::Integer(false, 8, 8); -static U16: Type = Type::Integer(false, 16, 16); -static U32: Type = Type::Integer(false, 32, 32); -static U64: Type = Type::Integer(false, 64, 64); -static F32: Type = Type::Float(32); -static F64: Type = Type::Float(64); - -static I32_8: Type = Type::Integer(true, 32, 8); - -static I8x8: Type = Type::Vector(&I8, None, 8); -static U8x8: Type = Type::Vector(&U8, None, 8); -static I8x16: Type = Type::Vector(&I8, None, 16); -static U8x16: Type = Type::Vector(&U8, None, 16); -static I8x32: Type = Type::Vector(&I8, None, 32); -static U8x32: Type = Type::Vector(&U8, None, 32); -static I8x64: Type = Type::Vector(&I8, None, 64); -static U8x64: Type = Type::Vector(&U8, None, 64); -static I8x128: Type = Type::Vector(&I8, None, 128); -static U8x128: Type = Type::Vector(&U8, None, 128); -static I8x256: Type = Type::Vector(&I8, None, 256); -static U8x256: Type = Type::Vector(&U8, None, 256); - -static I16x4: Type = Type::Vector(&I16, None, 4); -static U16x4: Type = Type::Vector(&U16, None, 4); -static I16x8: Type = Type::Vector(&I16, None, 8); -static U16x8: Type = Type::Vector(&U16, None, 8); -static I16x16: Type = Type::Vector(&I16, None, 16); -static U16x16: Type = Type::Vector(&U16, None, 16); -static I16x32: Type = Type::Vector(&I16, None, 32); -static U16x32: Type = Type::Vector(&U16, None, 32); -static I16x64: Type = Type::Vector(&I16, None, 64); -static U16x64: Type = Type::Vector(&U16, None, 64); -static I16x128: Type = Type::Vector(&I16, None, 128); -static U16x128: Type = Type::Vector(&U16, None, 128); - -static I32x2: Type = Type::Vector(&I32, None, 2); -static U32x2: Type = Type::Vector(&U32, None, 2); -static I32x4: Type = Type::Vector(&I32, None, 4); -static U32x4: Type = Type::Vector(&U32, None, 4); -static I32x8: Type = Type::Vector(&I32, None, 8); -static U32x8: Type = Type::Vector(&U32, None, 8); -static I32x16: Type = Type::Vector(&I32, None, 16); -static U32x16: Type = Type::Vector(&U32, None, 16); -static I32x32: Type = Type::Vector(&I32, None, 32); -static U32x32: Type = Type::Vector(&U32, None, 32); -static I32x64: Type = Type::Vector(&I32, None, 64); -static U32x64: Type = Type::Vector(&U32, None, 64); - -static I64x1: Type = Type::Vector(&I64, None, 1); -static U64x1: Type = Type::Vector(&U64, None, 1); -static I64x2: Type = Type::Vector(&I64, None, 2); -static U64x2: Type = Type::Vector(&U64, None, 2); -static I64x4: Type = Type::Vector(&I64, None, 4); -static U64x4: Type = Type::Vector(&U64, None, 4); - -static F32x2: Type = Type::Vector(&F32, None, 2); -static F32x4: Type = Type::Vector(&F32, None, 4); -static F32x8: Type = Type::Vector(&F32, None, 8); -static F64x1: Type = Type::Vector(&F64, None, 1); -static F64x2: Type = Type::Vector(&F64, None, 2); -static F64x4: Type = Type::Vector(&F64, None, 4); - -static I32x4_F32: Type = Type::Vector(&I32, Some(&F32), 4); -static I32x8_F32: Type = Type::Vector(&I32, Some(&F32), 8); -static I64x2_F64: Type = Type::Vector(&I64, Some(&F64), 2); -static I64x4_F64: Type = Type::Vector(&I64, Some(&F64), 4); - -static VOID: Type = Type::Void; - -mod x86; -mod arm; -mod aarch64; -mod nvptx; -mod hexagon; -mod powerpc; - -impl Intrinsic { - pub fn find(name: &str) -> Option { - if name.starts_with("x86_") { - x86::find(name) - } else if name.starts_with("arm_") { - arm::find(name) - } else if name.starts_with("aarch64_") { - aarch64::find(name) - } else if name.starts_with("nvptx_") { - nvptx::find(name) - } else if name.starts_with("Q6_") { - hexagon::find(name) - } else if name.starts_with("powerpc_") { - powerpc::find(name) - } else { - None - } - } -} diff --git a/src/librustc_platform_intrinsics/nvptx.rs b/src/librustc_platform_intrinsics/nvptx.rs deleted file mode 100644 index 41278463bae77..0000000000000 --- a/src/librustc_platform_intrinsics/nvptx.rs +++ /dev/null @@ -1,79 +0,0 @@ -// DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py -// ignore-tidy-linelength - -#![allow(unused_imports)] - -use {Intrinsic, Type}; -use IntrinsicDef::Named; - -pub fn find(name: &str) -> Option { - if !name.starts_with("nvptx") { return None } - Some(match &name["nvptx".len()..] { - "_syncthreads" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::VOID, - definition: Named("llvm.cuda.syncthreads") - }, - "_block_dim_x" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::I32, - definition: Named("llvm.nvvm.read.ptx.sreg.ntid.x") - }, - "_block_dim_y" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::I32, - definition: Named("llvm.nvvm.read.ptx.sreg.ntid.y") - }, - "_block_dim_z" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::I32, - definition: Named("llvm.nvvm.read.ptx.sreg.ntid.z") - }, - "_block_idx_x" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::I32, - definition: Named("llvm.nvvm.read.ptx.sreg.ctaid.x") - }, - "_block_idx_y" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::I32, - definition: Named("llvm.nvvm.read.ptx.sreg.ctaid.y") - }, - "_block_idx_z" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::I32, - definition: Named("llvm.nvvm.read.ptx.sreg.ctaid.z") - }, - "_grid_dim_x" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::I32, - definition: Named("llvm.nvvm.read.ptx.sreg.nctaid.x") - }, - "_grid_dim_y" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::I32, - definition: Named("llvm.nvvm.read.ptx.sreg.nctaid.y") - }, - "_grid_dim_z" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::I32, - definition: Named("llvm.nvvm.read.ptx.sreg.nctaid.z") - }, - "_thread_idx_x" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::I32, - definition: Named("llvm.nvvm.read.ptx.sreg.tid.x") - }, - "_thread_idx_y" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::I32, - definition: Named("llvm.nvvm.read.ptx.sreg.tid.y") - }, - "_thread_idx_z" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::I32, - definition: Named("llvm.nvvm.read.ptx.sreg.tid.z") - }, - _ => return None, - }) -} diff --git a/src/librustc_platform_intrinsics/powerpc.rs b/src/librustc_platform_intrinsics/powerpc.rs deleted file mode 100644 index d745090107c62..0000000000000 --- a/src/librustc_platform_intrinsics/powerpc.rs +++ /dev/null @@ -1,439 +0,0 @@ -// DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py -// ignore-tidy-linelength - -#![allow(unused_imports)] - -use {Intrinsic, Type}; -use IntrinsicDef::Named; - -pub fn find(name: &str) -> Option { - if !name.starts_with("powerpc") { return None } - Some(match &name["powerpc".len()..] { - "_vec_perm" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I32x4, &::I32x4, &::I8x16]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vperm") - }, - "_vec_mradds" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vmhraddshs") - }, - "_vec_cmpb" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vcmpbfp") - }, - "_vec_cmpeqb" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.ppc.altivec.vcmpequb") - }, - "_vec_cmpeqh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vcmpequh") - }, - "_vec_cmpeqw" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vcmpequw") - }, - "_vec_cmpgtub" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.ppc.altivec.vcmpgtub") - }, - "_vec_cmpgtuh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vcmpgtuh") - }, - "_vec_cmpgtuw" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vcmpgtuw") - }, - "_vec_cmpgtsb" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.ppc.altivec.vcmpgtsb") - }, - "_vec_cmpgtsh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vcmpgtsh") - }, - "_vec_cmpgtsw" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vcmpgtsw") - }, - "_vec_maxsb" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.ppc.altivec.vmaxsb") - }, - "_vec_maxub" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.ppc.altivec.vmaxub") - }, - "_vec_maxsh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vmaxsh") - }, - "_vec_maxuh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.ppc.altivec.vmaxuh") - }, - "_vec_maxsw" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vmaxsw") - }, - "_vec_maxuw" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ppc.altivec.vmaxuw") - }, - "_vec_minsb" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.ppc.altivec.vminsb") - }, - "_vec_minub" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.ppc.altivec.vminub") - }, - "_vec_minsh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vminsh") - }, - "_vec_minuh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.ppc.altivec.vminuh") - }, - "_vec_minsw" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vminsw") - }, - "_vec_minuw" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ppc.altivec.vminuw") - }, - "_vec_subsbs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.ppc.altivec.vsubsbs") - }, - "_vec_sububs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.ppc.altivec.vsububs") - }, - "_vec_subshs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vsubshs") - }, - "_vec_subuhs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.ppc.altivec.vsubuhs") - }, - "_vec_subsws" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vsubsws") - }, - "_vec_subuws" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ppc.altivec.vsubuws") - }, - "_vec_subc" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ppc.altivec.vsubcuw") - }, - "_vec_addsbs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.ppc.altivec.vaddsbs") - }, - "_vec_addubs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.ppc.altivec.vaddubs") - }, - "_vec_addshs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vaddshs") - }, - "_vec_adduhs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.ppc.altivec.vadduhs") - }, - "_vec_addsws" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vaddsws") - }, - "_vec_adduws" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ppc.altivec.vadduws") - }, - "_vec_addc" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ppc.altivec.vaddcuw") - }, - "_vec_mulesb" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vmulesb") - }, - "_vec_muleub" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.ppc.altivec.vmuleub") - }, - "_vec_mulesh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vmulesh") - }, - "_vec_muleuh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ppc.altivec.vmuleuh") - }, - "_vec_mulosb" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vmulosb") - }, - "_vec_muloub" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.ppc.altivec.vmuloub") - }, - "_vec_mulosh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vmulosh") - }, - "_vec_mulouh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ppc.altivec.vmulouh") - }, - "_vec_avgsb" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.ppc.altivec.vavgsb") - }, - "_vec_avgub" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.ppc.altivec.vavgub") - }, - "_vec_avgsh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vavgsh") - }, - "_vec_avguh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.ppc.altivec.vavguh") - }, - "_vec_avgsw" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vavgsw") - }, - "_vec_avguw" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ppc.altivec.vavguw") - }, - "_vec_packssh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.ppc.altivec.vpkshss") - }, - "_vec_packsuh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.ppc.altivec.vpkuhus") - }, - "_vec_packssw" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vpkswss") - }, - "_vec_packsuw" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.ppc.altivec.vpkuwus") - }, - "_vec_packsush" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.ppc.altivec.vpkshus") - }, - "_vec_packsusw" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.ppc.altivec.vpkswus") - }, - "_vec_packpx" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vpkpx") - }, - "_vec_unpacklsb" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vupklsb") - }, - "_vec_unpacklsh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vupklsh") - }, - "_vec_unpackhsb" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vupkhsb") - }, - "_vec_unpackhsh" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vupkhsh") - }, - "_vec_madds" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.ppc.altivec.vmhaddshs") - }, - "_vec_msumubm" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ppc.altivec.vmsumubm") - }, - "_vec_msumuhm" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U16x8, &::U16x8, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ppc.altivec.vmsumuhm") - }, - "_vec_msummbm" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, &::U8x16, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vmsummbm") - }, - "_vec_msumshm" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vmsumshm") - }, - "_vec_msumshs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I16x8, &::I16x8, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vmsumshs") - }, - "_vec_msumuhs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U16x8, &::U16x8, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ppc.altivec.vmsumuhs") - }, - "_vec_sum2s" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vsum2sws") - }, - "_vec_sum4sbs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vsum4sbs") - }, - "_vec_sum4ubs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.ppc.altivec.vsum4ubs") - }, - "_vec_sum4shs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vsum4shs") - }, - "_vec_sums" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.ppc.altivec.vsumsws") - }, - "_vec_madd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.ppc.altivec.vmaddfp") - }, - "_vec_nmsub" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.ppc.altivec.vnmsubfp") - }, - "_vec_expte" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.ppc.altivec.vexptefp") - }, - "_vec_floor" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.ppc.altivec.vrfim") - }, - "_vec_ceil" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.ppc.altivec.vrfip") - }, - "_vec_round" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.ppc.altivec.vrfin") - }, - "_vec_trunc" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.ppc.altivec.vrfiz") - }, - "_vec_loge" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.ppc.altivec.vlogefp") - }, - "_vec_re" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.ppc.altivec.vrefp") - }, - "_vec_rsqrte" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.ppc.altivec.vrsqrtefp") - }, - _ => return None, - }) -} diff --git a/src/librustc_platform_intrinsics/x86.rs b/src/librustc_platform_intrinsics/x86.rs deleted file mode 100644 index 3f1ba912eee63..0000000000000 --- a/src/librustc_platform_intrinsics/x86.rs +++ /dev/null @@ -1,1369 +0,0 @@ -// DO NOT EDIT: autogenerated by etc/platform-intrinsics/generator.py -// ignore-tidy-linelength - -#![allow(unused_imports)] - -use {Intrinsic, Type}; -use IntrinsicDef::Named; - -pub fn find(name: &str) -> Option { - if !name.starts_with("x86") { return None } - Some(match &name["x86".len()..] { - "_mm256_abs_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x32]; &INPUTS }, - output: &::I8x32, - definition: Named("llvm.x86.avx2.pabs.b") - }, - "_mm256_abs_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x16]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.pabs.w") - }, - "_mm256_abs_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x8]; &INPUTS }, - output: &::I32x8, - definition: Named("llvm.x86.avx2.pabs.d") - }, - "_mm256_adds_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x32, &::I8x32]; &INPUTS }, - output: &::I8x32, - definition: Named("llvm.x86.avx2.padds.b") - }, - "_mm256_adds_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x32, &::U8x32]; &INPUTS }, - output: &::U8x32, - definition: Named("llvm.x86.avx2.paddus.b") - }, - "_mm256_adds_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.padds.w") - }, - "_mm256_adds_epu16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x16, &::U16x16]; &INPUTS }, - output: &::U16x16, - definition: Named("llvm.x86.avx2.paddus.w") - }, - "_mm256_avg_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x32, &::U8x32]; &INPUTS }, - output: &::U8x32, - definition: Named("llvm.x86.avx2.pavg.b") - }, - "_mm256_avg_epu16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x16, &::U16x16]; &INPUTS }, - output: &::U16x16, - definition: Named("llvm.x86.avx2.pavg.w") - }, - "_mm256_hadd_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.phadd.w") - }, - "_mm256_hadd_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x8, &::I32x8]; &INPUTS }, - output: &::I32x8, - definition: Named("llvm.x86.avx2.phadd.d") - }, - "_mm256_hadds_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.phadd.sw") - }, - "_mm256_hsub_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.phsub.w") - }, - "_mm256_hsub_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x8, &::I32x8]; &INPUTS }, - output: &::I32x8, - definition: Named("llvm.x86.avx2.phsub.d") - }, - "_mm256_hsubs_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.phsub.sw") - }, - "_mm256_madd_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::I32x8, - definition: Named("llvm.x86.avx2.pmadd.wd") - }, - "_mm256_maddubs_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x32, &::I8x32]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.pmadd.ub.sw") - }, - "_mm_mask_i32gather_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I32x4, { static PTR: Type = Type::Pointer(&::I32, Some(&::I8), true); &PTR }, &::I32x4, &::I32x4, &::I32_8]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.x86.avx2.gather.d.d") - }, - "_mm_mask_i32gather_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::F32x4, { static PTR: Type = Type::Pointer(&::F32, Some(&::I8), true); &PTR }, &::I32x4, &::I32x4_F32, &::I32_8]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.avx2.gather.d.ps") - }, - "_mm256_mask_i32gather_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I32x8, { static PTR: Type = Type::Pointer(&::I32, Some(&::I8), true); &PTR }, &::I32x8, &::I32x8, &::I32_8]; &INPUTS }, - output: &::I32x8, - definition: Named("llvm.x86.avx2.gather.d.d.256") - }, - "_mm256_mask_i32gather_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::F32x8, { static PTR: Type = Type::Pointer(&::F32, Some(&::I8), true); &PTR }, &::I32x8, &::I32x8_F32, &::I32_8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx2.gather.d.ps.256") - }, - "_mm_mask_i32gather_epi64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I64x2, { static PTR: Type = Type::Pointer(&::I64, Some(&::I8), true); &PTR }, &::I32x4, &::I64x2, &::I32_8]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.x86.avx2.gather.d.q") - }, - "_mm_mask_i32gather_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::F64x2, { static PTR: Type = Type::Pointer(&::F64, Some(&::I8), true); &PTR }, &::I32x4, &::I64x2_F64, &::I32_8]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.avx2.gather.d.pd") - }, - "_mm256_mask_i32gather_epi64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I64x4, { static PTR: Type = Type::Pointer(&::I64, Some(&::I8), true); &PTR }, &::I32x4, &::I64x4, &::I32_8]; &INPUTS }, - output: &::I64x4, - definition: Named("llvm.x86.avx2.gather.d.q.256") - }, - "_mm256_mask_i32gather_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::F64x4, { static PTR: Type = Type::Pointer(&::F64, Some(&::I8), true); &PTR }, &::I32x4, &::I64x4_F64, &::I32_8]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx2.gather.d.pd.256") - }, - "_mm_mask_i64gather_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I32x4, { static PTR: Type = Type::Pointer(&::I32, Some(&::I8), true); &PTR }, &::I64x2, &::I32x4, &::I32_8]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.x86.avx2.gather.q.d") - }, - "_mm_mask_i64gather_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::F32x4, { static PTR: Type = Type::Pointer(&::F32, Some(&::I8), true); &PTR }, &::I64x2, &::I32x4_F32, &::I32_8]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.avx2.gather.q.ps") - }, - "_mm256_mask_i64gather_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I32x4, { static PTR: Type = Type::Pointer(&::I32, Some(&::I8), true); &PTR }, &::I64x4, &::I32x4, &::I32_8]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.x86.avx2.gather.q.d") - }, - "_mm256_mask_i64gather_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::F32x4, { static PTR: Type = Type::Pointer(&::F32, Some(&::I8), true); &PTR }, &::I64x4, &::I32x4_F32, &::I32_8]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.avx2.gather.q.ps") - }, - "_mm_mask_i64gather_epi64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I64x2, { static PTR: Type = Type::Pointer(&::I64, Some(&::I8), true); &PTR }, &::I64x2, &::I64x2, &::I32_8]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.x86.avx2.gather.q.q") - }, - "_mm_mask_i64gather_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::F64x2, { static PTR: Type = Type::Pointer(&::F64, Some(&::I8), true); &PTR }, &::I64x2, &::I64x2_F64, &::I32_8]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.avx2.gather.q.pd") - }, - "_mm256_mask_i64gather_epi64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I64x4, { static PTR: Type = Type::Pointer(&::I64, Some(&::I8), true); &PTR }, &::I64x4, &::I64x4, &::I32_8]; &INPUTS }, - output: &::I64x4, - definition: Named("llvm.x86.avx2.gather.q.q.256") - }, - "_mm256_mask_i64gather_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::F64x4, { static PTR: Type = Type::Pointer(&::F64, Some(&::I8), true); &PTR }, &::I64x4, &::I64x4_F64, &::I32_8]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx2.gather.q.pd.256") - }, - "_mm_maskload_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::I32x4, Some(&::I8), true); &PTR }, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.x86.avx2.maskload.d") - }, - "_mm_maskload_epi64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::I64x2, Some(&::I8), true); &PTR }, &::I64x2]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.x86.avx2.maskload.q") - }, - "_mm256_maskload_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::I32x8, Some(&::I8), true); &PTR }, &::I32x8]; &INPUTS }, - output: &::I32x8, - definition: Named("llvm.x86.avx2.maskload.d.256") - }, - "_mm256_maskload_epi64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::I64x4, Some(&::I8), true); &PTR }, &::I64x4]; &INPUTS }, - output: &::I64x4, - definition: Named("llvm.x86.avx2.maskload.q.256") - }, - "_mm_maskstore_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I8), false); &PTR }, &::I32x4, &::I32x4]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.avx2.maskstore.d") - }, - "_mm_maskstore_epi64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I8), false); &PTR }, &::I64x2, &::I64x2]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.avx2.maskstore.q") - }, - "_mm256_maskstore_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [{ static PTR: Type = Type::Pointer(&::I32, Some(&::I8), false); &PTR }, &::I32x8, &::I32x8]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.avx2.maskstore.d.256") - }, - "_mm256_maskstore_epi64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [{ static PTR: Type = Type::Pointer(&::I64, Some(&::I8), false); &PTR }, &::I64x4, &::I64x4]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.avx2.maskstore.q.256") - }, - "_mm256_max_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x32, &::I8x32]; &INPUTS }, - output: &::I8x32, - definition: Named("llvm.x86.avx2.pmaxs.b") - }, - "_mm256_max_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x32, &::U8x32]; &INPUTS }, - output: &::U8x32, - definition: Named("llvm.x86.avx2.pmaxu.b") - }, - "_mm256_max_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.pmaxs.w") - }, - "_mm256_max_epu16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x16, &::U16x16]; &INPUTS }, - output: &::U16x16, - definition: Named("llvm.x86.avx2.pmaxu.w") - }, - "_mm256_max_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x8, &::I32x8]; &INPUTS }, - output: &::I32x8, - definition: Named("llvm.x86.avx2.pmaxs.d") - }, - "_mm256_max_epu32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x8, &::U32x8]; &INPUTS }, - output: &::U32x8, - definition: Named("llvm.x86.avx2.pmaxu.d") - }, - "_mm256_min_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x32, &::I8x32]; &INPUTS }, - output: &::I8x32, - definition: Named("llvm.x86.avx2.pmins.b") - }, - "_mm256_min_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x32, &::U8x32]; &INPUTS }, - output: &::U8x32, - definition: Named("llvm.x86.avx2.pminu.b") - }, - "_mm256_min_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.pmins.w") - }, - "_mm256_min_epu16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x16, &::U16x16]; &INPUTS }, - output: &::U16x16, - definition: Named("llvm.x86.avx2.pminu.w") - }, - "_mm256_min_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x8, &::I32x8]; &INPUTS }, - output: &::I32x8, - definition: Named("llvm.x86.avx2.pmins.d") - }, - "_mm256_min_epu32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x8, &::U32x8]; &INPUTS }, - output: &::U32x8, - definition: Named("llvm.x86.avx2.pminu.d") - }, - "_mm256_movemask_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x32]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx2.pmovmskb") - }, - "_mm256_mpsadbw_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x32, &::U8x32, &::I32_8]; &INPUTS }, - output: &::U16x16, - definition: Named("llvm.x86.avx2.mpsadbw") - }, - "_mm256_mul_epi64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x8, &::I32x8]; &INPUTS }, - output: &::I64x4, - definition: Named("llvm.x86.avx2.pmulq.dq") - }, - "_mm256_mul_epu64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x8, &::U32x8]; &INPUTS }, - output: &::U64x4, - definition: Named("llvm.x86.avx2.pmulq.dq") - }, - "_mm256_mulhi_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.pmulhw.w") - }, - "_mm256_mulhi_epu16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x16, &::U16x16]; &INPUTS }, - output: &::U16x16, - definition: Named("llvm.x86.avx2.pmulhw.w") - }, - "_mm256_mulhrs_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.pmul.hr.sw") - }, - "_mm256_packs_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::I8x32, - definition: Named("llvm.x86.avx2.packsswb") - }, - "_mm256_packus_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::U8x32, - definition: Named("llvm.x86.avx2.packuswb") - }, - "_mm256_packs_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x8, &::I32x8]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.packssdw") - }, - "_mm256_packus_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x8, &::I32x8]; &INPUTS }, - output: &::U16x16, - definition: Named("llvm.x86.avx2.packusdw") - }, - "_mm256_permutevar8x32_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x8, &::I32x8]; &INPUTS }, - output: &::I32x8, - definition: Named("llvm.x86.avx2.permd") - }, - "_mm256_permutevar8x32_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x8, &::I32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx2.permps") - }, - "_mm256_sad_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x32, &::U8x32]; &INPUTS }, - output: &::U64x4, - definition: Named("llvm.x86.avx2.psad.bw") - }, - "_mm256_shuffle_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x32, &::I8x32]; &INPUTS }, - output: &::I8x32, - definition: Named("llvm.x86.avx2.pshuf.b") - }, - "_mm256_sign_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x32, &::I8x32]; &INPUTS }, - output: &::I8x32, - definition: Named("llvm.x86.avx2.psign.b") - }, - "_mm256_sign_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.psign.w") - }, - "_mm256_sign_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x8, &::I32x8]; &INPUTS }, - output: &::I32x8, - definition: Named("llvm.x86.avx2.psign.d") - }, - "_mm256_subs_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x32, &::I8x32]; &INPUTS }, - output: &::I8x32, - definition: Named("llvm.x86.avx2.psubs.b") - }, - "_mm256_subs_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x32, &::U8x32]; &INPUTS }, - output: &::U8x32, - definition: Named("llvm.x86.avx2.psubus.b") - }, - "_mm256_subs_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x16, &::I16x16]; &INPUTS }, - output: &::I16x16, - definition: Named("llvm.x86.avx2.psubs.w") - }, - "_mm256_subs_epu16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x16, &::U16x16]; &INPUTS }, - output: &::U16x16, - definition: Named("llvm.x86.avx2.psubus.w") - }, - "_mm256_addsub_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x8, &::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.addsub.ps.256") - }, - "_mm256_addsub_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x4, &::F64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx.addsub.pd.256") - }, - "_mm256_blendv_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x8, &::F32x8, &::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.blendv.ps.256") - }, - "_mm256_blendv_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x4, &::F64x4, &::F64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx.blendv.pd.256") - }, - "_mm256_broadcast_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.vbroadcastf128.ps.256") - }, - "_mm256_broadcast_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::I8, None, true); &PTR }]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx.vbroadcastf128.pd.256") - }, - "_mm256_cmp_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x8, &::F32x8, &::I8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.cmp.ps.256") - }, - "_mm256_cmp_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x4, &::F64x4, &::I8]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx.cmp.pd.256") - }, - "_mm256_cvtepi32_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx.cvtdq2.pd.256") - }, - "_mm256_cvtepi32_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.cvtdq2.ps.256") - }, - "_mm256_cvtpd_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.x86.avx.cvt.pd2dq.256") - }, - "_mm256_cvtpd_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.avx.cvt.pd2.ps.256") - }, - "_mm256_cvtps_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x8]; &INPUTS }, - output: &::I32x8, - definition: Named("llvm.x86.avx.cvt.ps2dq.256") - }, - "_mm256_cvtps_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx.cvt.ps2.pd.256") - }, - "_mm256_cvttpd_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.x86.avx.cvtt.pd2dq.256") - }, - "_mm256_cvttps_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x8]; &INPUTS }, - output: &::I32x8, - definition: Named("llvm.x86.avx.cvtt.ps2dq.256") - }, - "_mm256_dp_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x8, &::F32x8, &::I32_8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.dp.ps.256") - }, - "_mm256_hadd_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x8, &::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.hadd.ps.256") - }, - "_mm256_hadd_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x4, &::F64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx.hadd.pd.256") - }, - "_mm256_hsub_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x8, &::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.hsub.ps.256") - }, - "_mm256_hsub_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x4, &::F64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx.hsub.pd.256") - }, - "_mm256_max_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x8, &::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.max.ps.256") - }, - "_mm256_max_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x4, &::F64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx.max.pd.256") - }, - "_mm_maskload_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::I8), true); &PTR }, &::I32x4_F32]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.avx.maskload.ps") - }, - "_mm_maskload_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::I8), true); &PTR }, &::I64x2_F64]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.avx.maskload.pd") - }, - "_mm256_maskload_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::I8), true); &PTR }, &::I32x8_F32]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.maskload.ps.256") - }, - "_mm256_maskload_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::I8), true); &PTR }, &::I64x4_F64]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx.maskload.pd.256") - }, - "_mm_maskstore_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::I8), false); &PTR }, &::I32x4_F32, &::F32x4]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.avx.maskstore.ps") - }, - "_mm_maskstore_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::I8), false); &PTR }, &::I64x2_F64, &::F64x2]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.avx.maskstore.pd") - }, - "_mm256_maskstore_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::I8), false); &PTR }, &::I32x8_F32, &::F32x8]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.avx.maskstore.ps.256") - }, - "_mm256_maskstore_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::I8), false); &PTR }, &::I64x4_F64, &::F64x4]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.avx.maskstore.pd.256") - }, - "_mm256_min_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x8, &::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.min.ps.256") - }, - "_mm256_min_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x4, &::F64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx.min.pd.256") - }, - "_mm256_movemask_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.movmsk.ps.256") - }, - "_mm256_movemask_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.movmsk.pd.256") - }, - "_mm_permutevar_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::I32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.avx.vpermilvar.ps") - }, - "_mm_permutevar_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::I64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.avx.vpermilvar.pd") - }, - "_mm256_permutevar_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x8, &::I32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.vpermilvar.ps.256") - }, - "_mm256_permutevar_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x4, &::I64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.avx.vpermilvar.pd.256") - }, - "_mm256_rcp_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.rcp.ps.256") - }, - "_mm256_rsqrt_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.avx.rsqrt.ps.256") - }, - "_mm256_storeu_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::F32x8, Some(&::U8), false); &PTR }, &::F32x8]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.avx.storeu.ps.256") - }, - "_mm256_storeu_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::F64x4, Some(&::U8), false); &PTR }, &::F64x4]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.avx.storeu.ps.256") - }, - "_mm256_storeu_si256" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::U8x32, Some(&::U8), false); &PTR }, &::U8x32]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.avx.storeu.dq.256") - }, - "_mm256_sqrt_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.sqrt.v8f32") - }, - "_mm256_sqrt_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.sqrt.v4f64") - }, - "_mm_testc_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.vtestc.ps") - }, - "_mm256_testc_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x8, &::F32x8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.vtestc.ps.256") - }, - "_mm_testc_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.vtestc.pd") - }, - "_mm256_testc_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x4, &::F64x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.vtestc.pd.256") - }, - "_mm256_testc_si256" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x4, &::U64x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.ptestc.256") - }, - "_mm_testnzc_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.vtestnzc.ps") - }, - "_mm256_testnzc_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x8, &::F32x8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.vtestnzc.ps.256") - }, - "_mm_testnzc_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.vtestnzc.pd") - }, - "_mm256_testnzc_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x4, &::F64x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.vtestnzc.pd.256") - }, - "_mm256_testnzc_si256" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x4, &::U64x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.ptestnzc.256") - }, - "_mm_testz_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.vtestz.ps") - }, - "_mm256_testz_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x8, &::F32x8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.vtestz.ps.256") - }, - "_mm_testz_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.vtestz.pd") - }, - "_mm256_testz_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x4, &::F64x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.vtestz.pd.256") - }, - "_mm256_testz_si256" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x4, &::U64x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.avx.ptestz.256") - }, - "_mm256_zeroall" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.avx.vzeroall") - }, - "_mm256_zeroupper" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.avx.vzeroupper") - }, - "_bmi2_bzhi_32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32, &::U32]; &INPUTS }, - output: &::U32, - definition: Named("llvm.x86.bmi.bzhi.32") - }, - "_bmi2_bzhi_64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64, &::U64]; &INPUTS }, - output: &::U64, - definition: Named("llvm.x86.bmi.bzhi.64") - }, - "_bmi2_pdep_32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32, &::U32]; &INPUTS }, - output: &::U32, - definition: Named("llvm.x86.bmi.pdep.32") - }, - "_bmi2_pdep_64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64, &::U64]; &INPUTS }, - output: &::U64, - definition: Named("llvm.x86.bmi.pdep.64") - }, - "_bmi2_pext_32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32, &::U32]; &INPUTS }, - output: &::U32, - definition: Named("llvm.x86.bmi.pext.32") - }, - "_bmi2_pext_64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64, &::U64]; &INPUTS }, - output: &::U64, - definition: Named("llvm.x86.bmi.pext.64") - }, - "_bmi_bextr_32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32, &::U32]; &INPUTS }, - output: &::U32, - definition: Named("llvm.x86.bmi.bextr.32") - }, - "_bmi_bextr_64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64, &::U64]; &INPUTS }, - output: &::U64, - definition: Named("llvm.x86.bmi.bextr.64") - }, - "_mm_fmadd_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.fma.vfmadd.ps") - }, - "_mm_fmadd_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.fma.vfmadd.pd") - }, - "_mm256_fmadd_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x8, &::F32x8, &::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.fma.vfmadd.ps.256") - }, - "_mm256_fmadd_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x4, &::F64x4, &::F64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.fma.vfmadd.pd.256") - }, - "_mm_fmaddsub_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.fma.vfmaddsub.ps") - }, - "_mm_fmaddsub_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.fma.vfmaddsub.pd") - }, - "_mm256_fmaddsub_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x8, &::F32x8, &::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.fma.vfmaddsub.ps.256") - }, - "_mm256_fmaddsub_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x4, &::F64x4, &::F64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.fma.vfmaddsub.pd.256") - }, - "_mm_fmsub_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.fma.vfmsub.ps") - }, - "_mm_fmsub_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.fma.vfmsub.pd") - }, - "_mm256_fmsub_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x8, &::F32x8, &::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.fma.vfmsub.ps.256") - }, - "_mm256_fmsub_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x4, &::F64x4, &::F64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.fma.vfmsub.pd.256") - }, - "_mm_fmsubadd_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.fma.vfmsubadd.ps") - }, - "_mm_fmsubadd_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.fma.vfmsubadd.pd") - }, - "_mm256_fmsubadd_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x8, &::F32x8, &::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.fma.vfmsubadd.ps.256") - }, - "_mm256_fmsubadd_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x4, &::F64x4, &::F64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.fma.vfmsubadd.pd.256") - }, - "_mm_fnmadd_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.fma.vfnmadd.ps") - }, - "_mm_fnmadd_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.fma.vfnmadd.pd") - }, - "_mm256_fnmadd_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x8, &::F32x8, &::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.fma.vfnmadd.ps.256") - }, - "_mm256_fnmadd_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x4, &::F64x4, &::F64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.fma.vfnmadd.pd.256") - }, - "_mm_fnmsub_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.fma.vfnmsub.ps") - }, - "_mm_fnmsub_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.fma.vfnmsub.pd") - }, - "_mm256_fnmsub_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x8, &::F32x8, &::F32x8]; &INPUTS }, - output: &::F32x8, - definition: Named("llvm.x86.fma.vfnmsub.ps.256") - }, - "_mm256_fnmsub_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x4, &::F64x4, &::F64x4]; &INPUTS }, - output: &::F64x4, - definition: Named("llvm.x86.fma.vfnmsub.pd.256") - }, - "_rdrand16_step" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16, &::I32]; &PARTS }); &AGG }, - definition: Named("llvm.x86.rdrand.16") - }, - "_rdrand32_step" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32, &::I32]; &PARTS }); &AGG }, - definition: Named("llvm.x86.rdrand.32") - }, - "_rdrand64_step" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64, &::I32]; &PARTS }); &AGG }, - definition: Named("llvm.x86.rdrand.64") - }, - "_rdseed16_step" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U16, &::I32]; &PARTS }); &AGG }, - definition: Named("llvm.x86.rdseed.16") - }, - "_rdseed32_step" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U32, &::I32]; &PARTS }); &AGG }, - definition: Named("llvm.x86.rdseed.32") - }, - "_rdseed64_step" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: { static AGG: Type = Type::Aggregate(false, { static PARTS: [&'static Type; 2] = [&::U64, &::I32]; &PARTS }); &AGG }, - definition: Named("llvm.x86.rdseed.64") - }, - "_mm_adds_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.x86.sse2.padds.b") - }, - "_mm_adds_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.x86.sse2.paddus.b") - }, - "_mm_adds_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.sse2.padds.w") - }, - "_mm_adds_epu16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.x86.sse2.paddus.w") - }, - "_mm_avg_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.x86.sse2.pavg.b") - }, - "_mm_avg_epu16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.x86.sse2.pavg.w") - }, - "_mm_lfence" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.sse2.lfence") - }, - "_mm_madd_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.x86.sse2.pmadd.wd") - }, - "_mm_maskmoveu_si128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x16, &::U8x16, { static PTR: Type = Type::Pointer(&::U8, None, false); &PTR }]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.sse2.maskmov.dqu") - }, - "_mm_max_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.sse2.pmaxs.w") - }, - "_mm_max_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.x86.sse2.pmaxu.b") - }, - "_mm_max_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.sse2.max.pd") - }, - "_mm_mfence" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.sse2.fence") - }, - "_mm_min_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.sse2.pmins.w") - }, - "_mm_min_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.x86.sse2.pminu.b") - }, - "_mm_min_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.sse2.min.pd") - }, - "_mm_movemask_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse2.movmsk.pd") - }, - "_mm_movemask_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse2.pmovmskb.128") - }, - "_mm_mul_epu32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.x86.sse2.pmulu.dq") - }, - "_mm_mulhi_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.sse2.pmulh.w") - }, - "_mm_mulhi_epu16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.x86.sse2.pmulhu.w") - }, - "_mm_packs_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.x86.sse2.packsswb.128") - }, - "_mm_packs_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.sse2.packssdw.128") - }, - "_mm_packus_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.x86.sse2.packuswb.128") - }, - "_mm_sad_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U64x2, - definition: Named("llvm.x86.sse2.psad.bw") - }, - "_mm_sfence" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 0] = []; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.sse2.sfence") - }, - "_mm_sqrt_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.sqrt.v2f64") - }, - "_mm_storeu_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::F64, Some(&::U8), false); &PTR }, &::F64x2]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.sse2.storeu.pd") - }, - "_mm_storeu_si128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::U8x16, Some(&::U8), false); &PTR }, &::U8x16]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.sse2.storeu.dq") - }, - "_mm_subs_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.x86.sse2.psubs.b") - }, - "_mm_subs_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::U8x16]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.x86.sse2.psubus.b") - }, - "_mm_subs_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.sse2.psubs.w") - }, - "_mm_subs_epu16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.x86.sse2.psubus.w") - }, - "_mm_addsub_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.sse3.addsub.ps") - }, - "_mm_addsub_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.sse3.addsub.pd") - }, - "_mm_hadd_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.sse3.hadd.ps") - }, - "_mm_hadd_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.sse3.hadd.pd") - }, - "_mm_hsub_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.sse3.hsub.ps") - }, - "_mm_hsub_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F64x2, &::F64x2]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.sse3.hsub.pd") - }, - "_mm_lddqu_si128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [{ static PTR: Type = Type::Pointer(&::U8x16, Some(&::I8), true); &PTR }]; &INPUTS }, - output: &::U8x16, - definition: Named("llvm.x86.sse3.ldu.dq") - }, - "_mm_dp_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::I32_8]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.sse41.dpps") - }, - "_mm_dp_pd" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::F64x2, &::F64x2, &::I32_8]; &INPUTS }, - output: &::F64x2, - definition: Named("llvm.x86.sse41.dppd") - }, - "_mm_max_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.x86.sse41.pmaxsb") - }, - "_mm_max_epu16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.x86.sse41.pmaxuw") - }, - "_mm_max_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.x86.sse41.pmaxsd") - }, - "_mm_max_epu32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.x86.sse41.pmaxud") - }, - "_mm_min_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.x86.sse41.pminsb") - }, - "_mm_min_epu16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U16x8, &::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.x86.sse41.pminuw") - }, - "_mm_min_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.x86.sse41.pminsd") - }, - "_mm_min_epu32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32x4, &::U32x4]; &INPUTS }, - output: &::U32x4, - definition: Named("llvm.x86.sse41.pminud") - }, - "_mm_minpos_epu16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::U16x8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.x86.sse41.phminposuw") - }, - "_mm_mpsadbw_epu8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::U8x16, &::U8x16, &::I32_8]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.x86.sse41.mpsadbw") - }, - "_mm_mul_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I64x2, - definition: Named("llvm.x86.sse41.pmuldq") - }, - "_mm_packus_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::U16x8, - definition: Named("llvm.x86.sse41.packusdw") - }, - "_mm_testc_si128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse41.ptestc") - }, - "_mm_testnzc_si128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse41.ptestnzc") - }, - "_mm_testz_si128" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64x2, &::U64x2]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse41.ptestz") - }, - "_mm_cmpestra" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I8x16, &::I32, &::I8x16, &::I32, &::I32_8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse42.pcmpestria128") - }, - "_mm_cmpestrc" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I8x16, &::I32, &::I8x16, &::I32, &::I32_8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse42.pcmpestric128") - }, - "_mm_cmpestri" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I8x16, &::I32, &::I8x16, &::I32, &::I32_8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse42.pcmpestri128") - }, - "_mm_cmpestrm" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I8x16, &::I32, &::I8x16, &::I32, &::I32_8]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.x86.sse42.pcmpestrm128") - }, - "_mm_cmpestro" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I8x16, &::I32, &::I8x16, &::I32, &::I32_8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse42.pcmpestrio128") - }, - "_mm_cmpestrs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I8x16, &::I32, &::I8x16, &::I32, &::I32_8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse42.pcmpestris128") - }, - "_mm_cmpestrz" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 5] = [&::I8x16, &::I32, &::I8x16, &::I32, &::I32_8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse42.pcmpestriz128") - }, - "_mm_cmpistra" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I32_8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse42.pcmpistria128") - }, - "_mm_cmpistrc" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I32_8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse42.pcmpistric128") - }, - "_mm_cmpistri" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I32_8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse42.pcmpistri128") - }, - "_mm_cmpistrm" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I32_8]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.x86.sse42.pcmpistrm128") - }, - "_mm_cmpistro" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I32_8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse42.pcmpistrio128") - }, - "_mm_cmpistrs" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I32_8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse42.pcmpistris128") - }, - "_mm_cmpistrz" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 3] = [&::I8x16, &::I8x16, &::I32_8]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse42.pcmpistriz128") - }, - "_mm_movemask_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::I32, - definition: Named("llvm.x86.sse.movmsk.ps") - }, - "_mm_max_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.sse.max.ps") - }, - "_mm_min_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::F32x4, &::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.sse.min.ps") - }, - "_mm_rsqrt_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.sse.rsqrt.ps") - }, - "_mm_rcp_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.x86.sse.rcp.ps") - }, - "_mm_sqrt_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS }, - output: &::F32x4, - definition: Named("llvm.sqrt.v4f32") - }, - "_mm_storeu_ps" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [{ static PTR: Type = Type::Pointer(&::F32, Some(&::I8), false); &PTR }, &::F32x4]; &INPUTS }, - output: &::VOID, - definition: Named("llvm.x86.sse.storeu.ps") - }, - "_mm_abs_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.x86.ssse3.pabs.b.128") - }, - "_mm_abs_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.ssse3.pabs.w.128") - }, - "_mm_abs_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 1] = [&::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.x86.ssse3.pabs.d.128") - }, - "_mm_hadd_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.ssse3.phadd.w.128") - }, - "_mm_hadd_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.x86.ssse3.phadd.d.128") - }, - "_mm_hadds_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.ssse3.phadd.sw.128") - }, - "_mm_hsub_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.ssse3.phsub.w.128") - }, - "_mm_hsub_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.x86.ssse3.phsub.d.128") - }, - "_mm_hsubs_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.ssse3.phsub.sw.128") - }, - "_mm_maddubs_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U8x16, &::I8x16]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.ssse3.pmadd.ub.sw.128") - }, - "_mm_mulhrs_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.ssse3.pmul.hr.sw.128") - }, - "_mm_shuffle_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.x86.ssse3.pshuf.b.128") - }, - "_mm_sign_epi8" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I8x16, &::I8x16]; &INPUTS }, - output: &::I8x16, - definition: Named("llvm.x86.ssse3.psign.b.128") - }, - "_mm_sign_epi16" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I16x8, &::I16x8]; &INPUTS }, - output: &::I16x8, - definition: Named("llvm.x86.ssse3.psign.w.128") - }, - "_mm_sign_epi32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::I32x4, &::I32x4]; &INPUTS }, - output: &::I32x4, - definition: Named("llvm.x86.ssse3.psign.d.128") - }, - "_tbm_bextri_u32" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U32, &::U32]; &INPUTS }, - output: &::U32, - definition: Named("llvm.x86.tbm.bextri.u32") - }, - "_tbm_bextri_u64" => Intrinsic { - inputs: { static INPUTS: [&'static Type; 2] = [&::U64, &::U64]; &INPUTS }, - output: &::U64, - definition: Named("llvm.x86.tbm.bextri.u64") - }, - _ => return None, - }) -} diff --git a/src/librustc_typeck/Cargo.toml b/src/librustc_typeck/Cargo.toml index 87f11b01a1d94..68b28a60fdff7 100644 --- a/src/librustc_typeck/Cargo.toml +++ b/src/librustc_typeck/Cargo.toml @@ -15,7 +15,6 @@ log = "0.4" rustc = { path = "../librustc" } rustc_data_structures = { path = "../librustc_data_structures" } rustc_errors = { path = "../librustc_errors" } -rustc_platform_intrinsics = { path = "../librustc_platform_intrinsics" } rustc_target = { path = "../librustc_target" } smallvec = { version = "0.6.7", features = ["union", "may_dangle"] } syntax = { path = "../libsyntax" } diff --git a/src/librustc_typeck/check/intrinsic.rs b/src/librustc_typeck/check/intrinsic.rs index 9f323b9116d6f..143715dff813b 100644 --- a/src/librustc_typeck/check/intrinsic.rs +++ b/src/librustc_typeck/check/intrinsic.rs @@ -1,17 +1,13 @@ //! Type-checking for the rust-intrinsic and platform-intrinsic //! intrinsics that the compiler exposes. -use intrinsics; use rustc::traits::{ObligationCause, ObligationCauseCode}; use rustc::ty::{self, TyCtxt, Ty}; use rustc::ty::subst::Subst; -use rustc::util::nodemap::FxHashMap; use require_same_types; use rustc_target::spec::abi::Abi; -use syntax::ast; use syntax::symbol::Symbol; -use syntax_pos::Span; use rustc::hir; @@ -402,8 +398,6 @@ pub fn check_platform_intrinsic_type<'a, 'tcx>(tcx: TyCtxt<'a, 'tcx, 'tcx>, tcx.mk_ty_param(n, name) }; - let def_id = tcx.hir().local_def_id(it.id); - let i_n_tps = tcx.generics_of(def_id).own_counts().types; let name = it.ident.as_str(); let (n_tps, inputs, output) = match &*name { @@ -461,159 +455,12 @@ pub fn check_platform_intrinsic_type<'a, 'tcx>(tcx: TyCtxt<'a, 'tcx, 'tcx>, } } _ => { - match intrinsics::Intrinsic::find(&name) { - Some(intr) => { - // this function is a platform specific intrinsic - if i_n_tps != 0 { - span_err!(tcx.sess, it.span, E0440, - "platform-specific intrinsic has wrong number of type \ - parameters: found {}, expected 0", - i_n_tps); - return - } - - let mut structural_to_nomimal = FxHashMap::default(); - - let sig = tcx.fn_sig(def_id); - let sig = sig.no_bound_vars().unwrap(); - if intr.inputs.len() != sig.inputs().len() { - span_err!(tcx.sess, it.span, E0444, - "platform-specific intrinsic has invalid number of \ - arguments: found {}, expected {}", - sig.inputs().len(), intr.inputs.len()); - return - } - let input_pairs = intr.inputs.iter().zip(sig.inputs()); - for (i, (expected_arg, arg)) in input_pairs.enumerate() { - match_intrinsic_type_to_type(tcx, &format!("argument {}", i + 1), it.span, - &mut structural_to_nomimal, expected_arg, arg); - } - match_intrinsic_type_to_type(tcx, "return value", it.span, - &mut structural_to_nomimal, - &intr.output, sig.output()); - return - } - None => { - span_err!(tcx.sess, it.span, E0441, - "unrecognized platform-specific intrinsic function: `{}`", name); - return; - } - } + let msg = format!("unrecognized platform-specific intrinsic function: `{}`", name); + tcx.sess.span_err(it.span, &msg); + return; } }; equate_intrinsic_type(tcx, it, n_tps, Abi::PlatformIntrinsic, hir::Unsafety::Unsafe, inputs, output) } - -// walk the expected type and the actual type in lock step, checking they're -// the same, in a kinda-structural way, i.e., `Vector`s have to be simd structs with -// exactly the right element type -fn match_intrinsic_type_to_type<'a, 'tcx>( - tcx: TyCtxt<'a, 'tcx, 'tcx>, - position: &str, - span: Span, - structural_to_nominal: &mut FxHashMap<&'a intrinsics::Type, Ty<'tcx>>, - expected: &'a intrinsics::Type, t: Ty<'tcx>) -{ - use intrinsics::Type::*; - - let simple_error = |real: &str, expected: &str| { - span_err!(tcx.sess, span, E0442, - "intrinsic {} has wrong type: found {}, expected {}", - position, real, expected) - }; - - match *expected { - Void => match t.sty { - ty::Tuple(ref v) if v.is_empty() => {}, - _ => simple_error(&format!("`{}`", t), "()"), - }, - // (The width we pass to LLVM doesn't concern the type checker.) - Integer(signed, bits, _llvm_width) => match (signed, bits, &t.sty) { - (true, 8, &ty::Int(ast::IntTy::I8)) | - (false, 8, &ty::Uint(ast::UintTy::U8)) | - (true, 16, &ty::Int(ast::IntTy::I16)) | - (false, 16, &ty::Uint(ast::UintTy::U16)) | - (true, 32, &ty::Int(ast::IntTy::I32)) | - (false, 32, &ty::Uint(ast::UintTy::U32)) | - (true, 64, &ty::Int(ast::IntTy::I64)) | - (false, 64, &ty::Uint(ast::UintTy::U64)) | - (true, 128, &ty::Int(ast::IntTy::I128)) | - (false, 128, &ty::Uint(ast::UintTy::U128)) => {}, - _ => simple_error(&format!("`{}`", t), - &format!("`{}{n}`", - if signed {"i"} else {"u"}, - n = bits)), - }, - Float(bits) => match (bits, &t.sty) { - (32, &ty::Float(ast::FloatTy::F32)) | - (64, &ty::Float(ast::FloatTy::F64)) => {}, - _ => simple_error(&format!("`{}`", t), - &format!("`f{n}`", n = bits)), - }, - Pointer(ref inner_expected, ref _llvm_type, const_) => { - match t.sty { - ty::RawPtr(ty::TypeAndMut { ty, mutbl }) => { - if (mutbl == hir::MutImmutable) != const_ { - simple_error(&format!("`{}`", t), - if const_ {"const pointer"} else {"mut pointer"}) - } - match_intrinsic_type_to_type(tcx, position, span, structural_to_nominal, - inner_expected, ty) - } - _ => simple_error(&format!("`{}`", t), "raw pointer"), - } - } - Vector(ref inner_expected, ref _llvm_type, len) => { - if !t.is_simd() { - simple_error(&format!("non-simd type `{}`", t), "simd type"); - return; - } - let t_len = t.simd_size(tcx); - if len as usize != t_len { - simple_error(&format!("vector with length {}", t_len), - &format!("length {}", len)); - return; - } - let t_ty = t.simd_type(tcx); - { - // check that a given structural type always has the same an intrinsic definition - let previous = structural_to_nominal.entry(expected).or_insert(t); - if *previous != t { - // this gets its own error code because it is non-trivial - span_err!(tcx.sess, span, E0443, - "intrinsic {} has wrong type: found `{}`, expected `{}` which \ - was used for this vector type previously in this signature", - position, - t, - *previous); - return; - } - } - match_intrinsic_type_to_type(tcx, - position, - span, - structural_to_nominal, - inner_expected, - t_ty) - } - Aggregate(_flatten, ref expected_contents) => { - match t.sty { - ty::Tuple(contents) => { - if contents.len() != expected_contents.len() { - simple_error(&format!("tuple with length {}", contents.len()), - &format!("tuple with length {}", expected_contents.len())); - return - } - for (e, c) in expected_contents.iter().zip(contents) { - match_intrinsic_type_to_type(tcx, position, span, structural_to_nominal, - e, c) - } - } - _ => simple_error(&format!("`{}`", t), - "tuple"), - } - } - } -} diff --git a/src/librustc_typeck/diagnostics.rs b/src/librustc_typeck/diagnostics.rs index 387dabe747ab8..4928001bc1ffe 100644 --- a/src/librustc_typeck/diagnostics.rs +++ b/src/librustc_typeck/diagnostics.rs @@ -3369,180 +3369,6 @@ extern "platform-intrinsic" { ``` "##, -E0440: r##" -A platform-specific intrinsic function has the wrong number of type -parameters. Erroneous code example: - -```compile_fail,E0440 -#![feature(repr_simd)] -#![feature(platform_intrinsics)] - -#[repr(simd)] -struct f64x2(f64, f64); - -extern "platform-intrinsic" { - fn x86_mm_movemask_pd(x: f64x2) -> i32; - // error: platform-specific intrinsic has wrong number of type - // parameters -} -``` - -Please refer to the function declaration to see if it corresponds -with yours. Example: - -``` -#![feature(repr_simd)] -#![feature(platform_intrinsics)] - -#[repr(simd)] -struct f64x2(f64, f64); - -extern "platform-intrinsic" { - fn x86_mm_movemask_pd(x: f64x2) -> i32; -} -``` -"##, - -E0441: r##" -An unknown platform-specific intrinsic function was used. Erroneous -code example: - -```compile_fail,E0441 -#![feature(repr_simd)] -#![feature(platform_intrinsics)] - -#[repr(simd)] -struct i16x8(i16, i16, i16, i16, i16, i16, i16, i16); - -extern "platform-intrinsic" { - fn x86_mm_adds_ep16(x: i16x8, y: i16x8) -> i16x8; - // error: unrecognized platform-specific intrinsic function -} -``` - -Please verify that the function name wasn't misspelled, and ensure -that it is declared in the rust source code (in the file -src/librustc_platform_intrinsics/x86.rs). Example: - -``` -#![feature(repr_simd)] -#![feature(platform_intrinsics)] - -#[repr(simd)] -struct i16x8(i16, i16, i16, i16, i16, i16, i16, i16); - -extern "platform-intrinsic" { - fn x86_mm_adds_epi16(x: i16x8, y: i16x8) -> i16x8; // ok! -} -``` -"##, - -E0442: r##" -Intrinsic argument(s) and/or return value have the wrong type. -Erroneous code example: - -```compile_fail,E0442 -#![feature(repr_simd)] -#![feature(platform_intrinsics)] - -#[repr(simd)] -struct i8x16(i8, i8, i8, i8, i8, i8, i8, i8, - i8, i8, i8, i8, i8, i8, i8, i8); -#[repr(simd)] -struct i32x4(i32, i32, i32, i32); -#[repr(simd)] -struct i64x2(i64, i64); - -extern "platform-intrinsic" { - fn x86_mm_adds_epi16(x: i8x16, y: i32x4) -> i64x2; - // error: intrinsic arguments/return value have wrong type -} -``` - -To fix this error, please refer to the function declaration to give -it the awaited types. Example: - -``` -#![feature(repr_simd)] -#![feature(platform_intrinsics)] - -#[repr(simd)] -struct i16x8(i16, i16, i16, i16, i16, i16, i16, i16); - -extern "platform-intrinsic" { - fn x86_mm_adds_epi16(x: i16x8, y: i16x8) -> i16x8; // ok! -} -``` -"##, - -E0443: r##" -Intrinsic argument(s) and/or return value have the wrong type. -Erroneous code example: - -```compile_fail,E0443 -#![feature(repr_simd)] -#![feature(platform_intrinsics)] - -#[repr(simd)] -struct i16x8(i16, i16, i16, i16, i16, i16, i16, i16); -#[repr(simd)] -struct i64x8(i64, i64, i64, i64, i64, i64, i64, i64); - -extern "platform-intrinsic" { - fn x86_mm_adds_epi16(x: i16x8, y: i16x8) -> i64x8; - // error: intrinsic argument/return value has wrong type -} -``` - -To fix this error, please refer to the function declaration to give -it the awaited types. Example: - -``` -#![feature(repr_simd)] -#![feature(platform_intrinsics)] - -#[repr(simd)] -struct i16x8(i16, i16, i16, i16, i16, i16, i16, i16); - -extern "platform-intrinsic" { - fn x86_mm_adds_epi16(x: i16x8, y: i16x8) -> i16x8; // ok! -} -``` -"##, - -E0444: r##" -A platform-specific intrinsic function has wrong number of arguments. -Erroneous code example: - -```compile_fail,E0444 -#![feature(repr_simd)] -#![feature(platform_intrinsics)] - -#[repr(simd)] -struct f64x2(f64, f64); - -extern "platform-intrinsic" { - fn x86_mm_movemask_pd(x: f64x2, y: f64x2, z: f64x2) -> i32; - // error: platform-specific intrinsic has invalid number of arguments -} -``` - -Please refer to the function declaration to see if it corresponds -with yours. Example: - -``` -#![feature(repr_simd)] -#![feature(platform_intrinsics)] - -#[repr(simd)] -struct f64x2(f64, f64); - -extern "platform-intrinsic" { - fn x86_mm_movemask_pd(x: f64x2) -> i32; // ok! -} -``` -"##, - E0516: r##" The `typeof` keyword is currently reserved but unimplemented. Erroneous code example: diff --git a/src/librustc_typeck/lib.rs b/src/librustc_typeck/lib.rs index c55a1258ce955..8bd484aa0d352 100644 --- a/src/librustc_typeck/lib.rs +++ b/src/librustc_typeck/lib.rs @@ -82,7 +82,6 @@ extern crate syntax_pos; extern crate arena; #[macro_use] extern crate rustc; -extern crate rustc_platform_intrinsics as intrinsics; extern crate rustc_data_structures; extern crate rustc_errors as errors; extern crate rustc_target; diff --git a/src/test/run-pass/simd/simd-upgraded.rs b/src/test/run-pass/simd/simd-upgraded.rs deleted file mode 100644 index afba298d33d54..0000000000000 --- a/src/test/run-pass/simd/simd-upgraded.rs +++ /dev/null @@ -1,24 +0,0 @@ -// run-pass -#![allow(stable_features)] -#![allow(non_camel_case_types)] - -// Test that removed LLVM SIMD intrinsics continue -// to work via the "AutoUpgrade" mechanism. - -#![feature(cfg_target_feature, repr_simd)] -#![feature(platform_intrinsics, stmt_expr_attributes)] - -#[repr(simd)] -#[derive(PartialEq, Debug)] -struct i16x8(i16, i16, i16, i16, i16, i16, i16, i16); - -fn main() { - #[cfg(target_feature = "sse2")] unsafe { - extern "platform-intrinsic" { - fn x86_mm_min_epi16(x: i16x8, y: i16x8) -> i16x8; - } - assert_eq!(x86_mm_min_epi16(i16x8(0, 1, 2, 3, 4, 5, 6, 7), - i16x8(7, 6, 5, 4, 3, 2, 1, 0)), - i16x8(0, 1, 2, 3, 3, 2, 1, 0)); - }; -} diff --git a/src/test/ui/error-codes/E0440.rs b/src/test/ui/error-codes/E0440.rs deleted file mode 100644 index 8ac47f5ab5306..0000000000000 --- a/src/test/ui/error-codes/E0440.rs +++ /dev/null @@ -1,13 +0,0 @@ -#![feature(repr_simd)] -#![feature(platform_intrinsics)] -#![allow(non_camel_case_types)] - -#[repr(simd)] -struct f64x2(f64, f64); - -extern "platform-intrinsic" { - fn x86_mm_movemask_pd(x: f64x2) -> i32; //~ ERROR E0440 -} - -fn main () { -} diff --git a/src/test/ui/error-codes/E0440.stderr b/src/test/ui/error-codes/E0440.stderr deleted file mode 100644 index e153fb0f73f6f..0000000000000 --- a/src/test/ui/error-codes/E0440.stderr +++ /dev/null @@ -1,9 +0,0 @@ -error[E0440]: platform-specific intrinsic has wrong number of type parameters: found 1, expected 0 - --> $DIR/E0440.rs:9:5 - | -LL | fn x86_mm_movemask_pd(x: f64x2) -> i32; //~ ERROR E0440 - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error: aborting due to previous error - -For more information about this error, try `rustc --explain E0440`. diff --git a/src/test/ui/error-codes/E0441.rs b/src/test/ui/error-codes/E0441.rs deleted file mode 100644 index 90bdbe96c2d65..0000000000000 --- a/src/test/ui/error-codes/E0441.rs +++ /dev/null @@ -1,12 +0,0 @@ -#![feature(repr_simd)] -#![feature(platform_intrinsics)] -#![allow(non_camel_case_types)] - -#[repr(simd)] -struct i16x8(i16, i16, i16, i16, i16, i16, i16, i16); - -extern "platform-intrinsic" { - fn x86_mm_adds_ep16(x: i16x8, y: i16x8) -> i16x8; //~ ERROR E0441 -} - -fn main() {} diff --git a/src/test/ui/error-codes/E0441.stderr b/src/test/ui/error-codes/E0441.stderr deleted file mode 100644 index 73eddb2604e47..0000000000000 --- a/src/test/ui/error-codes/E0441.stderr +++ /dev/null @@ -1,9 +0,0 @@ -error[E0441]: unrecognized platform-specific intrinsic function: `x86_mm_adds_ep16` - --> $DIR/E0441.rs:9:5 - | -LL | fn x86_mm_adds_ep16(x: i16x8, y: i16x8) -> i16x8; //~ ERROR E0441 - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error: aborting due to previous error - -For more information about this error, try `rustc --explain E0441`. diff --git a/src/test/ui/error-codes/E0442.rs b/src/test/ui/error-codes/E0442.rs deleted file mode 100644 index a6eb59610f75a..0000000000000 --- a/src/test/ui/error-codes/E0442.rs +++ /dev/null @@ -1,20 +0,0 @@ -#![feature(repr_simd)] -#![feature(platform_intrinsics)] -#![allow(non_camel_case_types)] - -#[repr(simd)] -struct i8x16(i8, i8, i8, i8, i8, i8, i8, i8, - i8, i8, i8, i8, i8, i8, i8, i8); -#[repr(simd)] -struct i32x4(i32, i32, i32, i32); -#[repr(simd)] -struct i64x2(i64, i64); - -extern "platform-intrinsic" { - fn x86_mm_adds_epi16(x: i8x16, y: i32x4) -> i64x2; - //~^ ERROR E0442 - //~| ERROR E0442 - //~| ERROR E0442 -} - -fn main() {} diff --git a/src/test/ui/error-codes/E0442.stderr b/src/test/ui/error-codes/E0442.stderr deleted file mode 100644 index 017d4617a973a..0000000000000 --- a/src/test/ui/error-codes/E0442.stderr +++ /dev/null @@ -1,21 +0,0 @@ -error[E0442]: intrinsic argument 1 has wrong type: found vector with length 16, expected length 8 - --> $DIR/E0442.rs:14:5 - | -LL | fn x86_mm_adds_epi16(x: i8x16, y: i32x4) -> i64x2; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0442]: intrinsic argument 2 has wrong type: found vector with length 4, expected length 8 - --> $DIR/E0442.rs:14:5 - | -LL | fn x86_mm_adds_epi16(x: i8x16, y: i32x4) -> i64x2; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0442]: intrinsic return value has wrong type: found vector with length 2, expected length 8 - --> $DIR/E0442.rs:14:5 - | -LL | fn x86_mm_adds_epi16(x: i8x16, y: i32x4) -> i64x2; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error: aborting due to 3 previous errors - -For more information about this error, try `rustc --explain E0442`. diff --git a/src/test/ui/error-codes/E0443.rs b/src/test/ui/error-codes/E0443.rs deleted file mode 100644 index 4940f1d75399b..0000000000000 --- a/src/test/ui/error-codes/E0443.rs +++ /dev/null @@ -1,14 +0,0 @@ -#![feature(repr_simd)] -#![feature(platform_intrinsics)] -#![allow(non_camel_case_types)] - -#[repr(simd)] -struct i16x8(i16, i16, i16, i16, i16, i16, i16, i16); -#[repr(simd)] -struct i64x8(i64, i64, i64, i64, i64, i64, i64, i64); - -extern "platform-intrinsic" { - fn x86_mm_adds_epi16(x: i16x8, y: i16x8) -> i64x8; //~ ERROR E0443 -} - -fn main() {} diff --git a/src/test/ui/error-codes/E0443.stderr b/src/test/ui/error-codes/E0443.stderr deleted file mode 100644 index 4c2e6418fed9a..0000000000000 --- a/src/test/ui/error-codes/E0443.stderr +++ /dev/null @@ -1,9 +0,0 @@ -error[E0443]: intrinsic return value has wrong type: found `i64x8`, expected `i16x8` which was used for this vector type previously in this signature - --> $DIR/E0443.rs:11:5 - | -LL | fn x86_mm_adds_epi16(x: i16x8, y: i16x8) -> i64x8; //~ ERROR E0443 - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error: aborting due to previous error - -For more information about this error, try `rustc --explain E0443`. diff --git a/src/test/ui/error-codes/E0444.rs b/src/test/ui/error-codes/E0444.rs deleted file mode 100644 index 3d73339bf9aa4..0000000000000 --- a/src/test/ui/error-codes/E0444.rs +++ /dev/null @@ -1,12 +0,0 @@ -#![feature(repr_simd)] -#![feature(platform_intrinsics)] -#![allow(non_camel_case_types)] - -#[repr(simd)] -struct f64x2(f64, f64); - -extern "platform-intrinsic" { - fn x86_mm_movemask_pd(x: f64x2, y: f64x2, z: f64x2) -> i32; //~ ERROR E0444 -} - -fn main() {} diff --git a/src/test/ui/error-codes/E0444.stderr b/src/test/ui/error-codes/E0444.stderr deleted file mode 100644 index 0a894f7edc614..0000000000000 --- a/src/test/ui/error-codes/E0444.stderr +++ /dev/null @@ -1,9 +0,0 @@ -error[E0444]: platform-specific intrinsic has invalid number of arguments: found 3, expected 1 - --> $DIR/E0444.rs:9:5 - | -LL | fn x86_mm_movemask_pd(x: f64x2, y: f64x2, z: f64x2) -> i32; //~ ERROR E0444 - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error: aborting due to previous error - -For more information about this error, try `rustc --explain E0444`. diff --git a/src/test/ui/intrinsic-invalid-number-of-arguments.rs b/src/test/ui/intrinsic-invalid-number-of-arguments.rs deleted file mode 100644 index 7823e7d12a408..0000000000000 --- a/src/test/ui/intrinsic-invalid-number-of-arguments.rs +++ /dev/null @@ -1,15 +0,0 @@ -// Test number of arguments in platform-specific intrinsic function -// This is the error E0444 - -#![feature(repr_simd, platform_intrinsics)] -#![allow(non_camel_case_types)] - -#[repr(simd)] -struct f64x2(f64, f64); - -extern "platform-intrinsic" { - fn x86_mm_movemask_pd(x: f64x2, y: f64x2, z: f64x2) -> i32; //~ platform-specific intrinsic -} - -pub fn main() { -} diff --git a/src/test/ui/intrinsic-invalid-number-of-arguments.stderr b/src/test/ui/intrinsic-invalid-number-of-arguments.stderr deleted file mode 100644 index e2874d554eea1..0000000000000 --- a/src/test/ui/intrinsic-invalid-number-of-arguments.stderr +++ /dev/null @@ -1,9 +0,0 @@ -error[E0444]: platform-specific intrinsic has invalid number of arguments: found 3, expected 1 - --> $DIR/intrinsic-invalid-number-of-arguments.rs:11:5 - | -LL | fn x86_mm_movemask_pd(x: f64x2, y: f64x2, z: f64x2) -> i32; //~ platform-specific intrinsic - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error: aborting due to previous error - -For more information about this error, try `rustc --explain E0444`. diff --git a/src/test/ui/platform-intrinsic-params.rs b/src/test/ui/platform-intrinsic-params.rs deleted file mode 100644 index 5759a10e6c5d4..0000000000000 --- a/src/test/ui/platform-intrinsic-params.rs +++ /dev/null @@ -1,6 +0,0 @@ -#![feature(platform_intrinsics)] -extern "platform-intrinsic" { - fn x86_mm_movemask_ps() -> i32; //~ERROR found 0, expected 1 -} - -fn main() { } diff --git a/src/test/ui/platform-intrinsic-params.stderr b/src/test/ui/platform-intrinsic-params.stderr deleted file mode 100644 index 17671ce6113de..0000000000000 --- a/src/test/ui/platform-intrinsic-params.stderr +++ /dev/null @@ -1,9 +0,0 @@ -error[E0444]: platform-specific intrinsic has invalid number of arguments: found 0, expected 1 - --> $DIR/platform-intrinsic-params.rs:3:5 - | -LL | fn x86_mm_movemask_ps() -> i32; //~ERROR found 0, expected 1 - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error: aborting due to previous error - -For more information about this error, try `rustc --explain E0444`. diff --git a/src/test/ui/simd-intrinsic/simd-intrinsic-declaration-type.rs b/src/test/ui/simd-intrinsic/simd-intrinsic-declaration-type.rs deleted file mode 100644 index 7405678696a0b..0000000000000 --- a/src/test/ui/simd-intrinsic/simd-intrinsic-declaration-type.rs +++ /dev/null @@ -1,59 +0,0 @@ -#![feature(repr_simd, platform_intrinsics)] -#![allow(non_camel_case_types)] - -#[repr(simd)] -struct i16x8(i16, i16, i16, i16, i16, i16, i16, i16); -#[repr(simd)] -struct u16x8(u16, u16, u16, u16, u16, u16, u16, u16); - -#[repr(simd)] -struct i8x16(i8, i8, i8, i8, i8, i8, i8, i8, - i8, i8, i8, i8, i8, i8, i8, i8); -#[repr(simd)] -struct i32x4(i32, i32, i32, i32); -#[repr(simd)] -struct f32x4(f32, f32, f32, f32); -#[repr(simd)] -struct i64x2(i64, i64); - -// correct signatures work well -mod right { - use {i16x8, u16x8}; - extern "platform-intrinsic" { - fn x86_mm_adds_epi16(x: i16x8, y: i16x8) -> i16x8; - fn x86_mm_adds_epu16(x: u16x8, y: u16x8) -> u16x8; - } -} -// but incorrect ones don't. - -mod signedness { - use {i16x8, u16x8}; - // signedness matters - extern "platform-intrinsic" { - fn x86_mm_adds_epi16(x: u16x8, y: u16x8) -> u16x8; - //~^ ERROR intrinsic argument 1 has wrong type - //~^^ ERROR intrinsic argument 2 has wrong type - //~^^^ ERROR intrinsic return value has wrong type - fn x86_mm_adds_epu16(x: i16x8, y: i16x8) -> i16x8; - //~^ ERROR intrinsic argument 1 has wrong type - //~^^ ERROR intrinsic argument 2 has wrong type - //~^^^ ERROR intrinsic return value has wrong type - } -} -// as do lengths -extern "platform-intrinsic" { - fn x86_mm_adds_epi16(x: i8x16, y: i32x4) -> i64x2; - //~^ ERROR intrinsic argument 1 has wrong type - //~^^ ERROR intrinsic argument 2 has wrong type - //~^^^ ERROR intrinsic return value has wrong type -} -// and so does int vs. float: -extern "platform-intrinsic" { - fn x86_mm_max_ps(x: i32x4, y: i32x4) -> i32x4; - //~^ ERROR intrinsic argument 1 has wrong type - //~^^ ERROR intrinsic argument 2 has wrong type - //~^^^ ERROR intrinsic return value has wrong type -} - - -fn main() {} diff --git a/src/test/ui/simd-intrinsic/simd-intrinsic-declaration-type.stderr b/src/test/ui/simd-intrinsic/simd-intrinsic-declaration-type.stderr deleted file mode 100644 index 22df5e42d2607..0000000000000 --- a/src/test/ui/simd-intrinsic/simd-intrinsic-declaration-type.stderr +++ /dev/null @@ -1,75 +0,0 @@ -error[E0442]: intrinsic argument 1 has wrong type: found vector with length 16, expected length 8 - --> $DIR/simd-intrinsic-declaration-type.rs:45:5 - | -LL | fn x86_mm_adds_epi16(x: i8x16, y: i32x4) -> i64x2; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0442]: intrinsic argument 2 has wrong type: found vector with length 4, expected length 8 - --> $DIR/simd-intrinsic-declaration-type.rs:45:5 - | -LL | fn x86_mm_adds_epi16(x: i8x16, y: i32x4) -> i64x2; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0442]: intrinsic return value has wrong type: found vector with length 2, expected length 8 - --> $DIR/simd-intrinsic-declaration-type.rs:45:5 - | -LL | fn x86_mm_adds_epi16(x: i8x16, y: i32x4) -> i64x2; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0442]: intrinsic argument 1 has wrong type: found `i32`, expected `f32` - --> $DIR/simd-intrinsic-declaration-type.rs:52:5 - | -LL | fn x86_mm_max_ps(x: i32x4, y: i32x4) -> i32x4; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0442]: intrinsic argument 2 has wrong type: found `i32`, expected `f32` - --> $DIR/simd-intrinsic-declaration-type.rs:52:5 - | -LL | fn x86_mm_max_ps(x: i32x4, y: i32x4) -> i32x4; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0442]: intrinsic return value has wrong type: found `i32`, expected `f32` - --> $DIR/simd-intrinsic-declaration-type.rs:52:5 - | -LL | fn x86_mm_max_ps(x: i32x4, y: i32x4) -> i32x4; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0442]: intrinsic argument 1 has wrong type: found `u16`, expected `i16` - --> $DIR/simd-intrinsic-declaration-type.rs:33:9 - | -LL | fn x86_mm_adds_epi16(x: u16x8, y: u16x8) -> u16x8; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0442]: intrinsic argument 2 has wrong type: found `u16`, expected `i16` - --> $DIR/simd-intrinsic-declaration-type.rs:33:9 - | -LL | fn x86_mm_adds_epi16(x: u16x8, y: u16x8) -> u16x8; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0442]: intrinsic return value has wrong type: found `u16`, expected `i16` - --> $DIR/simd-intrinsic-declaration-type.rs:33:9 - | -LL | fn x86_mm_adds_epi16(x: u16x8, y: u16x8) -> u16x8; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0442]: intrinsic argument 1 has wrong type: found `i16`, expected `u16` - --> $DIR/simd-intrinsic-declaration-type.rs:37:9 - | -LL | fn x86_mm_adds_epu16(x: i16x8, y: i16x8) -> i16x8; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0442]: intrinsic argument 2 has wrong type: found `i16`, expected `u16` - --> $DIR/simd-intrinsic-declaration-type.rs:37:9 - | -LL | fn x86_mm_adds_epu16(x: i16x8, y: i16x8) -> i16x8; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0442]: intrinsic return value has wrong type: found `i16`, expected `u16` - --> $DIR/simd-intrinsic-declaration-type.rs:37:9 - | -LL | fn x86_mm_adds_epu16(x: i16x8, y: i16x8) -> i16x8; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error: aborting due to 12 previous errors - -For more information about this error, try `rustc --explain E0442`. diff --git a/src/test/ui/simd-intrinsic/simd-intrinsic-single-nominal-type.rs b/src/test/ui/simd-intrinsic/simd-intrinsic-single-nominal-type.rs deleted file mode 100644 index f38ef2e93e7d5..0000000000000 --- a/src/test/ui/simd-intrinsic/simd-intrinsic-single-nominal-type.rs +++ /dev/null @@ -1,23 +0,0 @@ -#![feature(repr_simd, platform_intrinsics)] - -#[repr(simd)] -struct A(i16, i16, i16, i16, i16, i16, i16, i16); -#[repr(simd)] -struct B(i16, i16, i16, i16, i16, i16, i16, i16); - -// each intrinsic definition has to use the same nominal type for any -// vector structure throughout that declaration (i.e., every instance -// of i16x8 in each `fn ...;` needs to be either A or B) - -extern "platform-intrinsic" { - fn x86_mm_adds_epi16(x: A, y: A) -> B; - //~^ ERROR intrinsic return value has wrong type: found `B`, expected `A` - fn x86_mm_subs_epi16(x: A, y: B) -> A; - //~^ ERROR intrinsic argument 2 has wrong type: found `B`, expected `A` - - // ok: - fn x86_mm_max_epi16(x: B, y: B) -> B; - fn x86_mm_min_epi16(x: A, y: A) -> A; -} - -fn main() {} diff --git a/src/test/ui/simd-intrinsic/simd-intrinsic-single-nominal-type.stderr b/src/test/ui/simd-intrinsic/simd-intrinsic-single-nominal-type.stderr deleted file mode 100644 index 2754dd17b9963..0000000000000 --- a/src/test/ui/simd-intrinsic/simd-intrinsic-single-nominal-type.stderr +++ /dev/null @@ -1,15 +0,0 @@ -error[E0443]: intrinsic return value has wrong type: found `B`, expected `A` which was used for this vector type previously in this signature - --> $DIR/simd-intrinsic-single-nominal-type.rs:13:5 - | -LL | fn x86_mm_adds_epi16(x: A, y: A) -> B; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error[E0443]: intrinsic argument 2 has wrong type: found `B`, expected `A` which was used for this vector type previously in this signature - --> $DIR/simd-intrinsic-single-nominal-type.rs:15:5 - | -LL | fn x86_mm_subs_epi16(x: A, y: B) -> A; - | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -error: aborting due to 2 previous errors - -For more information about this error, try `rustc --explain E0443`.