diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 0244ff3b..c7e7756e 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -54,53 +54,47 @@ jobs: runs-on: ubuntu-latest needs: [check] strategy: + fail-fast: false matrix: - # Options are all, none, strict and const include: - - { rust: stable, vendor: Atmel, options: all } - - { rust: stable, vendor: Atmel, options: "" } - - { rust: stable, vendor: Freescale, options: all } - - { rust: stable, vendor: Freescale, options: "" } - - { rust: stable, vendor: Fujitsu, options: "" } - - { rust: stable, vendor: Fujitsu, options: "--atomics" } - - { rust: stable, vendor: GD32, options: all } - - { rust: stable, vendor: GD32, options: "" } - - { rust: stable, vendor: Holtek, options: all } - - { rust: stable, vendor: Holtek, options: "" } - - { rust: stable, vendor: Microchip, options: "" } - - { rust: stable, vendor: Microchip, options: "--atomics" } - - { rust: stable, vendor: Nordic, options: all } - - { rust: stable, vendor: Nordic, options: "" } - - { rust: stable, vendor: Nuvoton, options: "" } - - { rust: stable, vendor: Nuvoton, options: "--atomics" } - - { rust: stable, vendor: NXP, options: all } - - { rust: stable, vendor: NXP, options: "" } - - { rust: stable, vendor: RISC-V, options: "" } - - { rust: stable, vendor: RISC-V, options: "--atomics" } - - { rust: stable, vendor: SiliconLabs, options: all } - - { rust: stable, vendor: SiliconLabs, options: "" } - - { rust: stable, vendor: Spansion, options: "" } - - { rust: stable, vendor: Spansion, options: "--atomics" } - - { rust: stable, vendor: STMicro, options: "" } - - { rust: stable, vendor: STMicro, options: "--atomics" } - - { rust: stable, vendor: STM32-patched, options: "--strict -f enum_value::p: --max-cluster-size --atomics --atomics-feature atomics --impl-debug --impl-defmt defmt" } - - { rust: stable, vendor: Toshiba, options: all } - - { rust: stable, vendor: Toshiba, options: "" } - # Test MSRV - - { rust: 1.76.0, vendor: Nordic, options: "" } - # Use nightly for architectures which don't support stable - - { rust: nightly, vendor: MSP430, options: "--atomics" } - - { rust: nightly, vendor: MSP430, options: "" } - # Workaround for _1token0 - - { rust: nightly-2024-09-25, vendor: Espressif, options: "--atomics --ident-formats-theme legacy" } - - { rust: nightly-2024-09-25, vendor: Espressif, options: "--ident-format register:::Reg" } + - { vendor: Atmel } + - { vendor: Atmel, options: "-- --strict --atomics" } + - { vendor: Freescale } + - { vendor: Freescale, options: "-- --strict --atomics" } + - { vendor: Fujitsu } + - { vendor: Fujitsu, options: "-- --atomics" } + - { vendor: Holtek } + - { vendor: Holtek, options: "-- --strict --atomics" } + - { vendor: Atmel } + - { vendor: Atmel, options: "-- --strict --atomics" } + - { vendor: Microchip } + - { vendor: Microchip, options: "-- --atomics" } + - { vendor: Nordic } + - { vendor: Nordic, options: "-- --strict --atomics" } + - { vendor: Nuvoton } + - { vendor: Nuvoton, options: "-- --atomics" } + - { vendor: NXP } + - { vendor: NXP, options: "-- --strict --atomics" } + - { vendor: SiFive } + - { vendor: SiFive, options: "-- --atomics" } + - { vendor: SiliconLabs, options: "" } + - { vendor: SiliconLabs, options: "-- --strict --atomics" } + - { vendor: Spansion } + - { vendor: Spansion, options: "-- --atomics" } + - { vendor: STMicro } + - { vendor: STMicro, options: "-- --atomics" } + - { vendor: STMicro, options: "-- --strict -f enum_value::p: --max-cluster-size --atomics --atomics-feature atomics --impl-debug --impl-defmt defmt" } + - { vendor: Toshiba } + - { vendor: Toshiba, options: "-- --strict --atomics" } + - { vendor: TexasInstruments } + - { vendor: TexasInstruments, options: "-- --atomics" } + - { vendor: Espressif } + - { vendor: Espressif, options: "-- --atomics" } steps: - uses: actions/checkout@v4 - - uses: dtolnay/rust-toolchain@master - with: - toolchain: ${{ matrix.rust }} + - uses: dtolnay/rust-toolchain@stable - name: Cache uses: Swatinem/rust-cache@v2 @@ -109,13 +103,25 @@ jobs: run: | cargo install svd2rust --path . - - name: Run CI script for `${{ matrix.vendor }}` under rust `${{ matrix.rust }}` with options=`${{ matrix.options }}` - env: - VENDOR: ${{ matrix.vendor }} - OPTIONS: ${{ matrix.options }} - COMMAND: check - RUST_TOOLCHAIN: ${{ matrix.rust }} - run: bash ci/script.sh + - name: Run regression tool + run: cargo regress tests -m ${{ matrix.vendor }} ${{ matrix.options }} + + ci-msrv-check: + runs-on: ubuntu-latest + needs: [check] + steps: + - uses: actions/checkout@v4 + + - name: Self install + run: | + cargo install svd2rust --path . + + # Install the MSRV toolchain + - uses: dtolnay/rust-toolchain@1.76.0 + - name: Run reression tool with MSRV + # The MSRV only applies to the generated crate. The regress tool should still be run with + # stable. + run: cargo +stable regress tests --toolchain 1.76.0 -m Nordic -- --strict --atomics ci-clippy: runs-on: ubuntu-latest diff --git a/ci/svd2rust-regress/Cargo.toml b/ci/svd2rust-regress/Cargo.toml index 3b882db7..bd32d497 100644 --- a/ci/svd2rust-regress/Cargo.toml +++ b/ci/svd2rust-regress/Cargo.toml @@ -3,6 +3,7 @@ edition = "2021" name = "svd2rust-regress" version = "0.1.0" authors = ["James Munns ", "The svd2rust developers"] +rust-version = "1.82.0" [dependencies] clap = { version = "4.1", features = ["color", "derive", "string", "env"] } diff --git a/ci/svd2rust-regress/all-tests.yml b/ci/svd2rust-regress/all-tests.yml new file mode 100644 index 00000000..06501c71 --- /dev/null +++ b/ci/svd2rust-regress/all-tests.yml @@ -0,0 +1,2139 @@ +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9CN11 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9CN12 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9G09 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9G15 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9G20 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9G25 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9G35 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9M10 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9M11 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9N12 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9X25 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9X35 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3A4C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3A8C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N00A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N00B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N0A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N0B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N0C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N1A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N1B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N1C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N2A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N2B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N2C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N4A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N4B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N4C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S1A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S1B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S1C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S2A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S2B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S2C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S4A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S4B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S4C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S8B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S8C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3SD8B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3SD8C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3U1C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3U1E + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3U2C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3U2E + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3U4C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3U4E + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3X4C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3X4E + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3X8C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3X8E + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM4S16B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM4S16C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM4S8B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM4S8C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM4SD32B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM4SD32C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMA5D31 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMA5D33 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMA5D34 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMA5D35 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21E15A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21E16A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21E17A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21E18A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21G16A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21G17A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21G18A + svd_url: https://raw.githubusercontent.com/wez/atsamd21-rs/master/svd/ATSAMD21G18A.svd + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21J16A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21J17A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21J18A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMR21E16A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMR21E17A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMR21E18A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMR21G16A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMR21G17A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMR21G18A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MKV56F20 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MKV56F22 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MKV56F24 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MKV58F20 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MKV58F22 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MKV58F24 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MK61F15 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MK61F15WS + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MK70F12 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MK70F15 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MK70F15WS + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MK02F12810 +- arch: cortex-m + mfgr: Freescale + chip: MK10D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK10D5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK10D7 +- arch: cortex-m + mfgr: Freescale + chip: MK10DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK10F12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK11D5 +- arch: cortex-m + mfgr: Freescale + chip: MK11D5WS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK11DA5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK12D5 +- arch: cortex-m + mfgr: Freescale + chip: MK20D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK20D5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK20D7 +- arch: cortex-m + mfgr: Freescale + chip: MK20DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK20F12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK21D5 +- arch: cortex-m + mfgr: Freescale + chip: MK21D5WS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK21DA5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK21F12 +- arch: cortex-m + mfgr: Freescale + chip: MK21FA12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK22D5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK22F12 +- arch: cortex-m + mfgr: Freescale + chip: MK22F12810 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK22F25612 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK22F51212 +- arch: cortex-m + mfgr: Freescale + chip: MK22FA12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK24F12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK24F25612 +- arch: cortex-m + mfgr: Freescale + chip: MK26F18 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK30D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK30D7 +- arch: cortex-m + mfgr: Freescale + chip: MK30DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK40D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK40D7 +- arch: cortex-m + mfgr: Freescale + chip: MK40DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK50D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK50D7 +- arch: cortex-m + mfgr: Freescale + chip: MK50DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK51D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK51D7 +- arch: cortex-m + mfgr: Freescale + chip: MK51DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK52D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK52DZ10 +- arch: cortex-m + mfgr: Freescale + chip: MK53D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK53DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK60D10 +- arch: cortex-m + mfgr: Freescale + chip: MK60DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK60F15 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK63F12 +- arch: cortex-m + mfgr: Freescale + chip: MK64F12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK65F18 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK66F18 +- arch: cortex-m + mfgr: Freescale + chip: MK80F25615 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK81F25615 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK82F25615 +- arch: cortex-m + mfgr: Freescale + chip: MKE14F16 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE14Z7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE15Z7 +- arch: cortex-m + mfgr: Freescale + chip: MKE16F16 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE18F16 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL28T7_CORE0 +- arch: cortex-m + mfgr: Freescale + chip: MKL28T7_CORE1 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL28Z7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL81Z7 +- arch: cortex-m + mfgr: Freescale + chip: MKL82Z7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKS22F12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV10Z1287 +- arch: cortex-m + mfgr: Freescale + chip: MKV10Z7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV11Z7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV30F12810 +- arch: cortex-m + mfgr: Freescale + chip: MKV31F12810 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV31F25612 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV31F51212 +- arch: cortex-m + mfgr: Freescale + chip: MKV40F15 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV42F16 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV43F15 +- arch: cortex-m + mfgr: Freescale + chip: MKV44F15 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV44F16 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV45F15 +- arch: cortex-m + mfgr: Freescale + chip: MKV46F15 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV46F16 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKW20Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKW21D5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKW21Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKW22D5 +- arch: cortex-m + mfgr: Freescale + chip: MKW24D5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKW30Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKW31Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKW40Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKW41Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE02Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKE04Z1284 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE04Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE06Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKE14D7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE15D7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL02Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKL03Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL04Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL05Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKL13Z644 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL14Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL15Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKL16Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL17Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL17Z644 +- arch: cortex-m + mfgr: Freescale + chip: MKL24Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL25Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL26Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKL27Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL27Z644 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL33Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKL33Z644 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL34Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL36Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKL43Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL46Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKM14ZA5 +- arch: cortex-m + mfgr: Freescale + chip: MKM33ZA5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKM34Z7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKM34ZA5 +- arch: cortex-m + mfgr: Freescale + chip: MKW01Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: SKEAZ1284 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: SKEAZN642 +- arch: cortex-m + mfgr: Freescale + chip: SKEAZN84 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF10xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF10xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF11xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF11xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF11xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF11xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF12xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF12xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF13xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF13xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF13xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF13xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF14xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF14xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF14xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF15xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF15xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF15xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF1AxL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF1AxM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF1AxN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF31xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF31xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF31xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF31xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF34xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF34xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF34xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF42xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF42xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFA3xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFA3xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFA3xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFA4xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFA4xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFA4xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFAAxL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFAAxM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFAAxN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFB4xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFB4xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFB4xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B160L +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B160R +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B360L +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B360R +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B460L +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B460R +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B560L +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B560R +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF10xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF10xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF11xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF11xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF11xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF11xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF12xJ +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF12xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF12xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF12xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF12xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF12xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF21xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF21xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF30xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF30xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF31xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF31xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF31xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF31xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF32xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF32xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF32xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF32xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF32xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF40xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF40xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF41xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF41xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF41xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF41xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF42xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF42xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF50xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF50xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF51xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF51xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF51xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF51xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF52xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF52xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF52xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF52xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF52xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF61xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF61xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BFD1xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BFD1xT +- arch: cortex-m + mfgr: Fujitsu + chip: S6E1A1 +- arch: cortex-m + mfgr: Fujitsu + chip: S6E2CC +- arch: cortex-m + mfgr: Holtek + chip: ht32f125x +- arch: cortex-m + mfgr: Holtek + chip: ht32f175x +- arch: cortex-m + mfgr: Holtek + chip: ht32f275x +- arch: cortex-m + mfgr: Nordic + chip: nrf51 +- arch: cortex-m + mfgr: Nordic + chip: nrf52 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Nuvoton + chip: M051_Series + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Nuvoton + chip: NUC100_Series + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11Exx_v5 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11Uxx_v7 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11xx_v6a + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11xx_v6 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC13Uxx_v1 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC15xx_v0.7 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC800_v0.3 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11E6x_v0.8 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC176x5x_v0.2 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11Cxx_v9 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC178x_7x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC178x_7x_v0.8 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC408x_7x_v0.7 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11Axxv0.6 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11D14_svd_v4 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC13xx_svd_v1 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC18xx_svd_v18 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC43xx_43Sxx + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC1102_4_v4 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC5410x_v0.4 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: MK22F25612 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: NXP + chip: MK22F51212 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: NXP + chip: MKW41Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3C1x4_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3C1x6_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3C1x7_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3L1x4_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3L1x6_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3L1x7_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3U1x4_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3U1x6_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3U1x7_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3L1x8_SVD + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Spansion + chip: MB9AF12xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF12xL + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF42xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF42xL + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF12xJ + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF12xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF12xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF16xx + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF32xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF32xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF36xx + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF42xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF42xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF46xx + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF52xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF52xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF56xx + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF10xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF10xR +- arch: cortex-m + mfgr: Spansion + chip: MB9AF11xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF11xL +- arch: cortex-m + mfgr: Spansion + chip: MB9AF11xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF11xN +- arch: cortex-m + mfgr: Spansion + chip: MB9AF13xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF13xL +- arch: cortex-m + mfgr: Spansion + chip: MB9AF13xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF13xN +- arch: cortex-m + mfgr: Spansion + chip: MB9AF14xL + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF14xM +- arch: cortex-m + mfgr: Spansion + chip: MB9AF14xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF15xM +- arch: cortex-m + mfgr: Spansion + chip: MB9AF15xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF15xR +- arch: cortex-m + mfgr: Spansion + chip: MB9AF31xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF31xL +- arch: cortex-m + mfgr: Spansion + chip: MB9AF31xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF31xN +- arch: cortex-m + mfgr: Spansion + chip: MB9AF34xL + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF34xM +- arch: cortex-m + mfgr: Spansion + chip: MB9AF34xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AFA3xL +- arch: cortex-m + mfgr: Spansion + chip: MB9AFA3xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AFA3xN +- arch: cortex-m + mfgr: Spansion + chip: MB9AFA4xL + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AFA4xM +- arch: cortex-m + mfgr: Spansion + chip: MB9AFA4xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AFB4xL +- arch: cortex-m + mfgr: Spansion + chip: MB9AFB4xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AFB4xN +- arch: cortex-m + mfgr: Spansion + chip: MB9BF10xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF10xR +- arch: cortex-m + mfgr: Spansion + chip: MB9BF11xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF11xR +- arch: cortex-m + mfgr: Spansion + chip: MB9BF11xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF11xT +- arch: cortex-m + mfgr: Spansion + chip: MB9BF12xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF12xL +- arch: cortex-m + mfgr: Spansion + chip: MB9BF12xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF21xS +- arch: cortex-m + mfgr: Spansion + chip: MB9BF21xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF30xN +- arch: cortex-m + mfgr: Spansion + chip: MB9BF30xR + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF31xN +- arch: cortex-m + mfgr: Spansion + chip: MB9BF31xR + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF31xS +- arch: cortex-m + mfgr: Spansion + chip: MB9BF31xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF32xK +- arch: cortex-m + mfgr: Spansion + chip: MB9BF32xL + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF32xM +- arch: cortex-m + mfgr: Spansion + chip: MB9BF40xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF40xR +- arch: cortex-m + mfgr: Spansion + chip: MB9BF41xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF41xR +- arch: cortex-m + mfgr: Spansion + chip: MB9BF41xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF41xT +- arch: cortex-m + mfgr: Spansion + chip: MB9BF50xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF50xR +- arch: cortex-m + mfgr: Spansion + chip: MB9BF51xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF51xR +- arch: cortex-m + mfgr: Spansion + chip: MB9BF51xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF51xT +- arch: cortex-m + mfgr: Spansion + chip: MB9BF52xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF52xL +- arch: cortex-m + mfgr: Spansion + chip: MB9BF52xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF61xS +- arch: cortex-m + mfgr: Spansion + chip: MB9BF61xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BFD1xS +- arch: cortex-m + mfgr: Spansion + chip: MB9BFD1xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: STMicro + chip: STM32F030 +- arch: cortex-m + mfgr: STMicro + chip: STM32F0x2 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f0x2.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32F103 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f103.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32F411 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f411.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32F469 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f469.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32F723 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f723.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32G070 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32g070.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32G473 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32g473.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32H753 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32h753.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32L0x3 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32l0x3.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32L162 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32l162.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32L4x6 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32l4x6.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32L562 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32l562.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32MP157 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32mp157.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32WB55 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32wb55.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32WLE5 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32wle5.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32C011 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32c011.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32F031x +- arch: cortex-m + mfgr: STMicro + chip: STM32F042x +- arch: cortex-m + mfgr: STMicro + chip: STM32F072x +- arch: cortex-m + mfgr: STMicro + chip: STM32F091x +- arch: cortex-m + mfgr: STMicro + chip: STM32F0xx +- arch: cortex-m + mfgr: STMicro + chip: STM32F100xx +- arch: cortex-m + mfgr: STMicro + chip: STM32F101xx +- arch: cortex-m + mfgr: STMicro + chip: STM32F102xx +- arch: cortex-m + mfgr: STMicro + chip: STM32F105xx +- arch: cortex-m + mfgr: STMicro + chip: STM32F107xx +- arch: cortex-m + mfgr: STMicro + chip: STM32F20x +- arch: cortex-m + mfgr: STMicro + chip: STM32F21x +- arch: cortex-m + mfgr: STMicro + chip: STM32F301 +- arch: cortex-m + mfgr: STMicro + chip: STM32F302 +- arch: cortex-m + mfgr: STMicro + chip: STM32F303 +- arch: cortex-m + mfgr: STMicro + chip: STM32F3x4 +- arch: cortex-m + mfgr: STMicro + chip: STM32F373 +- arch: cortex-m + mfgr: STMicro + chip: STM32F401 +- arch: cortex-m + mfgr: STMicro + chip: STM32F405 +- arch: cortex-m + mfgr: STMicro + chip: STM32F407 +- arch: cortex-m + mfgr: STMicro + chip: STM32F410 +- arch: cortex-m + mfgr: STMicro + chip: STM32F412 +- arch: cortex-m + mfgr: STMicro + chip: STM32F413 +- arch: cortex-m + mfgr: STMicro + chip: STM32F427 +- arch: cortex-m + mfgr: STMicro + chip: STM32F429 +- arch: cortex-m + mfgr: STMicro + chip: STM32F446 +- arch: cortex-m + mfgr: STMicro + chip: STM32F7x +- arch: cortex-m + mfgr: STMicro + chip: STM32F7x2 +- arch: cortex-m + mfgr: STMicro + chip: STM32F7x5 +- arch: cortex-m + mfgr: STMicro + chip: STM32F7x6 +- arch: cortex-m + mfgr: STMicro + chip: STM32F7x7 +- arch: cortex-m + mfgr: STMicro + chip: STM32F7x9 +- arch: cortex-m + mfgr: STMicro + chip: STM32G07x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: STMicro + chip: STM32G431xx +- arch: cortex-m + mfgr: STMicro + chip: STM32G441xx +- arch: cortex-m + mfgr: STMicro + chip: STM32G471xx +- arch: cortex-m + mfgr: STMicro + chip: STM32G474xx +- arch: cortex-m + mfgr: STMicro + chip: STM32G483xx +- arch: cortex-m + mfgr: STMicro + chip: STM32G484xx +- arch: cortex-m + mfgr: STMicro + chip: STM32L100 +- arch: cortex-m + mfgr: STMicro + chip: STM32L15xC +- arch: cortex-m + mfgr: STMicro + chip: STM32L15xxE +- arch: cortex-m + mfgr: STMicro + chip: STM32L15xxxA +- arch: cortex-m + mfgr: STMicro + chip: STM32L1xx +- arch: cortex-m + mfgr: STMicro + chip: STM32W108 +- arch: cortex-m + mfgr: STMicro + chip: STM32L051x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: STMicro + chip: STM32L052x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: STMicro + chip: STM32L053x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: STMicro + chip: STM32L062x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: STMicro + chip: STM32L063x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Toshiba + chip: M365 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Toshiba + chip: M367 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Toshiba + chip: M368 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Toshiba + chip: M369 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Toshiba + chip: M36B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Toshiba + chip: M061 +- arch: riscv + mfgr: SiFive + chip: E310x + svd_url: https://raw.githubusercontent.com/riscv-rust/e310x/master/e310x/e310x.svd + should_pass: false + run_when: never +- arch: msp430 + mfgr: TexasInstruments + chip: msp430g2553 + svd_url: https://github.com/pftbest/msp430g2553/raw/v0.1.3-svd/msp430g2553.svd +- arch: msp430 + mfgr: TexasInstruments + chip: msp430fr2355 + svd_url: https://raw.githubusercontent.com/YuhanLiin/msp430fr2355/master/msp430fr2355.svd +- arch: xtensa-lx + mfgr: Espressif + chip: esp32 + svd_url: https://raw.githubusercontent.com/espressif/svd/main/svd/esp32.svd +- arch: xtensa-lx + mfgr: Espressif + chip: esp32s2 + svd_url: https://raw.githubusercontent.com/espressif/svd/main/svd/esp32s2.svd +- arch: xtensa-lx + mfgr: Espressif + chip: esp32s3 + svd_url: https://raw.githubusercontent.com/espressif/svd/main/svd/esp32s3.svd +- arch: riscv + mfgr: Espressif + chip: esp32c3 + svd_url: https://raw.githubusercontent.com/espressif/svd/main/svd/esp32c3.svd +- arch: mips + mfgr: Microchip + chip: pic32mx170f256b + svd_url: https://raw.githubusercontent.com/kiffie/pic32-pac/master/pic32mx1xxfxxxb/PIC32MX170F256B.svd.patched +- arch: mips + mfgr: Microchip + chip: pic32mx270f256b + svd_url: https://raw.githubusercontent.com/kiffie/pic32-pac/master/pic32mx2xxfxxxb/PIC32MX270F256B.svd.patched diff --git a/ci/svd2rust-regress/src/diff.rs b/ci/svd2rust-regress/src/diff.rs index d155c56a..de4d0d31 100644 --- a/ci/svd2rust-regress/src/diff.rs +++ b/ci/svd2rust-regress/src/diff.rs @@ -208,6 +208,9 @@ impl Diffing { .to_owned(), svd_url: Some(url.to_owned()), should_pass: true, + skip_check: false, + suffix: Default::default(), + opts: Default::default(), run_when: crate::tests::RunWhen::Always, }, _ => { @@ -232,10 +235,10 @@ impl Diffing { ) => last_args.as_deref(), None => None, }); - let join = |opt1: Option<&str>, opt2: Option<&str>| -> Option { + let join = |opt1: Option<&str>, opt2: Option<&str>| -> Option> { match (opt1, opt2) { - (Some(str1), Some(str2)) => Some(format!("{} {}", str1, str2)), - (Some(str), None) | (None, Some(str)) => Some(str.to_owned()), + (Some(str1), Some(str2)) => vec![str1.to_owned(), str2.to_owned()].into(), + (Some(str), None) | (None, Some(str)) => Some(vec![str.to_owned()]), (None, None) => None, } }; @@ -243,14 +246,14 @@ impl Diffing { .setup_case( &opts.output_dir.join("baseline"), &baseline_bin, - join(baseline_cmd, last_args).as_deref(), + &join(baseline_cmd, last_args), ) .with_context(|| "couldn't create head")?; let current = test .setup_case( &opts.output_dir.join("current"), ¤t_bin, - join(current_cmd, last_args).as_deref(), + &join(current_cmd, last_args), ) .with_context(|| "couldn't create base")?; diff --git a/ci/svd2rust-regress/src/main.rs b/ci/svd2rust-regress/src/main.rs index 4d0fdf77..22b03985 100644 --- a/ci/svd2rust-regress/src/main.rs +++ b/ci/svd2rust-regress/src/main.rs @@ -17,6 +17,7 @@ use std::path::PathBuf; use std::process::{exit, Command}; use std::sync::atomic::{AtomicBool, Ordering}; use std::time::Instant; +use svd_test::WorkspaceTomlGuard; use wildmatch::WildMatch; #[derive(Debug, serde::Deserialize)] @@ -61,20 +62,20 @@ pub struct TestAll { /// Filter by manufacturer, may be combined with other filters #[clap( - short = 'm', - long = "manufacturer", - ignore_case = true, - value_parser = manufacturers(), -)] + short = 'm', + long = "manufacturer", + ignore_case = true, + value_parser = manufacturers(), + )] pub mfgr: Option, /// Filter by architecture, may be combined with other filters #[clap( - short = 'a', - long = "architecture", - ignore_case = true, - value_parser = architectures(), -)] + short = 'a', + long = "architecture", + ignore_case = true, + value_parser = architectures(), + )] pub arch: Option, /// Include tests expected to fail (will cause a non-zero return code) @@ -99,7 +100,7 @@ pub struct TestAll { #[clap(short = 'p', long = "svd2rust-path", default_value = default_svd2rust())] pub current_bin_path: PathBuf, #[clap(last = true)] - pub command: Option, + pub passthrough_opts: Option>, // TODO: Specify smaller subset of tests? Maybe with tags? // TODO: Compile svd2rust? } @@ -148,7 +149,7 @@ pub struct Test { #[clap(short = 'p', long = "svd2rust-path", default_value = default_svd2rust())] pub current_bin_path: PathBuf, #[clap(last = true)] - pub command: Option, + pub passthrough_opts: Option>, } impl Test { @@ -161,6 +162,7 @@ impl Test { Self { chip: Some(_), .. } => {} _ => unreachable!("clap should not allow this"), } + let _toml_guard = WorkspaceTomlGuard::new()?; let test = if let (Some(url), Some(arch)) = (&self.url, &self.arch) { tests::TestCase { arch: svd2rust::Target::parse(arch)?, @@ -177,6 +179,9 @@ impl Test { .to_owned(), svd_url: Some(url.clone()), should_pass: true, + skip_check: false, + suffix: Default::default(), + opts: Default::default(), run_when: tests::RunWhen::default(), } } else { @@ -186,7 +191,7 @@ impl Test { .ok_or_else(|| anyhow::anyhow!("no test found for chip"))? .to_owned() }; - test.test(opts, &self.current_bin_path, self.command.as_deref())?; + test.test(opts, &self.current_bin_path, &self.passthrough_opts)?; Ok(()) } } @@ -235,11 +240,14 @@ impl TestAll { "No tests run, you might want to use `--bad-tests` and/or `--long-test`" ); } + + let toml_guard = WorkspaceTomlGuard::new()?; + let any_fails = AtomicBool::new(false); tests.par_iter().for_each(|t| { let start = Instant::now(); - match t.test(opt, &self.current_bin_path, self.command.as_deref()) { + match t.test(opt, &self.current_bin_path, &self.passthrough_opts) { Ok(s) => { if let Some(stderrs) = s { let mut buf = String::new(); @@ -293,6 +301,8 @@ impl TestAll { } } }); + drop(toml_guard); + if any_fails.load(Ordering::Acquire) { exit(1); } else { diff --git a/ci/svd2rust-regress/src/svd_test.rs b/ci/svd2rust-regress/src/svd_test.rs index 97de00da..4801bd3e 100644 --- a/ci/svd2rust-regress/src/svd_test.rs +++ b/ci/svd2rust-regress/src/svd_test.rs @@ -17,15 +17,14 @@ const CRATES_ALL: &[&str] = &[ ]; const CRATES_MSP430: &[&str] = &["msp430 = \"0.4.0\"", "msp430-rt = \"0.4.0\""]; const CRATES_ATOMICS: &[&str] = - &["portable-atomic = { version = \"0.3.16\", default-features = false }"]; + &["portable-atomic = { version = \"1\", default-features = false }"]; const CRATES_CORTEX_M: &[&str] = &["cortex-m = \"0.7.6\"", "cortex-m-rt = \"0.7\""]; const CRATES_RISCV: &[&str] = &["riscv = \"0.12.1\"", "riscv-rt = \"0.13.0\""]; -const CRATES_XTENSALX: &[&str] = &["xtensa-lx-rt = \"0.9.0\"", "xtensa-lx = \"0.6.0\""]; const CRATES_MIPS: &[&str] = &["mips-mcu = \"0.1.0\""]; const PROFILE_ALL: &[&str] = &["[profile.dev]", "incremental = false"]; const FEATURES_ALL: &[&str] = &["[features]"]; const FEATURES_CORTEX_M: &[&str] = &["rt = [\"cortex-m-rt/device\"]"]; -const FEATURES_XTENSALX: &[&str] = &["default = [\"xtensa-lx/esp32\", \"xtensa-lx-rt/esp32\"]"]; +const FEATURES_XTENSA_LX: &[&str] = &["rt = []"]; const WORKSPACE_EXCLUDE: &[&str] = &["[workspace]"]; fn path_helper_base(base: &Path, input: &[&str]) -> PathBuf { @@ -143,25 +142,27 @@ impl TestCase { &self, opts: &Opts, bin_path: &Path, - command: Option<&str>, + cli_opts: &Option>, ) -> Result>, TestError> { let (chip_dir, mut process_stderr_paths) = self - .setup_case(&opts.output_dir, bin_path, command) + .setup_case(&opts.output_dir, bin_path, cli_opts) .with_context(|| anyhow!("when setting up case for {}", self.name()))?; // Run `cargo check`, capturing stderr to a log file - let cargo_check_err_file = path_helper_base(&chip_dir, &["cargo-check.err.log"]); - Command::new("cargo") - .arg("check") - .current_dir(&chip_dir) - .capture_outputs( - true, - "cargo check", - None, - Some(&cargo_check_err_file), - &process_stderr_paths, - ) - .with_context(|| "failed to check")?; - process_stderr_paths.push(cargo_check_err_file); + if !self.skip_check { + let cargo_check_err_file = path_helper_base(&chip_dir, &["cargo-check.err.log"]); + Command::new("cargo") + .arg("check") + .current_dir(&chip_dir) + .capture_outputs( + true, + "cargo check", + None, + Some(&cargo_check_err_file), + &process_stderr_paths, + ) + .with_context(|| "failed to check")?; + process_stderr_paths.push(cargo_check_err_file); + } Ok(if opts.verbose > 1 { Some(process_stderr_paths) } else { @@ -175,13 +176,15 @@ impl TestCase { &self, output_dir: &Path, svd2rust_bin_path: &Path, - command: Option<&str>, + command: &Option>, ) -> Result<(PathBuf, Vec), TestError> { let user = match std::env::var("USER") { Ok(val) => val, Err(_) => "rusttester".into(), }; - let chip_dir = output_dir.join(Case::Snake.sanitize(&self.name()).as_ref()); + let mut chip_name = self.name(); + chip_name = Case::Snake.cow_to_case(chip_name.into()).to_string(); + let chip_dir = output_dir.join(&chip_name); tracing::span::Span::current() .record("chip_dir", tracing::field::display(chip_dir.display())); if let Err(err) = fs::remove_dir_all(&chip_dir) { @@ -196,104 +199,34 @@ impl TestCase { self.name(), chip_dir.display() ); - // XXX: Workaround for https://github.com/rust-lang/cargo/issues/6009#issuecomment-1925445245 - let manifest_path = crate::get_cargo_workspace().join("Cargo.toml"); - let workspace_toml = - fs::read(&manifest_path).context("failed to read workspace Cargo.toml")?; + println!("chip_dir: {}", chip_dir.display()); Command::new("cargo") .env("USER", user) .arg("init") .arg("--name") - .arg(Case::Snake.sanitize(&self.name()).as_ref()) + .arg(chip_name) .arg("--vcs") .arg("none") + .arg("--lib") .arg(&chip_dir) .capture_outputs(true, "cargo init", None, None, &[]) .with_context(|| "Failed to cargo init")?; - std::fs::write(manifest_path, workspace_toml) - .context("failed to write workspace Cargo.toml")?; - - let svd_toml = path_helper_base(&chip_dir, &["Cargo.toml"]); - let mut file = OpenOptions::new() - .append(true) - .open(svd_toml) - .with_context(|| "Failed to open Cargo.toml for appending")?; - let crates = CRATES_ALL - .iter() - .chain(match &self.arch { - Target::CortexM => CRATES_CORTEX_M.iter(), - Target::RISCV => CRATES_RISCV.iter(), - Target::Mips => CRATES_MIPS.iter(), - Target::Msp430 => CRATES_MSP430.iter(), - Target::XtensaLX => CRATES_XTENSALX.iter(), - Target::None => unreachable!(), - }) - .chain(if command.unwrap_or_default().contains("--atomics") { - CRATES_ATOMICS.iter() - } else { - [].iter() - }) - .chain(PROFILE_ALL.iter()) - .chain(FEATURES_ALL.iter()) - .chain(match &self.arch { - Target::XtensaLX => FEATURES_XTENSALX.iter(), - Target::CortexM => FEATURES_CORTEX_M.iter(), - _ => [].iter(), - }) - .chain(WORKSPACE_EXCLUDE.iter()); - for c in crates { - writeln!(file, "{}", c).with_context(|| "Failed to append to file!")?; - } - tracing::info!("Downloading SVD"); - // FIXME: Avoid downloading multiple times, especially if we're using the diff command - let svd_url = &self.svd_url(); - let svd = reqwest::blocking::get(svd_url) - .with_context(|| format!("Failed to get svd URL: {svd_url}"))? - .error_for_status() - .with_context(|| anyhow!("Response is not ok for svd url"))? - .text() - .with_context(|| "SVD is bad text")?; + self.prepare_chip_test_toml(&chip_dir, command)?; + let chip_svd = self.prepare_svd_file(&chip_dir)?; + self.prepare_rust_toolchain_file(&chip_dir)?; - let chip_svd = format!("{}.svd", &self.chip); - let svd_file = path_helper_base(&chip_dir, &[&chip_svd]); - file_helper(&svd, &svd_file)?; let lib_rs_file = path_helper_base(&chip_dir, &["src", "lib.rs"]); let src_dir = path_helper_base(&chip_dir, &["src"]); let svd2rust_err_file = path_helper_base(&chip_dir, &["svd2rust.err.log"]); - let target = match self.arch { - Target::CortexM => "cortex-m", - Target::Msp430 => "msp430", - Target::Mips => "mips", - Target::RISCV => "riscv", - Target::XtensaLX => "xtensa-lx", - Target::None => unreachable!(), - }; - tracing::info!("Running svd2rust"); - let mut svd2rust_bin = Command::new(svd2rust_bin_path); - if let Some(command) = command { - if !command.is_empty() { - svd2rust_bin.args( - shell_words::split(command).context("unable to split command into args")?, - ); - } - } - svd2rust_bin - .args(["-i", &chip_svd]) - .args(["--target", target]) - .current_dir(&chip_dir) - .capture_outputs( - true, - "svd2rust", - Some(&lib_rs_file).filter(|_| { - !matches!( - self.arch, - Target::CortexM | Target::Msp430 | Target::XtensaLX - ) - }), - Some(&svd2rust_err_file), - &[], - )?; + self.run_svd2rust( + svd2rust_bin_path, + &chip_svd, + &chip_dir, + &lib_rs_file, + &svd2rust_err_file, + command, + )?; process_stderr_paths.push(svd2rust_err_file); match self.arch { Target::CortexM | Target::Mips | Target::Msp430 | Target::XtensaLX => { @@ -309,6 +242,7 @@ impl TestCase { .with_context(|| format!("couldn't parse {}", lib_rs_file.display()))?; File::options() .write(true) + .truncate(true) .open(&lib_rs_file) .with_context(|| format!("couldn't open {}", lib_rs_file.display()))? .write(prettyplease::unparse(&file).as_bytes()) @@ -370,6 +304,132 @@ impl TestCase { } Ok((chip_dir, process_stderr_paths)) } + + fn prepare_rust_toolchain_file(&self, chip_dir: &Path) -> Result<(), TestError> { + // Could be extended to let cargo install and use a specific toolchain. + let channel: Option = None; + + if let Some(channel) = channel { + let toolchain_file = path_helper_base(chip_dir, &["rust-toolchain.toml"]); + let mut file = OpenOptions::new() + .create(true) + .truncate(true) + .write(true) + .open(&toolchain_file) + .with_context(|| "failed to create toolchain file")?; + + writeln!(file, "[toolchain]\nchannel = \"{}\"", channel) + .with_context(|| "writing toolchain file failed")?; + } + + Ok(()) + } + + fn prepare_chip_test_toml( + &self, + chip_dir: &Path, + opts: &Option>, + ) -> Result<(), TestError> { + let svd_toml = path_helper_base(chip_dir, &["Cargo.toml"]); + let mut file = OpenOptions::new() + .append(true) + .open(svd_toml) + .with_context(|| "Failed to open Cargo.toml for appending")?; + + let cargo_toml_fragments = CRATES_ALL + .iter() + .chain(match &self.arch { + Target::CortexM => CRATES_CORTEX_M.iter(), + Target::RISCV => CRATES_RISCV.iter(), + Target::Mips => CRATES_MIPS.iter(), + Target::Msp430 => CRATES_MSP430.iter(), + Target::XtensaLX => [].iter(), + Target::None => unreachable!(), + }) + .chain(if let Some(opts) = opts { + if opts.iter().any(|v| v.contains("atomics")) { + CRATES_ATOMICS.iter() + } else { + [].iter() + } + } else { + [].iter() + }) + .chain(PROFILE_ALL.iter()) + .chain(FEATURES_ALL.iter()) + .chain(match &self.arch { + Target::CortexM => FEATURES_CORTEX_M.iter(), + Target::XtensaLX => FEATURES_XTENSA_LX.iter(), + _ => [].iter(), + }) + .chain(WORKSPACE_EXCLUDE.iter()); + for fragments in cargo_toml_fragments { + writeln!(file, "{}", fragments).with_context(|| "Failed to append to file!")?; + } + Ok(()) + } + + fn prepare_svd_file(&self, chip_dir: &Path) -> Result { + tracing::info!("Downloading SVD"); + // FIXME: Avoid downloading multiple times, especially if we're using the diff command + let svd_url = &self.svd_url(); + let svd = reqwest::blocking::get(svd_url) + .with_context(|| format!("Failed to get svd URL: {svd_url}"))? + .error_for_status() + .with_context(|| anyhow!("Response is not ok for svd url"))? + .text() + .with_context(|| "SVD is bad text")?; + + let chip_svd = format!("{}.svd", &self.chip); + let svd_file = path_helper_base(chip_dir, &[&chip_svd]); + file_helper(&svd, &svd_file)?; + Ok(chip_svd) + } + + fn run_svd2rust( + &self, + svd2rust_bin_path: &Path, + chip_svd: &str, + chip_dir: &Path, + lib_rs_file: &PathBuf, + svd2rust_err_file: &PathBuf, + cli_opts: &Option>, + ) -> Result<(), TestError> { + tracing::info!("Running svd2rust"); + + let target = match self.arch { + Target::CortexM => "cortex-m", + Target::Msp430 => "msp430", + Target::Mips => "mips", + Target::RISCV => "riscv", + Target::XtensaLX => "xtensa-lx", + Target::None => unreachable!(), + }; + let mut svd2rust_bin = Command::new(svd2rust_bin_path); + + let base_cmd = svd2rust_bin + .args(["-i", chip_svd]) + .args(["--target", target]); + if let Some(cli_opts) = cli_opts { + base_cmd.args(cli_opts); + } + if let Some(opts) = self.opts.as_ref() { + base_cmd.args(opts); + } + base_cmd.current_dir(chip_dir).capture_outputs( + true, + "svd2rust", + Some(lib_rs_file).filter(|_| { + !matches!( + self.arch, + Target::CortexM | Target::Msp430 | Target::XtensaLX + ) + }), + Some(svd2rust_err_file), + &[], + )?; + Ok(()) + } } fn visit_dirs(dir: &Path, cb: &mut dyn FnMut(&fs::DirEntry)) -> std::io::Result<()> { @@ -386,3 +446,33 @@ fn visit_dirs(dir: &Path, cb: &mut dyn FnMut(&fs::DirEntry)) -> std::io::Result< } Ok(()) } + +pub struct WorkspaceTomlGuard { + pub unmodified_toml: Vec, + pub manifest_path: PathBuf, +} + +impl WorkspaceTomlGuard { + pub fn new() -> Result { + // XXX: Workaround for + // https://github.com/rust-lang/cargo/issues/6009#issuecomment-1925445245 + // Calling cargo init will add the chip test directory to the workspace members, regardless + // of the exclude list. The unmodified manifest path is stored here and written + // back after cargo init. + let manifest_path = crate::get_cargo_workspace().join("Cargo.toml"); + let unmodified_toml = + fs::read(&manifest_path).with_context(|| "error reading manifest file")?; + Ok(Self { + unmodified_toml, + manifest_path, + }) + } +} + +impl Drop for WorkspaceTomlGuard { + fn drop(&mut self) { + if let Err(e) = std::fs::write(self.manifest_path.clone(), &self.unmodified_toml) { + tracing::error!("Failed to write back to manifest Cargo.toml: {}", e); + } + } +} diff --git a/ci/svd2rust-regress/src/tests.rs b/ci/svd2rust-regress/src/tests.rs index f1562a5d..4e40d4da 100644 --- a/ci/svd2rust-regress/src/tests.rs +++ b/ci/svd2rust-regress/src/tests.rs @@ -72,10 +72,16 @@ pub struct TestCase { pub mfgr: Manufacturer, pub chip: String, #[serde(default, skip_serializing_if = "Option::is_none")] + pub suffix: Option, + #[serde(default, skip_serializing_if = "Option::is_none")] + pub opts: Option>, + #[serde(default, skip_serializing_if = "Option::is_none")] pub svd_url: Option, #[serde(default = "true_")] pub should_pass: bool, #[serde(default)] + pub skip_check: bool, + #[serde(default)] pub run_when: RunWhen, } @@ -103,7 +109,12 @@ impl TestCase { } pub fn name(&self) -> String { - format!("{:?}-{}", self.mfgr, self.chip.replace('.', "_")) + let mut base_name = format!("{:?}-{}", self.mfgr, self.chip.replace('.', "_")); + if let Some(suffix) = &self.suffix { + base_name.push('-'); + base_name.push_str(suffix); + } + base_name } } diff --git a/ci/svd2rust-regress/tests.yml b/ci/svd2rust-regress/tests.yml index 06501c71..27e08a6d 100644 --- a/ci/svd2rust-regress/tests.yml +++ b/ci/svd2rust-regress/tests.yml @@ -1,1914 +1,506 @@ -- arch: cortex-m - mfgr: Atmel - chip: AT91SAM9CN11 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: AT91SAM9CN12 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: AT91SAM9G09 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: AT91SAM9G15 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: AT91SAM9G20 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: AT91SAM9G25 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: AT91SAM9G35 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: AT91SAM9M10 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: AT91SAM9M11 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: AT91SAM9N12 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: AT91SAM9X25 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: AT91SAM9X35 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3A4C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3A8C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N00A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N00B - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N0A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N0B - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N0C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N1A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N1B - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N1C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N2A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N2B - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N2C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N4A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N4B - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3N4C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3S1A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3S1B - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3S1C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3S2A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3S2B - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3S2C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3S4A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3S4B - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3S4C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3S8B - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3S8C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3SD8B - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3SD8C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3U1C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3U1E - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3U2C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3U2E - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3U4C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3U4E - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3X4C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3X4E - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3X8C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM3X8E - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM4S16B - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM4S16C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM4S8B - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM4S8C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM4SD32B - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAM4SD32C - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMA5D31 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMA5D33 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMA5D34 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMA5D35 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMD21E15A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMD21E16A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMD21E17A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMD21E18A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMD21G16A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMD21G17A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMD21G18A - svd_url: https://raw.githubusercontent.com/wez/atsamd21-rs/master/svd/ATSAMD21G18A.svd - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Atmel - chip: ATSAMD21J16A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMD21J17A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMD21J18A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMR21E16A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMR21E17A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMR21E18A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMR21G16A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMR21G17A - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Atmel - chip: ATSAMR21G18A - should_pass: false - run_when: never +# Atmel - BAD-SVD missing resetValue + +# Freescale - arch: cortex-m mfgr: Freescale - chip: MKV56F20 - should_pass: false - run_when: never + chip: MK02F12810 - arch: cortex-m mfgr: Freescale - chip: MKV56F22 - should_pass: false - run_when: never + chip: MK10D7 - arch: cortex-m mfgr: Freescale - chip: MKV56F24 - should_pass: false - run_when: never + chip: MK12D5 - arch: cortex-m mfgr: Freescale - chip: MKV58F20 - should_pass: false - run_when: never + chip: MK21D5 - arch: cortex-m mfgr: Freescale - chip: MKV58F22 - should_pass: false - run_when: never + chip: MK21F12 - arch: cortex-m mfgr: Freescale - chip: MKV58F24 - should_pass: false - run_when: never + chip: MK30D7 - arch: cortex-m mfgr: Freescale - chip: MK61F15 - should_pass: false - run_when: never + chip: MK40D7 - arch: cortex-m mfgr: Freescale - chip: MK61F15WS - should_pass: false - run_when: never + chip: MK52DZ10 - arch: cortex-m mfgr: Freescale - chip: MK70F12 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Freescale - chip: MK70F15 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Freescale - chip: MK70F15WS - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Freescale - chip: MK02F12810 -- arch: cortex-m - mfgr: Freescale - chip: MK10D10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK10D5 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK10D7 -- arch: cortex-m - mfgr: Freescale - chip: MK10DZ10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK10F12 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK11D5 -- arch: cortex-m - mfgr: Freescale - chip: MK11D5WS - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK11DA5 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK12D5 -- arch: cortex-m - mfgr: Freescale - chip: MK20D10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK20D5 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK20D7 -- arch: cortex-m - mfgr: Freescale - chip: MK20DZ10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK20F12 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK21D5 -- arch: cortex-m - mfgr: Freescale - chip: MK21D5WS - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK21DA5 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK21F12 -- arch: cortex-m - mfgr: Freescale - chip: MK21FA12 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK22D5 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK22F12 -- arch: cortex-m - mfgr: Freescale - chip: MK22F12810 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK22F25612 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK22F51212 -- arch: cortex-m - mfgr: Freescale - chip: MK22FA12 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK24F12 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK24F25612 -- arch: cortex-m - mfgr: Freescale - chip: MK26F18 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK30D10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK30D7 -- arch: cortex-m - mfgr: Freescale - chip: MK30DZ10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK40D10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK40D7 -- arch: cortex-m - mfgr: Freescale - chip: MK40DZ10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK50D10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK50D7 -- arch: cortex-m - mfgr: Freescale - chip: MK50DZ10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK51D10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK51D7 -- arch: cortex-m - mfgr: Freescale - chip: MK51DZ10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK52D10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK52DZ10 -- arch: cortex-m - mfgr: Freescale - chip: MK53D10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK53DZ10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK60D10 -- arch: cortex-m - mfgr: Freescale - chip: MK60DZ10 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK60F15 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK63F12 -- arch: cortex-m - mfgr: Freescale - chip: MK64F12 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK65F18 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK66F18 -- arch: cortex-m - mfgr: Freescale - chip: MK80F25615 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MK81F25615 - should_pass: true - run_when: not-short + chip: MK66F18 - arch: cortex-m mfgr: Freescale chip: MK82F25615 -- arch: cortex-m - mfgr: Freescale - chip: MKE14F16 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKE14Z7 - should_pass: true - run_when: not-short - arch: cortex-m mfgr: Freescale chip: MKE15Z7 - arch: cortex-m - mfgr: Freescale - chip: MKE16F16 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKE18F16 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL28T7_CORE0 -- arch: cortex-m - mfgr: Freescale - chip: MKL28T7_CORE1 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL28Z7 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL81Z7 -- arch: cortex-m - mfgr: Freescale - chip: MKL82Z7 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKS22F12 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKV10Z1287 -- arch: cortex-m - mfgr: Freescale - chip: MKV10Z7 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKV11Z7 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKV30F12810 -- arch: cortex-m - mfgr: Freescale - chip: MKV31F12810 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKV31F25612 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKV31F51212 -- arch: cortex-m - mfgr: Freescale - chip: MKV40F15 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKV42F16 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKV43F15 -- arch: cortex-m - mfgr: Freescale - chip: MKV44F15 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKV44F16 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKV45F15 -- arch: cortex-m - mfgr: Freescale - chip: MKV46F15 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKV46F16 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKW20Z4 -- arch: cortex-m - mfgr: Freescale - chip: MKW21D5 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKW21Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKW22D5 -- arch: cortex-m - mfgr: Freescale - chip: MKW24D5 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKW30Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKW31Z4 -- arch: cortex-m - mfgr: Freescale - chip: MKW40Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKW41Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKE02Z4 -- arch: cortex-m - mfgr: Freescale - chip: MKE04Z1284 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKE04Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKE06Z4 -- arch: cortex-m - mfgr: Freescale - chip: MKE14D7 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKE15D7 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL02Z4 -- arch: cortex-m - mfgr: Freescale - chip: MKL03Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL04Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL05Z4 -- arch: cortex-m - mfgr: Freescale - chip: MKL13Z644 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL14Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL15Z4 -- arch: cortex-m - mfgr: Freescale - chip: MKL16Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL17Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL17Z644 -- arch: cortex-m - mfgr: Freescale - chip: MKL24Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL25Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL26Z4 -- arch: cortex-m - mfgr: Freescale - chip: MKL27Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL27Z644 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL33Z4 -- arch: cortex-m - mfgr: Freescale - chip: MKL33Z644 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL34Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL36Z4 -- arch: cortex-m - mfgr: Freescale - chip: MKL43Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKL46Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKM14ZA5 -- arch: cortex-m - mfgr: Freescale - chip: MKM33ZA5 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKM34Z7 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: MKM34ZA5 -- arch: cortex-m - mfgr: Freescale - chip: MKW01Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: SKEAZ1284 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Freescale - chip: SKEAZN642 -- arch: cortex-m - mfgr: Freescale - chip: SKEAZN84 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF10xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF10xR -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF11xK -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF11xL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF11xM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF11xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF12xK -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF12xL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF13xK -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF13xL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF13xM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF13xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF14xL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF14xM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF14xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF15xM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF15xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF15xR -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF1AxL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF1AxM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF1AxN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF31xK -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF31xL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF31xM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF31xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF34xL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF34xM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF34xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF42xK -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AF42xL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AFA3xL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AFA3xM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AFA3xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AFA4xL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AFA4xM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AFA4xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AFAAxL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AFAAxM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AFAAxN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AFB4xL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AFB4xM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9AFB4xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9B160L -- arch: cortex-m - mfgr: Fujitsu - chip: MB9B160R -- arch: cortex-m - mfgr: Fujitsu - chip: MB9B360L -- arch: cortex-m - mfgr: Fujitsu - chip: MB9B360R -- arch: cortex-m - mfgr: Fujitsu - chip: MB9B460L -- arch: cortex-m - mfgr: Fujitsu - chip: MB9B460R -- arch: cortex-m - mfgr: Fujitsu - chip: MB9B560L -- arch: cortex-m - mfgr: Fujitsu - chip: MB9B560R -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF10xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF10xR -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF11xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF11xR -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF11xS -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF11xT -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF12xJ -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF12xK -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF12xL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF12xM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF12xS -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF12xT -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF21xS -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF21xT -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF30xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF30xR -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF31xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF31xR -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF31xS -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF31xT -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF32xK -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF32xL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF32xM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF32xS -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF32xT -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF40xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF40xR -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF41xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF41xR -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF41xS -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF41xT -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF42xS -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF42xT -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF50xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF50xR -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF51xN -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF51xR -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF51xS -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF51xT -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF52xK -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF52xL -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF52xM -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF52xS -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF52xT -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF61xS -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BF61xT -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BFD1xS -- arch: cortex-m - mfgr: Fujitsu - chip: MB9BFD1xT -- arch: cortex-m - mfgr: Fujitsu - chip: S6E1A1 -- arch: cortex-m - mfgr: Fujitsu - chip: S6E2CC -- arch: cortex-m - mfgr: Holtek - chip: ht32f125x -- arch: cortex-m - mfgr: Holtek - chip: ht32f175x -- arch: cortex-m - mfgr: Holtek - chip: ht32f275x -- arch: cortex-m - mfgr: Nordic - chip: nrf51 -- arch: cortex-m - mfgr: Nordic - chip: nrf52 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Nuvoton - chip: M051_Series - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Nuvoton - chip: NUC100_Series - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC11Exx_v5 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC11Uxx_v7 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC11xx_v6a - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC11xx_v6 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC13Uxx_v1 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC15xx_v0.7 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC800_v0.3 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC11E6x_v0.8 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC176x5x_v0.2 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC11Cxx_v9 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC178x_7x - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC178x_7x_v0.8 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC408x_7x_v0.7 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC11Axxv0.6 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC11D14_svd_v4 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC13xx_svd_v1 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC18xx_svd_v18 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC43xx_43Sxx - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC1102_4_v4 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: LPC5410x_v0.4 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: NXP - chip: MK22F25612 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: NXP - chip: MK22F51212 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: NXP - chip: MKW41Z4 - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: SiliconLabs - chip: SIM3C1x4_SVD - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: SiliconLabs - chip: SIM3C1x6_SVD - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: SiliconLabs - chip: SIM3C1x7_SVD - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: SiliconLabs - chip: SIM3L1x4_SVD - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: SiliconLabs - chip: SIM3L1x6_SVD - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: SiliconLabs - chip: SIM3L1x7_SVD - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: SiliconLabs - chip: SIM3U1x4_SVD - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: SiliconLabs - chip: SIM3U1x6_SVD - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: SiliconLabs - chip: SIM3U1x7_SVD - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: SiliconLabs - chip: SIM3L1x8_SVD - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Spansion - chip: MB9AF12xK - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Spansion - chip: MB9AF12xL - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Spansion - chip: MB9AF42xK - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Spansion - chip: MB9AF42xL - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Spansion - chip: MB9BF12xJ - should_pass: true - run_when: not-short + mfgr: Freescale + chip: MKL28T7_CORE0 - arch: cortex-m - mfgr: Spansion - chip: MB9BF12xS - should_pass: true - run_when: not-short + mfgr: Freescale + chip: MKL81Z7 - arch: cortex-m - mfgr: Spansion - chip: MB9BF12xT - should_pass: true - run_when: not-short + mfgr: Freescale + chip: MKV10Z1287 - arch: cortex-m - mfgr: Spansion - chip: MB9BF16xx - should_pass: true - run_when: not-short + mfgr: Freescale + chip: MKV31F51212 - arch: cortex-m - mfgr: Spansion - chip: MB9BF32xS - should_pass: true - run_when: not-short + mfgr: Freescale + chip: MKV45F15 - arch: cortex-m - mfgr: Spansion - chip: MB9BF32xT - should_pass: true - run_when: not-short + mfgr: Freescale + chip: MKW22D5 - arch: cortex-m - mfgr: Spansion - chip: MB9BF36xx - should_pass: true - run_when: not-short + mfgr: Freescale + chip: MKE02Z4 - arch: cortex-m - mfgr: Spansion - chip: MB9BF42xS - should_pass: true - run_when: not-short + mfgr: Freescale + chip: MKE06Z4 - arch: cortex-m - mfgr: Spansion - chip: MB9BF42xT - should_pass: true - run_when: not-short + mfgr: Freescale + chip: MKL05Z4 - arch: cortex-m - mfgr: Spansion - chip: MB9BF46xx - should_pass: true - run_when: not-short + mfgr: Freescale + chip: MKL17Z644 - arch: cortex-m - mfgr: Spansion - chip: MB9BF52xS - should_pass: true - run_when: not-short + mfgr: Freescale + chip: MKL36Z4 - arch: cortex-m - mfgr: Spansion - chip: MB9BF52xT - should_pass: true - run_when: not-short + mfgr: Freescale + chip: MKM14ZA5 - arch: cortex-m - mfgr: Spansion - chip: MB9BF56xx - should_pass: true - run_when: not-short + mfgr: Freescale + chip: MKM34ZA5 - arch: cortex-m - mfgr: Spansion + mfgr: Freescale + chip: SKEAZN642 + +# Fujitsu +- arch: cortex-m + mfgr: Fujitsu chip: MB9AF10xN - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF10xR - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF11xK - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF11xL - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF11xM - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF11xN - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu + chip: MB9AF12xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF12xL +- arch: cortex-m + mfgr: Fujitsu chip: MB9AF13xK - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF13xL - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF13xM - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF13xN - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF14xL - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF14xM - arch: cortex-m - mfgr: Spansion - chip: MB9AF14xN - should_pass: true - run_when: not-short -- arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF15xM - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF15xN - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF15xR - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu + chip: MB9AF1AxL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF1AxM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF1AxN +- arch: cortex-m + mfgr: Fujitsu chip: MB9AF31xK - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF31xL - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF31xM - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF31xN - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF34xL - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF34xM - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AF34xN - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu + chip: MB9AF42xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF42xL +- arch: cortex-m + mfgr: Fujitsu chip: MB9AFA3xL - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AFA3xM - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AFA3xN - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AFA4xL - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AFA4xM - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AFA4xN - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu + chip: MB9AFAAxL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFAAxM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFAAxN +- arch: cortex-m + mfgr: Fujitsu chip: MB9AFB4xL - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AFB4xM - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9AFB4xN - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu + chip: MB9B160L +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B160R +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B360L +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B360R +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B460L +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B460R +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B560L +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B560R +- arch: cortex-m + mfgr: Fujitsu chip: MB9BF10xN - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF10xR - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF11xN - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF11xR - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF11xS - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF11xT - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu + chip: MB9BF12xJ +- arch: cortex-m + mfgr: Fujitsu chip: MB9BF12xK - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF12xL - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF12xM - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu + chip: MB9BF12xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF12xT +- arch: cortex-m + mfgr: Fujitsu chip: MB9BF21xS - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF21xT - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF30xN - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF30xR - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF31xN - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF31xR - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF31xS - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF31xT - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF32xK - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF32xL - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF32xM - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu + chip: MB9BF32xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF32xT +- arch: cortex-m + mfgr: Fujitsu chip: MB9BF40xN - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF40xR - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF41xN - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF41xR - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF41xS - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF41xT - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu + chip: MB9BF42xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF42xT +- arch: cortex-m + mfgr: Fujitsu chip: MB9BF50xN - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF50xR - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF51xN - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF51xR - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF51xS - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF51xT - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF52xK - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF52xL - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF52xM - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu + chip: MB9BF52xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF52xT +- arch: cortex-m + mfgr: Fujitsu chip: MB9BF61xS - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BF61xT - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BFD1xS - arch: cortex-m - mfgr: Spansion + mfgr: Fujitsu chip: MB9BFD1xT - should_pass: true - run_when: not-short - arch: cortex-m - mfgr: STMicro - chip: STM32F030 + mfgr: Fujitsu + chip: S6E1A1 + +# GD32 + +# Holtek - arch: cortex-m - mfgr: STMicro - chip: STM32F0x2 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32f0x2.svd.patched + mfgr: Holtek + chip: ht32f125x - arch: cortex-m - mfgr: STMicro - chip: STM32F103 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32f103.svd.patched + mfgr: Holtek + chip: ht32f175x - arch: cortex-m - mfgr: STMicro - chip: STM32F411 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32f411.svd.patched + mfgr: Holtek + chip: ht32f275x + +# Microchip +- arch: mips + mfgr: Microchip + chip: pic32mx170f256b + svd_url: https://raw.githubusercontent.com/kiffie/pic32-pac/master/pic32mx1xxfxxxb/PIC32MX170F256B.svd.patched +- arch: mips + mfgr: Microchip + chip: pic32mx270f256b + svd_url: https://raw.githubusercontent.com/kiffie/pic32-pac/master/pic32mx2xxfxxxb/PIC32MX270F256B.svd.patched + +# Nordic - arch: cortex-m - mfgr: STMicro - chip: STM32F469 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32f469.svd.patched + mfgr: Nordic + chip: nrf51 - arch: cortex-m - mfgr: STMicro - chip: STM32F723 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32f723.svd.patched + mfgr: Nordic + chip: nrf52 + should_pass: false + run_when: never + +# Nuvoton - arch: cortex-m - mfgr: STMicro - chip: STM32G070 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32g070.svd.patched + mfgr: Nuvoton + chip: NUC100_Series - arch: cortex-m - mfgr: STMicro - chip: STM32G473 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32g473.svd.patched + mfgr: Nuvoton + chip: M051_Series + +# NXP - arch: cortex-m - mfgr: STMicro - chip: STM32H753 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32h753.svd.patched + mfgr: NXP + chip: MK22F25612 - arch: cortex-m - mfgr: STMicro - chip: STM32L0x3 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32l0x3.svd.patched + mfgr: NXP + chip: MKW41Z4 + +# MSP430 +- arch: msp430 + mfgr: TexasInstruments + chip: msp430g2553 + skip_check: true + svd_url: https://github.com/pftbest/msp430g2553/raw/v0.3.0-svd/msp430g2553.svd +- arch: msp430 + mfgr: TexasInstruments + chip: msp430fr2355 + skip_check: true + svd_url: https://raw.githubusercontent.com/YuhanLiin/msp430fr2355/master/msp430fr2355.svd + +# RISC-V +- arch: riscv + mfgr: SiFive + chip: e310x + svd_url: https://raw.githubusercontent.com/riscv-rust/e310x/master/e310x/e310x.svd +- arch: riscv + mfgr: SiFive + chip: fu540 + svd_url: https://raw.githubusercontent.com/riscv-rust/fu540-pac/master/fu540.svd + +# SiliconLabs - arch: cortex-m - mfgr: STMicro - chip: STM32L162 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32l162.svd.patched + mfgr: SiliconLabs + chip: SIM3C1x4_SVD + svd_url: https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3C1x4.svd - arch: cortex-m - mfgr: STMicro - chip: STM32L4x6 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32l4x6.svd.patched + mfgr: SiliconLabs + chip: SIM3C1x6_SVD + svd_url: https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3C1x6.svd - arch: cortex-m - mfgr: STMicro - chip: STM32L562 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32l562.svd.patched + mfgr: SiliconLabs + chip: SIM3C1x7_SVD + svd_url: https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3C1x7.svd - arch: cortex-m - mfgr: STMicro - chip: STM32MP157 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32mp157.svd.patched + mfgr: SiliconLabs + chip: SIM3L1x4_SVD + svd_url: https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3L1x4.svd - arch: cortex-m - mfgr: STMicro - chip: STM32WB55 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32wb55.svd.patched + mfgr: SiliconLabs + chip: SIM3L1x6_SVD + svd_url: https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3L1x6.svd - arch: cortex-m - mfgr: STMicro - chip: STM32WLE5 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32wle5.svd.patched + mfgr: SiliconLabs + chip: SIM3L1x7_SVD + svd_url: https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3L1x7.svd +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3U1x4_SVD + svd_url: https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3U1x4.svd +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3U1x6_SVD + svd_url: https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3U1x6.svd +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3U1x7_SVD + svd_url: https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3U1x7.svd +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3L1x8_SVD + svd_url: https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3L1x8.svd + +# Spansion +- arch: cortex-m + mfgr: Spansion + chip: MB9BF36xx +- arch: cortex-m + mfgr: Spansion + chip: MB9BF46xx +- arch: cortex-m + mfgr: Spansion + chip: MB9BF56xx + +# STMicro - arch: cortex-m mfgr: STMicro - chip: STM32C011 - svd_url: https://stm32-rs.github.io/stm32-rs/stm32c011.svd.patched + chip: STM32F030 - arch: cortex-m mfgr: STMicro chip: STM32F031x @@ -1929,13 +521,7 @@ chip: STM32F100xx - arch: cortex-m mfgr: STMicro - chip: STM32F101xx -- arch: cortex-m - mfgr: STMicro - chip: STM32F102xx -- arch: cortex-m - mfgr: STMicro - chip: STM32F105xx + chip: STM32F103xx - arch: cortex-m mfgr: STMicro chip: STM32F107xx @@ -1948,33 +534,18 @@ - arch: cortex-m mfgr: STMicro chip: STM32F301 -- arch: cortex-m - mfgr: STMicro - chip: STM32F302 - arch: cortex-m mfgr: STMicro chip: STM32F303 -- arch: cortex-m - mfgr: STMicro - chip: STM32F3x4 -- arch: cortex-m - mfgr: STMicro - chip: STM32F373 - arch: cortex-m mfgr: STMicro chip: STM32F401 -- arch: cortex-m - mfgr: STMicro - chip: STM32F405 - arch: cortex-m mfgr: STMicro chip: STM32F407 - arch: cortex-m mfgr: STMicro chip: STM32F410 -- arch: cortex-m - mfgr: STMicro - chip: STM32F412 - arch: cortex-m mfgr: STMicro chip: STM32F413 @@ -1989,151 +560,132 @@ chip: STM32F446 - arch: cortex-m mfgr: STMicro - chip: STM32F7x -- arch: cortex-m - mfgr: STMicro - chip: STM32F7x2 -- arch: cortex-m - mfgr: STMicro - chip: STM32F7x5 + chip: STM32L100 - arch: cortex-m mfgr: STMicro - chip: STM32F7x6 + chip: STM32L15xC - arch: cortex-m mfgr: STMicro - chip: STM32F7x7 + chip: STM32L15xxE - arch: cortex-m mfgr: STMicro - chip: STM32F7x9 + chip: STM32L15xxxA - arch: cortex-m mfgr: STMicro - chip: STM32G07x - should_pass: false - run_when: never + chip: STM32L1xx - arch: cortex-m mfgr: STMicro - chip: STM32G431xx + chip: STM32W108 +# Patched - arch: cortex-m mfgr: STMicro - chip: STM32G441xx + chip: STM32F0x2 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f0x2.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32G471xx + chip: STM32F103 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f103.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32G474xx + chip: STM32F411 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f411.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32G483xx + chip: STM32F469 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f469.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32G484xx + chip: STM32F723 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f723.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32L100 + chip: STM32G070 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32g070.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32L15xC + chip: STM32G473 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32g473.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32L15xxE + chip: STM32H743 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32h743.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32L15xxxA + chip: STM32L0x3 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32l0x3.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32L1xx + chip: STM32L162 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32l162.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32W108 + chip: STM32L4x6 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32l4x6.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32L051x - should_pass: false - run_when: never + chip: STM32L562 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32l562.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32L052x - should_pass: false - run_when: never + chip: STM32MP157 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32mp157.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32L053x - should_pass: false - run_when: never + chip: STM32WB55 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32wb55.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32L062x - should_pass: false - run_when: never + chip: STM32WLE5 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32wle5.svd.patched - arch: cortex-m mfgr: STMicro - chip: STM32L063x - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Toshiba - chip: M365 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Toshiba - chip: M367 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Toshiba - chip: M368 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Toshiba - chip: M369 - should_pass: false - run_when: never -- arch: cortex-m - mfgr: Toshiba - chip: M36B - should_pass: false - run_when: never + chip: STM32C011 + suffix: patched + svd_url: https://stm32-rs.github.io/stm32-rs/stm32c011.svd.patched + +# Toschiba - arch: cortex-m mfgr: Toshiba chip: M061 -- arch: riscv - mfgr: SiFive - chip: E310x - svd_url: https://raw.githubusercontent.com/riscv-rust/e310x/master/e310x/e310x.svd - should_pass: false - run_when: never -- arch: msp430 - mfgr: TexasInstruments - chip: msp430g2553 - svd_url: https://github.com/pftbest/msp430g2553/raw/v0.1.3-svd/msp430g2553.svd -- arch: msp430 - mfgr: TexasInstruments - chip: msp430fr2355 - svd_url: https://raw.githubusercontent.com/YuhanLiin/msp430fr2355/master/msp430fr2355.svd + +# Espressif +# Xtensa requires special LLVM fork and nightly compiler, so skip the checks for now. - arch: xtensa-lx mfgr: Espressif chip: esp32 + opts: + - --ident-formats-theme + - legacy svd_url: https://raw.githubusercontent.com/espressif/svd/main/svd/esp32.svd - arch: xtensa-lx mfgr: Espressif chip: esp32s2 + opts: + - --ident-formats-theme + - legacy svd_url: https://raw.githubusercontent.com/espressif/svd/main/svd/esp32s2.svd - arch: xtensa-lx mfgr: Espressif chip: esp32s3 + opts: + - --ident-formats-theme + - legacy svd_url: https://raw.githubusercontent.com/espressif/svd/main/svd/esp32s3.svd - arch: riscv mfgr: Espressif chip: esp32c3 svd_url: https://raw.githubusercontent.com/espressif/svd/main/svd/esp32c3.svd -- arch: mips - mfgr: Microchip - chip: pic32mx170f256b - svd_url: https://raw.githubusercontent.com/kiffie/pic32-pac/master/pic32mx1xxfxxxb/PIC32MX170F256B.svd.patched -- arch: mips - mfgr: Microchip - chip: pic32mx270f256b - svd_url: https://raw.githubusercontent.com/kiffie/pic32-pac/master/pic32mx2xxfxxxb/PIC32MX270F256B.svd.patched diff --git a/src/util.rs b/src/util.rs index f97cb378..fd7bb3c2 100644 --- a/src/util.rs +++ b/src/util.rs @@ -71,9 +71,9 @@ impl Case { }, } } + pub fn sanitize<'a>(&self, s: &'a str) -> Cow<'a, str> { let s = sanitize(s); - self.cow_to_case(s) } }