[Bug Report] Wrong sign bit when 0 is multiplied by a negative number

[zhangkanqi]

Environment:

RSD version: bd7c5c1

Bug Description:

There is an instruction fmul.s ft9, fs4, ft8, where fs4=0x00000000 and ft8=0x998a3664.

After the fmul.s instruction, the result of ft9 in RSD is 0x00000000. However, the result in spike is 0x80000000.

It seems that RSD mistakes the sign bit of the final result?

[lpha-z]

Thank you for finding the bug.

@ RSD team: Fix the following 32'h00000000 to 32'h80000000. The identity element of floating-point addition is -0.0, not +0.0.

            if(fpuCode[i] == FC_MUL) begin
                fmaAddend[i] = 32'h00000000;
            end

https://github.com/rsd-devel/rsd/blob/master/Processor/Src/Pipeline/FPBackEnd/FPExecutionStage.sv#L180

[zhangkanqi]

Thanks for your confirmation!

[lpha-z]

We reopen this report because this bug has not been fixed yet.
When we finish fixing, we will close this report.