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mokee-ex-v2.patch
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mokee-ex-v2.patch
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Makefile | 4 +-
arch/arm/Makefile | 1 +
arch/arm/configs/aries-perf-usr_defconfig | 159 ++++++++-
arch/arm/mach-msm/Kconfig | 18 +
arch/arm/mach-msm/Makefile | 2 +
arch/arm/mach-msm/acpuclock-8064.c | 337 +++++++++---------
arch/arm/mach-msm/acpuclock-krait.c | 49 +++
arch/arm/mach-msm/board-8064-regulator.c | 10 +-
arch/arm/mach-msm/board-8064.c | 2 +-
arch/arm/mach-msm/board-aries-gpu.c | 23 +-
arch/arm/mach-msm/board-aries-regulator.c | 10 +-
arch/arm/mach-msm/board-aries.c | 18 +-
arch/arm/mach-msm/clock-8960.c | 81 ++++-
arch/arm/mach-msm/clock-pll.c | 37 ++
arch/arm/mach-msm/cpufreq.c | 79 +++++
arch/arm/mach-msm/include/mach/kgsl.h | 2 +
arch/arm/vfp/Makefile | 2 +-
drivers/cpufreq/Kconfig | 26 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/cpufreq.c | 321 +++++++++++++-----
drivers/cpufreq/cpufreq_stats.c | 4 +-
drivers/gpu/ion/Makefile | 1 +
drivers/gpu/ion/msm/Makefile | 1 +
drivers/gpu/msm/Makefile | 2 +-
drivers/gpu/msm/kgsl_pwrctrl.c | 69 +++-
drivers/input/touchscreen/Kconfig | 6 +
drivers/input/touchscreen/atmel_mxt_ts.c | 544 +++++++++++++++++++++++++++++-
drivers/staging/prima/Makefile | 6 +-
include/linux/cpufreq.h | 11 +-
29 files changed, 1526 insertions(+), 300 deletions(-)
diff --git a/Makefile b/Makefile
index a687963..53e4e3b 100644
--- a/Makefile
+++ b/Makefile
@@ -370,10 +370,10 @@ KBUILD_CFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
-Wno-format-security \
-fno-delete-null-pointer-checks
KBUILD_AFLAGS_KERNEL :=
-KBUILD_CFLAGS_KERNEL :=
+KBUILD_CFLAGS_KERNEL := -mcpu=cortex-a15 -mfpu=neon-vfpv4
KBUILD_AFLAGS := -D__ASSEMBLY__
KBUILD_AFLAGS_MODULE := -DMODULE
-KBUILD_CFLAGS_MODULE := -DMODULE
+KBUILD_CFLAGS_MODULE := -DMODULE -mcpu=cortex-a15 -mfpu=neon-vfpv4
KBUILD_LDFLAGS_MODULE := -T $(srctree)/scripts/module-common.lds
# Read KERNELRELEASE from include/config/kernel.release (if it exists)
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index d9f4657..4283596 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -68,6 +68,7 @@ arch-$(CONFIG_CPU_32v5) :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5t
arch-$(CONFIG_CPU_32v4T) :=-D__LINUX_ARM_ARCH__=4 -march=armv4t
arch-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4 -march=armv4
arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3
+arch-$(CONFIG_ARCH_MSM_KRAIT) :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-mcpu=cortex-a15,-march=armv7-a,-mfpu=neon-vfpv4)
# This selects how we optimise for the processor.
tune-$(CONFIG_CPU_ARM610) :=-mtune=arm610
diff --git a/arch/arm/configs/aries-perf-usr_defconfig b/arch/arm/configs/aries-perf-usr_defconfig
index 5d3d71a..7a99a76 100644
--- a/arch/arm/configs/aries-perf-usr_defconfig
+++ b/arch/arm/configs/aries-perf-usr_defconfig
@@ -18,7 +18,7 @@ CONFIG_NAMESPACES=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_BZIP2=y
CONFIG_RD_LZMA=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_PANIC_TIMEOUT=5
CONFIG_ASHMEM=y
CONFIG_EMBEDDED=y
@@ -30,12 +30,30 @@ CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_EFI_PARTITION=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_TEST is not set
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_ROW=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_ROW=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="row"
+
+CONFIG_MMU=y
CONFIG_ARCH_MSM=y
CONFIG_ARCH_MSM8960=y
-CONFIG_ARCH_MSM8930=y
+# CONFIG_ARCH_MSM8930 is not set
CONFIG_ARCH_APQ8064=y
CONFIG_MSM_KRAIT_TBB_ABORT_HANDLER=y
+CONFIG_ARCH_MSM_KRAIT=y
+CONFIG_MSM_SMP=y
+CONFIG_ARCH_MSM_KRAITMP=y
CONFIG_MACH_APQ8064_MTP=y
CONFIG_MACH_MITWO=y
# CONFIG_MSM_STACKED_MEMORY is not set
@@ -69,26 +87,36 @@ CONFIG_MSM_TZ_LOG=y
CONFIG_MSM_RPM_LOG=y
CONFIG_MSM_RPM_STATS_LOG=y
CONFIG_MSM_RPM_RBCPR_STATS_LOG=y
+CONFIG_IOMMU_API=y
CONFIG_MSM_BUS_SCALING=y
CONFIG_MSM_BUS_RPM_MULTI_TIER_ENABLED=y
CONFIG_MSM_WATCHDOG=y
CONFIG_MSM_DLOAD_MODE=y
+CONFIG_MSM_QDSP6_CODECS=y
+CONFIG_MSM_AUDIO_QDSP6=y
CONFIG_MSM_JTAG=y
-CONFIG_MSM_EBI_ERP=y
+CONFIG_MSM_MULTIMEDIA_USE_ION=y
+# CONFIG_MSM_EBI_ERP is not set
CONFIG_MSM_CACHE_ERP=y
CONFIG_MSM_L1_ERR_PANIC=y
-CONFIG_MSM_L1_RECOV_ERR_PANIC=y
-CONFIG_MSM_L1_ERR_LOG=y
-CONFIG_MSM_L2_ERP_PRINT_ACCESS_ERRORS=y
-CONFIG_MSM_L2_ERP_1BIT_PANIC=y
+# CONFIG_MSM_L1_RECOV_ERR_PANIC is not set
+# CONFIG_MSM_L1_ERR_LOG is not set
+# CONFIG_MSM_L2_ERP_PRINT_ACCESS_ERRORS is not set
+# CONFIG_MSM_L2_ERP_1BIT_PANIC is not set
CONFIG_MSM_L2_ERP_2BIT_PANIC=y
CONFIG_MSM_DCVS=y
CONFIG_MSM_CACHE_DUMP=y
CONFIG_MSM_CACHE_DUMP_ON_PANIC=y
CONFIG_MSM_HSIC_SYSMON=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
CONFIG_STRICT_MEMORY_RWX=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_HAVE_SMP=y
CONFIG_SMP=y
# UART
CONFIG_MSM_UART_HS_USE_HS=y
@@ -98,7 +126,7 @@ CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
CONFIG_HIGHMEM=y
-CONFIG_VMALLOC_RESERVE=0x19000000
+# CONFIG_VMALLOC_RESERVE=0x19000000 is not set
CONFIG_COMPACTION=y
CONFIG_CC_STACKPROTECTOR=y
CONFIG_CP_ACCESS=y
@@ -110,6 +138,7 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
+CONFIG_VFPv3=y
CONFIG_NEON=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_WAKELOCK=y
@@ -247,13 +276,26 @@ CONFIG_BT_HCISMD=y
CONFIG_CFG80211=y
# CONFIG_CFG80211_WEXT is not set
CONFIG_RFKILL=y
+CONFIG_DMA_SHARED_BUFFER=y
CONFIG_GENLOCK=y
CONFIG_GENLOCK_MISCDEVICE=y
CONFIG_SYNC=y
CONFIG_SW_SYNC=y
-CONFIG_SW_SYNC_USER=y
+# CONFIG_SW_SYNC_USER is not set
CONFIG_CONNECTOR=y
-# CONFIG_CMA is not set
+CONFIG_CMA=y
+# CONFIG_CMA_DEBUG is not set
+
+#
+# Default contiguous memory area size:
+#
+CONFIG_CMA_SIZE_MBYTES=16
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_UID_STAT=y
@@ -331,6 +373,8 @@ CONFIG_RMI4_DEV=y
CONFIG_N_SMUX=y
CONFIG_N_SMUX_LOOPBACK=y
CONFIG_SMUX_CTL=y
+CONFIG_DEVMEM=y
+CONFIG_DEVKMEM=y
CONFIG_SERIAL_MSM_HS=y
CONFIG_SERIAL_MSM_HSL=y
CONFIG_DIAG_CHAR=y
@@ -369,6 +413,7 @@ CONFIG_REGULATOR_MSM_GPIO=y
CONFIG_MEDIA_SUPPORT=y
CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_MSM_WFD=y
CONFIG_USER_RC_INPUT=y
@@ -392,13 +437,31 @@ CONFIG_IMX074_EEPROM=y
CONFIG_IMX091_EEPROM=y
CONFIG_MSM_GEMINI=y
CONFIG_QUP_EXCLUSIVE_TO_CAMERA=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEOBUF2_CORE=y
CONFIG_MSM_VIDC=y
+CONFIG_VIDEOBUF2_MEMOPS=y
+CONFIG_VIDEOBUF2_DMA_CONTIG=y
+CONFIG_VIDEOBUF2_VMALLOC=y
+CONFIG_VIDEOBUF2_DMA_SG=y
+CONFIG_VIDEOBUF2_MSM_MEM=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
# CONFIG_MSM_VIDC_V4L2 is not set
+
CONFIG_RADIO_ADAPTERS=y
# CONFIG_MSM_MERCURY is not set
CONFIG_MSM_CSI20_HEADER=y
CONFIG_RADIO_IRIS=y
CONFIG_RADIO_IRIS_TRANSPORT=m
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+CONFIG_FB_MSM_LCDC_HW=y
CONFIG_ION=y
CONFIG_ION_MSM=y
CONFIG_MSM_KGSL=y
@@ -406,9 +469,19 @@ CONFIG_KGSL_PER_PROCESS_PAGE_TABLE=y
CONFIG_MSM_KGSL_PAGE_TABLE_COUNT=24
CONFIG_FB=y
CONFIG_FB_VIRTUAL=y
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_MSM_VIDC=y
+CONFIG_MSM_VIDC_1080P=y
+CONFIG_MSM_VIDC_VENC=y
+CONFIG_MSM_VIDC_VDEC=y
+# CONFIG_MSM_VIDC_CONTENT_PROTECTION is not set
CONFIG_FB_MSM=y
# CONFIG_FB_MSM_BACKLIGHT is not set
CONFIG_FB_MSM_TRIPLE_BUFFER=y
+# CONFIG_FB_MSM_MDP22 is not set
+# CONFIG_FB_MSM_MDP30 is not set
+# CONFIG_FB_MSM_MDP31 is not set
CONFIG_FB_MSM_MDP40=y
CONFIG_FB_MSM_MIPI_DSI_CABC=y
CONFIG_FB_MSM_OVERLAY=y
@@ -437,7 +510,17 @@ CONFIG_SND=y
CONFIG_SND_DYNAMIC_MINORS=y
CONFIG_SND_USB_AUDIO=y
CONFIG_SND_SOC=y
+#
+# MSM SoC Audio support
+#
+CONFIG_SND_SOC_MSM_HOSTLESS_PCM=y
+CONFIG_SND_SOC_MSM_QDSP6_HDMI_AUDIO=y
+CONFIG_SND_SOC_MSM_QDSP6_INTF=y
+CONFIG_SND_SOC_VOICE=y
+CONFIG_SND_SOC_QDSP6=y
CONFIG_SND_SOC_MSM8960=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_WCD9310=y
# CONFIG_UHID is not set
CONFIG_HID_A4TECH=y
CONFIG_HID_ACRUX=y
@@ -494,7 +577,7 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_EHSET=y
CONFIG_USB_EHCI_MSM=y
CONFIG_USB_EHCI_MSM_HSIC=y
-CONFIG_USB_EHCI_MSM_HOST4=y
+# CONFIG_USB_EHCI_MSM_HOST4 is not set
CONFIG_USB_ACM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DEBUG=y
@@ -527,7 +610,7 @@ CONFIG_MMC_CLKGATE=y
CONFIG_MMC_PARANOID_SD_INIT=y
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_TEST=m
+# CONFIG_MMC_TEST is not set
CONFIG_MMC_MSM=y
CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT=y
# CONFIG_MMC_MSM_SDC2_SUPPORT is not set
@@ -544,8 +627,12 @@ CONFIG_RTC_DRV_PM8XXX=y
CONFIG_STAGING=y
CONFIG_ANDROID=y
CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ASHMEM=y
CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_PERSISTENT_RAM=y
CONFIG_ANDROID_RAM_CONSOLE=y
+# CONFIG_PERSISTENT_TRACER is not set
+CONFIG_ANDROID_TIMED_OUTPUT=y
CONFIG_ANDROID_TIMED_GPIO=y
CONFIG_ANDROID_LOW_MEMORY_KILLER=y
CONFIG_ANDROID_LOW_MEMORY_KILLER_AUTODETECT_OOM_ADJ_VALUES=y
@@ -583,8 +670,56 @@ CONFIG_SECURITY=y
CONFIG_SECURITY_NETWORK=y
CONFIG_LSM_MMAP_MIN_ADDR=4096
CONFIG_SECURITY_SELINUX=y
+CONFIG_CRYPTO=y
CONFIG_CRYPTO_NULL=y
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_USER is not set
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+#
+# Block modes
+#
CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+
CONFIG_CRYPTO_TWOFISH=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRC_CCITT=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_ARM=y
+
+# EX Config
+#
+CONFIG_KSM=y
+CONFIG_CPU_VOLTAGE_TABLE=y
+CONFIG_S2W=y
+CONFIG_GPU_VOLTAGE_TABLE=y
+CONFIG_MSM_SLEEPER=y
+CONFIG_CPU_FREQ_GOV_INTELLIACTIVE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_INTELLIACTIVE is not set
+CONFIG_LOCALVERSION="-Mokee-EX"
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 68cc5ff..da016df 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1648,6 +1648,24 @@ config MSM_CPU_FREQ_MIN
endif # CPU_FREQ_MSM
+config GPU_VOLTAGE_TABLE
+ bool "Enable GPU Voltage Table via sysfs for adjustments"
+ default n
+ help
+ Adreno User Voltage Control
+
+config MSM_SLEEPER
+ bool "Limit max frequency and shut off cores while screen is off"
+ default n
+ help
+ Limit max frequency and shut off cores while screen is off
+
+config CPU_VOLTAGE_TABLE
+ bool "Enable CPU Voltage Table via sysfs for adjustements"
+ default n
+ help
+ Krait User Votlage Control
+
config MSM_AVS_HW
bool "Enable Adaptive Voltage Scaling (AVS)"
default n
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index d505bd1..1a07f55 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -399,3 +399,5 @@ endif
obj-$(CONFIG_MSM_CPU_PWRCTL) += msm_cpu_pwrctl.o
obj-$(CONFIG_ARCH_RANDOM) += early_random.o
+
+obj-$(CONFIG_MSM_SLEEPER) += msm-sleeper.o
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index 0fe1793..5f4b0b1 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -98,6 +98,7 @@ static struct scalable scalable[] __initdata = {
/*
* The correct maximum rate for 8064ab in 600 MHZ.
* We rely on the RPM rounding requests up here.
+ * bus(前端总线)频率
*/
static struct msm_bus_paths bw_level_tbl[] __initdata = {
[0] = BW_MBPS(640), /* At least 80 MHz on bus. */
@@ -115,6 +116,7 @@ static struct msm_bus_scale_pdata bus_scale_data __initdata = {
.name = "acpuclk-8064",
};
+/* l2(二级缓存)频率 */
static struct l2_level l2_freq_tbl[] __initdata = {
[0] = { { 384000, PLL_8, 0, 0x00 }, 950000, 1050000, 1 },
[1] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 },
@@ -134,33 +136,8 @@ static struct l2_level l2_freq_tbl[] __initdata = {
{ }
};
+/* 8064各体质频率 */
static struct acpu_level tbl_slow[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 1075000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1100000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1237500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1250000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_nom[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 925000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
@@ -183,45 +160,21 @@ static struct acpu_level tbl_nom[] __initdata = {
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1187500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1187500 },
{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1200000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(14), 1225000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1250000 },
{ 0, { 0 } }
};
-static struct acpu_level tbl_fast[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 975000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1000000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1025000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1075000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1075000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1100000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1100000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1125000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1125000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1137500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1137500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1150000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_faster[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 962500 },
+static struct acpu_level tbl_nom[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 825000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 850000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 850000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 875000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 950000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 950000 },
{ 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 975000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 975000 },
{ 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1000000 },
@@ -235,6 +188,64 @@ static struct acpu_level tbl_faster[] __initdata = {
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1112500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },
{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1125000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(14), 1150000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1175000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_fast[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 800000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 800000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 800000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 825000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 825000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 850000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 850000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 900000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 925000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 950000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1000000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1000000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1025000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1025000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1050000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1050000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1062500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1062500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1075000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(14), 1100000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1125000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_faster[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 800000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 800000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 800000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 825000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 825000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 850000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 850000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 887500 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 900000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 925000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 975000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 975000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1000000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1000000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1025000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1025000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1037500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1037500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1050000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(14), 1075000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1100000 },
{ 0, { 0 } }
};
@@ -350,132 +361,141 @@ static struct acpu_level tbl_PVS6_1512MHz[] __initdata = {
{ 0, { 0 } }
};
+/* 8064T各体质频率 */
static struct acpu_level tbl_PVS0_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1000000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1037500 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1075000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1087500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1125000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1150000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1175000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1225000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1250000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 912500 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 950000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 975000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 987500 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1025000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1037500 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1075000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1100000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1125000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1175000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1200000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1250000 },
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS1_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1012500 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1037500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1050000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1087500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1150000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1187500 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1200000 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS2_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 937500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 950000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 975000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1000000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1012500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1037500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1075000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1100000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1137500 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1162500 },
- { 0, { 0 } }
-};
-
-static struct acpu_level tbl_PVS3_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 887500 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 900000 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 975000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 987500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1000000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 937500 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 962500 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 975000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1012500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1037500 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1062500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1100000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1075000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1112500 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1125000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1220000 },
{ 0, { 0 } }
};
-static struct acpu_level tbl_PVS4_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
+static struct acpu_level tbl_PVS2_1700MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 825000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 837500 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 850000 },
{ 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
{ 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
{ 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 950000 },
{ 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 962500 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 975000 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1000000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1037500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1075000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1100000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 987500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1025000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1050000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1087500 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1112500 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1162500 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_PVS3_1700MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 800000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 800000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 800000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 800000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 800000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 850000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 875000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 900000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 912500 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 925000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 962500 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 987500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1125000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level tbl_PVS4_1700MHz[] __initdata = {
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 800000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 800000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 800000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 800000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 812500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 825000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 850000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 875000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 887000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 900000 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 925000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 962500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1000000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1025000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1100000 },
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS5_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 987500 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1012500 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1050000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1075000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 800000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 800000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 800000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 800000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 812500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 825000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 850000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 862500 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 875000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 887500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 912500 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 937500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 975000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1000000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1075000 },
{ 0, { 0 } }
};
static struct acpu_level tbl_PVS6_1700MHz[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 875000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 875000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 887500 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 900000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 925000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 937500 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 950000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 962500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 975000 },
- { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 1000000 },
- { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 1025000 },
- { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 1050000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 800000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 800000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 800000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 800000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 812500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 825000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 850000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 862500 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 875000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 887500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 900000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(14), 925000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(14), 950000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(14), 975000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(14), 1050000 },
{ 0, { 0 } }
};
+/* 8064AB各体质频率 */
static struct acpu_level tbl_PVS0_2000MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
@@ -609,6 +629,7 @@ static struct acpu_level tbl_PVS6_2000MHz[] __initdata = {
{ 0, { 0 } }
};
+/* 跟据speed_bin和pvs来选择频率表，最后一个值为boost_uv(动态浮动电压) */
static struct pvs_table pvs_tables[NUM_SPEED_BINS][NUM_PVS] __initdata = {
[0][PVS_SLOW] = {tbl_slow, sizeof(tbl_slow), 0 },
[0][PVS_NOMINAL] = {tbl_nom, sizeof(tbl_nom), 25000 },
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index 64b162e..17d18f4 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -925,6 +925,55 @@ static void __init bus_init(const struct l2_level *l2_level)
dev_err(drv.dev, "initial bandwidth req failed (%d)\n", ret);
}
+/* cpu电压控制 */
+#ifdef CONFIG_CPU_VOLTAGE_TABLE
+
+#define HFPLL_MIN_VDD 800000
+#define HFPLL_MAX_VDD 1300000
+
+ssize_t acpuclk_get_vdd_levels_str(char *buf) {
+
+ int i, len = 0;
+
+ if (buf) {
+ mutex_lock(&driver_lock);
+
+ for (i = 0; drv.acpu_freq_tbl[i].speed.khz; i++) {
+ /* updated to use uv required by 8x60 architecture - faux123 */
+ len += sprintf(buf + len, "%8lu: %8d\n", drv.acpu_freq_tbl[i].speed.khz,
+ drv.acpu_freq_tbl[i].vdd_core );
+ }
+
+ mutex_unlock(&driver_lock);
+ }
+ return len;
+}
+
+/* updated to use uv required by 8x60 architecture - faux123 */
+void acpuclk_set_vdd(unsigned int khz, int vdd_uv) {
+
+ int i;
+ unsigned int new_vdd_uv;
+
+ mutex_lock(&driver_lock);
+
+ for (i = 0; drv.acpu_freq_tbl[i].speed.khz; i++) {
+ if (khz == 0)
+ new_vdd_uv = min(max((unsigned int)(drv.acpu_freq_tbl[i].vdd_core + vdd_uv),
+ (unsigned int)HFPLL_MIN_VDD), (unsigned int)HFPLL_MAX_VDD);
+ else if ( drv.acpu_freq_tbl[i].speed.khz == khz)
+ new_vdd_uv = min(max((unsigned int)vdd_uv,
+ (unsigned int)HFPLL_MIN_VDD), (unsigned int)HFPLL_MAX_VDD);
+ else
+ continue;
+
+ drv.acpu_freq_tbl[i].vdd_core = new_vdd_uv;
+ }
+ pr_warn("faux123: user voltage table modified!\n");
+ mutex_unlock(&driver_lock);
+}
+#endif /* CONFIG_CPU_VOTALGE_TABLE */
+
#ifdef CONFIG_CPU_FREQ_MSM
static struct cpufreq_frequency_table freq_table[NR_CPUS][35];
diff --git a/arch/arm/mach-msm/board-8064-regulator.c b/arch/arm/mach-msm/board-8064-regulator.c
index f3750d2..a7640f2 100644
--- a/arch/arm/mach-msm/board-8064-regulator.c
+++ b/arch/arm/mach-msm/board-8064-regulator.c
@@ -576,18 +576,18 @@ mpq8064_gpio_regulator_pdata[] __devinitdata = {
SX150X_GPIO(4, 15), "avc_5v"),
};
-/* SAW regulator constraints */
+/* SAW regulator constraints 主板CPU接口电压 */
struct regulator_init_data msm8064_saw_regulator_pdata_8921_s5 =
/* ID vreg_name min_uV max_uV */
- SAW_VREG_INIT(S5, "8921_s5", 850000, 1300000);
+ SAW_VREG_INIT(S5, "8921_s5", 775000, 1300000);
struct regulator_init_data msm8064_saw_regulator_pdata_8921_s6 =
- SAW_VREG_INIT(S6, "8921_s6", 850000, 1300000);
+ SAW_VREG_INIT(S6, "8921_s6", 775000, 1300000);
struct regulator_init_data msm8064_saw_regulator_pdata_8821_s0 =
/* ID vreg_name min_uV max_uV */
- SAW_VREG_INIT(8821_S0, "8821_s0", 850000, 1300000);
+ SAW_VREG_INIT(8821_S0, "8821_s0", 775000, 1300000);
struct regulator_init_data msm8064_saw_regulator_pdata_8821_s1 =
- SAW_VREG_INIT(8821_S1, "8821_s1", 850000, 1300000);
+ SAW_VREG_INIT(8821_S1, "8821_s1", 775000, 1300000);
/* PM8921 regulator constraints */
struct pm8xxx_regulator_platform_data
diff --git a/arch/arm/mach-msm/board-8064.c b/arch/arm/mach-msm/board-8064.c
index c775520..6787caa 100644
--- a/arch/arm/mach-msm/board-8064.c
+++ b/arch/arm/mach-msm/board-8064.c
@@ -103,7 +103,7 @@
#define MSM_ION_MFC_META_SIZE 0x40000 /* 256 Kbytes */
#define MSM_CONTIG_MEM_SIZE 0x65000
#ifdef CONFIG_MSM_IOMMU
-#define MSM_ION_MM_SIZE 0x3800000
+#define MSM_ION_MM_SIZE 0x5C00000
#define MSM_ION_SF_SIZE 0
#define MSM_ION_QSECOM_SIZE 0x780000 /* (7.5MB) */
#define MSM_ION_HEAP_NUM 8
diff --git a/arch/arm/mach-msm/board-aries-gpu.c b/arch/arm/mach-msm/board-aries-gpu.c
index f6b4fff..12e0aee 100644
--- a/arch/arm/mach-msm/board-aries-gpu.c
+++ b/arch/arm/mach-msm/board-aries-gpu.c
@@ -22,6 +22,8 @@
#include "devices.h"
#include "board-aries.h"
+uint32_t max_gpu = 1;
+
#ifdef CONFIG_MSM_DCVS
static struct msm_dcvs_freq_entry grp3d_freq[] = {
{0, 900, 0, 0, 0},
@@ -88,6 +90,7 @@ static struct msm_bus_vectors grp3d_init_vectors[] = {
},
};
+/* gpu带宽，单位mbps */
static struct msm_bus_vectors grp3d_low_vectors[] = {
{
.src = MSM_BUS_MASTER_GRAPHICS_3D,
@@ -221,7 +224,7 @@ static struct kgsl_device_iommu_data kgsl_3d0_iommu_data[] = {
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
.pwrlevel = {
{
- .gpu_freq = 400000000,
+ .gpu_freq = 450000000,
.bus_freq = 4,
.io_fraction = 0,
},
@@ -272,12 +275,28 @@ struct platform_device device_kgsl_3d0 = {
},
};
+/*gpuoc*/
+static int __init read_max_gpu(char *gpu_oc)
+{
+ if (strcmp(gpu_oc, "1") == 0) {
+ max_gpu = 1;
+ } else {
+ max_gpu = 0;
+ }
+ return 0;
+}
+
+__setup("gpu_oc=", read_max_gpu);
+/*end gpuoc*/
+
void __init apq8064_init_gpu(void)
{
unsigned int version = socinfo_get_version();
+ if (max_gpu == 0)
+ kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 400000000;
if (cpu_is_apq8064ab())
- kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 450000000;
+ kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 400000000;
if (SOCINFO_VERSION_MAJOR(version) == 2) {
kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 2, 0, 2);
} else {
diff --git a/arch/arm/mach-msm/board-aries-regulator.c b/arch/arm/mach-msm/board-aries-regulator.c
index cdc67a2..966e45d 100644
--- a/arch/arm/mach-msm/board-aries-regulator.c
+++ b/arch/arm/mach-msm/board-aries-regulator.c
@@ -541,18 +541,18 @@ mpq8064_gpio_regulator_pdata[] __devinitdata = {
SX150X_GPIO(4, 15), "avc_5v"),
};