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rk628_csi_v4l2.c
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rk628_csi_v4l2.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
*
* Author: Dingxian Wen <[email protected]>
*/
#include <linux/clk.h>
#include <linux/compat.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/rk-camera-module.h>
#include <linux/slab.h>
#include <linux/timer.h>
#include <linux/v4l2-dv-timings.h>
#include <linux/version.h>
#include <linux/videodev2.h>
#include <linux/workqueue.h>
#include <linux/rk_hdmirx_class.h>
#include <media/v4l2-controls_rockchip.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-dv-timings.h>
#include <media/v4l2-event.h>
#include <media/v4l2-fwnode.h>
#include <video/videomode.h>
#include "rk628.h"
#include "rk628_combrxphy.h"
#include "rk628_combtxphy.h"
#include "rk628_csi.h"
#include "rk628_cru.h"
#include "rk628_dsi.h"
#include "rk628_hdmirx.h"
#include "rk628_mipi_dphy.h"
static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "debug level (0-3)");
#define DRIVER_VERSION KERNEL_VERSION(0, 0x0, 0x8)
#define RK628_CSI_NAME "rk628-csi"
#define EDID_NUM_BLOCKS_MAX 2
#define EDID_BLOCK_SIZE 128
#define RK628_CSI_LINK_FREQ_LOW 350000000
#define RK628_CSI_LINK_FREQ_HIGH 600000000
#define RK628_CSI_PIXEL_RATE_LOW 400000000
#define RK628_CSI_PIXEL_RATE_HIGH 600000000
#define MIPI_DATARATE_MBPS_LOW 700
#define MIPI_DATARATE_MBPS_HIGH 1250
#define POLL_INTERVAL_MS 1000
#define MODETCLK_CNT_NUM 1000
#define MODETCLK_HZ 49500000
#define RXPHY_CFG_MAX_TIMES 15
#define CSITX_ERR_RETRY_TIMES 3
#define YUV422_8BIT 0x1e
enum tx_mode_type {
CSI_MODE,
DSI_MODE,
};
struct rk628_plat_data {
int bus_fmt;
int tx_mode;
};
struct rk628_csi {
struct device *dev;
struct i2c_client *i2c_client;
struct rk628 *rk628;
struct media_pad pad;
struct v4l2_subdev sd;
struct v4l2_dv_timings src_timings;
struct v4l2_dv_timings timings;
struct v4l2_ctrl_handler hdl;
struct v4l2_ctrl *detect_tx_5v_ctrl;
struct v4l2_ctrl *audio_sampling_rate_ctrl;
struct v4l2_ctrl *audio_present_ctrl;
struct v4l2_ctrl *link_freq;
struct v4l2_ctrl *pixel_rate;
struct gpio_desc *enable_gpio;
struct gpio_desc *reset_gpio;
struct gpio_desc *power_gpio;
struct gpio_desc *plugin_det_gpio;
struct clk *soc_24M;
struct clk *clk_hdmirx_aud;
struct clk *clk_vop;
struct clk *clk_rx_read;
struct delayed_work delayed_work_enable_hotplug;
struct delayed_work delayed_work_res_change;
struct timer_list timer;
struct work_struct work_i2c_poll;
struct mutex confctl_mutex;
const struct rk628_csi_mode *cur_mode;
const char *module_facing;
const char *module_name;
const char *len_name;
u32 module_index;
u8 edid_blocks_written;
u64 lane_mbps;
u8 csi_lanes_in_use;
u32 mbus_fmt_code;
u8 fps;
u32 stream_state;
int hdmirx_irq;
int plugin_irq;
bool nosignal;
bool rxphy_pwron;
bool txphy_pwron;
bool enable_hdcp;
bool scaler_en;
bool hpd_output_inverted;
bool avi_rcv_rdy;
bool vid_ints_en;
bool continues_clk;
struct rk628_hdcp hdcp;
bool i2s_enable_default;
HAUDINFO audio_info;
struct rk628_combtxphy *txphy;
struct rk628_dsi dsi;
const struct rk628_plat_data *plat_data;
struct device *classdev;
};
struct rk628_csi_mode {
u32 width;
u32 height;
struct v4l2_fract max_fps;
u32 hts_def;
u32 vts_def;
u32 exp_def;
};
static const s64 link_freq_menu_items[] = {
RK628_CSI_LINK_FREQ_LOW,
RK628_CSI_LINK_FREQ_HIGH,
};
static const struct v4l2_dv_timings_cap rk628_csi_timings_cap = {
.type = V4L2_DV_BT_656_1120,
/* keep this initialization for compatibility with GCC < 4.4.6 */
.reserved = { 0 },
V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 600000000,
V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED |
V4L2_DV_BT_CAP_REDUCED_BLANKING |
V4L2_DV_BT_CAP_CUSTOM)
};
static u8 edid_init_data[] = {
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
0x49, 0x73, 0x8D, 0x62, 0x00, 0x88, 0x88, 0x88,
0x08, 0x1E, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
0x6E, 0x28, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00,
0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
0x37, 0x34, 0x39, 0x2D, 0x66, 0x48, 0x44, 0x37,
0x32, 0x30, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
0x00, 0x14, 0x78, 0x01, 0xFF, 0x1D, 0x00, 0x0A,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x18,
0x02, 0x03, 0x1A, 0x71, 0x47, 0x5F, 0x90, 0x22,
0x04, 0x11, 0x02, 0x01, 0x23, 0x09, 0x07, 0x01,
0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0C, 0x00,
0x10, 0x00, 0x02, 0x3A, 0x80, 0x18, 0x71, 0x38,
0x2D, 0x40, 0x58, 0x2C, 0x45, 0x00, 0x20, 0xC2,
0x31, 0x00, 0x00, 0x1E, 0x01, 0x1D, 0x00, 0x72,
0x51, 0xD0, 0x1E, 0x20, 0x6E, 0x28, 0x55, 0x00,
0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E, 0x02, 0x3A,
0x80, 0xD0, 0x72, 0x38, 0x2D, 0x40, 0x10, 0x2C,
0x45, 0x80, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E,
0x01, 0x1D, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40,
0x58, 0x2C, 0x45, 0x00, 0xC0, 0x6C, 0x00, 0x00,
0x00, 0x18, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x1C,
0x16, 0x20, 0x58, 0x2C, 0x25, 0x00, 0xC0, 0x6C,
0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC1,
};
static struct rkmodule_csi_dphy_param rk3588_dcphy_param = {
.vendor = PHY_VENDOR_SAMSUNG,
.lp_vol_ref = 0,
.lp_hys_sw = {3, 0, 0, 0},
.lp_escclk_pol_sel = {1, 0, 0, 0},
.skew_data_cal_clk = {0, 3, 3, 3},
.clk_hs_term_sel = 2,
.data_hs_term_sel = {2, 2, 2, 2},
.reserved = {0},
};
static const struct rk628_csi_mode supported_modes[] = {
{
.width = 3840,
.height = 2160,
.max_fps = {
.numerator = 10000,
.denominator = 300000,
},
.hts_def = 4400,
.vts_def = 2250,
}, {
.width = 1920,
.height = 1080,
.max_fps = {
.numerator = 10000,
.denominator = 600000,
},
.hts_def = 2200,
.vts_def = 1125,
}, {
.width = 1280,
.height = 720,
.max_fps = {
.numerator = 10000,
.denominator = 600000,
},
.hts_def = 1650,
.vts_def = 750,
}, {
.width = 720,
.height = 576,
.max_fps = {
.numerator = 10000,
.denominator = 500000,
},
.hts_def = 864,
.vts_def = 625,
}, {
.width = 720,
.height = 480,
.max_fps = {
.numerator = 10000,
.denominator = 600000,
},
.hts_def = 858,
.vts_def = 525,
},
};
static struct v4l2_dv_timings dst_timing = {
.type = V4L2_DV_BT_656_1120,
.bt = {
.interlaced = V4L2_DV_PROGRESSIVE,
.width = 1920,
.height = 1080,
.hfrontporch = 88,
.hsync = 44,
.hbackporch = 148,
.vfrontporch = 4,
.vsync = 5,
.vbackporch = 36,
.pixelclock = 148500000,
},
};
static void rk628_post_process_setup(struct v4l2_subdev *sd);
static void rk628_csi_enable_interrupts(struct v4l2_subdev *sd, bool en);
static int rk628_csi_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
static int rk628_csi_s_dv_timings(struct v4l2_subdev *sd,
struct v4l2_dv_timings *timings);
static int rk628_csi_s_edid(struct v4l2_subdev *sd,
struct v4l2_subdev_edid *edid);
static int mipi_dphy_power_on(struct rk628_csi *csi);
static void mipi_dphy_power_off(struct rk628_csi *csi);
static int rk628_hdmirx_phy_power_on(struct v4l2_subdev *sd);
static int rk628_hdmirx_phy_power_off(struct v4l2_subdev *sd);
static int rk628_hdmirx_phy_setup(struct v4l2_subdev *sd);
static void rk628_csi_format_change(struct v4l2_subdev *sd);
static void enable_stream(struct v4l2_subdev *sd, bool enable);
static void rk628_hdmirx_vid_enable(struct v4l2_subdev *sd, bool en);
static void rk628_csi_set_csi(struct v4l2_subdev *sd);
static void rk628_hdmirx_hpd_ctrl(struct v4l2_subdev *sd, bool en);
static void rk628_hdmirx_controller_reset(struct v4l2_subdev *sd);
static bool rk628_rcv_supported_res(struct v4l2_subdev *sd, u32 width,
u32 height);
static void rk628_dsi_set_scs(struct rk628_csi *csi);
static void rk628_dsi_enable(struct v4l2_subdev *sd);
static inline struct rk628_csi *to_csi(struct v4l2_subdev *sd)
{
return container_of(sd, struct rk628_csi, sd);
}
static bool tx_5v_power_present(struct v4l2_subdev *sd)
{
bool ret;
int val, i, cnt;
struct rk628_csi *csi = to_csi(sd);
/* Direct Mode */
if (!csi->plugin_det_gpio)
return true;
cnt = 0;
for (i = 0; i < 5; i++) {
val = gpiod_get_value(csi->plugin_det_gpio);
if (val > 0)
cnt++;
usleep_range(500, 600);
}
ret = (cnt >= 3) ? true : false;
v4l2_dbg(1, debug, sd, "%s: %d\n", __func__, ret);
return ret;
}
static inline bool no_signal(struct v4l2_subdev *sd)
{
struct rk628_csi *csi = to_csi(sd);
v4l2_dbg(1, debug, sd, "%s no signal:%d\n", __func__, csi->nosignal);
return csi->nosignal;
}
static inline bool audio_present(struct v4l2_subdev *sd)
{
struct rk628_csi *csi = to_csi(sd);
return rk628_hdmirx_audio_present(csi->audio_info);
}
static int get_audio_sampling_rate(struct v4l2_subdev *sd)
{
struct rk628_csi *csi = to_csi(sd);
if (no_signal(sd))
return 0;
return rk628_hdmirx_audio_fs(csi->audio_info);
}
static void rk628_hdmirx_ctrl_enable(struct v4l2_subdev *sd, int en)
{
u32 mask;
struct rk628_csi *csi = to_csi(sd);
if (en) {
/* don't enable audio until N CTS updated */
mask = HDMI_ENABLE_MASK;
v4l2_dbg(1, debug, sd, "%s: %#x %d\n", __func__, mask, en);
rk628_i2c_update_bits(csi->rk628, HDMI_RX_DMI_DISABLE_IF,
mask, HDMI_ENABLE(1) | AUD_ENABLE(1));
} else {
mask = AUD_ENABLE_MASK | HDMI_ENABLE_MASK;
v4l2_dbg(1, debug, sd, "%s: %#x %d\n", __func__, mask, en);
rk628_i2c_update_bits(csi->rk628, HDMI_RX_DMI_DISABLE_IF,
mask, HDMI_ENABLE(0) | AUD_ENABLE(0));
}
}
static int rk628_csi_get_detected_timings(struct v4l2_subdev *sd,
struct v4l2_dv_timings *timings)
{
struct rk628_csi *csi = to_csi(sd);
struct v4l2_bt_timings *bt = &timings->bt;
u32 hact, vact, htotal, vtotal, fps, status;
u32 val;
u32 modetclk_cnt_hs, modetclk_cnt_vs, hs, vs;
u32 hofs_pix, hbp, hfp, vbp, vfp;
u32 tmds_clk, tmdsclk_cnt;
u64 tmp_data;
int retry = 0;
__retry:
memset(timings, 0, sizeof(struct v4l2_dv_timings));
timings->type = V4L2_DV_BT_656_1120;
rk628_i2c_read(csi->rk628, HDMI_RX_SCDC_REGS1, &val);
status = val;
rk628_i2c_read(csi->rk628, HDMI_RX_MD_STS, &val);
bt->interlaced = val & ILACE_STS ?
V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
rk628_i2c_read(csi->rk628, HDMI_RX_MD_HACT_PX, &val);
hact = val & 0xffff;
rk628_i2c_read(csi->rk628, HDMI_RX_MD_VAL, &val);
vact = val & 0xffff;
rk628_i2c_read(csi->rk628, HDMI_RX_MD_HT1, &val);
htotal = (val >> 16) & 0xffff;
rk628_i2c_read(csi->rk628, HDMI_RX_MD_VTL, &val);
vtotal = val & 0xffff;
rk628_i2c_read(csi->rk628, HDMI_RX_MD_HT1, &val);
hofs_pix = val & 0xffff;
rk628_i2c_read(csi->rk628, HDMI_RX_MD_VOL, &val);
vbp = (val & 0xffff) + 1;
rk628_i2c_read(csi->rk628, HDMI_RX_HDMI_CKM_RESULT, &val);
tmdsclk_cnt = val & 0xffff;
tmp_data = tmdsclk_cnt;
tmp_data = ((tmp_data * MODETCLK_HZ) + MODETCLK_CNT_NUM / 2);
do_div(tmp_data, MODETCLK_CNT_NUM);
tmds_clk = tmp_data;
if (!htotal || !vtotal) {
v4l2_err(&csi->sd, "timing err, htotal:%d, vtotal:%d\n",
htotal, vtotal);
if (retry++ < 5)
goto __retry;
goto TIMING_ERR;
}
fps = (tmds_clk + (htotal * vtotal) / 2) / (htotal * vtotal);
rk628_i2c_read(csi->rk628, HDMI_RX_MD_HT0, &val);
modetclk_cnt_hs = val & 0xffff;
hs = (tmdsclk_cnt * modetclk_cnt_hs + MODETCLK_CNT_NUM / 2) /
MODETCLK_CNT_NUM;
rk628_i2c_read(csi->rk628, HDMI_RX_MD_VSC, &val);
modetclk_cnt_vs = val & 0xffff;
vs = (tmdsclk_cnt * modetclk_cnt_vs + MODETCLK_CNT_NUM / 2) /
MODETCLK_CNT_NUM;
vs = (vs + htotal / 2) / htotal;
if ((hofs_pix < hs) || (htotal < (hact + hofs_pix)) ||
(vtotal < (vact + vs + vbp))) {
v4l2_err(sd, "timing err, total:%dx%d, act:%dx%d, hofs:%d, hs:%d, vs:%d, vbp:%d\n",
htotal, vtotal, hact, vact, hofs_pix, hs, vs, vbp);
goto TIMING_ERR;
}
hbp = hofs_pix - hs;
hfp = htotal - hact - hofs_pix;
vfp = vtotal - vact - vs - vbp;
v4l2_dbg(2, debug, sd, "cnt_num:%d, tmds_cnt:%d, hs_cnt:%d, vs_cnt:%d, hofs:%d\n",
MODETCLK_CNT_NUM, tmdsclk_cnt, modetclk_cnt_hs, modetclk_cnt_vs, hofs_pix);
bt->width = hact;
bt->height = vact;
bt->hfrontporch = hfp;
bt->hsync = hs;
bt->hbackporch = hbp;
bt->vfrontporch = vfp;
bt->vsync = vs;
bt->vbackporch = vbp;
bt->pixelclock = htotal * vtotal * fps;
if (bt->interlaced == V4L2_DV_INTERLACED) {
bt->height *= 2;
bt->il_vsync = bt->vsync + 1;
bt->pixelclock /= 2;
}
if (vact == 1080 && vtotal > 1500)
goto __retry;
v4l2_dbg(1, debug, sd, "SCDC_REGS1:%#x, act:%dx%d, total:%dx%d, fps:%d, pixclk:%llu\n",
status, hact, vact, htotal, vtotal, fps, bt->pixelclock);
v4l2_dbg(1, debug, sd, "hfp:%d, hs:%d, hbp:%d, vfp:%d, vs:%d, vbp:%d, interlace:%d\n",
bt->hfrontporch, bt->hsync, bt->hbackporch, bt->vfrontporch, bt->vsync,
bt->vbackporch, bt->interlaced);
csi->src_timings = *timings;
if (csi->scaler_en)
*timings = csi->timings;
return 0;
TIMING_ERR:
return -ENOLCK;
}
static void rk628_hdmirx_config_all(struct v4l2_subdev *sd)
{
int ret;
struct rk628_csi *csi = to_csi(sd);
rk628_hdmirx_controller_setup(csi->rk628);
ret = rk628_hdmirx_phy_setup(sd);
if (ret >= 0) {
rk628_csi_format_change(sd);
csi->nosignal = false;
}
}
static void rk628_csi_delayed_work_enable_hotplug(struct work_struct *work)
{
struct delayed_work *dwork = to_delayed_work(work);
struct rk628_csi *csi = container_of(dwork, struct rk628_csi,
delayed_work_enable_hotplug);
struct v4l2_subdev *sd = &csi->sd;
bool plugin;
mutex_lock(&csi->confctl_mutex);
csi->avi_rcv_rdy = false;
plugin = tx_5v_power_present(sd);
v4l2_ctrl_s_ctrl(csi->detect_tx_5v_ctrl, plugin);
v4l2_dbg(1, debug, sd, "%s: 5v_det:%d\n", __func__, plugin);
if (plugin) {
rk628_csi_enable_interrupts(sd, false);
rk628_hdmirx_audio_setup(csi->audio_info);
rk628_hdmirx_set_hdcp(csi->rk628, &csi->hdcp, csi->enable_hdcp);
rk628_hdmirx_hpd_ctrl(sd, true);
rk628_hdmirx_config_all(sd);
rk628_csi_enable_interrupts(sd, true);
rk628_i2c_update_bits(csi->rk628, GRF_SYSTEM_CON0,
SW_I2S_DATA_OEN_MASK, SW_I2S_DATA_OEN(0));
} else {
rk628_csi_enable_interrupts(sd, false);
enable_stream(sd, false);
cancel_delayed_work(&csi->delayed_work_res_change);
rk628_hdmirx_audio_cancel_work_audio(csi->audio_info, true);
rk628_hdmirx_hpd_ctrl(sd, false);
rk628_hdmirx_phy_power_off(sd);
rk628_hdmirx_controller_reset(sd);
csi->nosignal = true;
}
mutex_unlock(&csi->confctl_mutex);
if (csi->plat_data->tx_mode == DSI_MODE && plugin)
enable_stream(sd, true);
}
static int rk628_check_resulotion_change(struct v4l2_subdev *sd)
{
u32 val;
struct rk628_csi *csi = to_csi(sd);
u32 htotal, vtotal;
u32 old_htotal, old_vtotal;
struct v4l2_bt_timings *bt = &csi->src_timings.bt;
rk628_i2c_read(csi->rk628, HDMI_RX_MD_HT1, &val);
htotal = (val >> 16) & 0xffff;
rk628_i2c_read(csi->rk628, HDMI_RX_MD_VTL, &val);
vtotal = val & 0xffff;
old_htotal = bt->hfrontporch + bt->hsync + bt->width + bt->hbackporch;
old_vtotal = bt->vfrontporch + bt->vsync + bt->height + bt->vbackporch;
v4l2_dbg(1, debug, sd, "new mode: %d x %d\n", htotal, vtotal);
v4l2_dbg(1, debug, sd, "old mode: %d x %d\n", old_htotal, old_vtotal);
if (htotal != old_htotal || vtotal != old_vtotal)
return 1;
return 0;
}
static void rk628_delayed_work_res_change(struct work_struct *work)
{
struct delayed_work *dwork = to_delayed_work(work);
struct rk628_csi *csi = container_of(dwork, struct rk628_csi,
delayed_work_res_change);
struct v4l2_subdev *sd = &csi->sd;
bool plugin;
mutex_lock(&csi->confctl_mutex);
csi->avi_rcv_rdy = false;
plugin = tx_5v_power_present(sd);
v4l2_dbg(1, debug, sd, "%s: 5v_det:%d\n", __func__, plugin);
if (plugin) {
if (rk628_check_resulotion_change(sd)) {
v4l2_dbg(1, debug, sd, "res change, recfg ctrler and phy!\n");
rk628_hdmirx_audio_cancel_work_audio(csi->audio_info, true);
rk628_hdmirx_phy_power_off(sd);
rk628_hdmirx_controller_reset(sd);
rk628_hdmirx_audio_setup(csi->audio_info);
rk628_hdmirx_set_hdcp(csi->rk628, &csi->hdcp, csi->enable_hdcp);
rk628_hdmirx_hpd_ctrl(sd, true);
rk628_hdmirx_config_all(sd);
rk628_csi_enable_interrupts(sd, true);
rk628_i2c_update_bits(csi->rk628, GRF_SYSTEM_CON0,
SW_I2S_DATA_OEN_MASK,
SW_I2S_DATA_OEN(0));
} else {
rk628_csi_format_change(sd);
csi->nosignal = false;
rk628_csi_enable_interrupts(sd, true);
}
}
mutex_unlock(&csi->confctl_mutex);
if (csi->plat_data->tx_mode == DSI_MODE && plugin)
rk628_dsi_enable(sd);
}
static void rk628_hdmirx_hpd_ctrl(struct v4l2_subdev *sd, bool en)
{
u8 en_level, set_level;
struct rk628_csi *csi = to_csi(sd);
v4l2_dbg(1, debug, sd, "%s: %sable, hpd invert:%d\n", __func__,
en ? "en" : "dis", csi->hpd_output_inverted);
en_level = csi->hpd_output_inverted ? 0 : 1;
set_level = en ? en_level : !en_level;
rk628_i2c_update_bits(csi->rk628, HDMI_RX_HDMI_SETUP_CTRL,
HOT_PLUG_DETECT_MASK, HOT_PLUG_DETECT(set_level));
}
static int rk628_csi_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
{
struct rk628_csi *csi = to_csi(sd);
return v4l2_ctrl_s_ctrl(csi->detect_tx_5v_ctrl,
tx_5v_power_present(sd));
}
static int rk628_csi_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
{
struct rk628_csi *csi = to_csi(sd);
return v4l2_ctrl_s_ctrl(csi->audio_sampling_rate_ctrl,
get_audio_sampling_rate(sd));
}
static int rk628_csi_s_ctrl_audio_present(struct v4l2_subdev *sd)
{
struct rk628_csi *csi = to_csi(sd);
return v4l2_ctrl_s_ctrl(csi->audio_present_ctrl,
audio_present(sd));
}
static int rk628_csi_update_controls(struct v4l2_subdev *sd)
{
int ret = 0;
ret |= rk628_csi_s_ctrl_detect_tx_5v(sd);
ret |= rk628_csi_s_ctrl_audio_sampling_rate(sd);
ret |= rk628_csi_s_ctrl_audio_present(sd);
return ret;
}
static void rk62_csi_reset(struct v4l2_subdev *sd)
{
struct rk628_csi *csi = to_csi(sd);
rk628_control_assert(csi->rk628, RGU_CSI);
udelay(10);
rk628_control_deassert(csi->rk628, RGU_CSI);
rk628_i2c_write(csi->rk628, CSITX_SYS_CTRL0_IMD, 0x1);
usleep_range(1000, 1100);
rk628_i2c_write(csi->rk628, CSITX_SYS_CTRL0_IMD, 0x0);
}
static void enable_csitx(struct v4l2_subdev *sd)
{
u32 i, ret, val;
struct rk628_csi *csi = to_csi(sd);
for (i = 0; i < CSITX_ERR_RETRY_TIMES; i++) {
rk628_csi_set_csi(sd);
rk628_i2c_update_bits(csi->rk628, CSITX_CSITX_EN,
DPHY_EN_MASK |
CSITX_EN_MASK,
DPHY_EN(1) |
CSITX_EN(1));
rk628_i2c_write(csi->rk628, CSITX_CONFIG_DONE, CONFIG_DONE_IMD);
msleep(40);
rk628_i2c_write(csi->rk628, CSITX_ERR_INTR_CLR_IMD, 0xffffffff);
rk628_i2c_update_bits(csi->rk628, CSITX_SYS_CTRL1,
BYPASS_SELECT_MASK, BYPASS_SELECT(0));
rk628_i2c_write(csi->rk628, CSITX_CONFIG_DONE, CONFIG_DONE_IMD);
msleep(40);
ret = rk628_i2c_read(csi->rk628, CSITX_ERR_INTR_RAW_STATUS_IMD, &val);
if (!ret && !val)
break;
v4l2_err(sd, "%s csitx err, retry:%d, err status:%#x, ret:%d\n",
__func__, i, val, ret);
}
}
static void rk628_dsi_set_scs(struct rk628_csi *csi)
{
u8 video_fmt;
u32 val;
int avi_rdy;
mutex_lock(&csi->confctl_mutex);
avi_rdy = rk628_is_avi_ready(csi->rk628, csi->avi_rcv_rdy);
mutex_unlock(&csi->confctl_mutex);
rk628_i2c_read(csi->rk628, HDMI_RX_PDEC_AVI_PB, &val);
video_fmt = (val & VIDEO_FORMAT_MASK) >> 5;
v4l2_info(&csi->sd, "%s PDEC_AVI_PB:%#x, video format:%d\n",
__func__, val, video_fmt);
if (video_fmt) {
if (csi->dsi.vid_mode == VIDEO_MODE)
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_Y2R_EN(1) | SW_YUV2VYU_SWP(1));
else
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_Y2R_EN(1) | SW_YUV2VYU_SWP(0));
} else {
if (csi->dsi.vid_mode == VIDEO_MODE)
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_Y2R_EN(0) | SW_YUV2VYU_SWP(1));
else
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_Y2R_EN(0) | SW_YUV2VYU_SWP(0));
}
/* if avi packet is not stable, reset ctrl*/
if (!avi_rdy) {
csi->nosignal = true;
schedule_delayed_work(&csi->delayed_work_enable_hotplug, HZ / 20);
}
}
static void rk628_dsi_enable(struct v4l2_subdev *sd)
{
struct rk628_csi *csi = to_csi(sd);
rk628_post_process_setup(sd);
if (csi->txphy_pwron) {
v4l2_dbg(1, debug, sd,
"%s: txphy already power on, power off\n", __func__);
mipi_dphy_power_off(csi);
csi->txphy_pwron = false;
}
csi->dsi.rk628 = csi->rk628;
csi->dsi.timings = csi->timings;
csi->dsi.lane_mbps = csi->lane_mbps;
rk628_mipi_dsi_power_on(&csi->dsi);
csi->txphy_pwron = true;
v4l2_dbg(2, debug, sd, "%s: txphy power on!\n", __func__);
usleep_range(1000, 1500);
rk628_dsi_set_scs(csi);
}
static void enable_dsitx(struct v4l2_subdev *sd)
{
struct rk628_csi *csi = to_csi(sd);
/* rst for dsi0 */
rk628_control_assert(csi->rk628, RGU_DSI0);
usleep_range(20, 40);
rk628_control_deassert(csi->rk628, RGU_DSI0);
usleep_range(20, 40);
rk628_dsi_enable(sd);
}
static void rk628_dsi_enable_stream(struct v4l2_subdev *sd, bool en)
{
struct rk628_csi *csi = to_csi(sd);
if (en) {
rk628_hdmirx_vid_enable(sd, true);
rk628_i2c_write(csi->rk628, GRF_SCALER_CON0, SCL_EN(1));
rk628_dsi_set_scs(csi);
return;
}
rk628_hdmirx_vid_enable(sd, false);
rk628_i2c_write(csi->rk628, GRF_SCALER_CON0, SCL_EN(0));
}
static void enable_stream(struct v4l2_subdev *sd, bool en)
{
struct rk628_csi *csi = to_csi(sd);
v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, en ? "en" : "dis");
if (en) {
rk628_hdmirx_vid_enable(sd, true);
if (csi->plat_data->tx_mode == DSI_MODE)
enable_dsitx(sd);
else
enable_csitx(sd);
} else {
if (csi->plat_data->tx_mode == CSI_MODE) {
rk628_hdmirx_vid_enable(sd, false);
rk628_i2c_update_bits(csi->rk628, CSITX_CSITX_EN,
DPHY_EN_MASK |
CSITX_EN_MASK,
DPHY_EN(0) |
CSITX_EN(0));
rk628_i2c_write(csi->rk628, CSITX_CONFIG_DONE,
CONFIG_DONE_IMD);
} else {
rk628_dsi_enable_stream(sd, en);
}
}
}
static void rk628_post_process_setup(struct v4l2_subdev *sd)
{
struct rk628_csi *csi = to_csi(sd);
struct v4l2_bt_timings *bt = &csi->src_timings.bt;
struct v4l2_bt_timings *dst_bt = &csi->timings.bt;
struct videomode src, dst;
u64 dst_pclk;
src.hactive = bt->width;
src.hfront_porch = bt->hfrontporch;
src.hsync_len = bt->hsync;
src.hback_porch = bt->hbackporch;
src.vactive = bt->height;
src.vfront_porch = bt->vfrontporch;
src.vsync_len = bt->vsync;
src.vback_porch = bt->vbackporch;
src.pixelclock = bt->pixelclock;
src.flags = 0;
if (bt->interlaced == V4L2_DV_INTERLACED)
src.flags |= DISPLAY_FLAGS_INTERLACED;
if (!src.pixelclock) {
enable_stream(sd, false);
csi->nosignal = true;
schedule_delayed_work(&csi->delayed_work_enable_hotplug, HZ / 20);
return;
}
dst.hactive = dst_bt->width;
dst.hfront_porch = dst_bt->hfrontporch;
dst.hsync_len = dst_bt->hsync;
dst.hback_porch = dst_bt->hbackporch;
dst.vactive = dst_bt->height;
dst.vfront_porch = dst_bt->vfrontporch;
dst.vsync_len = dst_bt->vsync;
dst.vback_porch = dst_bt->vbackporch;
dst.pixelclock = dst_bt->pixelclock;
rk628_post_process_en(csi->rk628, &src, &dst, &dst_pclk);
dst_bt->pixelclock = dst_pclk;
}
static void rk628_csi_set_csi(struct v4l2_subdev *sd)
{
struct rk628_csi *csi = to_csi(sd);
u8 video_fmt;
u8 lanes = csi->csi_lanes_in_use;
u8 lane_num;
u8 dphy_lane_en;
u32 wc_usrdef, val;
int avi_rdy;
lane_num = lanes - 1;
dphy_lane_en = (1 << (lanes + 1)) - 1;
wc_usrdef = csi->timings.bt.width * 2;
rk62_csi_reset(sd);
rk628_post_process_setup(sd);
if (csi->txphy_pwron) {
v4l2_dbg(1, debug, sd,
"%s: txphy already power on, power off\n", __func__);
mipi_dphy_power_off(csi);
csi->txphy_pwron = false;
}
mipi_dphy_power_on(csi);
csi->txphy_pwron = true;
v4l2_dbg(2, debug, sd, "%s: txphy power on!\n", __func__);
usleep_range(1000, 1500);
rk628_i2c_update_bits(csi->rk628, CSITX_CSITX_EN,
VOP_UV_SWAP_MASK |
VOP_YUV422_EN_MASK |
VOP_P2_EN_MASK |
LANE_NUM_MASK |
DPHY_EN_MASK |
CSITX_EN_MASK,
VOP_UV_SWAP(1) |
VOP_YUV422_EN(1) |
VOP_P2_EN(1) |
LANE_NUM(lane_num) |
DPHY_EN(0) |
CSITX_EN(0));
rk628_i2c_update_bits(csi->rk628, CSITX_SYS_CTRL1,
BYPASS_SELECT_MASK,
BYPASS_SELECT(1));
rk628_i2c_write(csi->rk628, CSITX_CONFIG_DONE, CONFIG_DONE_IMD);
rk628_i2c_write(csi->rk628, CSITX_SYS_CTRL2, VOP_WHOLE_FRM_EN | VSYNC_ENABLE);
if (csi->continues_clk)
rk628_i2c_update_bits(csi->rk628, CSITX_SYS_CTRL3_IMD,
CONT_MODE_CLK_CLR_MASK |
CONT_MODE_CLK_SET_MASK |
NON_CONTINUOUS_MODE_MASK,
CONT_MODE_CLK_CLR(0) |
CONT_MODE_CLK_SET(1) |
NON_CONTINUOUS_MODE(0));
else
rk628_i2c_update_bits(csi->rk628, CSITX_SYS_CTRL3_IMD,
CONT_MODE_CLK_CLR_MASK |
CONT_MODE_CLK_SET_MASK |
NON_CONTINUOUS_MODE_MASK,
CONT_MODE_CLK_CLR(0) |
CONT_MODE_CLK_SET(0) |
NON_CONTINUOUS_MODE(1));
rk628_i2c_write(csi->rk628, CSITX_VOP_PATH_CTRL,
VOP_WC_USERDEFINE(wc_usrdef) |
VOP_DT_USERDEFINE(YUV422_8BIT) |
VOP_PIXEL_FORMAT(0) |
VOP_WC_USERDEFINE_EN(1) |
VOP_DT_USERDEFINE_EN(1) |
VOP_PATH_EN(1));
rk628_i2c_update_bits(csi->rk628, CSITX_DPHY_CTRL,
CSI_DPHY_EN_MASK,
CSI_DPHY_EN(dphy_lane_en));
rk628_i2c_write(csi->rk628, CSITX_CONFIG_DONE, CONFIG_DONE_IMD);
v4l2_dbg(1, debug, sd, "%s csi cofig done\n", __func__);
mutex_lock(&csi->confctl_mutex);
avi_rdy = rk628_is_avi_ready(csi->rk628, csi->avi_rcv_rdy);
mutex_unlock(&csi->confctl_mutex);
rk628_i2c_read(csi->rk628, HDMI_RX_PDEC_AVI_PB, &val);
video_fmt = (val & VIDEO_FORMAT_MASK) >> 5;
v4l2_dbg(1, debug, &csi->sd, "%s PDEC_AVI_PB:%#x, video format:%d\n",
__func__, val, video_fmt);
if (video_fmt) {
/* yuv data: cfg SW_YUV2VYU_SWP */
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_YUV2VYU_SWP(1) |
SW_R2Y_EN(0));
} else {
/* rgb data: cfg SW_R2Y_EN */
rk628_i2c_write(csi->rk628, GRF_CSC_CTRL_CON,
SW_YUV2VYU_SWP(0) |
SW_R2Y_EN(1));
}
/* if avi packet is not stable, reset ctrl*/
if (!avi_rdy) {
csi->nosignal = true;
schedule_delayed_work(&csi->delayed_work_enable_hotplug, HZ / 20);
}
}
static int rk628_hdmirx_phy_power_on(struct v4l2_subdev *sd)
{
struct rk628_csi *csi = to_csi(sd);
int ret, f;
/* Bit31 is used to distinguish HDMI cable mode and direct connection
* mode in the rk628_combrxphy driver.
* Bit31: 0 -direct connection mode;
* 1 -cable mode;
* The cable mode is to know the input clock frequency through cdr_mode
* in the rk628_combrxphy driver, and the cable mode supports up to
* 297M, so 297M is passed uniformly here.
*/
f = 297000 | BIT(31);
if (csi->rxphy_pwron) {
v4l2_dbg(1, debug, sd, "rxphy already power on, power off!\n");
ret = rk628_rxphy_power_off(csi->rk628);
if (ret)
v4l2_err(sd, "hdmi rxphy power off failed!\n");
else
csi->rxphy_pwron = false;
usleep_range(100, 110);
}
if (csi->rxphy_pwron == false) {
rk628_hdmirx_ctrl_enable(sd, 0);
ret = rk628_rxphy_power_on(csi->rk628, f);
if (ret) {
csi->rxphy_pwron = false;
v4l2_err(sd, "hdmi rxphy power on failed\n");
} else {
csi->rxphy_pwron = true;
}
rk628_hdmirx_ctrl_enable(sd, 1);
msleep(100);
}
return ret;
}
static int rk628_hdmirx_phy_power_off(struct v4l2_subdev *sd)
{
struct rk628_csi *csi = to_csi(sd);
if (csi->rxphy_pwron) {
v4l2_dbg(1, debug, sd, "rxphy power off!\n");
rk628_rxphy_power_off(csi->rk628);
csi->rxphy_pwron = false;
}
usleep_range(100, 100);
return 0;
}