From 99b1a7606a6a702c67d12236bb71f5e1700a51d3 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Thu, 23 Feb 2023 13:19:03 -0500 Subject: [PATCH 01/13] Capstone auto-sync branch as subprocject. --- meson.build | 6 ++++++ meson_options.txt | 2 +- subprojects/capstone-auto-sync.wrap | 5 +++++ 3 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 subprojects/capstone-auto-sync.wrap diff --git a/meson.build b/meson.build index acf9caa21c9..588886e1440 100644 --- a/meson.build +++ b/meson.build @@ -210,6 +210,12 @@ if not capstone_dep.found() error('Subprojects are not updated. Please run `git clean -dxff subprojects/` to delete all local subprojects directories. If you want to compile against current subprojects then set option `subprojects_check=false`.') endif capstone_proj = subproject('capstone-v4', default_options: ['default_library=static']) + elif capstone_version == 'auto-sync' + r = run_command(py3_exe, check_meson_subproject_py, 'capstone-auto-sync', check: false) + if r.returncode() == 1 and get_option('subprojects_check') + error('Subprojects are not updated. Please run `git clean -dxff subprojects/` to delete all local subprojects directories. If you want to compile against current subprojects then set option `subprojects_check=false`.') + endif + capstone_proj = subproject('capstone-auto-sync', default_options: ['default_library=static']) else error('Wrong capstone version selected. Please use one of the supported versions.') endif diff --git a/meson_options.txt b/meson_options.txt index 7e586136509..5cbcf245570 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -19,7 +19,7 @@ option('rizin_bindings', type: 'string', value: '', description: 'Path where riz option('checks_level', type: 'integer', value: 9999, description: 'Value between 0 and 3 to enable different level of assert (see RZ_CHECKS_LEVEL). By default its value depends on buildtype (2 on debug, 1 on release).') option('use_sys_capstone', type: 'feature', value: 'disabled') -option('use_capstone_version', type: 'combo', choices: ['v3', 'v4', 'next', 'bundled'], value: 'bundled', description: 'Specify which version of capstone to use') +option('use_capstone_version', type: 'combo', choices: ['v3', 'v4', 'next', 'bundled', 'auto-sync'], value: 'bundled', description: 'Specify which version of capstone to use') option('use_sys_magic', type: 'feature', value: 'disabled') option('use_sys_libzip', type: 'feature', value: 'disabled') option('use_sys_libzip_openssl', type: 'boolean', value: false, description: 'Whether to use or not system openssl dependency to build libzip') diff --git a/subprojects/capstone-auto-sync.wrap b/subprojects/capstone-auto-sync.wrap new file mode 100644 index 00000000000..cf4a7c05abf --- /dev/null +++ b/subprojects/capstone-auto-sync.wrap @@ -0,0 +1,5 @@ +[wrap-git] +url = https://github.com/Rot127/capstone.git +revision = auto-sync +directory = capstone-auto-sync +depth = 1 From d5d20b10696765fa57dbe3a445cc677d3bea8f30 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Thu, 23 Feb 2023 13:31:23 -0500 Subject: [PATCH 02/13] Update enum names. --- librz/analysis/p/analysis_arm_cs.c | 13 +++++++------ librz/asm/p/asm_arm_cs.c | 7 +++---- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index adf21984b7b..d3d5fa5e2da 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -1028,21 +1028,22 @@ static void anop32(RzAnalysis *a, csh handle, RzAnalysisOp *op, cs_insn *insn, b } op->cycles = 1; /* grab family */ - if (cs_insn_group(handle, insn, ARM_GRP_CRYPTO)) { + if (cs_insn_group(handle, insn, ARM_FEATURE_HasAES)) { op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; - } else if (cs_insn_group(handle, insn, ARM_GRP_CRC)) { + } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasCRC)) { op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; #if CS_API_MAJOR >= 4 } else if (cs_insn_group(handle, insn, ARM_GRP_PRIVILEGE)) { op->family = RZ_ANALYSIS_OP_FAMILY_PRIV; - } else if (cs_insn_group(handle, insn, ARM_GRP_VIRTUALIZATION)) { + } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasVirtualization)) { op->family = RZ_ANALYSIS_OP_FAMILY_VIRT; #endif - } else if (cs_insn_group(handle, insn, ARM_GRP_NEON)) { + } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasNEON)) { op->family = RZ_ANALYSIS_OP_FAMILY_MMX; - } else if (cs_insn_group(handle, insn, ARM_GRP_FPARMV8)) { + } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasFPARMv8)) { op->family = RZ_ANALYSIS_OP_FAMILY_FPU; - } else if (cs_insn_group(handle, insn, ARM_GRP_THUMB2DSP)) { + } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasDSP) && + cs_insn_group(handle, insn, ARM_FEATURE_HasDSP)) { op->family = RZ_ANALYSIS_OP_FAMILY_MMX; } else { op->family = RZ_ANALYSIS_OP_FAMILY_CPU; diff --git a/librz/asm/p/asm_arm_cs.c b/librz/asm/p/asm_arm_cs.c index 5b614dd066a..f274c817d83 100644 --- a/librz/asm/p/asm_arm_cs.c +++ b/librz/asm/p/asm_arm_cs.c @@ -27,10 +27,9 @@ static bool check_features(RzAsm *a, cs_insn *insn) { for (i = 0; i < insn->detail->groups_count; i++) { int id = insn->detail->groups[i]; switch (id) { - case ARM_GRP_ARM: - case ARM_GRP_THUMB: - case ARM_GRP_THUMB1ONLY: - case ARM_GRP_THUMB2: + case ARM_FEATURE_IsARM: + case ARM_FEATURE_IsThumb: + case ARM_FEATURE_IsThumb2: continue; default: if (id < 128) { From b8d5c0fa1666e4aa95635c2a241bc399352c5bf9 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Thu, 23 Feb 2023 14:20:50 -0500 Subject: [PATCH 03/13] Use `auto-sync` capstone branch as default for build. --- meson_options.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meson_options.txt b/meson_options.txt index 5cbcf245570..341929e02a1 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -19,7 +19,7 @@ option('rizin_bindings', type: 'string', value: '', description: 'Path where riz option('checks_level', type: 'integer', value: 9999, description: 'Value between 0 and 3 to enable different level of assert (see RZ_CHECKS_LEVEL). By default its value depends on buildtype (2 on debug, 1 on release).') option('use_sys_capstone', type: 'feature', value: 'disabled') -option('use_capstone_version', type: 'combo', choices: ['v3', 'v4', 'next', 'bundled', 'auto-sync'], value: 'bundled', description: 'Specify which version of capstone to use') +option('use_capstone_version', type: 'combo', choices: ['v3', 'v4', 'next', 'bundled', 'auto-sync'], value: 'auto-sync', description: 'Specify which version of capstone to use') option('use_sys_magic', type: 'feature', value: 'disabled') option('use_sys_libzip', type: 'feature', value: 'disabled') option('use_sys_libzip_openssl', type: 'boolean', value: false, description: 'Whether to use or not system openssl dependency to build libzip') From bf8a67b8f3516120ec6c56aea4a409b189588bdc Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sun, 26 Feb 2023 23:15:21 -0500 Subject: [PATCH 04/13] Add TODO comment. --- librz/analysis/p/analysis_arm_cs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index d3d5fa5e2da..6c2d963b9a1 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -1771,6 +1771,7 @@ static int analysis_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *bu } else { patch_capstone_bugs(insn, a->bits, a->big_endian); if (mask & RZ_ANALYSIS_OP_MASK_DISASM) { + // TODO Remove after Capstone auto-sync update. op->mnemonic = rz_str_newf("%s%s%s", insn->mnemonic, insn->op_str[0] ? " " : "", From ed05be2a07e9782c1679d231dd4153e0a777579b Mon Sep 17 00:00:00 2001 From: Rot127 Date: Mon, 27 Feb 2023 20:18:10 -0500 Subject: [PATCH 05/13] Rename register alias to raw name. --- test/unit/test_tokens.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/unit/test_tokens.c b/test/unit/test_tokens.c index f7c20ef2099..20f98f6a21e 100644 --- a/test/unit/test_tokens.c +++ b/test/unit/test_tokens.c @@ -402,7 +402,7 @@ static bool test_rz_colorize_generic_1(void) { RzStrBuf *colored_asm = rz_asm_colorize_asm_str(&asmop->buf_asm, p, rz_asm_get_parse_param(a->reg, anaop->type), asmop->asm_toks); - RzStrBuf *expected = rz_strbuf_new("\x1b[33madc.w\x1b[0m\x1b[37m \x1b[0m\x1b[36mr8\x1b[0m\x1b[37m, \x1b[0m\x1b[36msb\x1b[0m\x1b[37m, \x1b[0m\x1b[36msl\x1b[0m\x1b[37m, \x1b[0m\x1b[37mlsl\x1b[0m\x1b[37m \x1b[0m\x1b[33m31\x1b[0m"); + RzStrBuf *expected = rz_strbuf_new("\x1b[33madc.w\x1b[0m\x1b[37m \x1b[0m\x1b[36mr8\x1b[0m\x1b[37m, \x1b[0m\x1b[36mr9\x1b[0m\x1b[37m, \x1b[0m\x1b[36mr10\x1b[0m\x1b[37m, \x1b[0m\x1b[37mlsl\x1b[0m\x1b[37m \x1b[0m\x1b[33m0x1f\x1b[0m"); char err_msg[2048]; snprintf(err_msg, sizeof(err_msg), "Colors of \"%s\" are incorrect. Should be \"%s\"\n.", rz_strbuf_get(colored_asm), rz_strbuf_get(expected)); mu_assert_true(rz_strbuf_equals(colored_asm, expected), err_msg); From 5c5f22f5cb2499dae57b0fc9f64edc9aa52be690 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Thu, 13 Apr 2023 10:39:09 -0500 Subject: [PATCH 06/13] Replace removed enum value. --- librz/analysis/p/analysis_arm_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index 6c2d963b9a1..e21aade485a 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -291,7 +291,7 @@ static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) { if (x->cc != ARM_CC_INVALID && x->cc != ARM_CC_AL) { pj_ks(pj, "cc", cc_name(x->cc)); } - if (x->mem_barrier != ARM_MB_INVALID) { + if (x->mem_barrier != ARM_MB_RESERVED_0) { pj_ki(pj, "mem_barrier", x->mem_barrier - 1); } pj_end(pj); From cf2054a4402a6254100220f85e55e8bc0add6571 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Thu, 23 Feb 2023 13:19:03 -0500 Subject: [PATCH 07/13] Capstone auto-sync branch as subprocject. --- meson.build | 6 ++++++ meson_options.txt | 2 +- subprojects/capstone-auto-sync.wrap | 5 +++++ 3 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 subprojects/capstone-auto-sync.wrap diff --git a/meson.build b/meson.build index 83c56bbc6e4..f0a9dc824d8 100644 --- a/meson.build +++ b/meson.build @@ -210,6 +210,12 @@ if not capstone_dep.found() error('Subprojects are not updated. Please run `git clean -dxff subprojects/` to delete all local subprojects directories. If you want to compile against current subprojects then set option `subprojects_check=false`.') endif capstone_proj = subproject('capstone-v4', default_options: ['default_library=static']) + elif capstone_version == 'auto-sync' + r = run_command(py3_exe, check_meson_subproject_py, 'capstone-auto-sync', check: false) + if r.returncode() == 1 and get_option('subprojects_check') + error('Subprojects are not updated. Please run `git clean -dxff subprojects/` to delete all local subprojects directories. If you want to compile against current subprojects then set option `subprojects_check=false`.') + endif + capstone_proj = subproject('capstone-auto-sync', default_options: ['default_library=static']) else error('Wrong capstone version selected. Please use one of the supported versions.') endif diff --git a/meson_options.txt b/meson_options.txt index 7e586136509..5cbcf245570 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -19,7 +19,7 @@ option('rizin_bindings', type: 'string', value: '', description: 'Path where riz option('checks_level', type: 'integer', value: 9999, description: 'Value between 0 and 3 to enable different level of assert (see RZ_CHECKS_LEVEL). By default its value depends on buildtype (2 on debug, 1 on release).') option('use_sys_capstone', type: 'feature', value: 'disabled') -option('use_capstone_version', type: 'combo', choices: ['v3', 'v4', 'next', 'bundled'], value: 'bundled', description: 'Specify which version of capstone to use') +option('use_capstone_version', type: 'combo', choices: ['v3', 'v4', 'next', 'bundled', 'auto-sync'], value: 'bundled', description: 'Specify which version of capstone to use') option('use_sys_magic', type: 'feature', value: 'disabled') option('use_sys_libzip', type: 'feature', value: 'disabled') option('use_sys_libzip_openssl', type: 'boolean', value: false, description: 'Whether to use or not system openssl dependency to build libzip') diff --git a/subprojects/capstone-auto-sync.wrap b/subprojects/capstone-auto-sync.wrap new file mode 100644 index 00000000000..cf4a7c05abf --- /dev/null +++ b/subprojects/capstone-auto-sync.wrap @@ -0,0 +1,5 @@ +[wrap-git] +url = https://github.com/Rot127/capstone.git +revision = auto-sync +directory = capstone-auto-sync +depth = 1 From 2ac340d2cd6614749710fbbf64e64b112c84d6f5 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Thu, 23 Feb 2023 13:31:23 -0500 Subject: [PATCH 08/13] Update enum names. --- librz/analysis/p/analysis_arm_cs.c | 13 +++++++------ librz/asm/p/asm_arm_cs.c | 7 +++---- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index adf21984b7b..d3d5fa5e2da 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -1028,21 +1028,22 @@ static void anop32(RzAnalysis *a, csh handle, RzAnalysisOp *op, cs_insn *insn, b } op->cycles = 1; /* grab family */ - if (cs_insn_group(handle, insn, ARM_GRP_CRYPTO)) { + if (cs_insn_group(handle, insn, ARM_FEATURE_HasAES)) { op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; - } else if (cs_insn_group(handle, insn, ARM_GRP_CRC)) { + } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasCRC)) { op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO; #if CS_API_MAJOR >= 4 } else if (cs_insn_group(handle, insn, ARM_GRP_PRIVILEGE)) { op->family = RZ_ANALYSIS_OP_FAMILY_PRIV; - } else if (cs_insn_group(handle, insn, ARM_GRP_VIRTUALIZATION)) { + } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasVirtualization)) { op->family = RZ_ANALYSIS_OP_FAMILY_VIRT; #endif - } else if (cs_insn_group(handle, insn, ARM_GRP_NEON)) { + } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasNEON)) { op->family = RZ_ANALYSIS_OP_FAMILY_MMX; - } else if (cs_insn_group(handle, insn, ARM_GRP_FPARMV8)) { + } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasFPARMv8)) { op->family = RZ_ANALYSIS_OP_FAMILY_FPU; - } else if (cs_insn_group(handle, insn, ARM_GRP_THUMB2DSP)) { + } else if (cs_insn_group(handle, insn, ARM_FEATURE_HasDSP) && + cs_insn_group(handle, insn, ARM_FEATURE_HasDSP)) { op->family = RZ_ANALYSIS_OP_FAMILY_MMX; } else { op->family = RZ_ANALYSIS_OP_FAMILY_CPU; diff --git a/librz/asm/p/asm_arm_cs.c b/librz/asm/p/asm_arm_cs.c index 5b614dd066a..f274c817d83 100644 --- a/librz/asm/p/asm_arm_cs.c +++ b/librz/asm/p/asm_arm_cs.c @@ -27,10 +27,9 @@ static bool check_features(RzAsm *a, cs_insn *insn) { for (i = 0; i < insn->detail->groups_count; i++) { int id = insn->detail->groups[i]; switch (id) { - case ARM_GRP_ARM: - case ARM_GRP_THUMB: - case ARM_GRP_THUMB1ONLY: - case ARM_GRP_THUMB2: + case ARM_FEATURE_IsARM: + case ARM_FEATURE_IsThumb: + case ARM_FEATURE_IsThumb2: continue; default: if (id < 128) { From 2ad90a0b61c9e1d9cd7abaeef5adfbdc1b6beded Mon Sep 17 00:00:00 2001 From: Rot127 Date: Thu, 23 Feb 2023 14:20:50 -0500 Subject: [PATCH 09/13] Use `auto-sync` capstone branch as default for build. --- meson_options.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meson_options.txt b/meson_options.txt index 5cbcf245570..341929e02a1 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -19,7 +19,7 @@ option('rizin_bindings', type: 'string', value: '', description: 'Path where riz option('checks_level', type: 'integer', value: 9999, description: 'Value between 0 and 3 to enable different level of assert (see RZ_CHECKS_LEVEL). By default its value depends on buildtype (2 on debug, 1 on release).') option('use_sys_capstone', type: 'feature', value: 'disabled') -option('use_capstone_version', type: 'combo', choices: ['v3', 'v4', 'next', 'bundled', 'auto-sync'], value: 'bundled', description: 'Specify which version of capstone to use') +option('use_capstone_version', type: 'combo', choices: ['v3', 'v4', 'next', 'bundled', 'auto-sync'], value: 'auto-sync', description: 'Specify which version of capstone to use') option('use_sys_magic', type: 'feature', value: 'disabled') option('use_sys_libzip', type: 'feature', value: 'disabled') option('use_sys_libzip_openssl', type: 'boolean', value: false, description: 'Whether to use or not system openssl dependency to build libzip') From f5526350e97e13536922dc74189fa498a1203600 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sun, 26 Feb 2023 23:15:21 -0500 Subject: [PATCH 10/13] Add TODO comment. --- librz/analysis/p/analysis_arm_cs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index d3d5fa5e2da..6c2d963b9a1 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -1771,6 +1771,7 @@ static int analysis_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *bu } else { patch_capstone_bugs(insn, a->bits, a->big_endian); if (mask & RZ_ANALYSIS_OP_MASK_DISASM) { + // TODO Remove after Capstone auto-sync update. op->mnemonic = rz_str_newf("%s%s%s", insn->mnemonic, insn->op_str[0] ? " " : "", From 488c406e6da1094cf1d6326b30b769b175bcdb5c Mon Sep 17 00:00:00 2001 From: Rot127 Date: Mon, 27 Feb 2023 20:18:10 -0500 Subject: [PATCH 11/13] Rename register alias to raw name. --- test/unit/test_tokens.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/unit/test_tokens.c b/test/unit/test_tokens.c index f7c20ef2099..20f98f6a21e 100644 --- a/test/unit/test_tokens.c +++ b/test/unit/test_tokens.c @@ -402,7 +402,7 @@ static bool test_rz_colorize_generic_1(void) { RzStrBuf *colored_asm = rz_asm_colorize_asm_str(&asmop->buf_asm, p, rz_asm_get_parse_param(a->reg, anaop->type), asmop->asm_toks); - RzStrBuf *expected = rz_strbuf_new("\x1b[33madc.w\x1b[0m\x1b[37m \x1b[0m\x1b[36mr8\x1b[0m\x1b[37m, \x1b[0m\x1b[36msb\x1b[0m\x1b[37m, \x1b[0m\x1b[36msl\x1b[0m\x1b[37m, \x1b[0m\x1b[37mlsl\x1b[0m\x1b[37m \x1b[0m\x1b[33m31\x1b[0m"); + RzStrBuf *expected = rz_strbuf_new("\x1b[33madc.w\x1b[0m\x1b[37m \x1b[0m\x1b[36mr8\x1b[0m\x1b[37m, \x1b[0m\x1b[36mr9\x1b[0m\x1b[37m, \x1b[0m\x1b[36mr10\x1b[0m\x1b[37m, \x1b[0m\x1b[37mlsl\x1b[0m\x1b[37m \x1b[0m\x1b[33m0x1f\x1b[0m"); char err_msg[2048]; snprintf(err_msg, sizeof(err_msg), "Colors of \"%s\" are incorrect. Should be \"%s\"\n.", rz_strbuf_get(colored_asm), rz_strbuf_get(expected)); mu_assert_true(rz_strbuf_equals(colored_asm, expected), err_msg); From 87bffaaf3f3284db3ba5672b3d9b623c6c322f1e Mon Sep 17 00:00:00 2001 From: Rot127 Date: Thu, 13 Apr 2023 10:39:09 -0500 Subject: [PATCH 12/13] Replace removed enum value. --- librz/analysis/p/analysis_arm_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index 6c2d963b9a1..e21aade485a 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -291,7 +291,7 @@ static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) { if (x->cc != ARM_CC_INVALID && x->cc != ARM_CC_AL) { pj_ks(pj, "cc", cc_name(x->cc)); } - if (x->mem_barrier != ARM_MB_INVALID) { + if (x->mem_barrier != ARM_MB_RESERVED_0) { pj_ki(pj, "mem_barrier", x->mem_barrier - 1); } pj_end(pj); From 35dee0748003621fa5fa86ba8f255e9455dae490 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sat, 6 May 2023 11:21:23 -0500 Subject: [PATCH 13/13] Fix build errors for recent CS auto-sync. --- librz/analysis/arch/arm/arm_accessors32.h | 2 +- librz/analysis/arch/arm/arm_esil32.c | 60 ++++++++-------- librz/analysis/arch/arm/arm_il32.c | 53 +++++++------- librz/analysis/p/analysis_arm_cs.c | 87 +++++++---------------- librz/asm/p/asm_arm_cs.c | 37 +--------- 5 files changed, 83 insertions(+), 156 deletions(-) diff --git a/librz/analysis/arch/arm/arm_accessors32.h b/librz/analysis/arch/arm/arm_accessors32.h index 81ebdd4b350..f86c22aa043 100644 --- a/librz/analysis/arch/arm/arm_accessors32.h +++ b/librz/analysis/arch/arm/arm_accessors32.h @@ -33,6 +33,6 @@ #define SHIFTTYPE(x) insn->detail->arm.operands[x].shift.type #define SHIFTVALUE(x) insn->detail->arm.operands[x].shift.value -#define ISWRITEBACK32() insn->detail->arm.writeback +#define ISWRITEBACK32() insn->detail->writeback #define ISPREINDEX32() (((OPCOUNT() == 2) && (ISMEM(1)) && (ISWRITEBACK32())) || ((OPCOUNT() == 3) && (ISMEM(2)) && (ISWRITEBACK32()))) #define ISPOSTINDEX32() (((OPCOUNT() == 3) && (ISIMM(2) || ISREG(2)) && (ISWRITEBACK32())) || ((OPCOUNT() == 4) && (ISIMM(3) || ISREG(3)) && (ISWRITEBACK32()))) diff --git a/librz/analysis/arch/arm/arm_esil32.c b/librz/analysis/arch/arm/arm_esil32.c index 65a755b23fd..2f354a61277 100644 --- a/librz/analysis/arch/arm/arm_esil32.c +++ b/librz/analysis/arch/arm/arm_esil32.c @@ -66,65 +66,65 @@ RZ_IPI const char *rz_arm_cs_esil_prefix_cond(RzAnalysisOp *op, int cond_type) { close_cond[1] = ",}"; int close_type = 0; switch (cond_type) { - case ARM_CC_EQ: + case ARMCC_EQ: close_type = 1; rz_strbuf_setf(&op->esil, "zf,?{,"); break; - case ARM_CC_NE: + case ARMCC_NE: close_type = 1; rz_strbuf_setf(&op->esil, "zf,!,?{,"); break; - case ARM_CC_HS: + case ARMCC_HS: close_type = 1; rz_strbuf_setf(&op->esil, "cf,?{,"); break; - case ARM_CC_LO: + case ARMCC_LO: close_type = 1; rz_strbuf_setf(&op->esil, "cf,!,?{,"); break; - case ARM_CC_MI: + case ARMCC_MI: close_type = 1; rz_strbuf_setf(&op->esil, "nf,?{,"); break; - case ARM_CC_PL: + case ARMCC_PL: close_type = 1; rz_strbuf_setf(&op->esil, "nf,!,?{,"); break; - case ARM_CC_VS: + case ARMCC_VS: close_type = 1; rz_strbuf_setf(&op->esil, "vf,?{,"); break; - case ARM_CC_VC: + case ARMCC_VC: close_type = 1; rz_strbuf_setf(&op->esil, "vf,!,?{,"); break; - case ARM_CC_HI: + case ARMCC_HI: close_type = 1; rz_strbuf_setf(&op->esil, "cf,zf,!,&,?{,"); break; - case ARM_CC_LS: + case ARMCC_LS: close_type = 1; rz_strbuf_setf(&op->esil, "cf,!,zf,|,?{,"); break; - case ARM_CC_GE: + case ARMCC_GE: close_type = 1; rz_strbuf_setf(&op->esil, "nf,vf,^,!,?{,"); break; - case ARM_CC_LT: + case ARMCC_LT: close_type = 1; rz_strbuf_setf(&op->esil, "nf,vf,^,?{,"); break; - case ARM_CC_GT: + case ARMCC_GT: // zf == 0 && nf == vf close_type = 1; rz_strbuf_setf(&op->esil, "zf,!,nf,vf,^,!,&,?{,"); break; - case ARM_CC_LE: + case ARMCC_LE: // zf == 1 || nf != vf close_type = 1; rz_strbuf_setf(&op->esil, "zf,nf,vf,^,|,?{,"); break; - case ARM_CC_AL: + case ARMCC_AL: // always executed break; default: @@ -383,7 +383,7 @@ PUSH { r4, r5, r6, r7, lr } rz_strbuf_appendf(&op->esil, "%s,%s,%d,+,=[4],", REG(i), ARG(0), (i + offset) * 4); } - if (insn->detail->arm.writeback == true) { // writeback, reg should be incremented + if (insn->detail->writeback == true) { // writeback, reg should be incremented rz_strbuf_appendf(&op->esil, "%d,%s,+=,", direction * (insn->detail->arm.op_count - 1) * 4, ARG(0)); } @@ -398,7 +398,7 @@ PUSH { r4, r5, r6, r7, lr } width += REGSIZE32(i); } // increment if writeback - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { rz_strbuf_appendf(&op->esil, "%d,%s,+=,", width, ARG(0)); } break; @@ -422,7 +422,7 @@ PUSH { r4, r5, r6, r7, lr } width += REGSIZE32(i); } // increment if writeback - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { rz_strbuf_appendf(&op->esil, "%d,%s,+=,", width, ARG(0)); } break; @@ -481,7 +481,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= for (i = 1; i < insn->detail->arm.op_count; i++) { rz_strbuf_appendf(&op->esil, "%s,%d,+,[4],%s,=,", ARG(0), (i + offset) * 4, REG(i)); } - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { rz_strbuf_appendf(&op->esil, "%d,%s,+=,", direction * (insn->detail->arm.op_count - 1) * 4, ARG(0)); } @@ -544,7 +544,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= disp = disp >= 0 ? disp : -disp; rz_strbuf_appendf(&op->esil, "%s,0x%x,%s,%c,0xffffffff,&,=[%d]", REG(0), disp, MEMBASE(1), sign, str_ldr_bytes); - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { rz_strbuf_appendf(&op->esil, ",%d,%s,%c,%s,=", disp, MEMBASE(1), sign, MEMBASE(1)); } @@ -555,7 +555,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= case ARM_SFT_LSL: rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,<<,+,0xffffffff,&,=[%d]", REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes); - if (insn->detail->arm.writeback) { // e.g. 'str r2, [r3, r1, lsl 4]!' + if (insn->detail->writeback) { // e.g. 'str r2, [r3, r1, lsl 4]!' rz_strbuf_appendf(&op->esil, ",%s,%d,%s,<<,+,%s,=", MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1)); } @@ -563,7 +563,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= case ARM_SFT_LSR: rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,>>,+,0xffffffff,&,=[%d]", REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes); - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { rz_strbuf_appendf(&op->esil, ",%s,%d,%s,>>,+,%s,=", MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1)); } @@ -571,7 +571,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= case ARM_SFT_ASR: rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,>>>>,+,0xffffffff,&,=[%d]", REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes); - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { rz_strbuf_appendf(&op->esil, ",%s,%d,%s,>>>>,+,%s,=", MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1)); } @@ -579,7 +579,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= case ARM_SFT_ROR: rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,>>>,+,0xffffffff,&,=[%d]", REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes); - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { rz_strbuf_appendf(&op->esil, ",%s,%d,%s,>>>,+,%s,=", MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1)); } @@ -594,7 +594,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= } else { // No shift rz_strbuf_appendf(&op->esil, "%s,%s,%s,+,0xffffffff,&,=[%d]", REG(0), MEMINDEX(1), MEMBASE(1), str_ldr_bytes); - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { rz_strbuf_appendf(&op->esil, ",%s,%s,+,%s,=", MEMINDEX(1), MEMBASE(1), MEMBASE(1)); } @@ -644,7 +644,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= disp = disp >= 0 ? disp : -disp; rz_strbuf_appendf(&op->esil, "%s,%d,%s,%c,0xffffffff,&,=[4],%s,4,%d,+,%s,%c,0xffffffff,&,=[4]", REG(0), disp, MEMBASE(2), sign, REG(1), disp, MEMBASE(2), sign); - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { rz_strbuf_appendf(&op->esil, ",%d,%s,%c,%s,=", disp, MEMBASE(2), sign, MEMBASE(2)); } @@ -654,7 +654,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= } else { rz_strbuf_appendf(&op->esil, "%s,%s,%s,+,0xffffffff,&,=[4],%s,4,%s,+,%s,+,0xffffffff,&,=[4]", REG(0), MEMINDEX(2), MEMBASE(2), REG(1), MEMINDEX(2), MEMBASE(2)); - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { rz_strbuf_appendf(&op->esil, ",%s,%s,+,%s,=", MEMINDEX(2), MEMBASE(2), MEMBASE(2)); } @@ -722,7 +722,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= rz_strbuf_appendf(&op->esil, "%d,%s,+,0xffffffff,&,DUP,[4],%s,=,4,+,[4],%s,=", MEMDISP(2), MEMBASE(2), REG(0), REG(1)); } - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { if (ISPOSTINDEX32()) { if (ISIMM(3)) { rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=", @@ -757,7 +757,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= rz_strbuf_appendf(&op->esil, "%s,%d,+,[1],%s,=", MEMBASE(1), MEMDISP(1), REG(0)); } - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { if (ISIMM(2)) { rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=", MEMBASE(1), IMM(2), MEMBASE(1)); @@ -850,7 +850,7 @@ r6,r5,r4,3,sp,[*],12,sp,+= rz_strbuf_appendf(&op->esil, "%d,%s,+,0xffffffff,&,[4],0x%x,&,%s,=", MEMDISP(1), MEMBASE(1), mask, REG(0)); } - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { if (ISIMM(2)) { rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=", MEMBASE(1), IMM(2), MEMBASE(1)); diff --git a/librz/analysis/arch/arm/arm_il32.c b/librz/analysis/arch/arm/arm_il32.c index b80d97e97be..442d788d43e 100644 --- a/librz/analysis/arch/arm/arm_il32.c +++ b/librz/analysis/arch/arm/arm_il32.c @@ -138,37 +138,37 @@ static RzILOpEffect *write_reg(arm_reg reg, RZ_OWN RZ_NONNULL RzILOpBitVector *v * IL for arm condition * unconditional is returned as NULL (rather than true), for simpler code */ -static RZ_NULLABLE RzILOpBool *cond(arm_cc c) { +static RZ_NULLABLE RzILOpBool *cond(ARMCC_CondCodes c) { switch (c) { - case ARM_CC_EQ: + case ARMCC_EQ: return VARG("zf"); - case ARM_CC_NE: + case ARMCC_NE: return INV(VARG("zf")); - case ARM_CC_HS: + case ARMCC_HS: return VARG("cf"); - case ARM_CC_LO: + case ARMCC_LO: return INV(VARG("cf")); - case ARM_CC_MI: + case ARMCC_MI: return VARG("nf"); - case ARM_CC_PL: + case ARMCC_PL: return INV(VARG("nf")); - case ARM_CC_VS: + case ARMCC_VS: return VARG("vf"); - case ARM_CC_VC: + case ARMCC_VC: return INV(VARG("vf")); - case ARM_CC_HI: + case ARMCC_HI: return AND(VARG("cf"), INV(VARG("zf"))); - case ARM_CC_LS: + case ARMCC_LS: return OR(INV(VARG("cf")), VARG("zf")); - case ARM_CC_GE: + case ARMCC_GE: return INV(XOR(VARG("nf"), VARG("vf"))); - case ARM_CC_LT: + case ARMCC_LT: return XOR(VARG("nf"), VARG("vf")); - case ARM_CC_GT: + case ARMCC_GT: return AND(INV(VARG("zf")), INV(XOR(VARG("nf"), VARG("vf")))); - case ARM_CC_LE: + case ARMCC_LE: return OR(VARG("zf"), XOR(VARG("nf"), VARG("vf"))); - case ARM_CC_AL: + case ARMCC_AL: default: return NULL; } @@ -578,7 +578,7 @@ static RzILOpEffect *ldr(cs_insn *insn, bool is_thumb) { if (!addr) { return NULL; } - bool writeback = insn->detail->arm.writeback; + bool writeback = insn->detail->writeback; if (ISIMM(mem_idx + 1)) { // capstone incorrectly sets writeback to false for e.g. 0400b1e4 ldrt r0, [r1], 4 writeback = true; @@ -667,7 +667,7 @@ static RzILOpEffect *str(cs_insn *insn, bool is_thumb) { if (!addr) { return NULL; } - bool writeback = insn->detail->arm.writeback; + bool writeback = insn->detail->writeback; if (ISIMM(mem_idx + 1)) { // capstone incorrectly sets writeback to false for e.g. 04b0ade4 strt fp, [sp], 4 writeback = true; @@ -969,7 +969,7 @@ static RzILOpEffect *stm(cs_insn *insn, bool is_thumb) { size_t op_first; arm_reg ptr_reg; bool writeback; - if (insn->id == ARM_INS_PUSH || insn->id == ARM_INS_VPUSH) { + if (insn->id == ARM_INS_PUSH) { op_first = 0; ptr_reg = ARM_REG_SP; writeback = true; @@ -979,7 +979,7 @@ static RzILOpEffect *stm(cs_insn *insn, bool is_thumb) { } op_first = 1; ptr_reg = REGID(0); - writeback = insn->detail->arm.writeback; + writeback = insn->detail->writeback; } size_t op_count = OPCOUNT() - op_first; if (!op_count) { @@ -990,9 +990,9 @@ static RzILOpEffect *stm(cs_insn *insn, bool is_thumb) { return NULL; } bool decrement = insn->id == ARM_INS_STMDA || insn->id == ARM_INS_STMDB || insn->id == ARM_INS_PUSH || - insn->id == ARM_INS_VSTMDB || insn->id == ARM_INS_VPUSH; + insn->id == ARM_INS_VSTMDB; bool before = insn->id == ARM_INS_STMDB || insn->id == ARM_INS_PUSH || insn->id == ARM_INS_VSTMDB || - insn->id == ARM_INS_STMIB || insn->id == ARM_INS_VPUSH; + insn->id == ARM_INS_STMIB; ut32 regsize = reg_bits(REGID(op_first)) / 8; RzILOpEffect *eff = NULL; // build up in reverse order so the result recurses in the second arg of seq (for tail-call optimization) @@ -1030,7 +1030,7 @@ static RzILOpEffect *ldm(cs_insn *insn, bool is_thumb) { size_t op_first; arm_reg ptr_reg; bool writeback; - if (insn->id == ARM_INS_POP || insn->id == ARM_INS_VPOP) { + if (insn->id == ARM_INS_POP) { op_first = 0; ptr_reg = ARM_REG_SP; writeback = true; @@ -1040,7 +1040,7 @@ static RzILOpEffect *ldm(cs_insn *insn, bool is_thumb) { } op_first = 1; ptr_reg = REGID(0); - writeback = insn->detail->arm.writeback; + writeback = insn->detail->writeback; } size_t op_count = OPCOUNT() - op_first; if (!op_count) { @@ -1633,7 +1633,7 @@ static RzILOpEffect *rfe(cs_insn *insn, bool is_thumb) { RzILOpEffect *wb = NULL; bool wordhigher = insn->id == ARM_INS_RFEDA || insn->id == ARM_INS_RFEIB; bool increment = insn->id == ARM_INS_RFEIA || insn->id == ARM_INS_RFEIB; - if (insn->detail->arm.writeback) { + if (insn->detail->writeback) { wb = write_reg(REGID(0), increment ? ADD(DUP(base), U32(8)) : SUB(DUP(base), U32(8))); if (!wb) { @@ -2360,7 +2360,6 @@ static RzILOpEffect *il_unconditional(csh *handle, cs_insn *insn, bool is_thumb) case ARM_INS_PLD: case ARM_INS_PLDW: case ARM_INS_PLI: - case ARM_INS_YIELD: // barriers/synchronization case ARM_INS_DMB: case ARM_INS_DSB: @@ -2630,11 +2629,9 @@ static RzILOpEffect *il_unconditional(csh *handle, cs_insn *insn, bool is_thumb) // Advanced SIMD and Floating-point case ARM_INS_VSTMIA: case ARM_INS_VSTMDB: - case ARM_INS_VPUSH: return stm(insn, is_thumb); case ARM_INS_VLDMIA: case ARM_INS_VLDMDB: - case ARM_INS_VPOP: return ldm(insn, is_thumb); case ARM_INS_VMOV: return vmov(insn, is_thumb); diff --git a/librz/analysis/p/analysis_arm_cs.c b/librz/analysis/p/analysis_arm_cs.c index e21aade485a..b0f161c06be 100644 --- a/librz/analysis/p/analysis_arm_cs.c +++ b/librz/analysis/p/analysis_arm_cs.c @@ -129,41 +129,6 @@ static const char *vector_data_type_name(arm_vectordata_type type) { } } -static const char *cc_name(arm_cc cc) { - switch (cc) { - case ARM_CC_EQ: // Equal Equal - return "eq"; - case ARM_CC_NE: // Not equal Not equal, or unordered - return "ne"; - case ARM_CC_HS: // Carry set >, ==, or unordered - return "hs"; - case ARM_CC_LO: // Carry clear Less than - return "lo"; - case ARM_CC_MI: // Minus, negative Less than - return "mi"; - case ARM_CC_PL: // Plus, positive or zero >, ==, or unordered - return "pl"; - case ARM_CC_VS: // Overflow Unordered - return "vs"; - case ARM_CC_VC: // No overflow Not unordered - return "vc"; - case ARM_CC_HI: // Unsigned higher Greater than, or unordered - return "hi"; - case ARM_CC_LS: // Unsigned lower or same Less than or equal - return "ls"; - case ARM_CC_GE: // Greater than or equal Greater than or equal - return "ge"; - case ARM_CC_LT: // Less than Less than, or unordered - return "lt"; - case ARM_CC_GT: // Greater than Greater than - return "gt"; - case ARM_CC_LE: // Less than or equal <, ==, or unordered - return "le"; - default: - return ""; - } -} - static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) { int i; PJ *pj = pj_new(); @@ -273,7 +238,7 @@ static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) { if (x->update_flags) { pj_kb(pj, "update_flags", true); } - if (x->writeback) { + if (insn->detail->writeback) { pj_kb(pj, "writeback", true); } if (x->vector_size) { @@ -288,8 +253,8 @@ static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) { if (x->cps_flag != ARM_CPSFLAG_INVALID) { pj_ki(pj, "cps_flag", x->cps_flag); } - if (x->cc != ARM_CC_INVALID && x->cc != ARM_CC_AL) { - pj_ks(pj, "cc", cc_name(x->cc)); + if (x->cc != ARMCC_UNDEF && x->cc != ARMCC_AL) { + pj_ks(pj, "cc", ARMCondCodeToString(x->cc)); } if (x->mem_barrier != ARM_MB_RESERVED_0) { pj_ki(pj, "mem_barrier", x->mem_barrier - 1); @@ -550,24 +515,24 @@ static void opex64(RzStrBuf *buf, csh handle, cs_insn *insn) { } static int cond_cs2r2(int cc) { - if (cc == ARM_CC_AL || cc < 0) { + if (cc == ARMCC_AL || cc < 0) { cc = RZ_TYPE_COND_AL; } else { switch (cc) { - case ARM_CC_EQ: cc = RZ_TYPE_COND_EQ; break; - case ARM_CC_NE: cc = RZ_TYPE_COND_NE; break; - case ARM_CC_HS: cc = RZ_TYPE_COND_HS; break; - case ARM_CC_LO: cc = RZ_TYPE_COND_LO; break; - case ARM_CC_MI: cc = RZ_TYPE_COND_MI; break; - case ARM_CC_PL: cc = RZ_TYPE_COND_PL; break; - case ARM_CC_VS: cc = RZ_TYPE_COND_VS; break; - case ARM_CC_VC: cc = RZ_TYPE_COND_VC; break; - case ARM_CC_HI: cc = RZ_TYPE_COND_HI; break; - case ARM_CC_LS: cc = RZ_TYPE_COND_LS; break; - case ARM_CC_GE: cc = RZ_TYPE_COND_GE; break; - case ARM_CC_LT: cc = RZ_TYPE_COND_LT; break; - case ARM_CC_GT: cc = RZ_TYPE_COND_GT; break; - case ARM_CC_LE: cc = RZ_TYPE_COND_LE; break; + case ARMCC_EQ: cc = RZ_TYPE_COND_EQ; break; + case ARMCC_NE: cc = RZ_TYPE_COND_NE; break; + case ARMCC_HS: cc = RZ_TYPE_COND_HS; break; + case ARMCC_LO: cc = RZ_TYPE_COND_LO; break; + case ARMCC_MI: cc = RZ_TYPE_COND_MI; break; + case ARMCC_PL: cc = RZ_TYPE_COND_PL; break; + case ARMCC_VS: cc = RZ_TYPE_COND_VS; break; + case ARMCC_VC: cc = RZ_TYPE_COND_VC; break; + case ARMCC_HI: cc = RZ_TYPE_COND_HI; break; + case ARMCC_LS: cc = RZ_TYPE_COND_LS; break; + case ARMCC_GE: cc = RZ_TYPE_COND_GE; break; + case ARMCC_LT: cc = RZ_TYPE_COND_LT; break; + case ARMCC_GT: cc = RZ_TYPE_COND_GT; break; + case ARMCC_LE: cc = RZ_TYPE_COND_LE; break; } } return cc; @@ -902,7 +867,7 @@ static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) { } if (REGID(0) == ARM_REG_PC) { op->type = RZ_ANALYSIS_OP_TYPE_UJMP; - if (insn->detail->arm.cc != ARM_CC_AL) { + if (insn->detail->arm.cc != ARMCC_AL) { // op->type = RZ_ANALYSIS_OP_TYPE_MCJMP; op->type = RZ_ANALYSIS_OP_TYPE_UCJMP; } @@ -1114,7 +1079,7 @@ jmp $$ + 4 + ( [delta] * 2 ) for (i = 0; i < insn->detail->arm.op_count; i++) { if (insn->detail->arm.operands[i].type == ARM_OP_REG && insn->detail->arm.operands[i].reg == ARM_REG_PC) { - if (insn->detail->arm.cc == ARM_CC_AL) { + if (insn->detail->arm.cc == ARMCC_AL) { op->type = RZ_ANALYSIS_OP_TYPE_RET; } else { op->type = RZ_ANALYSIS_OP_TYPE_CRET; @@ -1159,7 +1124,7 @@ jmp $$ + 4 + ( [delta] * 2 ) op->type = RZ_ANALYSIS_OP_TYPE_ADD; if (REGID(0) == ARM_REG_PC) { op->type = RZ_ANALYSIS_OP_TYPE_UJMP; - if (REGID(1) == ARM_REG_PC && insn->detail->arm.cc != ARM_CC_AL) { + if (REGID(1) == ARM_REG_PC && insn->detail->arm.cc != ARMCC_AL) { // op->type = RZ_ANALYSIS_OP_TYPE_RCJMP; op->type = RZ_ANALYSIS_OP_TYPE_UCJMP; op->fail = addr + op->size; @@ -1342,7 +1307,7 @@ jmp $$ + 4 + ( [delta] * 2 ) op->disp = MEMDISP(1); if (REGID(0) == ARM_REG_PC) { op->type = RZ_ANALYSIS_OP_TYPE_UJMP; - if (insn->detail->arm.cc != ARM_CC_AL) { + if (insn->detail->arm.cc != ARMCC_AL) { // op->type = RZ_ANALYSIS_OP_TYPE_MCJMP; op->type = RZ_ANALYSIS_OP_TYPE_UCJMP; } @@ -1365,7 +1330,7 @@ jmp $$ + 4 + ( [delta] * 2 ) } else if (REGBASE(1) == ARM_REG_PC) { op->ptr = (addr & ~3LL) + (thumb ? 4 : 8) + MEMDISP(1); op->refptr = 4; - if (REGID(0) == ARM_REG_PC && insn->detail->arm.cc != ARM_CC_AL) { + if (REGID(0) == ARM_REG_PC && insn->detail->arm.cc != ARMCC_AL) { // op->type = RZ_ANALYSIS_OP_TYPE_MCJMP; op->type = RZ_ANALYSIS_OP_TYPE_UCJMP; op->fail = addr + op->size; @@ -1418,10 +1383,10 @@ jmp $$ + 4 + ( [delta] * 2 ) case ARM_INS_B: /* b.cc label */ op->cycles = 4; - if (insn->detail->arm.cc == ARM_CC_INVALID) { + if (insn->detail->arm.cc == ARMCC_UNDEF) { op->type = RZ_ANALYSIS_OP_TYPE_ILL; op->fail = addr + op->size; - } else if (insn->detail->arm.cc == ARM_CC_AL) { + } else if (insn->detail->arm.cc == ARMCC_AL) { op->type = RZ_ANALYSIS_OP_TYPE_JMP; op->fail = UT64_MAX; } else { @@ -1492,7 +1457,7 @@ jmp $$ + 4 + ( [delta] * 2 ) if (thumb && rz_arm_it_apply_cond(&ctx->it, insn)) { op->mnemonic = rz_str_newf("%s%s%s%s", rz_analysis_optype_to_string(op->type), - cc_name(insn->detail->arm.cc), + ARMCondCodeToString(insn->detail->arm.cc), insn->op_str[0] ? " " : "", insn->op_str); op->cond = (RzTypeCond)insn->detail->arm.cc; diff --git a/librz/asm/p/asm_arm_cs.c b/librz/asm/p/asm_arm_cs.c index f274c817d83..511f64361d8 100644 --- a/librz/asm/p/asm_arm_cs.c +++ b/librz/asm/p/asm_arm_cs.c @@ -47,41 +47,6 @@ static bool check_features(RzAsm *a, cs_insn *insn) { return true; } -static const char *cc_name(arm_cc cc) { - switch (cc) { - case ARM_CC_EQ: // Equal Equal - return "eq"; - case ARM_CC_NE: // Not equal Not equal, or unordered - return "ne"; - case ARM_CC_HS: // Carry set >, ==, or unordered - return "hs"; - case ARM_CC_LO: // Carry clear Less than - return "lo"; - case ARM_CC_MI: // Minus, negative Less than - return "mi"; - case ARM_CC_PL: // Plus, positive or zero >, ==, or unordered - return "pl"; - case ARM_CC_VS: // Overflow Unordered - return "vs"; - case ARM_CC_VC: // No overflow Not unordered - return "vc"; - case ARM_CC_HI: // Unsigned higher Greater than, or unordered - return "hi"; - case ARM_CC_LS: // Unsigned lower or same Less than or equal - return "ls"; - case ARM_CC_GE: // Greater than or equal Greater than or equal - return "ge"; - case ARM_CC_LT: // Less than Less than, or unordered - return "lt"; - case ARM_CC_GT: // Greater than Greater than - return "gt"; - case ARM_CC_LE: // Less than or equal <, ==, or unordered - return "le"; - default: - return ""; - } -} - static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) { ArmCSContext *ctx = (ArmCSContext *)a->plugin_data; @@ -161,7 +126,7 @@ static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) { if (thumb && rz_arm_it_apply_cond(&ctx->it, insn)) { char *tmpstr = rz_str_newf("%s%s", cs_insn_name(ctx->cd, insn->id), - cc_name(insn->detail->arm.cc)); + ARMCondCodeToString(insn->detail->arm.cc)); rz_str_cpy(insn->mnemonic, tmpstr); free(tmpstr); }