Testing #1614

[XVilka]

…gin design to monolithic; Basic ELF-reloc patching.

• Update instruction set to v5-v67 + HVX.
• Introduce monolithic plugin architecture to reverse opcodes in the same functions.
  • Analysis and Asm functionality was previously seperated and let to inconsistensies and incorrectly reversed opcodes.
• Add missing system instructions and registers.
• Enable search for immediates.
• Mark packets of instructions.
• Set more analysis data in RzAnalysisOp.
• Add basic ELF-reloc patching.
• Fix several disassembly and analysis bugs.
  • Jumps were not aligned to packet begin.
  • Endloop packets were not marked as such.
  • Rs.New registers were incorrectly disassembled.
  • Calling convention was out of date.
• Add several formatting configs for the produced disassembly.
  • Dis/Enable UTF-8.
  • Print or omit # prefix of immediates.
  • Print signed immediates with signe or as unsigned integers.

Your checklist for this pull request

• I've read the guidelines for contributing to this repository
• I made sure to follow the project's coding style
• I've documented or updated the documentation of every function and struct this PR changes. If not so I've explained why.
• I've added tests that prove my fix is effective or that my feature works (if possible)
• I've updated the rizin book with the relevant information (if needed)

Detailed description

...

Test plan

...

Closing issues

...

[XVilka]

Green.