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Hexagon update#1338

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Rot127 wants to merge 25 commits intorizinorg:devrizinorg/rizin:devfrom Rot127:hexagon-updateRot127/rizin:hexagon-updateCopy head branch name to clipboard

+109,981-50,058

Commits

Commits on Jul 10, 2021

• Add generated code

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  2abd3cc

Commits on Jul 20, 2021

• Sync source code with rz-hexagon.

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  3ef2a1d

• Apply requested change: Use rizin instead of r2 name.

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  0f83dd4

Commits on Aug 14, 2021

• Assign additional analysis instr. types.

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  57732eb

• Add analysis tests for jumps/calls, immext(), function recognition.

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  3df40c9

Commits on Aug 17, 2021

• Use RzStrBuf.len instead of deprecated RzAsmOp.size

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  4674d40

Commits on Aug 19, 2021

• Mark R0 as register which holds the systemcall number.

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  784eec2

• Enable immediate operand search via /ai.

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  c45cc36

• Set .val to last immediate of instruction.

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  5576e7d

Commits on Aug 24, 2021

• Replace ifs with else ifs to reduce comparisions.

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  c9fab0a

• Fix ASAN errors by moving code into functions.

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  515ff31

Commits on Aug 25, 2021

• Apply clang-format on casm.c

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  7ec6bb4

• Remove unused variables.

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  5027b3e

• Add HVX calling convention.

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  9717087

• Print up to 5 argument registers in retrieved CC.

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  f73ab8c

• Remove waring if non existing registers shall be decoded.

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  2aca254

• Order instructions from low to high address to fix test.

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  316b768

Commits on Aug 26, 2021

• Set correct packet prefix in tests.

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  9e4fac7

• Add more detected registers in test cases.

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  02797af

• Track instr.<->packet membership relative to last instr.

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  47ebbe8

• Sort test cases again...

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  75f0b17

Commits on Sep 1, 2021

• -1 to UT64_MAX, Spelling, remove condition with no effect.

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  faa8681

Commits on Sep 6, 2021

• ESIL is not supported yet.

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  4eaf977

• Add Hexagon relocation formulars.

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  b4f266c

• Merge branch 'dev' into hexagon-update

  Rot127

  authored
  908a907