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This repository has been archived by the owner on Mar 27, 2021. It is now read-only.
I am not an expert when it comes to symmetric multiprocessing, but theoretically all cores (=CPUs) could support SMP, right? I mean as long as they have the Zicsr extension?! 🤔
Several instances of the same core can be attached to the same memory system and since each core can determine it's ID via mhartid SMP is basically possible?
Well theoretically yes for some definitions of SMP, but I was thinking more of the now-common cache-coherent SMP, where the implementation of A can play a role (i.e. atomic update implemented by sending back-to-back read/write to memory might achieve atomicity in a single-core context, but not in SMP). You also need cache coherency support if the core includes some private caches(s).
It still might be considered more a property of the SoC platform than of the core, granted.
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There could be an additional column for cores/SoC platform that can be used in SMP mode.
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