diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml index de9590807..5d370ce93 100644 --- a/.github/workflows/compile.yml +++ b/.github/workflows/compile.yml @@ -20,13 +20,13 @@ jobs: run: eval $(opam env) && test/run_tests.sh - name: Upload test results if: always() - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v4 with: name: tests.xml path: test/tests.xml - name: Upload event payload if: always() - uses: actions/upload-artifact@v2 + uses: actions/upload-artifact@v4 with: name: event.json path: ${{ github.event_path }} diff --git a/Makefile b/Makefile index 0f66cbaf1..3e948ef84 100644 --- a/Makefile +++ b/Makefile @@ -36,6 +36,10 @@ SAIL_DEFAULT_INST += riscv_insts_zks.sail SAIL_DEFAULT_INST += riscv_insts_zbkb.sail SAIL_DEFAULT_INST += riscv_insts_zbkx.sail +# Example custom extension (do not include this in the +# usual model build.) +SAIL_DEFAULT_INST += riscv_insts_custom_xmpl.sail + SAIL_SEQ_INST = $(SAIL_DEFAULT_INST) riscv_jalr_seq.sail SAIL_RMEM_INST = $(SAIL_DEFAULT_INST) riscv_jalr_rmem.sail riscv_insts_rmem.sail @@ -119,8 +123,8 @@ export LEM_DIR C_WARNINGS ?= #-Wall -Wextra -Wno-unused-label -Wno-unused-parameter -Wno-unused-but-set-variable -Wno-unused-function -C_INCS = $(addprefix c_emulator/,riscv_prelude.h riscv_platform_impl.h riscv_platform.h riscv_softfloat.h) -C_SRCS = $(addprefix c_emulator/,riscv_prelude.c riscv_platform_impl.c riscv_platform.c riscv_softfloat.c riscv_sim.c) +C_INCS = $(addprefix c_emulator/,riscv_prelude.h riscv_platform_impl.h riscv_platform.h riscv_softfloat.h rv_cfg_func.h) +C_SRCS = $(addprefix c_emulator/,riscv_prelude.c riscv_platform_impl.c riscv_platform.c riscv_softfloat.c riscv_sim.c rv_cfg_func.c) SOFTFLOAT_DIR = c_emulator/SoftFloat-3e SOFTFLOAT_INCDIR = $(SOFTFLOAT_DIR)/source/include @@ -134,6 +138,10 @@ GMP_FLAGS = $(shell pkg-config --cflags gmp) GMP_LIBS = $(shell pkg-config --libs gmp || echo -lgmp) ZLIB_FLAGS = $(shell pkg-config --cflags zlib) ZLIB_LIBS = $(shell pkg-config --libs zlib) +FYAML_FLAGS = $(shell pkg-config --cflags libfyaml) +FYAML_LIBS = $(shell pkg-config --libs libfyaml) +PCRE2_FLAGS = $(shell pkg-config --cflags) +PCRE2_LIBS = $(shell pkg-config --libs libpcre2-8) C_FLAGS = -I $(SAIL_LIB_DIR) -I c_emulator $(GMP_FLAGS) $(ZLIB_FLAGS) $(SOFTFLOAT_FLAGS) C_LIBS = $(GMP_LIBS) $(ZLIB_LIBS) $(SOFTFLOAT_LIBS) @@ -233,7 +241,7 @@ ocaml_emulator/tracecmp: ocaml_emulator/tracecmp.ml generated_definitions/c/riscv_model_$(ARCH).c: $(SAIL_SRCS) model/main.sail Makefile mkdir -p generated_definitions/c - $(SAIL) $(SAIL_FLAGS) -O -Oconstant_fold -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_SRCS) model/main.sail -o $(basename $@) + $(SAIL) $(SAIL_FLAGS) -O -Oconstant_fold -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_include rv_cfg_func.h -c_no_main $(SAIL_SRCS) model/main.sail -o $(basename $@) generated_definitions/c2/riscv_model_$(ARCH).c: $(SAIL_SRCS) model/main.sail Makefile mkdir -p generated_definitions/c2 @@ -271,7 +279,7 @@ rvfi_preserve_fns=-c_preserve rvfi_set_instr_packet \ generated_definitions/c/riscv_rvfi_model_$(ARCH).c: $(SAIL_RVFI_SRCS) model/main.sail Makefile mkdir -p generated_definitions/c - $(SAIL) $(rvfi_preserve_fns) $(SAIL_FLAGS) -O -Oconstant_fold -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_RVFI_SRCS) model/main.sail -o $(basename $@) + $(SAIL) $(rvfi_preserve_fns) $(SAIL_FLAGS) -O -Oconstant_fold -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_include rv_cfg_func.h -c_no_main $(SAIL_RVFI_SRCS) model/main.sail -o $(basename $@) sed -i -e '/^[[:space:]]*$$/d' $@ c_emulator/riscv_rvfi_$(ARCH): generated_definitions/c/riscv_rvfi_model_$(ARCH).c $(C_INCS) $(C_SRCS) $(SOFTFLOAT_LIBS) Makefile diff --git a/README.md b/README.md index d51e6473d..7f7010483 100644 --- a/README.md +++ b/README.md @@ -270,6 +270,9 @@ sail-riscv - test // test files - riscv-tests // snapshot of tests from the riscv/riscv-tests github repo - os-boot // information and sample files for booting OS images +- cookbook // RISC-V cookbook examples and documentation + - doc // the asciidoc documentation + - functional_code_examples // code examples ``` Getting started @@ -345,9 +348,33 @@ Some useful options are: configuring whether misaligned accesses trap whether page-table walks update PTE bits (`--enable-dirty-update` for C and `-enable-dirty-update` for OCaml). -### Experimental integration with riscv-config +### Integration with RISCV-Config + +RISCV-Config ( https://github.com/riscv-software-src/riscv-config ) is the +configuration standard used by the RISC-V Architectural Compatability Tests +to specify how a RISC-V core is configured. The RISC-V architecture allows +for many implementation specific configurations such as: + +- Supported (implemented) ISA extensions +- Misaligned address support (ie - HW support or trap) +- Configuration of WARL fields in CSRs +- Memory map + +RISCV-Config utilizes YAML and YAML schemas to describe the configuration. +There are two YAML files that get examined: 1) an ISA YAML file that +describes the configuration of a RISC-V core (ie - supported ISA extensions, +CSR configurations, etc), and 2) a platform YAML file that describes +the platform configurations (ie - reset address, CLIC support, etc). + +Configuration is done at run-time not at compile time. (Note: there +was an earlier PR (PR #43) that integrated RISCV-Config as a compile-time +capability. See: [integration with riscv-config](https://github.com/rems-project/sail-riscv/pull/43) +It was determined that a run-time solution was needed rather than a compile-time solution.) +Command line switches specify the YAML files that are to be used. + +When adding new extensions to the model, corresponding configuration parameters +need to be added to RISCV-Config. -There is also (as yet unmerged) support for [integration with riscv-config](https://github.com/rems-project/sail-riscv/pull/43) to allow configuring the compiled model according to a riscv-config yaml specification. ### Booting OS images @@ -383,6 +410,7 @@ Authors Nathaniel Wesley Filardo, Microsoft; Peter Rugg, University of Cambridge; Scott Johnson, Aril Computer Corp. + William C. McSpadden, RISC-V, International; Funding ------- diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c index b1504a727..fc1f1101f 100644 --- a/c_emulator/riscv_platform_impl.c +++ b/c_emulator/riscv_platform_impl.c @@ -3,6 +3,10 @@ #include /* Settings of the platform implementation, with common defaults. */ +char *RV64ISA = ""; +char *RV32ISA = ""; +char *RV128ISA = ""; + bool rv_enable_pmp = false; bool rv_enable_zfinx = false; bool rv_enable_rvc = true; @@ -14,6 +18,8 @@ bool rv_enable_dirty_update = false; bool rv_enable_misaligned = false; bool rv_mtval_has_illegal_inst_bits = false; +uint64_t rv_reset_address = UINT64_C(0x0); + uint64_t rv_ram_base = UINT64_C(0x80000000); uint64_t rv_ram_size = UINT64_C(0x4000000); diff --git a/c_emulator/riscv_platform_impl.h b/c_emulator/riscv_platform_impl.h index 165fb94d7..a695fe300 100644 --- a/c_emulator/riscv_platform_impl.h +++ b/c_emulator/riscv_platform_impl.h @@ -5,7 +5,12 @@ /* Settings of the platform implementation. */ -#define DEFAULT_RSTVEC 0x00001000 +// #define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_RSTVEC rv_cfg_c_int("/reset/address") + +extern char *RV64ISA; +extern char *RV32ISA; +extern char *RV128ISA; extern bool rv_enable_pmp; extern bool rv_enable_zfinx; @@ -17,6 +22,8 @@ extern bool rv_enable_dirty_update; extern bool rv_enable_misaligned; extern bool rv_mtval_has_illegal_inst_bits; +extern uint64_t rv_reset_address; + extern uint64_t rv_ram_base; extern uint64_t rv_ram_size; diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c index 9a37c18e1..2797b79cb 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c @@ -1,3 +1,4 @@ +// vim: set tabstop=2 shiftwidth=2 expandtab #include #include #include @@ -11,6 +12,13 @@ #include #include #include +#include + +//This macro must be defined before including pcre2.h. For a program that uses +//only one code unit width, it makes it possible to use generic function names +//such as pcre2_compile(). +#define PCRE2_CODE_UNIT_WIDTH 8 +#include #include "elf.h" #include "sail.h" @@ -22,15 +30,14 @@ #include "riscv_platform_impl.h" #include "riscv_sail.h" +#include "rv_cfg_func.h" + #ifdef ENABLE_SPIKE #include "tv_spike_intf.h" #else struct tv_spike_t; #endif -const char *RV64ISA = "RV64IMAC"; -const char *RV32ISA = "RV32IMAC"; - /* Selected CSRs from riscv-isa-sim/riscv/encoding.h */ #define CSR_STVEC 0x105 #define CSR_SEPC 0x141 @@ -108,15 +115,7 @@ char *sailcov_file = NULL; #endif static struct option options[] = { - {"enable-dirty-update", no_argument, 0, 'd'}, - {"enable-misaligned", no_argument, 0, 'm'}, - {"enable-pmp", no_argument, 0, 'P'}, - {"enable-next", no_argument, 0, 'N'}, - {"ram-size", required_argument, 0, 'z'}, - {"disable-compressed", no_argument, 0, 'C'}, - {"disable-writable-misa", no_argument, 0, 'I'}, - {"disable-fdext", no_argument, 0, 'F'}, - {"mtval-has-illegal-inst-bits", no_argument, 0, 'i'}, +// {"mtval-has-illegal-inst-bits", no_argument, 0, 'i'}, {"device-tree-blob", required_argument, 0, 'b'}, {"terminal-log", required_argument, 0, 't'}, {"show-times", required_argument, 0, 'p'}, @@ -130,7 +129,8 @@ static struct option options[] = { {"trace", optional_argument, 0, 'v'}, {"no-trace", optional_argument, 0, 'V'}, {"inst-limit", required_argument, 0, 'l'}, - {"enable-zfinx", no_argument, 0, 'x'}, + {"platform-config", required_argument, 0, 'y'}, + {"isa-config", required_argument, 0, 'u'}, #ifdef SAILCOV {"sailcov-file", required_argument, 0, 'c'}, #endif @@ -219,70 +219,49 @@ char *process_args(int argc, char **argv) while(true) { c = getopt_long(argc, argv, "a" - "d" - "m" - "P" - "C" - "N" "I" - "F" - "i" +// "i" "s" "p" - "z:" "b:" "t:" "T:" "g:" "h" + "y:" + "u:" #ifdef RVFI_DII "r:" #endif "V::" "v::" "l:" - "x" #ifdef SAILCOV "c:" #endif , options, NULL); if (c == -1) break; switch (c) { - case 'a': - report_arch(); - break; - case 'd': - fprintf(stderr, "enabling dirty update.\n"); - rv_enable_dirty_update = true; - break; - case 'm': - fprintf(stderr, "enabling misaligned access.\n"); - rv_enable_misaligned = true; - break; - case 'P': - fprintf(stderr, "enabling PMP support.\n"); - rv_enable_pmp = true; - break; - case 'C': - fprintf(stderr, "disabling RVC compressed instructions.\n"); - rv_enable_rvc = false; - break; - case 'N': - fprintf(stderr, "enabling N extension.\n"); - rv_enable_next = true; - break; - case 'I': - fprintf(stderr, "disabling writable misa CSR.\n"); - rv_enable_writable_misa = false; + case 'y': + if ( rv_cfg_c_build_from_file(RV_CFG_PLATFORM, optarg) == 0 ) { + fprintf(stderr, "unable to build fast-yaml document from %s\n", optarg); + exit(1); + } break; - case 'F': - fprintf(stderr, "disabling floating point (F and D extensions).\n"); - rv_enable_fdext = false; + + case 'u': + if ( rv_cfg_c_build_from_file(RV_CFG_ISA, optarg) == 0 ) { + fprintf(stderr, "unable to build fast-yaml document from %s\n", optarg); + exit(1); + } break; - case 'i': - fprintf(stderr, "enabling storing illegal instruction bits in mtval.\n"); - rv_mtval_has_illegal_inst_bits = true; + case 'a': + report_arch(); break; +// case 'i': +// fprintf(stderr, "enabling storing illegal instruction bits in mtval.\n"); +// rv_mtval_has_illegal_inst_bits = true; +// break; case 's': do_dump_dts = true; break; @@ -290,16 +269,6 @@ char *process_args(int argc, char **argv) fprintf(stderr, "will show execution times on completion.\n"); do_show_times = true; break; - case 'z': - ram_size = atol(optarg); - if (ram_size) { - fprintf(stderr, "setting ram-size to %" PRIu64 " MB\n", ram_size); - rv_ram_size = ram_size << 20; - } else { - fprintf(stderr, "invalid ram-size '%s' provided.\n", optarg); - exit(1); - } - break; case 'b': dtb_file = strdup(optarg); fprintf(stderr, "using %s as DTB file.\n", dtb_file); @@ -335,11 +304,6 @@ char *process_args(int argc, char **argv) case 'l': insn_limit = atoi(optarg); break; - case 'x': - fprintf(stderr, "enabling Zfinx support.\n"); - rv_enable_zfinx = true; - rv_enable_fdext = false; - break; #ifdef SAILCOV case 'c': sailcov_file = strdup(optarg); @@ -471,29 +435,34 @@ void tick_spike() void init_sail_reset_vector(uint64_t entry) { +// TODO: This code is commented out because we don't want the +// the Sail model setting up and executing any code. BUT.... +// the question is: will the Sail model load the .elf file +// into the appropriate place in memory? + #define RST_VEC_SIZE 8 - uint32_t reset_vec[RST_VEC_SIZE] = { - 0x297, // auipc t0,0x0 - 0x28593 + (RST_VEC_SIZE * 4 << 20), // addi a1, t0, &dtb - 0xf1402573, // csrr a0, mhartid - is_32bit_model() ? - 0x0182a283u : // lw t0,24(t0) - 0x0182b283u, // ld t0,24(t0) - 0x28067, // jr t0 - 0, - (uint32_t) (entry & 0xffffffff), - (uint32_t) (entry >> 32) - }; +// uint32_t reset_vec[RST_VEC_SIZE] = { +// 0x297, // auipc t0,0x0 +// 0x28593 + (RST_VEC_SIZE * 4 << 20), // addi a1, t0, &dtb +// 0xf1402573, // csrr a0, mhartid +// is_32bit_model() ? +// 0x0182a283u : // lw t0,24(t0) +// 0x0182b283u, // ld t0,24(t0) +// 0x28067, // jr t0 +// 0, +// (uint32_t) (entry & 0xffffffff), +// (uint32_t) (entry >> 32) +// }; rv_rom_base = DEFAULT_RSTVEC; uint64_t addr = rv_rom_base; - for (int i = 0; i < sizeof(reset_vec); i++) - write_mem(addr++, (uint64_t)((char *)reset_vec)[i]); - - if (dtb && dtb_len) { - for (size_t i = 0; i < dtb_len; i++) - write_mem(addr++, dtb[i]); - } +// for (int i = 0; i < sizeof(reset_vec); i++) +// write_mem(addr++, (uint64_t)((char *)reset_vec)[i]); +// +// if (dtb && dtb_len) { +// for (size_t i = 0; i < dtb_len; i++) +// write_mem(addr++, dtb[i]); +// } #ifdef ENABLE_SPIKE if (dtb && dtb_len) { @@ -527,7 +496,7 @@ void init_sail_reset_vector(uint64_t entry) /* set rom size */ rv_rom_size = rom_end - rv_rom_base; /* boot at reset vector */ - zPC = rv_rom_base; + zPC = rv_reset_address; } void preinit_sail() @@ -976,10 +945,16 @@ void init_logs() int main(int argc, char **argv) { + rv_cfg_c_init(); + char *file = process_args(argc, argv); + // Initialize the RISC-V Configuration elements. + // Must be done after command line arguments are processed in + // order to get RISCV-Config filenames. + rv_cfg_c_configure(); + // Initialize model so that we can check or report its architecture. preinit_sail(); - char *file = process_args(argc, argv); init_logs(); if (gettimeofday(&init_start, NULL) < 0) { diff --git a/c_emulator/rv_cfg_func.c b/c_emulator/rv_cfg_func.c new file mode 100644 index 000000000..c175d1a5c --- /dev/null +++ b/c_emulator/rv_cfg_func.c @@ -0,0 +1,452 @@ +// vim: set tabstop=4 shiftwidth=4 expandtab +// ============================================================================ +// Filename: rv_cfg_func.c +// +// Description: Functions to be called by Sail and C to get values from a yaml file. +// +// Author(s): Bill McSpadden (bill@riscv.org) +// +// Revision: See git log +// ============================================================================ + +#include +#include "rv_cfg_func.h" +#include "string.h" + +/* RISC-V Config YAML configuration support */ +static char *rv_config_platform_file = NULL; +static int rv_config_platform_fd = 0; +static struct fy_document *rv_config_fyd_platform = NULL; + +static char *rv_config_isa_file = NULL; +static int rv_config_isa_fd = 0; +static struct fy_document *rv_config_fyd_isa = NULL; + +// rv_cfg_enum2string_a is built (in rv_cfg_init()) so that the +// array index is the enum value. A poor man's associative array. +static rv_cfg_enum2string_t rv_cfg_enum2string_a[RV_CFG_LAST]; + +#define EXPAND(__ENUM2STR__) { __ENUM2STR__, #__ENUM2STR__ } +static rv_cfg_enum2string_t rv_cfg_enum2string_init_a[] = + { + EXPAND(RV_CFG_ISA), + EXPAND(RV_CFG_PLATFORM), + EXPAND(RV_CFG_DEBUG), + }; + +static rv_cfg_enum2doc_t rv_cfg_enum2doc_a[RV_CFG_LAST]; + +extern int64_t zxlen_val; + +// ============================================================================ +int +rv_cfg_c_init() + { + for (int i = 0; i < RV_CFG_LAST; i++) + { + rv_cfg_enum2string_a[rv_cfg_enum2string_init_a[i].e].e = rv_cfg_enum2string_init_a[i].e; + rv_cfg_enum2string_a[rv_cfg_enum2string_init_a[i].e].s = rv_cfg_enum2string_init_a[i].s; + } + + } + +// ============================================================================ +int +rv_cfg_c_configure(void) + { + char * RV_ISA; + + + // ==================================================================== + // Get the ISA string. Much of the configuration is derived from this + // string. + RV_ISA = rv_cfg_c_string("/hart0/ISA"); + + // ==================================================================== + // Do the configuration. + rv_enable_rvc = rv_cfg_c_ext_enable(RV_ISA, "C"); + rv_enable_fdext = rv_cfg_c_ext_enable(RV_ISA, "F"); + rv_enable_next = rv_cfg_c_ext_enable(RV_ISA, "N"); + rv_enable_zfinx = rv_cfg_c_ext_enable(RV_ISA, "Zfinx"); + rv_enable_dirty_update = rv_cfg_c_ext_enable(RV_ISA, "Ssptead"); //TODO: Use this, .... + //rv_enable_dirty_update = rv_cfg_c_bool_c("/hart0/pte_dirty_update_enable"); // .... not this + + rv_enable_misaligned = rv_cfg_c_bool("/hart0/hw_data_misaligned_support"); + + rv_enable_pmp = ( + (rv_cfg_c_bool("/hart0/pmpaddr0/rv32/accessible") ) || + (rv_cfg_c_bool("/hart0/pmpaddr0/rv64/accessible") ) + ) ; + + rv_ram_size = rv_cfg_c_int("/ram_size") << 20; // Convert to MBs + rv_reset_address = rv_cfg_c_int("/reset/address"); + + rv_enable_writable_misa = rv_cfg_c_path_exists("/hart0/misa/rv32/extensions/type/warl"); + rv_mtval_has_illegal_inst_bits = rv_cfg_c_bool("/hart0/mtval/has_illegal_inst_bits"); + + // ==================================================================== + // Print out the configuration that you just pulled out from the + // RISCV-Config files. Print it out in terms of the Golden Model + // variables that are used in Sail. +#define CFG_STRING_FMT "%-56s" + printf("=================================================================================\n"); + printf("Start: RISC-V Golden Model configuration values.....\n"); + printf(CFG_STRING_FMT "'%s'\n", "RV_ISA: ", RV_ISA); + printf(CFG_STRING_FMT "%s\n", "C ext support (rv_enable_rvc): " , rv_enable_rvc ? "true" : "false"); + printf(CFG_STRING_FMT "%s\n", "F/D ext support (rv_enable_fdext):", rv_enable_fdext ? "true" : "false"); + printf(CFG_STRING_FMT "%s\n", "N ext support (rv_enable_next): ", rv_enable_next ? "true" : "false"); + printf(CFG_STRING_FMT "%s\n", "Zfinx ext support (rv_enable_zfinx): ", rv_enable_zfinx ? "true" : "false"); + printf(CFG_STRING_FMT "%s\n", "enable misaligned support (rv_enable_misaligned): ", rv_enable_misaligned ? "true" : "false"); + printf(CFG_STRING_FMT "%s\n", "enable pmp support (rv_enable_pmp): ", rv_enable_pmp ? "true" : "false"); + printf(CFG_STRING_FMT "%ld MB\n", "ram size (rv_ram_size): ", rv_ram_size >> 20); + printf(CFG_STRING_FMT "0x%lx\n", "reset address (rv_reset_address, zPC): ", rv_reset_address); + printf(CFG_STRING_FMT "%s\n", "PTE dirty update enable (rv_enable_dirty_update): ", rv_enable_dirty_update ? "true" : "false"); + printf(CFG_STRING_FMT "%s\n", "writable misa (rv_enable_writable_misa): ", rv_enable_writable_misa ? "true" : "false"); + printf(CFG_STRING_FMT "%s\n", "mtval: illegal inst (rv_mtval_has_illegal_inst_bits): ", rv_mtval_has_illegal_inst_bits ? "true" : "false"); + printf("End: RISC-V Golden Model configuration values.....\n"); + printf("=================================================================================\n"); + + // ==================================== + // Error checking of configuration. + // Most error checking of allowed configurations is done + // by the RISCV-Config validator script. It is assumed + // that the user has validated his implementation-specific + // config file using the validator script. + // + // TODO: Would it make sense to run the validator script + // here in order to ensure that legal configurations + // are being run? I believe RISCOF already does this + // when running the arch-tests. + +// TODO: Need a method for getting XLEN from the Sail model so +// that we can compare it against the ISA string. +// // ==================================== +// // Error checking of configuration. XLEN +// printf("%s, %d: zxlen_val: %ld\n", __FILE__, __LINE__, zxlen_val); +// if (zxlen_val == 32) +// { +// if (!rv_cfg_c_ext_enable(RV_ISA, "RV32")) +// { +// fprintf(stderr, "%s, %d: incompatable settings for zxlen_val and RV_ISA. both must be 32.", +// __FILE__, __LINE__); +// exit(1); +// } +// RV32ISA = RV_ISA; +// } +// else if (zxlen_val == 64) +// { +// if (!rv_cfg_c_ext_enable(RV_ISA, "RV64")) +// { +// fprintf(stderr, "%s, %d: incompatable settings for zxlen_val and RV_ISA. both must be 64.", +// __FILE__, __LINE__); +// exit(1); +// } +// RV64ISA = RV_ISA; +// } +// else if (zxlen_val == 128) +// { +// if (!rv_cfg_c_ext_enable(RV_ISA, "RV128")) +// { +// fprintf(stderr, "%s, %d: incompatable settings for zxlen_val and RV_ISA. both must be 128.", +// __FILE__, __LINE__); +// exit(1); +// } +// RV128ISA = RV_ISA; +// } +// else +// { +// fprintf(stderr, "%s, %d: invalid setting for zxlen_val: %d.", +// __FILE__, __LINE__, zxlen_val); +// } + + // ==================================== + // Check extension settings for mutual exclusivity + // TODO: should I introduce 'assert' as an error reporting mechanism + // instead of this ad hoc mechanism? + if ((rv_enable_fdext == true) && (rv_enable_zfinx == true)) + { + fprintf(stderr, "%s, %d: incompatable settings for [fd]ext and Zfinx. both cannot be enabled.", + __FILE__, __LINE__); + exit(1); + } + + } + +// ============================================================================ +bool +rv_cfg_c_path_exists(char * path) + { + struct fy_path_parse_cfg cfg; + struct fy_path_parser *fypp; + bool ret; + + cfg.flags = FYPPCF_QUIET; + cfg.userdata = NULL; + cfg.diag = NULL; + + fypp = fy_path_parser_create(&cfg); + ret = (fy_path_parse_expr_from_string(fypp, path, -1) == NULL) ? false : true; + fy_path_parser_destroy(fypp); + + return(ret); + } + +// ============================================================================ +bool +rv_cfg_c_bool(char * key_str) + { + char *s; + + s = rv_cfg_c_string(key_str); + + if ( strcmp("true", s) == 0) + { + return(true); + } + else if ( strcmp("false", s) == 0 ) + { + return(false); + } + else + { + fprintf(stderr, "%s, %d: internal error. '%s' does not appear to be a bool.\n", + __FILE__, __LINE__, key_str); + exit(1); + } + } + +// ============================================================================ +int +rv_cfg_c_ext_enable(char * isa_str, char * ext_pattern) + { + pcre2_code *re; + int errornumber; + PCRE2_SIZE erroroffset; + pcre2_match_data *match_data; + int rc; + + re = pcre2_compile( + ext_pattern, /* the pattern */ + PCRE2_ZERO_TERMINATED, /* indicates pattern is zero-terminated */ + 0, /* default options */ + &errornumber, /* for error number */ + &erroroffset, /* for error offset */ + NULL); /* use default compile context */ + + if (re == NULL) // Compilation failed + { + PCRE2_UCHAR buffer[256]; + pcre2_get_error_message(errornumber, buffer, sizeof(buffer)); + printf("PCRE2 compilation failed at offset %d: %s\n", (int)erroroffset, + buffer); + } + + match_data = pcre2_match_data_create_from_pattern(re, NULL); + + rc = pcre2_match( + re, /* the compiled pattern */ + isa_str, /* the subject string */ + strlen(isa_str), /* the length of the subject */ + 0, /* start at offset 0 in the subject */ + 0, /* default options */ + match_data, /* block for storing the result */ + NULL); /* use default match context */ + + if ((rc == 0) || (rc == -1)) // Does not match + { + return(0); + } + else if (rc == 1) + { + return(1); + } + else + { + fprintf(stderr, "%s, %d: unexpected match return value, %d, for '%s' in ISA string %s\n", + __FILE__, __LINE__, rc, ext_pattern, isa_str); + exit(1); + } + } + +// ============================================================================ +char * +rv_cfg_c_get_string(rv_cfg_e e) + { + return(rv_cfg_enum2string_a[e].s); + } + +// ============================================================================ +rv_cfg_e +rv_cfg_c_get_enum(char * s) + { + for (int i = 0; i < (sizeof(rv_cfg_enum2string_a)/sizeof(rv_cfg_enum2string_t)); i++) + { + if ( strcmp(rv_cfg_enum2string_a[i].s, s) == 0 ) + { + return(rv_cfg_enum2string_a[i].e); + } + } + fprintf(stderr, "%s, %d: error: internal error. bad lookup of '%s'\n", __FILE__, __LINE__, s); + exit(1); + } + + +// ============================================================================ +int +rv_cfg_c_build_from_file(rv_cfg_e rv_cfg_type, char * filename ) + { + struct stat buffer; + struct fy_document *fyd = NULL; + + printf("%s file: %s\n", rv_cfg_c_get_string(rv_cfg_type), filename); + if ( (stat(filename, &buffer) == -1) ) + { + fprintf(stderr, "%s, %d: error: file, %s, does not exist.\n", __FILE__, __LINE__, filename); + return(0); + } + + rv_cfg_enum2doc_a[rv_cfg_type].fyd = fy_document_build_from_file(NULL, filename); + if (! rv_cfg_enum2doc_a[rv_cfg_type].fyd) + { + fprintf(stderr, "unable to build document from %s\n", filename); + return(0); + } + rv_cfg_enum2doc_a[rv_cfg_type].filename = filename; + rv_cfg_enum2doc_a[rv_cfg_type].e = rv_cfg_type; + + printf("%s, %d: rv_cfg file, '%s', loaded successfully as %s.\n", + __FILE__, __LINE__, rv_cfg_enum2doc_a[rv_cfg_type].filename, + rv_cfg_c_get_string(rv_cfg_enum2doc_a[rv_cfg_type].e)); + + return (1); + } + + +// ============================================================================ +unsigned int +rv_cfg_c_int(char * key_str) + { + struct fy_document *fyd = NULL; + //unsigned int yaml_val_int; + int yaml_val_int; + int count; + char *tmp_str; + + + for (int i = 0; i < RV_CFG_LAST; i++) + { + char *conversion_str; + if ( (fyd = rv_cfg_enum2doc_a[i].fyd) == NULL) + { + continue; + } + + conversion_str = " %i"; + tmp_str = malloc(strlen(key_str) + strlen(conversion_str) + 1); + strcpy(tmp_str, key_str); + strcat(tmp_str, conversion_str); + //printf("%s, %d: scanf string: %s\n", __FILE__, __LINE__, tmp_str); + + count = fy_document_scanf(fyd, tmp_str, &yaml_val_int); + if (count == 1) + { + free(tmp_str); + return(yaml_val_int); + } + free(tmp_str); + } + + // If we've gotten to this point, we've gone through each of the + // rv_cfg files and didn't find the pattern OR the pattern + // didn't match the conversion string. In either case, there is + // something wrong. + + fprintf(stderr, "%s, %d: the key, %s, was not found.\n", __FILE__, __LINE__, key_str); + exit(1); + return(0); // Never taken. + } + +// ============================================================================ +char * +rv_cfg_c_string(char * key_str) + { + struct fy_document *fyd = NULL; +// char *yaml_val_string; + char yaml_val_string[1024]; + int count; + char *tmp_str; + char *ret_str_ptr; + + for (int i = 0; i < RV_CFG_LAST; i++) + { + char *conversion_str; + if ( (fyd = rv_cfg_enum2doc_a[i].fyd) == NULL) + { + continue; + } + + //printf("%s, %d: checking yaml file, %s\n", __FILE__, __LINE__, rv_cfg_enum2doc_a[i].filename); + conversion_str = " %1023s"; + tmp_str = malloc(strlen(key_str) + strlen(conversion_str) + 1); + strcpy(tmp_str, key_str); + strcat(tmp_str, conversion_str); + //printf("%s, %d: scanf string: '%s'\n", __FILE__, __LINE__, tmp_str); + + count = fy_document_scanf(fyd, tmp_str, yaml_val_string); + if (count == 1) + { + free(tmp_str); + ret_str_ptr = malloc(strlen(yaml_val_string)); // TODO: where should this be freed? + strcpy(ret_str_ptr, yaml_val_string); + return(ret_str_ptr); + } + free(tmp_str); + } + + // If we've gotten to this point, we've gone through each of the + // rv_cfg files and didn't find the pattern OR the pattern + // didn't match the conversion string. In either case, there is + // something wrong. + + fprintf(stderr, "%s, %d: the key, '%s', was not found.\n", __FILE__, __LINE__, key_str); + exit(1); + return(0); // Never taken. + } + +// ============================================================================ +void +rv_cfg_c_dump_yaml_c(char *yaml_filename) + { + struct fy_document *fyd = NULL; + + fyd = fy_document_build_from_file(NULL, yaml_filename); + fy_emit_document_to_fp(fyd, FYECF_DEFAULT | FYECF_SORT_KEYS, stdout); + free(fyd); + } + +// ============================================================================ +int +rv_cfg_s_int(sail_int *zret_int, char * yaml_key_str) + { +// printf("%s, %d: entering rv_cfg_s_int()\n", __FILE__, __LINE__); + mpz_set_ui(*zret_int, rv_cfg_c_int(yaml_key_str)); + return(1); + } + +// ============================================================================ +int +//rv_cfg_s_string(sail_string **s, char * yaml_key_str) +rv_cfg_s_string(sail_string s, char * yaml_key_str) + { +// printf("%s, %d: entering rv_cfg_string()\n", __FILE__, __LINE__); + s = rv_cfg_c_string(yaml_key_str); + return(1); + } + +// ============================================================================ +unit +rv_cfg_s_dump_yaml(char *yaml_filename) + { + rv_cfg_c_dump_yaml(yaml_filename); + } + diff --git a/c_emulator/rv_cfg_func.h b/c_emulator/rv_cfg_func.h new file mode 100644 index 000000000..036bd76a0 --- /dev/null +++ b/c_emulator/rv_cfg_func.h @@ -0,0 +1,85 @@ +// vim: set tabstop=4 shiftwidth=4 expandtab +// ============================================================================ +// Filename: rv_cfg_func.h +// +// Description: Functions prototype support for rv_cfg +// +// Author(s): Bill McSpadden (bill@riscv.org) +// +// Revision: See git log +// ============================================================================ + +#pragma once + +#include "sail.h" +#include +#include +#include "riscv_platform_impl.h" + +//This macro must be defined before including pcre2.h. For a program that uses +//only one code unit width, it makes it possible to use generic function names +//such as pcre2_compile(). +#define PCRE2_CODE_UNIT_WIDTH 8 +#include + +// ================================================== +// typedefs and structs + +// Keep these in monotonically increasing linear order +// as they are used as indices into an array where the +// index is the enum. +typedef enum + { + RV_CFG_ISA = 0, + RV_CFG_PLATFORM = 1, + RV_CFG_DEBUG = 2, + RV_CFG_LAST = 3 + } rv_cfg_e; + +typedef struct rv_cfg_enum2string_tt + { + rv_cfg_e e; + char * s; + } rv_cfg_enum2string_t; + +typedef struct rv_cfg_enum2doc_tt + { + rv_cfg_e e; + struct fy_document * fyd; + char * filename; + } rv_cfg_enum2doc_t; + +// ================================================== +// Function prototypes just for the C side of things. +// The items in this section should only be used on +// the C side of the simulator. + +int rv_cfg_c_init(void); +char * rv_cfg_c_get_string(rv_cfg_e e); +rv_cfg_e rv_cfg_c_get_enum(char * s); +int rv_cfg_c_build_from_file(rv_cfg_e rv_cfg_type, char * filename ); +unsigned int rv_cfg_c_int(char *); +char * rv_cfg_c_string(char *); +bool rv_cfg_c_bool(char *); +int rv_cfg_c_configure(void); +void rv_cfg_c_dump_yaml(char *); +int rv_cfg_c_ext_enable(char * isa_str, char * ext_pattern); +bool rv_cfg_c_bool(char * key_str); +bool rv_cfg_c_path_exists(char * path); + + + +// ================================================== +// Function prototypes for the Sail interface + +// It doesn't appear that Sail does anything with the +// function's return value. "return values" are done +// by passing a pointer to a return value struct, which +// is the first element in the function's argument list. + +int rv_cfg_s_int(sail_int *, char *); +int rv_cfg_s_string(sail_string , char *); +bool rv_cfg_s_bool(sail_string , char *); +unit rv_cfg_s_dump_yaml(char *); + +//#endif diff --git a/cookbook/doc/Makefile b/cookbook/doc/Makefile new file mode 100644 index 000000000..6ea49d8fd --- /dev/null +++ b/cookbook/doc/Makefile @@ -0,0 +1,80 @@ +# vim: set tabstop=4 shiftwidth=4 noexpandtab +# ================================================================ +# Filename: Makefile +# +# Description: Makefile for building a complete RISC-V Sail cookbook +# +# asciidoctor-reducer needs to be installed +# +# Because github does not handle 'include' directives, +# we use asciidoctor-reducer to pull in the various +# include files into one adoc file which can be +# rendered by github. +# +# NOTE: Some git trickery is needed in order to ensure that +# the complete file has been compiled to the latest +# level and then committed. See the .git/hooks/pre-commit +# and .git/hooks/post-commit so see how this is done. +# +# Author(s): Bill McSpadden (bill@riscv.org) +# +# Revision: See git logs +# +# ================================================================ + +#============== +# Includes +#============== + + +#============== +# Make variables +#============== + +FINAL_ADOC_TARGET := TheRISCVSailCookbook_Complete.adoc +TOP_ADOC_FILE := TheRISCVSailCookbook_Main.adoc +FINAL_PDF_TARGET := TheRISCVSailCookbook_Complete.pdf + +ALL_DEPENDENCIES := +CODE_SNIPPETS_DIR := ../functional_code_examples +ALL_DEPENDENCIES += + +# hello_world example +#HELLO_WORLD_DIR := ${CODE_SNIPPETS_DIR}/hello_world +#HELLO_WORLD_FILES := ${HELLO_WORLD_DIR}/hello_world.sail ${HELLO_WORLD_DIR}/Makefile + +ALL_DEPENDENCIES += ${HELLO_WORLD_FILES} + + +TMP_ADOC := ./tmp.adoc + +#============== +# Targets and rules +#============== +all : ${FINAL_ADOC_TARGET} ${FINAL_PDF_TARGET} + +echo_final_adoc_target : + echo ${FINAL_ADOC_TARGET} ; + + +${FINAL_ADOC_TARGET} : ${TOP_ADOC_FILE} ${ALL_DEPENDENCIES} + asciidoctor-reducer $< -o $@ ; + rm -f ${TMP_ADOC} ; + echo "// =========================================================================" >> ${TMP_ADOC} ; + echo "// DO NOT EDIT. AUTOGENERATED FILE. You probably want to edit $<" >> ${TMP_ADOC} ; + echo "// =========================================================================" >> ${TMP_ADOC} ; + mv $@ $@.tmp ; + cat ${TMP_ADOC} $@.tmp > $@ ; + rm -f $@.tmp ${TMP_ADOC} ; + +${FINAL_PDF_TARGET} : ${FINAL_ADOC_TARGET} + asciidoctor-pdf $< + + +.PHONY: clean +clean: + rm -f ${FINAL_ADOC_TARGET} ${FINAL_PDF_TARGET} ${TMP_ADOC} + + + + diff --git a/cookbook/doc/RISCV_model_FAQ.adoc b/cookbook/doc/RISCV_model_FAQ.adoc new file mode 100644 index 000000000..051816aab --- /dev/null +++ b/cookbook/doc/RISCV_model_FAQ.adoc @@ -0,0 +1,95 @@ +=== Frequently Asked Questions about the Sail RISC-V Golden Model + +<> + +<> + +<> + +<> + +<> + +<> + +<> + +<> + +<> + + +[#q_is_there_support_for_multi_hart_multi_core_simulation] +==== Q: Is there support for multi-HART or multi-Core simulation? + +A: There is no inherent support for multi-HART or multi-Core within the existing RISC-V Sail model. +There are future plans for adding this kind of simulation. It is needed in order to simulate +(in a meaningful way) the atomic memory operations and to evaluate memory consistency +and coherency. + +// ( The following is from email between Bill McSpadden and Martin Berger ) +// ( Subject: RISC-V Sail model questions, round 1: Multi-core, MTIMER, MMIO, main loop) +// ( Date: Feb 15, 2022, 7:20AM) + +The model isn't directly about testing. Testing is a separate +activity. The point of the model is to be as clear as possible. and we +should keep testing and the model separate. + +// ( The following is from email between Bill McSpadden and Martin Berger ) +// ( Subject: RISC-V Sail model questions, round 1: Multi-core, MTIMER, MMIO, main loop) +// ( Date: Feb 15, 2022, 7:20AM) + +[#q_what_are_ml_files__what_are_their_purpose] +==== Q: What are .ml files? What are their purpose? + +A: These are OCaml files. They are to the ocaml emulator what the .c +files are to the c emulator. I question the need for an OCaml emulator +,see also https://github.com/riscv/sail-riscv/issues/138 + +[#q__is_there_any_support_for_MTIMER] +==== Q: Is there any support for MTIMER? + +A: Yes. MTIMER functionality lives in riscv_platform.sail. At this date (2022-05-27) it lives +at a fixed MMIO space as specified by the MCONFIG CSR. In the future, once the Golden Model supports +the RISCV_config YAML structure, the MTIMER can be assigned any address. + +[#q__is_the__main_loop__coded_in_Sail] +==== Q: Is the "main loop" coded in Sail? + +A: The initial answer to this question ("The main execution loop can be found in `main.sail``.") +is incorrect. main.sail is not executed in the RISC-V model, even though it is +compiled into the model. + +The main loop is actually found on the C side in the file `c_emulator/riscv_sim.c` +in the function `run_sail()``. In this function, the Sail function, `zstep()`, is +called (which is the Sail function, `step()` ) + +[#q-can-gdb-attach-to-the-riscv-golden-model-to-debug-riscv-code] +==== Q: Can gdb attach to the RISCV Golden Model to debug RISCV code? + +A: Not at this time (2022-05-27). It is being looked at as an enhancement. + +[#q__why_two_executables] +==== Q: There are two C executables built: riscv_sim_RV32 and riscv_sim_RV64. Is there a reason why we need two executables? Can't XLEN be treated as a run-time setting rather than a compile time setting? + +A: (Response from Martin Berger) I think this would require a redesign of the Sail code because of the way Sail's liquid types work. Currently xlen is a global type constant, that is used, directly or indirectly, everywhere. As a type-constant it is used during type checking. The typing system might (note the subjunctive) be flexible enough to turn this into a type-parameter, but probably not without major code surgery. I think we should ask the Cambridge team why they decided on the current approach. + +[#q___is_there_support_in_the_model_for_misaligned_memory_accesses] +==== Q: Is there support in the model for misaligned memory accesses? + +A: (Response from Martin Berger) Short answer: I don't know. Alignment stuff is distributed all over the code base. riscv_platform.sail has some configuration options for this. Maybe that's a place to start looking? + + +// ( The following is some sample questions based on HGttG,Hitchhikers Guide to the Galax) + +[#q-what-is-the-meaning-of-life-the-universe-and-everything] +==== Q: What is the meaning of life, the universe and everything? + +A: 42 + +[#q-what-does-the-answer-to-what-is-the-meaning-of-life-the-universe-and-everything-mean] +==== Q: What does the answer to "What is the meaning of life, the universe and everything" mean? + +A: One must construct an experimental, organic computer to compute the meaning. +Project 'Earth' is one such computer. Timeframe for an expected answer is... soon. + diff --git a/cookbook/doc/TheRISCVSailCookbook_Complete.adoc b/cookbook/doc/TheRISCVSailCookbook_Complete.adoc new file mode 100644 index 000000000..e8a50e8c2 --- /dev/null +++ b/cookbook/doc/TheRISCVSailCookbook_Complete.adoc @@ -0,0 +1,927 @@ +// ========================================================================= +// DO NOT EDIT. AUTOGENERATED FILE. You probably want to edit TheRISCVSailCookbook_Main.adoc +// ========================================================================= +:doctype: book +:sectids: +The RISCV Sail Golden Model: A Cookbook for the RISCV ISA +========================================================= +William C. McSpadden ; Martin Berger + +:toc: +:toc-placement: preamble +:toclevels: 2 + +:showtitle: + +// Need some preamble to get TOC +{empty} + + +[#list_of_programming_examples] +== List of programming examples (in increasing complexity) + +The main purpose of this document, is to give the user a set +of programming examples for working on the RISC-V Sail model +(often referred to as the RISC-V Golden Model). The examples +will show the user how to change or extend the model. And it +will also show the user how to write a RISC-V program (in both +assembler and C) and then run it on the Golden Model. + +You should read and utilize this document after you have a good +handle on the Sail programming language. + +<> + +<> + + +:sectnums: +== Introduction + + + +== How to contribute (Bill) + + +=== Coding and indentation style + + +=== Brevity + +Program examples should be short, both in terms of number-of-lines and in terms of execution time. +Each example should focus on one simple item. And the execution of the example item should be clear. +The example should be short, standalone and easy to maintain. + + +=== Maintainership (when something breaks) + +We would also ask that if you contribute a code example, that you would maintain it. + +== Sail installation + +TBD + +=== Ubuntu (Bill Mc.) + +TBD + +=== MacOS (Martin) + +TBD + +=== Docker + +Docker is used as a .... + +=== Windows + + +=== Windows: Cygwin (Bill Mc., low priority) + + +=== Other? + + +== Basic description +=== What Sail is +Sail is a programming language that is targetted for + specifying an ISA. Once specified, a set of +instructions (usually found in a .elf file) can then +be executed on the "model" and the results observed. + +The model is a sequential model only; at this time, +there are no semantics allowing for any type of parallel +execution. + +=== What sail is not +Sail is not an RTL (Register Transfer Language). +There is no direct support for timing (as in clock +timing) and there is no support for parallel execution, +all things that an RTL contains. + +=== version management and what to expect +TBD + +[#platform-configuration] +== Platform Configuration example (Bill) + +TBD + +// All code and asciidoc description for "add a new extension" +// is in the functional code example directory. +[#add-a-new-extension] +== Example: Add A New Extension and a New CSR + +The main purpose of this cookbook, is to explain how someone can add +an extension (and a CSR) to the RISC-V Sail model. This example attempts +to add a very simple instruction and a very simple CSR to the model. One +instruction will be added into the custom opcode space. And that +instruction will be used to manipulate the new CSR, which can then +be accessed by the existing CSR instructions. + +This is an example of what *is*, not necessarily what it should be. +This follows a pattern from the existing code. + +First, we will walk through the pertinent sections of the RISC-V specifications +to see what the specifications have to say about adding instructions. + +Let's start with the Unprivileged Specification + +image:images/UnprivTitle.png[] + +Chapter 26 of the Unpriv Spec ("Extending RISC-V") describes how you can extend +the RISC-V instruction set. In this chapter, we find the following... + +image:images/unpriv_ch26_1_non_standard_encoding_space.png[] + +This encoding space can be found in chapter 24 in the instruction space listings. +This where you go to find encoding space that has been reserved for custom +extensions. + +You should be familiar with the various types of encodings that RISC-V +has defined. These can be found in chapter 2 of the UnPriv Spec. Here +are the very basic encodings... + +image:images/unpriv_ch2_2_base_instruction_formats.png[] + +Almost certainly you will want to use one of these formats, as all existing +RISC-V instructions use one of these types or their variants. Now, having +said all that, this example is going to do something a bit different. +For the purposes of this example, I simply wanted to create a single +instruction that has the side effect of writing a custom CSR with an immediate +value. So, when we get to the Sail implementation of the instruction, you will +see that I created a new type, and X-type. [red]#WARNING: this is not a +pattern you should follow. This is for educational purposes only.# + +Now, let's figure out what opcode bits you should use. Go to chapter +24 of the UnPriv Spec. + +See unpriv spec, chapter 24, "RV32/64G Instruction Set Listings" + +image:images/unpriv_ch24_inst_set_listings.png[] + +Here we see the opcode bits (bits 6::0) that can be used for a 32-bit opcode. +This is imporatant. If you stray into other opcode space, you will almost +certainly end up hurting yourself and creating confusion. + +At this point, I should mention that are naming conventions for extensions that +get added to the instructions set. See unpriv spec, chapter 27, +"ISA Extension Naming Convention", especially +setion 27.10, "Non-Standard Extension Names". Following is the pertinent +portion.... + +image:images/unpriv_ch27_10_non_standard_extension_names.png[] + +For this example, we are adding a single instruction: xmpl. The name +for this particular extension will be called "Xxmpl". + +Now that we've covered the instruction and its name and its opcode, let's +move on to the addition of a new CSR. First, we need to move to the +Priv Spec. Why? Because inherent in the access of the CSR is the +concept of privilege. CSRs are typically have some sort of privilege mode +associated with them. So, go the Priv Spec, go to chapter 2 and look at +Table 2.1 (which is reprinted below). Within this table, you will see several +regions that are used for custom implementations. + +image:images/PrivTitle.png[] + + +See priv spec, chapter 2, "CSR Listings", Table 2.1 + +image:images/AllocationOfRISCV_CSRs.png[] + +For the purpose of this example, we are going to use the region +that is marked with a black rectangle. The CSR will be a custom +read-only CSR that can only be accessed from the machine privilege +level. + +So now that we've seen what the specifications say, let's take a look at +what that means for the Sail model. + +Note: there is a coding style guideline at the top of this github +repository (CODE_STYLE.md). I have attempted to follow the style in the example. +If you add code to the model, please make the effort to follow the +coding guidelines. + +First, let's be clear what we're going to implement in this example. + +Single instruction: xmpl + +CSR: xmpl_csr + +* Takes an unsigned immediate and puts the value into the xmpl_csr +* The +xmpl_csr+ can be read by the normal CSR instructions. +* +xmpl_csr+ cannot be written with any form of the CSR instructions; +it should generate an exception. + +As you will see in this example, adding an instruction is actually +pretty simple. It only requires the addition of one file and the modification +of the top level Makefile. Adding a CSR is actually a bit more complicated; +no new file is needed, but no less than 5 files need to be touched. + +Following is the list of files that will be added/touched for this example. +We'll walk through each one of them, one by one. However, a lot of the +code will be obvious. + +Files: + +* (new) model/riscv_insts_custom_xmpl.sail : the implmentation of the instruction and the CSR. +* (exists) Makefile : must add riscv_insts_xample.sail to the list of source files +* (exists) model/riscv_types.sail : need to add new instruction to the proper instruction opcode grouping. +* (exists) model/riscv_csr_map.sail : the address map of the CSR registers. +* (exists) mpodel/iscv_insts_zicsr.sail : need to add new CSR functionality. +* (exists) model/riscv_csr_map.sail : need to add new CSR name to the mapping +* (exists) model/riscv_sys_control.sail : need to add the new CSR name to the list found in is_CSR_defined(). +* (new) cookbook/functional_code_examples/add_a_new_extension/test.S : for testing the new instruction features + +Following is the file that implements the xmpl instruction. + +model/riscv_insts_custom_xmpl.sail: + +[source, sail] +---- +// vim: set tabstop=2 shiftwidth=2 expandtab +// ============================================================================ +// Filename: riscv_insts_custom_xmpl.sail +// +// Description: Example for adding a custom instruction, xmpl, to the RISCV model +// +// Author(s): Bill McSpadden (bill@riscv.org) +// +// Revision: See revision control log +// ============================================================================ + +/* ********************************************************************* */ +/* This file specifies an example custom instruction */ +/* It can also be used as an example when adding other ratified */ +/* extensions (while also using the ISA nomenclature). */ + +union clause ast = XTYPE : (bits(25), xop) + +mapping encdec_x_xmpl : xop <-> bits(7) = { + RISCV_X_XMPL <-> 0b0101011 // inst[6:5] == 01, inst[4:2] == 010 --> custom-0 +} + +mapping clause encdec = XTYPE(imm, xop) + <-> imm @ encdec_x_xmpl(xop) + + +function clause execute (XTYPE(imm, xop)) = { + let csr_val : bitvector(25, dec) = imm; + xmpl_csr_2->FieldWARL() = csr_val ; + RETIRE_SUCCESS +} + +mapping x_xmpl_mnemonic : xop <-> string = { + RISCV_X_XMPL <-> "x.xmpl" +} + +mapping clause assembly = XTYPE(imm, xop) + <-> x_xmpl_mnemonic(xop) ^ " " ^ hex_bits_25(imm) + + + + + + + + + + + +---- + +We now need to change the top-level makefile to bring in this new file. + +Makefile (around lines 26-37): +``` +SAIL_DEFAULT_INST += riscv_insts_zba.sail +SAIL_DEFAULT_INST += riscv_insts_zbb.sail +SAIL_DEFAULT_INST += riscv_insts_zbc.sail +SAIL_DEFAULT_INST += riscv_insts_zbs.sail + +SAIL_DEFAULT_INST += riscv_insts_zfh.sail + +SAIL_DEFAULT_INST += riscv_insts_zkn.sail +SAIL_DEFAULT_INST += riscv_insts_zks.sail + +SAIL_DEFAULT_INST += riscv_insts_zbkb.sail +SAIL_DEFAULT_INST += riscv_insts_zbkx.sail + +# Example custom extension (do not include this in the +# usual model build.) +SAIL_DEFAULT_INST += riscv_insts_custom_xmpl.sail +``` + +//model/riscv_types.sail : need to add new instruction to the proper instruction opcode grouping. +//``` +//TODO: What changes did I make to this file???? +// Apparently, I did nothing +//``` + +The new CSR (actually 2 CSRs; I was playing around with the +Sail capabilities of mappings, so you will see references to two) +need a mapping from their address to their names. This is done +in the following file. + +model/riscv_csr_map.sail (around lines 115-120): +``` +. +. +mapping clause csr_name_map = 0xF11 <-> "mvendorid" +mapping clause csr_name_map = 0xF12 <-> "marchid" +mapping clause csr_name_map = 0xF13 <-> "mimpid" +mapping clause csr_name_map = 0xF14 <-> "mhartid" +mapping clause csr_name_map = 0xFC0 <-> "xmpl_csr" // Custom CSR example +mapping clause csr_name_map = 0xFC1 <-> "xmpl_2_csr" // Custom CSR example +. +. + +``` + +The code that actually does the reads/writes to the CSRs using the +Zicsr extension instructions is found in the following file. Note +that only the Read of the CSR is supported, no writes. This was done +to check out what happens when you try to write a read-only register. + +model/iscv_insts_zicsr.sail (around line 137): +``` +. +. +function readCSR csr : csreg -> xlenbits = { + let res : xlenbits = + match (csr, sizeof(xlen)) { + . + . + /* machine mode, custom extension example */ + (0xFC0, _) => xmpl_csr, // error: Xmpl_csr is not a subtype of bitvector(32, dec) + (0xFC1, _) => xmpl_csr_2.bits(), + . + . +``` + +The following file provides a function to see if the CSR is defined. + +model/riscv_sys_control.sail (within function +is_CSR_defined()+ ): +``` +function is_CSR_defined( csr : csreg, p : Privilege) -> bool = +. +. + /* custom CSRs */ + 0xFC0 => p == Machine, // xmpl_csr Example custom csr + 0xFC1 => p == Machine, // xmpl_csr_2 Example custom csr +. +. + +``` +And with that, we have completed the implementation of the CSR for this +example. At this point, you should probably try and compile. Got to the +root directory of your repo, and run... + +``` +make ARCH=RV32 csim +``` + +If you've made it this fair, you need to do a little testing of your new +instruction and your new CSR. However, your GNU assembler (or whatever it +is that you're using) probably has no idea what +xmpl+ is. So, how do you +write some assembly code to test out your new instruction? Let's take +a look at one way to test the new instruction. + + +cookbook/functional_code_examples/add_a_new_extension/test.S : for testing the new instruction features + +[source, assembler] +---- + 1 // vim: tabstop=2 shiftwidth=2 expandtab + 2 // -------------------------------------------------------------------------------------------- + 3 /// @file test.S + 4 /// + 5 /// + 6 /// @brief RISC-V asm code for testing an example custom instruction + 7 /// + 8 /// @author Bill McSpadden (RISC-V Internation) (bill@riscv.org) + 9 // -------------------------------------------------------------------------------------------- + 10 + 11 #ifndef CONFIG_BASE + 12 #error The C pre-processor variable, CONFIG_BASE, must be set. + 13 #endif + 14 + 15 // -------------------------------------------------------- + 16 // Support for a custom extension + 17 + 18 #define X_XMPL_OPCODE (0x2b) // inst[6:5] == 01, inst[4:2] == 1011 --> custom-0 + 19 #define X_XMPL(__imm__) .word (__imm__ << 7) | (X_XMPL_OPCODE << 0) + 20 + 21 #define XO (0) + 22 #define X1 (1) + 23 #define X2 (2) + 24 #define X3 (3) + 25 #define X4 (4) + 26 #define X5 (5) + 27 #define X6 (6) + 28 #define X7 (7) + 29 #define X8 (8) + 30 #define X9 (9) + 31 #define X10 (10) + 32 #define X11 (11) + 33 #define X12 (12) + 34 #define X13 (13) + 35 #define X14 (14) + 36 #define X15 (15) + 37 #define X16 (16) + 38 #define X17 (17) + 39 #define X18 (18) + 40 #define X19 (19) + 41 #define X20 (20) + 42 #define X21 (21) + 43 #define X22 (22) + 44 #define X23 (23) + 45 #define X24 (24) + 46 #define X25 (25) + 47 #define X26 (26) + 48 #define X27 (27) + 49 #define X28 (28) + 50 #define X29 (29) + 51 #define X30 (30) + 52 #define X31 (31) + 53 + 54 + 55 + 56 + 57 // -------------------------------------------------------- + 58 // Memory-mapped machine timer registers and other support + 59 // for generating a timer interrupt + 60 + 61 //#define MMR_MTIMEL (CONFIG_BASE + 0x0000) + 62 //#define MMR_MTIMEH (CONFIG_BASE + 0x0004) + 63 //#define MMR_MTIMECMPL (CONFIG_BASE + 0x0008) + 64 //#define MMR_MTIMECMPH (CONFIG_BASE + 0x000C) + 65 + 66 #define MMR_MTIMEL (CONFIG_BASE + 0xbff8) + 67 #define MMR_MTIMEH (CONFIG_BASE + 0xbffc) + 68 #define MMR_MTIMECMPL (CONFIG_BASE + 0x4000) + 69 #define MMR_MTIMECMPH (CONFIG_BASE + 0x4004) + 70 + 71 #define TIMER_COUNT (100) + 72 #define WATCHDOG_COUNT (100000) + 73 + 74 #define MSTATUS_MIE 0x00000008 + 75 #define MSTATUS_FS 0x00006000 + 76 #define MSTATUS_XS 0x00018000 + 77 + 78 #define MIE_MTIE 0x80 + 79 + 80 + 81 // -------------------------------------------------------- + 82 // mcause bit definitions + 83 + 84 #define MCAUSE_SUPERVISOR_SOFTWARE_INTERRUPT (0x1 << (__riscv_xlen - 1) + 1) + 85 #define MCAUSE_MACHINE_TIMER_INTERRUPT (0x1 << (__riscv_xlen - 1) + 7) + 86 #define MCAUSE_ILLEGAL_INSTRUCTION (0x0 << (__riscv_xlen - 1) + 2) + 87 + 88 // -------------------------------------------------------- + 89 // Support for tohost/fromhost + 90 + 91 #define PASS_CODE 1 + 92 #define FAIL_CODE 1337 + 93 + 94 + 95 // -------------------------------------------------------- + 96 // Support for 32/64 bit compilation. + 97 + 98 #if __riscv_xlen == 64 + 99 # define LREG ld + 100 # define SREG sd + 101 # define REGBYTES 8 + 102 #else + 103 # define LREG lw + 104 # define SREG sw + 105 # define REGBYTES 4 + 106 #endif + 107 + 108 #define XMPL_CSR (0xfc0) + 109 #define XMPL_CSR_2 (0xfc1) + 110 + 111 // -------------------------------------------------------- + 112 // Following power-on reset, we start executing at _start. + 113 // We jump to "reset_vector" + 114 // + 115 .section ".text.init" + 116 .globl _start + 117 _start: + 118 la x5, reset_vector + 119 jr x5 + 120 // -------------------------------------------------------- + 121 + 122 + 123 // -------------------------------------------------------- + 124 // Initialization of the processor, starting with the + 125 // register file. + 126 reset_vector: + 127 li x1, 0 + 128 li x2, 0 + 129 li x3, 0 + 130 li x4, 0 + 131 li x5, 0 + 132 li x6, 0 + 133 li x7, 0 + 134 li x8, 0 + 135 li x9, 0 + 136 li x10, 0 + 137 li x11, 0 + 138 li x12, 0 + 139 li x13, 0 + 140 li x14, 0 + 141 li x15, 0 + 142 li x16, 0 + 143 li x17, 0 + 144 li x18, 0 + 145 li x19, 0 + 146 li x20, 0 + 147 li x21, 0 + 148 li x22, 0 + 149 li x23, 0 + 150 li x24, 0 + 151 li x25, 0 + 152 li x26, 0 + 153 li x27, 0 + 154 li x28, 0 + 155 li x29, 0 + 156 li x30, 0 + 157 li x31, 0 + 158 + 159 // -------------------------------------------------------- + 160 // PMP configuration + 161 + 162 # configure pmp to enable all accesses + 163 li t0, 0x1f + 164 csrw pmpcfg0, t0 + 165 li t0, 0xffffffff + 166 csrw pmpaddr0, t0 + 167 + 168 // -------------------------------------------------------- + 169 // initialize machine trap vector + 170 la x5, machine_trap_entry + 171 csrw mtvec, x5 + 172 + 173 + 174 // -------------------------------------------------------- + 175 // The test! + 176 + 177 the_test_begin: + 178 X_XMPL(0x0dead) + 179 csrr x3, XMPL_CSR_2 + 180 + 181 // li x4, 0x76543210 + 182 // csrw XMPL_CSR_2, x4 // Q: What happens to a write to a read-only csr? + 183 // // A: illegal_instruction trap + 184 the_test_end: + 185 + 186 + 187 + 188 + 189 // -------------------------------------------------------- + 190 // PASS: The end of the test, if successful + 191 j_target_end_pass: + 192 // exit code construction + 193 li x10, PASS_CODE + 194 la x13, tohost + 195 sw x10, 0(x13) + 196 la x5, j_target_end_pass + 197 jalr x5 + 198 j j_target_end_fail // should never be taken + 199 + 200 // -------------------------------------------------------- + 201 + 202 // -------------------------------------------------------- + 203 // FAIL: The end of the test, if unsuccessful + 204 j_target_end_fail: + 205 // exit code construction + 206 li x10, FAIL_CODE + 207 la x13, tohost + 208 sw x10, 0(x13) + 209 la x5, j_target_end_fail + 210 jalr x5 + 211 + 212 + 213 // -------------------------------------------------------- + 214 // In support of vectored interrupt, although it's not + 215 // being used in this test. + 216 + 217 .align 4 + 218 machine_trap_entry: + 219 j machine_trap_entry_0 + 220 .align 2 + 221 j machine_trap_entry_1 + 222 .align 2 + 223 j machine_trap_entry_2 + 224 .align 2 + 225 j machine_trap_entry_3 + 226 .align 2 + 227 j machine_trap_entry_4 + 228 .align 2 + 229 j machine_trap_entry_5 + 230 .align 2 + 231 j machine_trap_entry_6 + 232 .align 2 + 233 j machine_trap_entry_7 + 234 .align 2 + 235 j machine_trap_entry_8 + 236 .align 2 + 237 j machine_trap_entry_9 + 238 .align 2 + 239 j machine_trap_entry_10 + 240 .align 2 + 241 j machine_trap_entry_11 + 242 // -------------------------------------------------------- + 243 + 244 + 245 // -------------------------------------------------------- + 246 .align 2 + 247 machine_trap_entry_0: + 248 csrr x7, mcause + 249 li x6, MCAUSE_MACHINE_TIMER_INTERRUPT + 250 bne x7, x6, not_a_timer_interrupt + 251 li x6, 0x1 + 252 la x7, timer_interrupt_flag + 253 sw x6, 0(x7) + 254 + 255 // Turn off timer interrupt. No longer needed + 256 addi x7, x0, MIE_MTIE + 257 csrc mie, x7 + 258 + 259 // Clear interrupt + 260 li x7, MSTATUS_MIE + 261 csrc mstatus, x7 + 262 + 263 // and return + 264 mret + 265 + 266 not_a_timer_interrupt: + 267 // Do not try and correct the opcode, and do not + 268 // do an mret. This should probably be the last + 269 // part of this simple test. + 270 csrr x7, mcause + 271 li x6, MCAUSE_ILLEGAL_INSTRUCTION + 272 j j_target_end_fail + 273 // -------------------------------------------------------- + 274 + 275 // -------------------------------------------------------- + 276 // None of these machine traps should have been taken + 277 // Jump to test failure + 278 machine_trap_entry_1: + 279 machine_trap_entry_2: + 280 machine_trap_entry_3: + 281 machine_trap_entry_4: + 282 machine_trap_entry_5: + 283 machine_trap_entry_6: + 284 machine_trap_entry_7: + 285 machine_trap_entry_8: + 286 machine_trap_entry_9: + 287 machine_trap_entry_10: + 288 machine_trap_entry_11: + 289 csrr x7, mcause // Do the read so that it appears in the log file for debug. + 290 j j_target_end_fail + 291 // -------------------------------------------------------- + 292 + 293 + 294 + 295 // -------------------------------------------------------- + 296 // Memory locations for specific usage. + 297 .section ".tdata.begin" + 298 .globl _tdata_begin + 299 _tdata_begin: + 300 + 301 .section ".tdata.end" + 302 .globl _tdata_end + 303 _tdata_end: + 304 + 305 .section ".tbss.end" + 306 .globl _tbss_end + 307 _tbss_end: + 308 + 309 .section ".tohost","aw",@progbits + 310 .align 6 + 311 .globl tohost + 312 tohost: .dword 0 + 313 + 314 .section ".fromhost","aw",@progbits + 315 .align 6 + 316 .globl fromhost + 317 fromhost: .dword 0 + 318 + 319 .align 6 + 320 .global timer_interrupt_flag + 321 timer_interrupt_flag: .dword 0 + 322 + 323 + 324 + 325 +---- + + + + +What does the test.dump file look like? Remember, the RISC-V assembler knows nothing +about the custom instruction we have added. + +cookbook/functional_code_examples/add_a_new_extension/test.dump: +``` + . + . + 89 80000062 : + 90 80000062: 0dead12b 0xdead12b + 91 80000066: fc1021f3 csrr gp,0xfc1 + . + . +``` + +Note that the disassembler has no idea what to do with the opcode, +0x0dead12b+. +So, it just leaves it as a word at location +0x80000062+. + +Now that you've compiled an assembly language program +and gotten a .elf file, you are now ready to run it against +your model. The executable is found at: +/c_emulator/riscv_sim_RV32+. +To run the simulation from the example directory, perform the following... + +``` +../../../c_emulator/riscv_sim_RV32 test.elf +``` + +The simulator will send its output to stdout. You can capture it in the +usual file I/O redirection method. + + +What does the Sail log look like? +``` +. +. + 424 model/riscv_step.sail + 425 model/riscv_step.sail:75.25-75.32 + 426 entering step() function... + 427 + 428 mem[X,0x80000062] -> 0xD12B + 429 mem[X,0x80000064] -> 0x0DEA + 430 [41] [M]: 0x80000062 (0x0DEAD12B) x.xmpl 1824162 + 431 + 432 + 433 model/riscv_step.sail + 434 model/riscv_step.sail:75.25-75.32 + 435 entering step() function... + 436 + 437 mem[X,0x80000066] -> 0x21F3 + 438 mem[X,0x80000068] -> 0xFC10 + 439 [42] [M]: 0x80000066 (0xFC1021F3) csrrs gp, xmpl_2_csr, zero + 440 CSR xmpl_2_csr -> 0x001BD5A2 + 441 x3 <- 0x001BD5A2 +. +. + +``` + +Note that on line 430, we see the execution of the custom instruction +and notice that the simlutor knows how to decode the instruction. On line 439, +we see that the normal RISCV instriucion, +csrrs+, can successfully read the +CSR. Woohoo! + +You will probably have to add command line switches to enable/disable extensions/functionality. +Files that need to be touched are: + +* (exists) c_emulator/riscv_sim.c : implements the longopts functionality +* (exists) model/riscv_sys_regs.sail : function signatures for sys_enable_XXX() functionms. +* (exists) c_emulator/riscv_platform_impl.* : global variables for holding enabled state vars +* (exists) c_emulator/riscv_platform.c : implements the C functions that will be made available to Sail; +functions like sys_enable_zfinx(). + +This is actually a separate topic that requires its own example +and will be added soon. + + +Other goals: + +* Demonstrate the experimental switch +* Demonstrate how to code WARL fields based on settings in the YAML files. + + + +== FAQs (Frequently Asked Questions) + +Following are a set of FAQs that were generated via set of questions to the Sail developers. + +=== Frequently Asked Questions about the Sail RISC-V Golden Model + +<> + +<> + +<> + +<> + +<> + +<> + +<> + +<> + +<> + + +[#q_is_there_support_for_multi_hart_multi_core_simulation] +==== Q: Is there support for multi-HART or multi-Core simulation? + +A: There is no inherent support for multi-HART or multi-Core within the existing RISC-V Sail model. +There are future plans for adding this kind of simulation. It is needed in order to simulate +(in a meaningful way) the atomic memory operations and to evaluate memory consistency +and coherency. + +// ( The following is from email between Bill McSpadden and Martin Berger ) +// ( Subject: RISC-V Sail model questions, round 1: Multi-core, MTIMER, MMIO, main loop) +// ( Date: Feb 15, 2022, 7:20AM) + +The model isn't directly about testing. Testing is a separate +activity. The point of the model is to be as clear as possible. and we +should keep testing and the model separate. + +// ( The following is from email between Bill McSpadden and Martin Berger ) +// ( Subject: RISC-V Sail model questions, round 1: Multi-core, MTIMER, MMIO, main loop) +// ( Date: Feb 15, 2022, 7:20AM) + +[#q_what_are_ml_files__what_are_their_purpose] +==== Q: What are .ml files? What are their purpose? + +A: These are OCaml files. They are to the ocaml emulator what the .c +files are to the c emulator. I question the need for an OCaml emulator +,see also https://github.com/riscv/sail-riscv/issues/138 + +[#q__is_there_any_support_for_MTIMER] +==== Q: Is there any support for MTIMER? + +A: Yes. MTIMER functionality lives in riscv_platform.sail. At this date (2022-05-27) it lives +at a fixed MMIO space as specified by the MCONFIG CSR. In the future, once the Golden Model supports +the RISCV_config YAML structure, the MTIMER can be assigned any address. + +[#q__is_the__main_loop__coded_in_Sail] +==== Q: Is the "main loop" coded in Sail? + +A: The initial answer to this question ("The main execution loop can be found in `main.sail``.") +is incorrect. main.sail is not executed in the RISC-V model, even though it is +compiled into the model. + +The main loop is actually found on the C side in the file `c_emulator/riscv_sim.c` +in the function `run_sail()``. In this function, the Sail function, `zstep()`, is +called (which is the Sail function, `step()` ) + +[#q-can-gdb-attach-to-the-riscv-golden-model-to-debug-riscv-code] +==== Q: Can gdb attach to the RISCV Golden Model to debug RISCV code? + +A: Not at this time (2022-05-27). It is being looked at as an enhancement. + +[#q__why_two_executables] +==== Q: There are two C executables built: riscv_sim_RV32 and riscv_sim_RV64. Is there a reason why we need two executables? Can't XLEN be treated as a run-time setting rather than a compile time setting? + +A: (Response from Martin Berger) I think this would require a redesign of the Sail code because of the way Sail's liquid types work. Currently xlen is a global type constant, that is used, directly or indirectly, everywhere. As a type-constant it is used during type checking. The typing system might (note the subjunctive) be flexible enough to turn this into a type-parameter, but probably not without major code surgery. I think we should ask the Cambridge team why they decided on the current approach. + +[#q___is_there_support_in_the_model_for_misaligned_memory_accesses] +==== Q: Is there support in the model for misaligned memory accesses? + +A: (Response from Martin Berger) Short answer: I don't know. Alignment stuff is distributed all over the code base. riscv_platform.sail has some configuration options for this. Maybe that's a place to start looking? + + +// ( The following is some sample questions based on HGttG,Hitchhikers Guide to the Galax) + +[#q-what-is-the-meaning-of-life-the-universe-and-everything] +==== Q: What is the meaning of life, the universe and everything? + +A: 42 + +[#q-what-does-the-answer-to-what-is-the-meaning-of-life-the-universe-and-everything-mean] +==== Q: What does the answer to "What is the meaning of life, the universe and everything" mean? + +A: One must construct an experimental, organic computer to compute the meaning. +Project 'Earth' is one such computer. Timeframe for an expected answer is... soon. + + + +== Colophon + +This document was prepared on an Ubuntu Linux workstation +using Microsofts VSCode for editing and rendering the asciidoc +text. + ++'shutter'+ was used for screenshots of various parts of the RISCV +specifications and were saved in PNG format. + +These screenshots were then edited using +'gimp'+ to highlight the +pertinent sections of the screenshot. + ++'asciidoctor-reducer'+ was used to combine and resolve all cross-document +references and put them into one .adoc file, TheRISCVSailCookbook_Complate.adoc. + +The pdf was created using +'asciidoctor-pdf'+ . + +See the Makefile, +cookbook/doc/Makefile+, for the recipe for building +the document. diff --git a/cookbook/doc/TheRISCVSailCookbook_Complete.pdf b/cookbook/doc/TheRISCVSailCookbook_Complete.pdf new file mode 100644 index 000000000..813fa4756 Binary files /dev/null and b/cookbook/doc/TheRISCVSailCookbook_Complete.pdf differ diff --git a/cookbook/doc/TheRISCVSailCookbook_Main.adoc b/cookbook/doc/TheRISCVSailCookbook_Main.adoc new file mode 100644 index 000000000..0bacf15db --- /dev/null +++ b/cookbook/doc/TheRISCVSailCookbook_Main.adoc @@ -0,0 +1,137 @@ +:doctype: book +:sectids: +The RISCV Sail Golden Model: A Cookbook for the RISCV ISA +========================================================= +William C. McSpadden ; Martin Berger + +:toc: +:toc-placement: preamble +:toclevels: 2 + +:showtitle: + +// Need some preamble to get TOC +{empty} + + +[#list_of_programming_examples] +== List of programming examples (in increasing complexity) + +The main purpose of this document, is to give the user a set +of programming examples for working on the RISC-V Sail model +(often referred to as the RISC-V Golden Model). The examples +will show the user how to change or extend the model. And it +will also show the user how to write a RISC-V program (in both +assembler and C) and then run it on the Golden Model. + +You should read and utilize this document after you have a good +handle on the Sail programming language. + +<> + +<> + + +:sectnums: +== Introduction + + + +== How to contribute (Bill) + + +=== Coding and indentation style + + +=== Brevity + +Program examples should be short, both in terms of number-of-lines and in terms of execution time. +Each example should focus on one simple item. And the execution of the example item should be clear. +The example should be short, standalone and easy to maintain. + + +=== Maintainership (when something breaks) + +We would also ask that if you contribute a code example, that you would maintain it. + +== Sail installation + +TBD + +=== Ubuntu (Bill Mc.) + +TBD + +=== MacOS (Martin) + +TBD + +=== Docker + +Docker is used as a .... + +=== Windows + + +=== Windows: Cygwin (Bill Mc., low priority) + + +=== Other? + + +== Basic description +=== What Sail is +Sail is a programming language that is targetted for + specifying an ISA. Once specified, a set of +instructions (usually found in a .elf file) can then +be executed on the "model" and the results observed. + +The model is a sequential model only; at this time, +there are no semantics allowing for any type of parallel +execution. + +=== What sail is not +Sail is not an RTL (Register Transfer Language). +There is no direct support for timing (as in clock +timing) and there is no support for parallel execution, +all things that an RTL contains. + +=== version management and what to expect +TBD + +[#platform-configuration] +== Platform Configuration example (Bill) + +TBD + +// All code and asciidoc description for "add a new extension" +// is in the functional code example directory. +include::../functional_code_examples/add_a_new_extension/add_a_new_extension.adoc[] + +== FAQs (Frequently Asked Questions) + +Following are a set of FAQs that were generated via set of questions to the Sail developers. + +include::./RISCV_model_FAQ.adoc[] + + +== Colophon + +This document was prepared on an Ubuntu Linux workstation +using Microsofts VSCode for editing and rendering the asciidoc +text. + ++'shutter'+ was used for screenshots of various parts of the RISCV +specifications and were saved in PNG format. + +These screenshots were then edited using +'gimp'+ to highlight the +pertinent sections of the screenshot. + ++'asciidoctor-reducer'+ was used to combine and resolve all cross-document +references and put them into one .adoc file, TheRISCVSailCookbook_Complate.adoc. + +The pdf was created using +'asciidoctor-pdf'+ . + +See the Makefile, +cookbook/doc/Makefile+, for the recipe for building +the document. + diff --git a/cookbook/doc/images/AllocationOfRISCV_CSRs.png b/cookbook/doc/images/AllocationOfRISCV_CSRs.png new file mode 120000 index 000000000..1e418f58c --- /dev/null +++ b/cookbook/doc/images/AllocationOfRISCV_CSRs.png @@ -0,0 +1 @@ +../../functional_code_examples/add_a_new_extension/images/AllocationOfRISCV_CSRs.png \ No newline at end of file diff --git a/cookbook/doc/images/PrivTitle.png b/cookbook/doc/images/PrivTitle.png new file mode 120000 index 000000000..6af47d38a --- /dev/null +++ b/cookbook/doc/images/PrivTitle.png @@ -0,0 +1 @@ +../../functional_code_examples/add_a_new_extension/images/PrivTitle.png \ No newline at end of file diff --git a/cookbook/doc/images/RISCV_base_instruction_formats.png b/cookbook/doc/images/RISCV_base_instruction_formats.png new file mode 120000 index 000000000..06e45bf57 --- /dev/null +++ b/cookbook/doc/images/RISCV_base_instruction_formats.png @@ -0,0 +1 @@ +../../functional_code_examples/add_a_new_extension/images/RISCV_base_instruction_formats.png \ No newline at end of file diff --git a/cookbook/doc/images/UnprivTitle.png b/cookbook/doc/images/UnprivTitle.png new file mode 120000 index 000000000..6c7ee3250 --- /dev/null +++ b/cookbook/doc/images/UnprivTitle.png @@ -0,0 +1 @@ +../../functional_code_examples/add_a_new_extension/images/UnprivTitle.png \ No newline at end of file diff --git a/cookbook/doc/images/unpriv_ch24_inst_set_listings.png b/cookbook/doc/images/unpriv_ch24_inst_set_listings.png new file mode 120000 index 000000000..5c295bdd1 --- /dev/null +++ b/cookbook/doc/images/unpriv_ch24_inst_set_listings.png @@ -0,0 +1 @@ +../../functional_code_examples/add_a_new_extension/images/unpriv_ch24_inst_set_listings.png \ No newline at end of file diff --git a/cookbook/doc/images/unpriv_ch26_1_non_standard_encoding_space.png b/cookbook/doc/images/unpriv_ch26_1_non_standard_encoding_space.png new file mode 120000 index 000000000..ccbddb262 --- /dev/null +++ b/cookbook/doc/images/unpriv_ch26_1_non_standard_encoding_space.png @@ -0,0 +1 @@ +../../functional_code_examples/add_a_new_extension/images/unpriv_ch26_1_non_standard_encoding_space.png \ No newline at end of file diff --git a/cookbook/doc/images/unpriv_ch27_10_non_standard_extension_names.png b/cookbook/doc/images/unpriv_ch27_10_non_standard_extension_names.png new file mode 120000 index 000000000..bdf2fb040 --- /dev/null +++ b/cookbook/doc/images/unpriv_ch27_10_non_standard_extension_names.png @@ -0,0 +1 @@ +../../functional_code_examples/add_a_new_extension/images/unpriv_ch27_10_non_standard_extension_names.png \ No newline at end of file diff --git a/cookbook/doc/images/unpriv_ch2_2_base_instruction_formats.png b/cookbook/doc/images/unpriv_ch2_2_base_instruction_formats.png new file mode 120000 index 000000000..6d30cf9e1 --- /dev/null +++ b/cookbook/doc/images/unpriv_ch2_2_base_instruction_formats.png @@ -0,0 +1 @@ +../../functional_code_examples/add_a_new_extension/images/unpriv_ch2_2_base_instruction_formats.png \ No newline at end of file diff --git a/cookbook/functional_code_examples/add_a_new_extension/Makefile b/cookbook/functional_code_examples/add_a_new_extension/Makefile new file mode 100644 index 000000000..96f541b08 --- /dev/null +++ b/cookbook/functional_code_examples/add_a_new_extension/Makefile @@ -0,0 +1,164 @@ +# vim: tabstop=4 shiftwidth=4 noexpandtab +# -------------------------------------------------------------------------------------------- +# @file Makefile +# +# LICENSE: +# +# Copyright 2021 Seagate Technology LLC and/or its Affiliates +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# +# +# @brief Makefile for building a sample test for stimulating a RISC-V trace encoder +# +# +# History: See git log +# +# @author Bill McSpadden (bill.mcspadden@seagate.com) +# -------------------------------------------------------------------------------------------- + + +# -------------------------------------------------------------------------------------------- +# USER MUST SET THESE TO A PROPER SETTING + +#XLEN := 64 +XLEN := 32 +#TOOL_OPT := elf +TOOL_OPT := linux-gnu +#RISCV := /apps/vlsi/tools/riscv/gnu_toolchain/102020/standard/riscv64-unknown-elf +RISCV := /opt/riscv32 +#RISCV := /opt/riscv${XLEN} +#CONFIG_BASE := 0x70080 +CONFIG_BASE := 0x80000000 +MARCH := -march=rv32imc -mabi=ilp32 +#MARCH := -march=rv32imc +#MARCH := -march=elf32lriscv_ilp32 +LD_FILE := ./riscv_test.ld +#RUN_TOOL := /home/billmc/riscv/sail-riscv.git/c_emulator/riscv_sim_RV32 +GIT_ROOT_DIR := /home/billmc/riscv/sail-riscv_br_billmcspadden-riscv.git +RUN_TOOL := ${GIT_ROOT_DIR}/c_emulator/riscv_sim_RV32 + +# USER MUST SET THESE TO A PROPER SETTING +# -------------------------------------------------------------------------------------------- +# +# + +ifndef RISCV +$(error The make variable, RISCV, must be set. It is the path to the compiler tool chain) +endif + +ifndef CONFIG_BASE +$(error The make variable, CONFIG_BASE, is not defined. It is needed for the test variable, also named CONFIG_BASE) +endif + +ifndef MARCH +$(error The make variable, MARCH, must be set.) +endif + +ifndef RUN_TOOL +$(error The make variable, RUN_TOOL, must be set.) +endif + + +BIN := ${RISCV}/bin + +CC := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-gcc +ASM := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-gcc +LD := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-ld +#LD := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-gcc +OBJDUMP := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-objdump + +TARGET := test.elf +DUMP := $(subst .elf,.dump,${TARGET}) + +ASM_SRC := $(wildcard *.S *.s) +ASM_OBJS := $(subst .S,.o,${ASM_SRC}) +ASM_FLAGS := -DCONFIG_BASE=${CONFIG_BASE} ${MARCH} +OBJDUMPFLAGS = -t -Dz + +LINE_NUMBERS := $(addsuffix .line_numbers,${ASM_SRC} ${DUMP}) + +C_SRC := $(wildcard *.c) +C_OBJS := $(subst .c,.o,${C_SRC}) +C_FLAGS := -DCONFIG_BASE=${CONFIG_BASE} ${MARCH} + +#LD_FLAGS := -T ${LD_FILE} ${MARCH} +#LD_FLAGS := -T ${LD_FILE} -march=elf32lriscv +LD_FLAGS := -T ${LD_FILE} + +OBJS := ${ASM_OBJS} ${C_OBJS} + +OUT_FILE := ./sim.out + +RUN_FLAGS := -u rv32i_isa.yaml -y rv32i_platform.yaml + +$(info =================================================================) +$(info Make variable settings....) +$(info RISCV: ${RISCV}) +$(info ASM_SRC: ${ASM_SRC}) +$(info ASM_FLAGS: ${ASM_FLAGS}) +$(info ASM_OBJS: ${ASM_OBJS}) +$(info C_SRC: ${C_SRC}) +$(info C_FLAGS: ${C_FLAGS}) +$(info C_OBJS: ${C_OBJS}) +$(info OBJS: ${OBJS}) +$(info LD_FLAGS: ${LD_FLAGS}) +$(info TARGET: ${TARGET}) +$(info DUMP: ${DUMP}) +$(info =================================================================) + + +all: build + + + + +${TARGET} : ${OBJS} ${LD_FILE} + ${LD} ${LD_FLAGS} -o $@ ${OBJS} + +${DUMP} : ${TARGET} + ${OBJDUMP} ${OBJDUMPFLAGS} ${TARGET} > $@ + + +%.o : %.S + ${ASM} -c ${ASM_FLAGS} -o $@ $< + + +%.o : %.c + ${CC} -c ${C_FLAGS} -o $@ $< + +line_numbers : ${LINE_NUMBERS} + +%.line_numbers : % + cat -n $< > $@ + +build: ${TARGET} ${DUMP} line_numbers + +dump: ${DUMP} + +install: + +clean: + rm -f ${OBJS} ${TARGET} ${DUMP} ${OUT_FILE} ${LINE_NUMBERS} + + +run: ${TARGET} + ${RUN_TOOL} ${RUN_FLAGS} ${TARGET} 2>&1 | tee ${OUT_FILE} + +clean_all: clean + + + + + diff --git a/cookbook/functional_code_examples/add_a_new_extension/add_a_new_extension.adoc b/cookbook/functional_code_examples/add_a_new_extension/add_a_new_extension.adoc new file mode 100644 index 000000000..39eed7583 --- /dev/null +++ b/cookbook/functional_code_examples/add_a_new_extension/add_a_new_extension.adoc @@ -0,0 +1,323 @@ +[#add-a-new-extension] +== Example: Add A New Extension and a New CSR + +The main purpose of this cookbook, is to explain how someone can add +an extension (and a CSR) to the RISC-V Sail model. This example attempts +to add a very simple instruction and a very simple CSR to the model. One +instruction will be added into the custom opcode space. And that +instruction will be used to manipulate the new CSR, which can then +be accessed by the existing CSR instructions. + +This is an example of what *is*, not necessarily what it should be. +This follows a pattern from the existing code. + +First, we will walk through the pertinent sections of the RISC-V specifications +to see what the specifications have to say about adding instructions. + +Let's start with the Unprivileged Specification + +image:images/UnprivTitle.png[] + +Chapter 26 of the Unpriv Spec ("Extending RISC-V") describes how you can extend +the RISC-V instruction set. In this chapter, we find the following... + +image:images/unpriv_ch26_1_non_standard_encoding_space.png[] + +This encoding space can be found in chapter 24 in the instruction space listings. +This where you go to find encoding space that has been reserved for custom +extensions. + +You should be familiar with the various types of encodings that RISC-V +has defined. These can be found in chapter 2 of the UnPriv Spec. Here +are the very basic encodings... + +image:images/unpriv_ch2_2_base_instruction_formats.png[] + +Almost certainly you will want to use one of these formats, as all existing +RISC-V instructions use one of these types or their variants. Now, having +said all that, this example is going to do something a bit different. +For the purposes of this example, I simply wanted to create a single +instruction that has the side effect of writing a custom CSR with an immediate +value. So, when we get to the Sail implementation of the instruction, you will +see that I created a new type, and X-type. [red]#WARNING: this is not a +pattern you should follow. This is for educational purposes only.# + +Now, let's figure out what opcode bits you should use. Go to chapter +24 of the UnPriv Spec. + +See unpriv spec, chapter 24, "RV32/64G Instruction Set Listings" + +image:images/unpriv_ch24_inst_set_listings.png[] + +Here we see the opcode bits (bits 6::0) that can be used for a 32-bit opcode. +This is imporatant. If you stray into other opcode space, you will almost +certainly end up hurting yourself and creating confusion. + +At this point, I should mention that are naming conventions for extensions that +get added to the instructions set. See unpriv spec, chapter 27, +"ISA Extension Naming Convention", especially +setion 27.10, "Non-Standard Extension Names". Following is the pertinent +portion.... + +image:images/unpriv_ch27_10_non_standard_extension_names.png[] + +For this example, we are adding a single instruction: xmpl. The name +for this particular extension will be called "Xxmpl". + +Now that we've covered the instruction and its name and its opcode, let's +move on to the addition of a new CSR. First, we need to move to the +Priv Spec. Why? Because inherent in the access of the CSR is the +concept of privilege. CSRs are typically have some sort of privilege mode +associated with them. So, go the Priv Spec, go to chapter 2 and look at +Table 2.1 (which is reprinted below). Within this table, you will see several +regions that are used for custom implementations. + +image:images/PrivTitle.png[] + + +See priv spec, chapter 2, "CSR Listings", Table 2.1 + +image:images/AllocationOfRISCV_CSRs.png[] + +For the purpose of this example, we are going to use the region +that is marked with a black rectangle. The CSR will be a custom +read-only CSR that can only be accessed from the machine privilege +level. + +So now that we've seen what the specifications say, let's take a look at +what that means for the Sail model. + +Note: there is a coding style guideline at the top of this github +repository (CODE_STYLE.md). I have attempted to follow the style in the example. +If you add code to the model, please make the effort to follow the +coding guidelines. + +First, let's be clear what we're going to implement in this example. + +Single instruction: xmpl + +CSR: xmpl_csr + +* Takes an unsigned immediate and puts the value into the xmpl_csr +* The +xmpl_csr+ can be read by the normal CSR instructions. +* +xmpl_csr+ cannot be written with any form of the CSR instructions; +it should generate an exception. + +As you will see in this example, adding an instruction is actually +pretty simple. It only requires the addition of one file and the modification +of the top level Makefile. Adding a CSR is actually a bit more complicated; +no new file is needed, but no less than 5 files need to be touched. + +Following is the list of files that will be added/touched for this example. +We'll walk through each one of them, one by one. However, a lot of the +code will be obvious. + +Files: + +* (new) model/riscv_insts_custom_xmpl.sail : the implmentation of the instruction and the CSR. +* (exists) Makefile : must add riscv_insts_xample.sail to the list of source files +* (exists) model/riscv_types.sail : need to add new instruction to the proper instruction opcode grouping. +* (exists) model/riscv_csr_map.sail : the address map of the CSR registers. +* (exists) mpodel/iscv_insts_zicsr.sail : need to add new CSR functionality. +* (exists) model/riscv_csr_map.sail : need to add new CSR name to the mapping +* (exists) model/riscv_sys_control.sail : need to add the new CSR name to the list found in is_CSR_defined(). +* (new) cookbook/functional_code_examples/add_a_new_extension/test.S : for testing the new instruction features + +Following is the file that implements the xmpl instruction. + +model/riscv_insts_custom_xmpl.sail: + +[source, sail] +---- +include::../../../model/riscv_insts_custom_xmpl.sail[] +---- + +We now need to change the top-level makefile to bring in this new file. + +Makefile (around lines 26-37): +``` +SAIL_DEFAULT_INST += riscv_insts_zba.sail +SAIL_DEFAULT_INST += riscv_insts_zbb.sail +SAIL_DEFAULT_INST += riscv_insts_zbc.sail +SAIL_DEFAULT_INST += riscv_insts_zbs.sail + +SAIL_DEFAULT_INST += riscv_insts_zfh.sail + +SAIL_DEFAULT_INST += riscv_insts_zkn.sail +SAIL_DEFAULT_INST += riscv_insts_zks.sail + +SAIL_DEFAULT_INST += riscv_insts_zbkb.sail +SAIL_DEFAULT_INST += riscv_insts_zbkx.sail + +# Example custom extension (do not include this in the +# usual model build.) +SAIL_DEFAULT_INST += riscv_insts_custom_xmpl.sail +``` + +//model/riscv_types.sail : need to add new instruction to the proper instruction opcode grouping. +//``` +//TODO: What changes did I make to this file???? +// Apparently, I did nothing +//``` + +The new CSR (actually 2 CSRs; I was playing around with the +Sail capabilities of mappings, so you will see references to two) +need a mapping from their address to their names. This is done +in the following file. + +model/riscv_csr_map.sail (around lines 115-120): +``` +. +. +mapping clause csr_name_map = 0xF11 <-> "mvendorid" +mapping clause csr_name_map = 0xF12 <-> "marchid" +mapping clause csr_name_map = 0xF13 <-> "mimpid" +mapping clause csr_name_map = 0xF14 <-> "mhartid" +mapping clause csr_name_map = 0xFC0 <-> "xmpl_csr" // Custom CSR example +mapping clause csr_name_map = 0xFC1 <-> "xmpl_2_csr" // Custom CSR example +. +. + +``` + +The code that actually does the reads/writes to the CSRs using the +Zicsr extension instructions is found in the following file. Note +that only the Read of the CSR is supported, no writes. This was done +to check out what happens when you try to write a read-only register. + +model/iscv_insts_zicsr.sail (around line 137): +``` +. +. +function readCSR csr : csreg -> xlenbits = { + let res : xlenbits = + match (csr, sizeof(xlen)) { + . + . + /* machine mode, custom extension example */ + (0xFC0, _) => xmpl_csr, // error: Xmpl_csr is not a subtype of bitvector(32, dec) + (0xFC1, _) => xmpl_csr_2.bits(), + . + . +``` + +The following file provides a function to see if the CSR is defined. + +model/riscv_sys_control.sail (within function +is_CSR_defined()+ ): +``` +function is_CSR_defined( csr : csreg, p : Privilege) -> bool = +. +. + /* custom CSRs */ + 0xFC0 => p == Machine, // xmpl_csr Example custom csr + 0xFC1 => p == Machine, // xmpl_csr_2 Example custom csr +. +. + +``` +And with that, we have completed the implementation of the CSR for this +example. At this point, you should probably try and compile. Got to the +root directory of your repo, and run... + +``` +make ARCH=RV32 csim +``` + +If you've made it this fair, you need to do a little testing of your new +instruction and your new CSR. However, your GNU assembler (or whatever it +is that you're using) probably has no idea what +xmpl+ is. So, how do you +write some assembly code to test out your new instruction? Let's take +a look at one way to test the new instruction. + + +cookbook/functional_code_examples/add_a_new_extension/test.S : for testing the new instruction features + +[source, assembler] +---- +include::./test.S.line_numbers[] +---- + + + + +What does the test.dump file look like? Remember, the RISC-V assembler knows nothing +about the custom instruction we have added. + +cookbook/functional_code_examples/add_a_new_extension/test.dump: +``` + . + . + 89 80000062 : + 90 80000062: 0dead12b 0xdead12b + 91 80000066: fc1021f3 csrr gp,0xfc1 + . + . +``` + +Note that the disassembler has no idea what to do with the opcode, +0x0dead12b+. +So, it just leaves it as a word at location +0x80000062+. + +Now that you've compiled an assembly language program +and gotten a .elf file, you are now ready to run it against +your model. The executable is found at: +/c_emulator/riscv_sim_RV32+. +To run the simulation from the example directory, perform the following... + +``` +../../../c_emulator/riscv_sim_RV32 test.elf +``` + +The simulator will send its output to stdout. You can capture it in the +usual file I/O redirection method. + + +What does the Sail log look like? +``` +. +. + 424 model/riscv_step.sail + 425 model/riscv_step.sail:75.25-75.32 + 426 entering step() function... + 427 + 428 mem[X,0x80000062] -> 0xD12B + 429 mem[X,0x80000064] -> 0x0DEA + 430 [41] [M]: 0x80000062 (0x0DEAD12B) x.xmpl 1824162 + 431 + 432 + 433 model/riscv_step.sail + 434 model/riscv_step.sail:75.25-75.32 + 435 entering step() function... + 436 + 437 mem[X,0x80000066] -> 0x21F3 + 438 mem[X,0x80000068] -> 0xFC10 + 439 [42] [M]: 0x80000066 (0xFC1021F3) csrrs gp, xmpl_2_csr, zero + 440 CSR xmpl_2_csr -> 0x001BD5A2 + 441 x3 <- 0x001BD5A2 +. +. + +``` + +Note that on line 430, we see the execution of the custom instruction +and notice that the simlutor knows how to decode the instruction. On line 439, +we see that the normal RISCV instriucion, +csrrs+, can successfully read the +CSR. Woohoo! + +You will probably have to add command line switches to enable/disable extensions/functionality. +Files that need to be touched are: + +* (exists) c_emulator/riscv_sim.c : implements the longopts functionality +* (exists) model/riscv_sys_regs.sail : function signatures for sys_enable_XXX() functionms. +* (exists) c_emulator/riscv_platform_impl.* : global variables for holding enabled state vars +* (exists) c_emulator/riscv_platform.c : implements the C functions that will be made available to Sail; +functions like sys_enable_zfinx(). + +This is actually a separate topic that requires its own example +and will be added soon. + + +Other goals: + +* Demonstrate the experimental switch +* Demonstrate how to code WARL fields based on settings in the YAML files. + + diff --git a/cookbook/functional_code_examples/add_a_new_extension/images/AllocationOfRISCV_CSRs.png b/cookbook/functional_code_examples/add_a_new_extension/images/AllocationOfRISCV_CSRs.png new file mode 100644 index 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@@ -0,0 +1,76 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +/******************************************************************************************* +/// LICENSE: +/// +/// Copyright 2021 Seagate Technology LLC and/or its Affiliates +/// +/// Licensed under the Apache License, Version 2.0 (the "License"); +/// you may not use this file except in compliance with the License. +/// You may obtain a copy of the License at +/// +/// http://www.apache.org/licenses/LICENSE-2.0 +/// +/// Unless required by applicable law or agreed to in writing, software +/// distributed under the License is distributed on an "AS IS" BASIS, +/// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +/// See the License for the specific language governing permissions and +/// limitations under the License. +********************************************************************************************/ + +/*----------------------------------------------------------------------*/ +/* Sections */ +/*----------------------------------------------------------------------*/ + +SECTIONS +{ + + /* text: test code section */ +/*. = 0x00000040; */ +/*. = 0x00001000; */ + . = 0x80000000; + .text.init : { *(.text.init) } + + .text : { *(.text) } + + /* data segment */ +/*. = 0x00080000; */ + .tohost ALIGN(0x1000) : { *(.tohost) } + .data : { *(.data) } + .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) } + .sdata : { + __global_pointer$ = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } + + /* bss segment */ + .sbss : { + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } + .bss : { *(.bss) } + + /* thread-local data segment */ + .tdata : + { + _tls_data = .; + *(.tdata.begin) + *(.tdata) + *(.tdata.end) + } + .tbss : + { + *(.tbss) + *(.tbss.end) + } + + __malloc_start = .; + . = . + 32768; + + /* End of uninitalized data segement */ + _end = .; + +} + diff --git a/cookbook/functional_code_examples/add_a_new_extension/rv32i_isa.yaml b/cookbook/functional_code_examples/add_a_new_extension/rv32i_isa.yaml new file mode 100644 index 000000000..6ca76f6c7 --- /dev/null +++ b/cookbook/functional_code_examples/add_a_new_extension/rv32i_isa.yaml @@ -0,0 +1,3119 @@ +hart_ids: [0] +hart0: &hart0 +# ISA: RV32IMAFCNSHUZicsr_Zifencei + ISA: RV64IMAFCNSHUZicsr_Zifencei_Ssptead + User_Spec_Version: '2.3' + supported_xlen: [32] + physical_addr_sz: 32 + pmp_granularity: 5 + hw_data_misaligned_support : true +# pte_dirty_update_enable : true # TODO: look for Ssptead in ISA string + misa: + reset-val: 0x401431A5 + rv32: + accessible: true + mxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + + - mxl[1:0] in [0x1] + wr_illegal: + - unchanged + extensions: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - extensions[25:0] in [0x0000000:0x3FFFFFF] + wr_illegal: + - unchanged + xmpl_csr: + reset-val: 0x0 + rv32: + accessible: true + Rsrvd: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - mxl[1:0] in [0x1] + wr_illegal: + - unchanged + FieldWARL: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - FieldWARL[24:0] in [0x0000000:0x3FFFFFF] + wr_illegal: + - unchanged + xmpl_csr_2: + mvendorid: + reset-val: 0xdeadbeef + rv32: + accessible: true + type: + ro_constant: 0xdeadbeef + rv64: + accessible: false + mtvec: + reset-val: 0x80010000 + rv32: + accessible: true + base: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - "base[29:0] bitmask [0x3FFFFFFF, 0x00000000]" + wr_illegal: + - "Unchanged" + mode: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - "mode[1:0] in [0x0,0x1]" + wr_illegal: + - "Unchanged" + sstatus: + reset-val: 0x0 + rv32: + accessible: true + uie: + implemented: false + sie: + implemented: true + upie: + implemented: false + spie: + implemented: true + spp: + implemented: true + fs: + implemented: false + xs: + implemented: true + sum: + implemented: true + mxr: + implemented: true + sd: + implemented: true + rv64: + accessible: false + vsstatus: + reset-val: 0x0 + rv32: + accessible: true + uie: + implemented: false + sie: + implemented: true + upie: + implemented: false + spie: + implemented: true + spp: + implemented: true + fs: + implemented: false + xs: + implemented: true + sum: + implemented: true + mxr: + implemented: true + sd: + implemented: true + rv64: + accessible: false + mstatus: + reset-val: 0x0 + rv32: + accessible: true + uie: + implemented: true + sie: + implemented: true + type: + wlrl: [0:1] + mie: + implemented: true + upie: + implemented: true + spie: + implemented: true + type: + wlrl: [0:1] + mpie: + implemented: true + spp: + implemented: true + type: + wlrl: [0:1] + mpp: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - mpp[1:0] in [0x0, 0x3] + wr_illegal: + - Unchanged + fs: + implemented: false + xs: + implemented: true + type: + ro_variable: true + mprv: + implemented: true + type: + wlrl: [0:1] + sum: + implemented: true + type: + wlrl: [0:1] + mxr: + implemented: true + type: + wlrl: [0:1] + tvm: + implemented: true + type: + wlrl: [0:1] + tw: + implemented: false + tsr: + implemented: true + type: + wlrl: [0:1] + sd: + implemented: true + type: + ro_variable: true + rv64: + accessible: false + + mip: + reset-val: 0 + rv32: + accessible: true + usip: + implemented: true + ssip: + implemented: true + msip: + implemented: true + type: + ro_variable: true + utip: + implemented: true + stip: + implemented: true + mtip: + implemented: true + type: + ro_variable: [0x01] + ueip: + implemented: true + seip: + implemented: true + meip: + implemented: true + type: + ro_variable: true + rv64: + accessible: false + hip: + reset-val: 0 + rv32: + accessible: true + vssip: + implemented: true + vstip: + implemented: true + vseip: + implemented: true + sgeip: + implemented: true + type: + ro_variable: true + rv64: + accessible: false + mie: + reset-val: 0 + rv32: + accessible: true + usie: + implemented: true + ssie: + implemented: true + msie: + implemented: true + type: + ro_variable: true + utie: + implemented: true + stie: + implemented: true + mtie: + implemented: true + ueie: + implemented: true + seie: + implemented: true + meie: + implemented: true + rv64: + accessible: false + hie: + reset-val: 0 + rv32: + accessible: true + vssie: + implemented: true + vstie: + implemented: true + vseie: + implemented: true + sgeie: + implemented: true + rv64: + accessible: false + mepc: + reset-val: 0x0 + rv32: + accessible: true + rv64: + accessible: false + mtval: + reset-val: 0x0 + has_illegal_inst_bits : false + rv32: + accessible: true + rv64: + accessible: false + mcause: + reset-val: 0 + rv32: + accessible: true + interrupt: + implemented: true + exception_code: + implemented: true + rv64: + accessible: false + + marchid: + rv32: + accessible: true + type: + ro_constant: 0x0 + rv64: + accessible: false + reset-val: 0x0 + mhartid: + rv32: + accessible: true + type: + ro_constant: 0x0 + rv64: + accessible: false + reset-val: 0x00 + mscratch: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mscratch[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter3: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter3[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + hpmcounter3: + rv32: + accessible: true + rv64: + accessible: false + reset-val: 0x0 + hpmcounter3h: + rv32: + accessible: true + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter4: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter4[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter4h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter4h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter5: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter5[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter6: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter6[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter7: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter7[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter8: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter8[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter9: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter9[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter10: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter10[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter11: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter11[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter12: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter12[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter13: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter13[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter14: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter14[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter15: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter15[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter16: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter16[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter17: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter17[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter18: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter18[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter19: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter19[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter20: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter20[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter21: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter21[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter22: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter22[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter23: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter23[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter24: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter24[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter25: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter25[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter26: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter26[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter27: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter27[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter28: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter28[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter29: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter29[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter30: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter30[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter31: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter31[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + + mhpmcounter3h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter3h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter5h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter5h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter6h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter6h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter7h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter7h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter8h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter8h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter9h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter9h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter10h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter10h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter11h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter11h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter12h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter12h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter13h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter13h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter14h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter14h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter15h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter15h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter16h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter16h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter17h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter17h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter18h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter18h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter19h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter19h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter20h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter20h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter21h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter21h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter22h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter22h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter23h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter23h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter24h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter24h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter25h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter25h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter26h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter26h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter27h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter27h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter28h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter28h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter29h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter29h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter30h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter30h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter31h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter31h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mcountinhibit: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcountinhibit[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent3: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent3[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent4: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent4[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent5: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent5[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent6: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent6[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent7: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent7[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent8: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent8[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent9: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent9[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent10: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent10[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent11: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent11[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent12: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent12[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent13: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent13[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent14: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent14[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent15: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent15[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent16: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent16[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent17: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent17[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent18: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent18[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent19: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent19[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent20: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent20[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent21: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent21[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent22: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent22[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent23: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent23[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent24: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent24[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent25: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent25[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent26: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent26[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent27: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent27[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent28: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent28[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent29: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent29[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent30: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent30[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent31: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent31[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mimpid: + rv32: + accessible: true + type: + ro_constant: 0x0 + rv64: + accessible: false + reset-val: 0 + mcounteren: + rv32: + accessible: true + rv64: + accessible: false + reset-val: 0 + pmpcfg0: + rv32: + accessible: true + pmp0cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp0cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp1cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp1cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp2cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp2cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp3cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp3cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg1: + rv32: + accessible: true + pmp4cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp4cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp5cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp5cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp6cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp6cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp7cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp7cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg2: + rv32: + accessible: true + pmp8cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp8cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp9cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp9cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp10cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp10cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp11cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp11cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg3: + rv32: + accessible: true + pmp12cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp12cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp13cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp13cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp14cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp14cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp15cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp15cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg4: + rv32: + accessible: true + pmp16cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp16cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp17cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp17cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp18cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp18cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp19cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp19cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg5: + rv32: + accessible: true + pmp20cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp20cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp21cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp21cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp22cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp22cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp23cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp23cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg6: + rv32: + accessible: true + pmp24cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp24cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp25cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp25cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp26cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp26cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp27cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp27cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg7: + rv32: + accessible: true + pmp28cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp28cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp29cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp29cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp30cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp30cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp31cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp31cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg8: + rv32: + accessible: true + pmp32cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp32cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp33cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp33cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp34cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp34cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp35cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp35cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg9: + rv32: + accessible: true + pmp36cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp36cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp37cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp37cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp38cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp38cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp39cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp39cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg10: + rv32: + accessible: true + pmp40cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp40cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp41cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp41cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp42cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp42cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp43cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp43cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg11: + rv32: + accessible: true + pmp44cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp44cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp45cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp45cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp46cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp46cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp47cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp47cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg12: + rv32: + accessible: true + pmp48cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp48cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp49cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp49cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp50cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp50cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp51cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp51cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg13: + rv32: + accessible: true + pmp52cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp52cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp53cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp53cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp54cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp54cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp55cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp55cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg14: + rv32: + accessible: true + pmp56cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp56cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp57cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp57cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp58cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp58cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp59cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp59cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg15: + rv32: + accessible: true + pmp60cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp60cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp61cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp61cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp62cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp62cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp63cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp63cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + mcycle: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mcycle[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + minstret: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - minstret[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + mcycleh: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mcycleh[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + minstreth: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - minstreth[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr0: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr0[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x20 + pmpaddr1: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr1[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr2: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr2[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr3: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr3[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr4: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr4[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr5: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr5[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr6: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr6[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr7: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr7[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr8: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr8[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr9: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr9[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr10: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr10[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr11: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr11[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr12: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr12[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr13: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr13[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr14: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr14[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr15: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr15[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr16: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr16[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr17: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr17[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr18: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr18[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr19: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr19[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr20: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr20[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr21: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr21[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr22: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr22[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr23: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr23[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr24: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr24[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr25: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr25[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr26: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr26[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr27: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr27[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr28: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr28[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr29: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr29[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr30: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr30[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr31: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr31[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr32: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr32[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr33: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr33[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr34: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr34[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr35: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr35[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr36: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr36[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr37: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr37[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr38: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr38[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr39: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr39[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr40: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr40[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr41: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr41[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr42: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr42[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr43: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr43[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr44: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr44[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr45: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr45[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr46: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr46[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr47: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr47[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr48: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr48[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr49: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr49[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr50: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr50[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr51: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr51[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr52: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr52[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr53: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr53[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr54: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr54[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr55: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr55[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr56: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr56[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr57: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr57[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr58: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr58[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr59: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr59[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr60: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr60[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr61: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr61[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr62: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr62[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr63: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr63[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + fcsr: + rv64: + accessible: false + rv32: + accessible: true + fflags: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - fflags[4:0] in [0x00:0x1F] + wr_illegal: + - Unchanged + frm: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - frm[2:0] in [0x0:0x7] + wr_illegal: + - Unchanged + time: + rv32: + accessible: true + type: + ro_variable: true + rv64: + accessible: false + reset-val: 0 + timeh: + rv32: + accessible: true + type: + ro_variable: true + rv64: + accessible: false + reset-val: 0 diff --git a/cookbook/functional_code_examples/add_a_new_extension/rv32i_platform.yaml b/cookbook/functional_code_examples/add_a_new_extension/rv32i_platform.yaml new file mode 100644 index 000000000..9748f523d --- /dev/null +++ b/cookbook/functional_code_examples/add_a_new_extension/rv32i_platform.yaml @@ -0,0 +1,15 @@ +nmi: + label: nmi_vector +reset: +# label: reset_vector +# address: 0x1000 + address: 0x80000000 +mtime: + implemented: True + address: 0x20000 + +# TODO: until we have a method for doing a memory map, +# we will keep with the original model of having 1 RAM +# block whose size can be given in MBs. +ram_size : 4 + diff --git a/cookbook/functional_code_examples/add_a_new_extension/test.S b/cookbook/functional_code_examples/add_a_new_extension/test.S new file mode 100644 index 000000000..988a07c07 --- /dev/null +++ b/cookbook/functional_code_examples/add_a_new_extension/test.S @@ -0,0 +1,325 @@ +// vim: tabstop=2 shiftwidth=2 expandtab +// -------------------------------------------------------------------------------------------- +/// @file test.S +/// +/// +/// @brief RISC-V asm code for testing an example custom instruction +/// +/// @author Bill McSpadden (RISC-V Internation) (bill@riscv.org) +// -------------------------------------------------------------------------------------------- + +#ifndef CONFIG_BASE +#error The C pre-processor variable, CONFIG_BASE, must be set. +#endif + +// -------------------------------------------------------- +// Support for a custom extension + +#define X_XMPL_OPCODE (0x2b) // inst[6:5] == 01, inst[4:2] == 1011 --> custom-0 +#define X_XMPL(__imm__) .word (__imm__ << 7) | (X_XMPL_OPCODE << 0) + +#define XO (0) +#define X1 (1) +#define X2 (2) +#define X3 (3) +#define X4 (4) +#define X5 (5) +#define X6 (6) +#define X7 (7) +#define X8 (8) +#define X9 (9) +#define X10 (10) +#define X11 (11) +#define X12 (12) +#define X13 (13) +#define X14 (14) +#define X15 (15) +#define X16 (16) +#define X17 (17) +#define X18 (18) +#define X19 (19) +#define X20 (20) +#define X21 (21) +#define X22 (22) +#define X23 (23) +#define X24 (24) +#define X25 (25) +#define X26 (26) +#define X27 (27) +#define X28 (28) +#define X29 (29) +#define X30 (30) +#define X31 (31) + + + + +// -------------------------------------------------------- +// Memory-mapped machine timer registers and other support +// for generating a timer interrupt + +//#define MMR_MTIMEL (CONFIG_BASE + 0x0000) +//#define MMR_MTIMEH (CONFIG_BASE + 0x0004) +//#define MMR_MTIMECMPL (CONFIG_BASE + 0x0008) +//#define MMR_MTIMECMPH (CONFIG_BASE + 0x000C) + +#define MMR_MTIMEL (CONFIG_BASE + 0xbff8) +#define MMR_MTIMEH (CONFIG_BASE + 0xbffc) +#define MMR_MTIMECMPL (CONFIG_BASE + 0x4000) +#define MMR_MTIMECMPH (CONFIG_BASE + 0x4004) + +#define TIMER_COUNT (100) +#define WATCHDOG_COUNT (100000) + +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 + +#define MIE_MTIE 0x80 + + +// -------------------------------------------------------- +// mcause bit definitions + +#define MCAUSE_SUPERVISOR_SOFTWARE_INTERRUPT (0x1 << (__riscv_xlen - 1) + 1) +#define MCAUSE_MACHINE_TIMER_INTERRUPT (0x1 << (__riscv_xlen - 1) + 7) +#define MCAUSE_ILLEGAL_INSTRUCTION (0x0 << (__riscv_xlen - 1) + 2) + +// -------------------------------------------------------- +// Support for tohost/fromhost + +#define PASS_CODE 1 +#define FAIL_CODE 1337 + + +// -------------------------------------------------------- +// Support for 32/64 bit compilation. + +#if __riscv_xlen == 64 +# define LREG ld +# define SREG sd +# define REGBYTES 8 +#else +# define LREG lw +# define SREG sw +# define REGBYTES 4 +#endif + +#define XMPL_CSR (0xfc0) +#define XMPL_CSR_2 (0xfc1) + +// -------------------------------------------------------- +// Following power-on reset, we start executing at _start. +// We jump to "reset_vector" +// + .section ".text.init" + .globl _start +_start: + la x5, reset_vector + jr x5 +// -------------------------------------------------------- + + +// -------------------------------------------------------- +// Initialization of the processor, starting with the +// register file. +reset_vector: + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + +// -------------------------------------------------------- +// PMP configuration + + # configure pmp to enable all accesses + li t0, 0x1f + csrw pmpcfg0, t0 + li t0, 0xffffffff + csrw pmpaddr0, t0 + +// -------------------------------------------------------- +// initialize machine trap vector + la x5, machine_trap_entry + csrw mtvec, x5 + + +// -------------------------------------------------------- +// The test! + +the_test_begin: + X_XMPL(0x0dead) + csrr x3, XMPL_CSR_2 + +// li x4, 0x76543210 +// csrw XMPL_CSR_2, x4 // Q: What happens to a write to a read-only csr? +// // A: illegal_instruction trap +the_test_end: + + + + +// -------------------------------------------------------- +// PASS: The end of the test, if successful +j_target_end_pass: + // exit code construction + li x10, PASS_CODE + la x13, tohost + sw x10, 0(x13) + la x5, j_target_end_pass + jalr x5 + j j_target_end_fail // should never be taken + +// -------------------------------------------------------- + +// -------------------------------------------------------- +// FAIL: The end of the test, if unsuccessful +j_target_end_fail: + // exit code construction + li x10, FAIL_CODE + la x13, tohost + sw x10, 0(x13) + la x5, j_target_end_fail + jalr x5 + + +// -------------------------------------------------------- +// In support of vectored interrupt, although it's not +// being used in this test. + + .align 4 +machine_trap_entry: + j machine_trap_entry_0 + .align 2 + j machine_trap_entry_1 + .align 2 + j machine_trap_entry_2 + .align 2 + j machine_trap_entry_3 + .align 2 + j machine_trap_entry_4 + .align 2 + j machine_trap_entry_5 + .align 2 + j machine_trap_entry_6 + .align 2 + j machine_trap_entry_7 + .align 2 + j machine_trap_entry_8 + .align 2 + j machine_trap_entry_9 + .align 2 + j machine_trap_entry_10 + .align 2 + j machine_trap_entry_11 +// -------------------------------------------------------- + + +// -------------------------------------------------------- + .align 2 +machine_trap_entry_0: + csrr x7, mcause + li x6, MCAUSE_MACHINE_TIMER_INTERRUPT + bne x7, x6, not_a_timer_interrupt + li x6, 0x1 + la x7, timer_interrupt_flag + sw x6, 0(x7) + + // Turn off timer interrupt. No longer needed + addi x7, x0, MIE_MTIE + csrc mie, x7 + + // Clear interrupt + li x7, MSTATUS_MIE + csrc mstatus, x7 + + // and return + mret + +not_a_timer_interrupt: + // Do not try and correct the opcode, and do not + // do an mret. This should probably be the last + // part of this simple test. + csrr x7, mcause + li x6, MCAUSE_ILLEGAL_INSTRUCTION + j j_target_end_fail +// -------------------------------------------------------- + +// -------------------------------------------------------- +// None of these machine traps should have been taken +// Jump to test failure +machine_trap_entry_1: +machine_trap_entry_2: +machine_trap_entry_3: +machine_trap_entry_4: +machine_trap_entry_5: +machine_trap_entry_6: +machine_trap_entry_7: +machine_trap_entry_8: +machine_trap_entry_9: +machine_trap_entry_10: +machine_trap_entry_11: + csrr x7, mcause // Do the read so that it appears in the log file for debug. + j j_target_end_fail +// -------------------------------------------------------- + + + +// -------------------------------------------------------- +// Memory locations for specific usage. +.section ".tdata.begin" +.globl _tdata_begin +_tdata_begin: + +.section ".tdata.end" +.globl _tdata_end +_tdata_end: + +.section ".tbss.end" +.globl _tbss_end +_tbss_end: + +.section ".tohost","aw",@progbits +.align 6 +.globl tohost +tohost: .dword 0 + +.section ".fromhost","aw",@progbits +.align 6 +.globl fromhost +fromhost: .dword 0 + +.align 6 +.global timer_interrupt_flag +timer_interrupt_flag: .dword 0 + + + + diff --git a/cookbook/functional_code_examples/br_j_asm/CMakeLists.txt b/cookbook/functional_code_examples/br_j_asm/CMakeLists.txt new file mode 100644 index 000000000..8ad406982 --- /dev/null +++ b/cookbook/functional_code_examples/br_j_asm/CMakeLists.txt @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: BSD-2-Clause +# SPDX-FileCopyrightText: Copyright 2019-2021 Siemens. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. + +cmake_minimum_required(VERSION 3.10 FATAL_ERROR) + +find_program(CMAKE_ASM_COMPILER riscv64-unknown-elf-gcc HINTS /opt/riscv/bin) +set(CMAKE_ASM_LINK_EXECUTABLE " -o ") + +project(br_j_asm ASM) + +add_executable(br_j_asm.riscv test.S) + +set(CONFIG_BASE 0x20010000) +set(CMAKE_ASM_FLAGS -DCONFIG_BASE=${CONFIG_BASE}) +# If using cmake > 3.13 you could use +#add_link_options(-T ${CMAKE_SOURCE_DIR}/riscv_test.ld.spike) +# instead of setting LINK_FLAGS +set_property(TARGET br_j_asm.riscv APPEND_STRING PROPERTY LINK_FLAGS " -T ${CMAKE_SOURCE_DIR}/riscv_test.ld.spike") diff --git a/cookbook/functional_code_examples/br_j_asm/LICENSE b/cookbook/functional_code_examples/br_j_asm/LICENSE new file mode 100644 index 000000000..d64569567 --- /dev/null +++ b/cookbook/functional_code_examples/br_j_asm/LICENSE @@ -0,0 +1,202 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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It is the path to the compiler tool chain) +endif + +ifndef CONFIG_BASE +$(error The make variable, CONFIG_BASE, is not defined. It is needed for the test variable, also named CONFIG_BASE) +endif + +ifndef MARCH +$(error The make variable, MARCH, must be set.) +endif + +ifndef RUN_TOOL +$(error The make variable, RUN_TOOL, must be set.) +endif + + +BIN := ${RISCV}/bin + +CC := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-gcc +ASM := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-gcc +LD := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-ld +#LD := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-gcc +OBJDUMP := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-objdump + +TARGET := test.elf +DUMP := $(subst .elf,.dump,${TARGET}) + +ASM_SRC := $(wildcard *.S *.s) +ASM_OBJS := $(subst .S,.o,${ASM_SRC}) +ASM_FLAGS := -DCONFIG_BASE=${CONFIG_BASE} ${MARCH} +OBJDUMPFLAGS = -t -Dz + +C_SRC := $(wildcard *.c) +C_OBJS := $(subst .c,.o,${C_SRC}) +C_FLAGS := -DCONFIG_BASE=${CONFIG_BASE} ${MARCH} + +#LD_FLAGS := -T ${LD_FILE} ${MARCH} +#LD_FLAGS := -T ${LD_FILE} -march=elf32lriscv +LD_FLAGS := -T ${LD_FILE} + +OBJS := ${ASM_OBJS} ${C_OBJS} + +OUT_FILE := ./sim.out + +RUN_FLAGS := -u rv32i_isa.yaml -y rv32i_platform.yaml + +$(info =================================================================) +$(info Make variable settings....) +$(info RISCV: ${RISCV}) +$(info ASM_SRC: ${ASM_SRC}) +$(info ASM_FLAGS: ${ASM_FLAGS}) +$(info ASM_OBJS: ${ASM_OBJS}) +$(info C_SRC: ${C_SRC}) +$(info C_FLAGS: ${C_FLAGS}) +$(info C_OBJS: ${C_OBJS}) +$(info OBJS: ${OBJS}) +$(info LD_FLAGS: ${LD_FLAGS}) +$(info TARGET: ${TARGET}) +$(info DUMP: ${DUMP}) +$(info =================================================================) + + +all: ${TARGET} ${DUMP} + + + + +${TARGET} : ${OBJS} ${LD_FILE} + ${LD} ${LD_FLAGS} -o $@ ${OBJS} + +${DUMP} : ${TARGET} + ${OBJDUMP} ${OBJDUMPFLAGS} ${TARGET} > $@ + + +%.o : %.S + ${ASM} -c ${ASM_FLAGS} -o $@ $< + +%.o : %.c + ${CC} -c ${C_FLAGS} -o $@ $< + + + +build: ${TARGET} ${DUMP} + +dump: ${DUMP} + +install: + +clean: + rm -f ${OBJS} ${TARGET} ${DUMP} ${OUT_FILE} + + +run: ${TARGET} + ${RUN_TOOL} ${RUN_FLAGS} ${TARGET} 2>&1 | tee ${OUT_FILE} + +clean_all: clean + + + + + + diff --git a/cookbook/functional_code_examples/br_j_asm/riscv_test.ld b/cookbook/functional_code_examples/br_j_asm/riscv_test.ld new file mode 100644 index 000000000..55aa2f541 --- /dev/null +++ b/cookbook/functional_code_examples/br_j_asm/riscv_test.ld @@ -0,0 +1,76 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +/******************************************************************************************* +/// LICENSE: +/// +/// Copyright 2021 Seagate Technology LLC and/or its Affiliates +/// +/// Licensed under the Apache License, Version 2.0 (the "License"); +/// you may not use this file except in compliance with the License. +/// You may obtain a copy of the License at +/// +/// http://www.apache.org/licenses/LICENSE-2.0 +/// +/// Unless required by applicable law or agreed to in writing, software +/// distributed under the License is distributed on an "AS IS" BASIS, +/// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +/// See the License for the specific language governing permissions and +/// limitations under the License. +********************************************************************************************/ + +/*----------------------------------------------------------------------*/ +/* Sections */ +/*----------------------------------------------------------------------*/ + +SECTIONS +{ + + /* text: test code section */ +/*. = 0x00000040; */ +/*. = 0x00001000; */ + . = 0x80000000; + .text.init : { *(.text.init) } + + .text : { *(.text) } + + /* data segment */ +/*. = 0x00080000; */ + .tohost ALIGN(0x1000) : { *(.tohost) } + .data : { *(.data) } + .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) } + .sdata : { + __global_pointer$ = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } + + /* bss segment */ + .sbss : { + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } + .bss : { *(.bss) } + + /* thread-local data segment */ + .tdata : + { + _tls_data = .; + *(.tdata.begin) + *(.tdata) + *(.tdata.end) + } + .tbss : + { + *(.tbss) + *(.tbss.end) + } + + __malloc_start = .; + . = . + 32768; + + /* End of uninitalized data segement */ + _end = .; + +} + diff --git a/cookbook/functional_code_examples/br_j_asm/riscv_test.ld.spike b/cookbook/functional_code_examples/br_j_asm/riscv_test.ld.spike new file mode 100644 index 000000000..ece1aefe0 --- /dev/null +++ b/cookbook/functional_code_examples/br_j_asm/riscv_test.ld.spike @@ -0,0 +1,73 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +/******************************************************************************************* +/// LICENSE: +/// +/// Copyright 2021 Seagate Technology LLC and/or its Affiliates +/// +/// Licensed under the Apache License, Version 2.0 (the "License"); +/// you may not use this file except in compliance with the License. +/// You may obtain a copy of the License at +/// +/// http://www.apache.org/licenses/LICENSE-2.0 +/// +/// Unless required by applicable law or agreed to in writing, software +/// distributed under the License is distributed on an "AS IS" BASIS, +/// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +/// See the License for the specific language governing permissions and +/// limitations under the License. +********************************************************************************************/ + +/*----------------------------------------------------------------------*/ +/* Sections */ +/*----------------------------------------------------------------------*/ + +SECTIONS +{ + + /* text: test code section */ + . = 0x80000040; + .text.init : { *(.text.init) } + + .text : { *(.text) } + + /* data segment */ + . = 0x80080000; + .tohost ALIGN(0x1000) : { *(.tohost) } + .data : { *(.data) } + .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) } + .sdata : { + __global_pointer$ = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } + + /* bss segment */ + .sbss : { + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } + .bss : { *(.bss) } + + /* thread-local data segment */ + .tdata : + { + _tls_data = .; + *(.tdata.begin) + *(.tdata) + *(.tdata.end) + } + .tbss : + { + *(.tbss) + *(.tbss.end) + } + + __malloc_start = .; + . = . + 32768; + + /* End of uninitalized data segement */ + _end = .; + +} diff --git a/cookbook/functional_code_examples/br_j_asm/rv32i_isa.yaml b/cookbook/functional_code_examples/br_j_asm/rv32i_isa.yaml new file mode 100644 index 000000000..68f3c85da --- /dev/null +++ b/cookbook/functional_code_examples/br_j_asm/rv32i_isa.yaml @@ -0,0 +1,3096 @@ +hart_ids: [0] +hart0: &hart0 +# ISA: RV32IMAFCNSHUZicsr_Zifencei + ISA: RV64IMAFCNSHUZicsr_Zifencei_Ssptead + User_Spec_Version: '2.3' + supported_xlen: [32] + physical_addr_sz: 32 + pmp_granularity: 5 + hw_data_misaligned_support : true +# pte_dirty_update_enable : true # TODO: look for Ssptead in ISA string + misa: + reset-val: 0x401431A5 + rv32: + accessible: true + mxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + + - mxl[1:0] in [0x1] + wr_illegal: + - unchanged + extensions: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - extensions[25:0] in [0x0000000:0x3FFFFFF] + wr_illegal: + - unchanged + mvendorid: + reset-val: 0xdeadbeef + rv32: + accessible: true + type: + ro_constant: 0xdeadbeef + rv64: + accessible: false + mtvec: + reset-val: 0x80010000 + rv32: + accessible: true + base: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - "base[29:0] bitmask [0x3FFFFFFF, 0x00000000]" + wr_illegal: + - "Unchanged" + mode: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - "mode[1:0] in [0x0,0x1]" + wr_illegal: + - "Unchanged" + sstatus: + reset-val: 0x0 + rv32: + accessible: true + uie: + implemented: false + sie: + implemented: true + upie: + implemented: false + spie: + implemented: true + spp: + implemented: true + fs: + implemented: false + xs: + implemented: true + sum: + implemented: true + mxr: + implemented: true + sd: + implemented: true + rv64: + accessible: false + vsstatus: + reset-val: 0x0 + rv32: + accessible: true + uie: + implemented: false + sie: + implemented: true + upie: + implemented: false + spie: + implemented: true + spp: + implemented: true + fs: + implemented: false + xs: + implemented: true + sum: + implemented: true + mxr: + implemented: true + sd: + implemented: true + rv64: + accessible: false + mstatus: + reset-val: 0x0 + rv32: + accessible: true + uie: + implemented: true + sie: + implemented: true + type: + wlrl: [0:1] + mie: + implemented: true + upie: + implemented: true + spie: + implemented: true + type: + wlrl: [0:1] + mpie: + implemented: true + spp: + implemented: true + type: + wlrl: [0:1] + mpp: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - mpp[1:0] in [0x0, 0x3] + wr_illegal: + - Unchanged + fs: + implemented: false + xs: + implemented: true + type: + ro_variable: true + mprv: + implemented: true + type: + wlrl: [0:1] + sum: + implemented: true + type: + wlrl: [0:1] + mxr: + implemented: true + type: + wlrl: [0:1] + tvm: + implemented: true + type: + wlrl: [0:1] + tw: + implemented: false + tsr: + implemented: true + type: + wlrl: [0:1] + sd: + implemented: true + type: + ro_variable: true + rv64: + accessible: false + + mip: + reset-val: 0 + rv32: + accessible: true + usip: + implemented: true + ssip: + implemented: true + msip: + implemented: true + type: + ro_variable: true + utip: + implemented: true + stip: + implemented: true + mtip: + implemented: true + type: + ro_variable: [0x01] + ueip: + implemented: true + seip: + implemented: true + meip: + implemented: true + type: + ro_variable: true + rv64: + accessible: false + hip: + reset-val: 0 + rv32: + accessible: true + vssip: + implemented: true + vstip: + implemented: true + vseip: + implemented: true + sgeip: + implemented: true + type: + ro_variable: true + rv64: + accessible: false + mie: + reset-val: 0 + rv32: + accessible: true + usie: + implemented: true + ssie: + implemented: true + msie: + implemented: true + type: + ro_variable: true + utie: + implemented: true + stie: + implemented: true + mtie: + implemented: true + ueie: + implemented: true + seie: + implemented: true + meie: + implemented: true + rv64: + accessible: false + hie: + reset-val: 0 + rv32: + accessible: true + vssie: + implemented: true + vstie: + implemented: true + vseie: + implemented: true + sgeie: + implemented: true + rv64: + accessible: false + mepc: + reset-val: 0x0 + rv32: + accessible: true + rv64: + accessible: false + mtval: + reset-val: 0x0 + has_illegal_inst_bits : false + rv32: + accessible: true + rv64: + accessible: false + mcause: + reset-val: 0 + rv32: + accessible: true + interrupt: + implemented: true + exception_code: + implemented: true + rv64: + accessible: false + + marchid: + rv32: + accessible: true + type: + ro_constant: 0x0 + rv64: + accessible: false + reset-val: 0x0 + mhartid: + rv32: + accessible: true + type: + ro_constant: 0x0 + rv64: + accessible: false + reset-val: 0x00 + mscratch: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mscratch[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter3: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter3[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + hpmcounter3: + rv32: + accessible: true + rv64: + accessible: false + reset-val: 0x0 + hpmcounter3h: + rv32: + accessible: true + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter4: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter4[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter4h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter4h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter5: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter5[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter6: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter6[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter7: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter7[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter8: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter8[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter9: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter9[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter10: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter10[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter11: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter11[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter12: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter12[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter13: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter13[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter14: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter14[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter15: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter15[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter16: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter16[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter17: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter17[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter18: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter18[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter19: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter19[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter20: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter20[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter21: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter21[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter22: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter22[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter23: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter23[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter24: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter24[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter25: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter25[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter26: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter26[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter27: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter27[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter28: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter28[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter29: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter29[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter30: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter30[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter31: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter31[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + + mhpmcounter3h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter3h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter5h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter5h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter6h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter6h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter7h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter7h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter8h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter8h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter9h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter9h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter10h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter10h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter11h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter11h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter12h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter12h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter13h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter13h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter14h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter14h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter15h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter15h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter16h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter16h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter17h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter17h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter18h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter18h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter19h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter19h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter20h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter20h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter21h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter21h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter22h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter22h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter23h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter23h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter24h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter24h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter25h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter25h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter26h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter26h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter27h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter27h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter28h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter28h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter29h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter29h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter30h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter30h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter31h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter31h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mcountinhibit: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcountinhibit[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent3: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent3[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent4: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent4[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent5: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent5[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent6: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent6[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent7: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent7[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent8: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent8[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent9: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent9[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent10: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent10[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent11: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent11[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent12: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent12[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent13: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent13[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent14: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent14[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent15: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent15[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent16: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent16[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent17: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent17[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent18: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent18[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent19: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent19[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent20: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent20[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent21: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent21[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent22: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent22[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent23: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent23[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent24: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent24[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent25: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent25[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent26: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent26[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent27: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent27[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent28: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent28[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent29: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent29[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent30: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent30[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent31: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent31[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mimpid: + rv32: + accessible: true + type: + ro_constant: 0x0 + rv64: + accessible: false + reset-val: 0 + mcounteren: + rv32: + accessible: true + rv64: + accessible: false + reset-val: 0 + pmpcfg0: + rv32: + accessible: true + pmp0cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp0cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp1cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp1cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp2cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp2cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp3cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp3cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg1: + rv32: + accessible: true + pmp4cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp4cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp5cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp5cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp6cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp6cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp7cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp7cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg2: + rv32: + accessible: true + pmp8cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp8cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp9cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp9cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp10cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp10cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp11cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp11cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg3: + rv32: + accessible: true + pmp12cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp12cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp13cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp13cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp14cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp14cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp15cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp15cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg4: + rv32: + accessible: true + pmp16cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp16cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp17cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp17cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp18cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp18cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp19cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp19cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg5: + rv32: + accessible: true + pmp20cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp20cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp21cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp21cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp22cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp22cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp23cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp23cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg6: + rv32: + accessible: true + pmp24cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp24cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp25cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp25cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp26cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp26cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp27cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp27cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg7: + rv32: + accessible: true + pmp28cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp28cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp29cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp29cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp30cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp30cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp31cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp31cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg8: + rv32: + accessible: true + pmp32cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp32cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp33cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp33cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp34cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp34cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp35cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp35cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg9: + rv32: + accessible: true + pmp36cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp36cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp37cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp37cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp38cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp38cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp39cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp39cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg10: + rv32: + accessible: true + pmp40cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp40cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp41cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp41cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp42cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp42cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp43cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp43cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg11: + rv32: + accessible: true + pmp44cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp44cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp45cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp45cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp46cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp46cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp47cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp47cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg12: + rv32: + accessible: true + pmp48cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp48cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp49cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp49cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp50cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp50cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp51cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp51cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg13: + rv32: + accessible: true + pmp52cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp52cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp53cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp53cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp54cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp54cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp55cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp55cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg14: + rv32: + accessible: true + pmp56cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp56cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp57cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp57cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp58cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp58cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp59cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp59cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg15: + rv32: + accessible: true + pmp60cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp60cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp61cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp61cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp62cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp62cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp63cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp63cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + mcycle: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mcycle[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + minstret: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - minstret[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + mcycleh: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mcycleh[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + minstreth: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - minstreth[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr0: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr0[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x20 + pmpaddr1: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr1[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr2: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr2[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr3: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr3[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr4: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr4[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr5: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr5[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr6: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr6[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr7: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr7[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr8: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr8[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr9: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr9[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr10: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr10[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr11: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr11[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr12: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr12[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr13: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr13[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr14: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr14[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr15: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr15[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr16: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr16[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr17: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr17[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr18: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr18[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr19: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr19[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr20: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr20[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr21: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr21[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr22: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr22[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr23: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr23[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr24: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr24[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr25: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr25[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr26: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr26[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr27: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr27[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr28: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr28[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr29: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr29[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr30: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr30[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr31: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr31[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr32: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr32[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr33: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr33[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr34: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr34[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr35: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr35[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr36: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr36[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr37: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr37[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr38: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr38[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr39: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr39[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr40: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr40[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr41: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr41[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr42: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr42[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr43: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr43[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr44: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr44[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr45: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr45[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr46: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr46[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr47: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr47[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr48: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr48[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr49: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr49[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr50: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr50[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr51: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr51[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr52: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr52[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr53: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr53[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr54: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr54[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr55: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr55[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr56: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr56[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr57: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr57[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr58: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr58[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr59: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr59[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr60: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr60[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr61: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr61[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr62: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr62[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr63: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr63[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + fcsr: + rv64: + accessible: false + rv32: + accessible: true + fflags: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - fflags[4:0] in [0x00:0x1F] + wr_illegal: + - Unchanged + frm: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - frm[2:0] in [0x0:0x7] + wr_illegal: + - Unchanged + time: + rv32: + accessible: true + type: + ro_variable: true + rv64: + accessible: false + reset-val: 0 + timeh: + rv32: + accessible: true + type: + ro_variable: true + rv64: + accessible: false + reset-val: 0 diff --git a/cookbook/functional_code_examples/br_j_asm/rv32i_platform.yaml b/cookbook/functional_code_examples/br_j_asm/rv32i_platform.yaml new file mode 100644 index 000000000..9748f523d --- /dev/null +++ b/cookbook/functional_code_examples/br_j_asm/rv32i_platform.yaml @@ -0,0 +1,15 @@ +nmi: + label: nmi_vector +reset: +# label: reset_vector +# address: 0x1000 + address: 0x80000000 +mtime: + implemented: True + address: 0x20000 + +# TODO: until we have a method for doing a memory map, +# we will keep with the original model of having 1 RAM +# block whose size can be given in MBs. +ram_size : 4 + diff --git a/cookbook/functional_code_examples/br_j_asm/test.S b/cookbook/functional_code_examples/br_j_asm/test.S new file mode 100644 index 000000000..a41ae51bd --- /dev/null +++ b/cookbook/functional_code_examples/br_j_asm/test.S @@ -0,0 +1,482 @@ +// vim: tabstop=2 shiftwidth=2 expandtab +// -------------------------------------------------------------------------------------------- +/// @file test.S +/// +/// LICENSE: +/// +/// Copyright 2021 Seagate Technology LLC and/or its Affiliates +/// +/// Licensed under the Apache License, Version 2.0 (the "License"); +/// you may not use this file except in compliance with the License. +/// You may obtain a copy of the License at +/// +/// http://www.apache.org/licenses/LICENSE-2.0 +/// +/// Unless required by applicable law or agreed to in writing, software +/// distributed under the License is distributed on an "AS IS" BASIS, +/// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +/// See the License for the specific language governing permissions and +/// limitations under the License. +/// +/// +/// +/// +/// @brief RISC-V asm code for testing code discontinuities with a RISC-V Trace encoder/decoder +/// +/// This is a *simple-and-short* test for providing stimulus to the Trace Encoder Module. +/// Do we get the expected trace messages and can we create the instruction +/// trace from these messages? +/// +/// This test executes roughly 250 instructions. It should generate most of +/// the basic trace messages. It does NOT test the te_support and message_lost +/// messages. +/// +/// The test generates a timer interrupt and a bad-opcode exception to check +/// for proper te_inst format 3 message behaviour. The interrupt handler +/// uses an mret to return. The bad-opcode exception handler does NOT perform +/// an 'mret'; instead it does a jump. +/// +/// Assembly language tests are notoriously difficult to read. This test is +/// worse than usual because I'm interested in testing forward and backward +/// branches and jumps. So, target destinations are placed not for readability, +/// but to test certain aspects of the trace messages. Sorry. +/// +/// No stack is set up for use. +/// +/// Threads are not used, supported or tested. +/// +/// Privilege levels are not changed. Everything is run in machine mode. +/// +/// With the exception of x0 (hardwired zero) and x1 (return address), all +/// registers are treated the same. The programmer is responsible for +/// consistent use of the registers. +/// +/// The convention for this test is to use the 'xN' nomenclature for register +/// names. This is to emphasize the fact that register usage is not +/// defined or enforced. +/// +/// This test utilizes the Berkeley tohost / fromhost convention. The convention +/// uses a pre-defined location in memory (label: 'tohost') to report +/// the success or failure of the test. If M[tohost] == 1, the test passed. +/// If M[tohost] == 1337 (0x539), then the test failed. +/// +/// One more important note: the initialization of Trace module is beyond the +/// scope of this test. The user must properly configure the +/// Trace module in order to get trace messages. +/// +/// +/// +/// @author Bill McSpadden (Seagate Technology) +// -------------------------------------------------------------------------------------------- + +#ifndef CONFIG_BASE +#error The C pre-processor variable, CONFIG_BASE, must be set. +#endif + + +// -------------------------------------------------------- +// Memory-mapped machine timer registers and other support +// for generating a timer interrupt + +//#define MMR_MTIMEL (CONFIG_BASE + 0x0000) +//#define MMR_MTIMEH (CONFIG_BASE + 0x0004) +//#define MMR_MTIMECMPL (CONFIG_BASE + 0x0008) +//#define MMR_MTIMECMPH (CONFIG_BASE + 0x000C) + +#define MMR_MTIMEL (CONFIG_BASE + 0xbff8) +#define MMR_MTIMEH (CONFIG_BASE + 0xbffc) +#define MMR_MTIMECMPL (CONFIG_BASE + 0x4000) +#define MMR_MTIMECMPH (CONFIG_BASE + 0x4004) + +#define TIMER_COUNT (100) +#define WATCHDOG_COUNT (100000) + +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 + +#define MIE_MTIE 0x80 + + +// -------------------------------------------------------- +// mcause bit definitions + +#define MCAUSE_SUPERVISOR_SOFTWARE_INTERRUPT (0x1 << (__riscv_xlen - 1) + 1) +#define MCAUSE_MACHINE_TIMER_INTERRUPT (0x1 << (__riscv_xlen - 1) + 7) +#define MCAUSE_ILLEGAL_INSTRUCTION (0x0 << (__riscv_xlen - 1) + 2) + +// -------------------------------------------------------- +// Support for tohost/fromhost + +#define PASS_CODE 1 +#define FAIL_CODE 1337 + + +// -------------------------------------------------------- +// Other test support definitions... + +#define BR_LOOP_COUNT 10 // For testing a simple br loop + + +// -------------------------------------------------------- +// Support for 32/64 bit compilation. + +#if __riscv_xlen == 64 +# define LREG ld +# define SREG sd +# define REGBYTES 8 +#else +# define LREG lw +# define SREG sw +# define REGBYTES 4 +#endif + + + +// -------------------------------------------------------- +// Following power-on reset, we start executing at _start. +// We jump to "reset_vector" +// + .section ".text.init" + .globl _start +_start: + la x5, reset_vector + jr x5 +// -------------------------------------------------------- + + +// -------------------------------------------------------- +// This block of code is placed (by placement in the code +// stream, not via the linker/loader) at a low address so +// that we can test a backwards jump (ie - a jump that will +// yield a negative offset). + .section ".text" +j_target_0: + nop + nop + la x5, j_target_2 + jalr x5 +// -------------------------------------------------------- + + +// -------------------------------------------------------- +// Initialization of the processor, starting with the +// register file. +reset_vector: + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + +// -------------------------------------------------------- +// PMP configuration + + # configure pmp to enable all accesses + li t0, 0x1f + csrw pmpcfg0, t0 + li t0, 0xffffffff + csrw pmpaddr0, t0 + +// -------------------------------------------------------- +// initialize machine trap vector + la x5, machine_trap_entry + csrw mtvec, x5 + +// -------------------------------------------------------- +// Initialization complete. Now for a series of branches and jumps. + +br_target_0: + nop + nop + li x5, 0 + beqz x5, br_target_1a // This is a forward branch + nop + nop + +br_target_1a: + li x5, BR_LOOP_COUNT + li x6, 1 +br_target_1: + nop + nop + sub x5, x5, x6 + bnez x5, br_target_1 // This is a backward branch + nop + nop + +// -------------------------------------------------------- +// Simple branches have been tested. Now let's do some simple +// tests of jumps. +br_target_2: + nop + nop + j j_target_1 // forwards jump; tests for positive offset + j j_target_end_fail // should never be taken + +j_target_1: + nop + nop + la x5, j_target_0 // backwards jump; tests for negative offset + jr x5 + j j_target_end_fail // should never be taken + +j_target_2: + nop + nop + la x5, timer_interrupt_test + jalr x5 + j j_target_end_fail // should never be taken + +j_exception_stimulus: + // Now, jump to a location that has an opcode of 0 + // This is an important test condition for RISC-V. The + // spec says that an except'd instruction is not retired. + // Yet, we really need to see the address of 'bad_opcode'. + // The trace spec handles this condition in that the address + // of the except'd instruction gets reported out in a message. + // Let's test it out.... + // + // Note that the excpetion handler for this case will *NOT* do an + // mret. It will jump to 'illegal_instruction_exception_return'. + + la x5, bad_opcode + jr x5 + j j_target_end_fail // should never be taken + +// -------------------------------------------------------- +// PASS: The end of the test, if successful +j_target_end_pass: + // exit code construction + li x10, PASS_CODE + la x13, tohost + sw x10, 0(x13) + la x5, j_target_end_pass + jalr x5 + j j_target_end_fail // should never be taken + +// -------------------------------------------------------- + +// -------------------------------------------------------- +// FAIL: The end of the test, if unsuccessful +j_target_end_fail: + // exit code construction + li x10, FAIL_CODE + la x13, tohost + sw x10, 0(x13) + la x5, j_target_end_fail + jalr x5 + +// -------------------------------------------------------- + +illegal_instruction_exception_return: + la x5, j_target_end_pass + jalr x5 + j j_target_end_fail // should never be taken + +// -------------------------------------------------------- +timer_interrupt_return: + la x5, j_exception_stimulus + jalr x5 + j j_target_end_fail // should never be taken + + +// -------------------------------------------------------- +// Now check to see if we can trace an interrupt. We'll use +// a timer to generate the interrupt. + +timer_interrupt_test: + addi x7, x0, TIMER_COUNT + + lui x8, MMR_MTIMECMPL >> 12 + sw x7, (MMR_MTIMECMPL & 0xfff)(x8) + + lui x8, MMR_MTIMECMPH >> 12 + sw x0, (MMR_MTIMECMPH & 0xfff)(x8) + + addi x7, x0, MIE_MTIE + csrs mie, x7 + + xor x8, x8, x8 // Clear the register + csrr x8, mstatus + + addi x7, x0, MSTATUS_MIE + csrs mstatus, x7 + + # Should get a timer interrupt sometime after setting mstatus.MIE + + li x6, WATCHDOG_COUNT // start count + li x4, 1 // decrement value + +timer_interrupt_long_loop: + + // Check to see if the timer interrupt handler wrote a memory + // location. + la x10, timer_interrupt_flag + lw x10, 0(x10) + li x11, 0x1 + beq x10, x11, timer_interrupt_return // this is the expected way to exit this loop. + // a timer interrupt is taken somewhere in the execution of this loop. + // the ISR for the timer will write the time interrupt flag to 1. + + sub x6, x6, x4 // decrement the loop count + csrr x8, mip // show mip in trace for debug + xor x8, x8, x8 + csrr x9, mstatus // show mstatus in trace for debug + xor x9, x9, x9 + bnez x6, timer_interrupt_long_loop // iterate again..... + + j j_target_end_fail // If we get here, timer_interrupt_flag was never written. + // this is probably due to the timer interrupt service routine + // never being called, which is probably because the interrupt + // never happened. failure + + +// -------------------------------------------------------- +// In support of vectored interrupt, although it's not +// being used in this test. + + .align 4 +machine_trap_entry: + j machine_trap_entry_0 + .align 2 + j machine_trap_entry_1 + .align 2 + j machine_trap_entry_2 + .align 2 + j machine_trap_entry_3 + .align 2 + j machine_trap_entry_4 + .align 2 + j machine_trap_entry_5 + .align 2 + j machine_trap_entry_6 + .align 2 + j machine_trap_entry_7 + .align 2 + j machine_trap_entry_8 + .align 2 + j machine_trap_entry_9 + .align 2 + j machine_trap_entry_10 + .align 2 + j machine_trap_entry_11 +// -------------------------------------------------------- + + +// -------------------------------------------------------- + .align 2 +machine_trap_entry_0: + csrr x7, mcause + li x6, MCAUSE_MACHINE_TIMER_INTERRUPT + bne x7, x6, not_a_timer_interrupt + li x6, 0x1 + la x7, timer_interrupt_flag + sw x6, 0(x7) + + // Turn off timer interrupt. No longer needed + addi x7, x0, MIE_MTIE + csrc mie, x7 + + // Clear interrupt + li x7, MSTATUS_MIE + csrc mstatus, x7 + + // and return + mret + +not_a_timer_interrupt: + // Do not try and correct the opcode, and do not + // do an mret. This should probably be the last + // part of this simple test. + csrr x7, mcause + li x6, MCAUSE_ILLEGAL_INSTRUCTION + beq x7, x6, illegal_instruction_exception_return + j j_target_end_fail +// -------------------------------------------------------- + +// -------------------------------------------------------- +// None of these machine traps should have been taken +// Jump to test failure +machine_trap_entry_1: +machine_trap_entry_2: +machine_trap_entry_3: +machine_trap_entry_4: +machine_trap_entry_5: +machine_trap_entry_6: +machine_trap_entry_7: +machine_trap_entry_8: +machine_trap_entry_9: +machine_trap_entry_10: +machine_trap_entry_11: + csrr x7, mcause // Do the read so that it appears in the log file for debug. + j j_target_end_fail +// -------------------------------------------------------- + + +// -------------------------------------------------------- +// Put a bad opcode (0x0000_0000) in memory as a bad opcode. +bad_opcode: + .word 0 + j j_target_end_fail // Should never get here. +// -------------------------------------------------------- + + + +// -------------------------------------------------------- +// Memory locations for specific usage. +.section ".tdata.begin" +.globl _tdata_begin +_tdata_begin: + +.section ".tdata.end" +.globl _tdata_end +_tdata_end: + +.section ".tbss.end" +.globl _tbss_end +_tbss_end: + +.section ".tohost","aw",@progbits +.align 6 +.globl tohost +tohost: .dword 0 + +.section ".fromhost","aw",@progbits +.align 6 +.globl fromhost +fromhost: .dword 0 + +.align 6 +.global timer_interrupt_flag +timer_interrupt_flag: .dword 0 + + + + diff --git a/cookbook/functional_code_examples/platform_configuration/Makefile b/cookbook/functional_code_examples/platform_configuration/Makefile new file mode 100644 index 000000000..0b078d964 --- /dev/null +++ b/cookbook/functional_code_examples/platform_configuration/Makefile @@ -0,0 +1,141 @@ +# vim: tabstop=4 shiftwidth=4 noexpandtab +# -------------------------------------------------------------------------------------------- +# @file Makefile +# +# LICENSE: +# +# Copyright 2021 Seagate Technology LLC and/or its Affiliates +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# +# +# @brief Makefile for building a sample test for stimulating a RISC-V trace encoder +# +# +# History: See git log +# +# @author Bill McSpadden (bill.mcspadden@seagate.com) +# -------------------------------------------------------------------------------------------- + + +# -------------------------------------------------------------------------------------------- +# USER MUST SET THESE TO A PROPER SETTING + +XLEN := 32 +TOOL_OPT := linux-gnu +RISCV := /opt/riscv${XLEN} +CONFIG_BASE := 0x80000000 +MARCH := -march=rv32imc -mabi=ilp32 +LD_FILE := ./riscv_test.ld +RUN_TOOL := ../../../c_emulator/riscv_sim_RV32 + +# USER MUST SET THESE TO A PROPER SETTING +# -------------------------------------------------------------------------------------------- +# +# + +ifndef RISCV +$(error The make variable, RISCV, must be set. It is the path to the compiler tool chain) +endif + +ifndef CONFIG_BASE +$(error The make variable, CONFIG_BASE, is not defined. It is needed for the test variable, also named CONFIG_BASE) +endif + +ifndef MARCH +$(error The make variable, MARCH, must be set.) +endif + +ifndef RUN_TOOL +$(error The make variable, RUN_TOOL, must be set.) +endif + + +BIN := ${RISCV}/bin + +CC := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-gcc +ASM := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-gcc +LD := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-ld +OBJDUMP := ${BIN}/riscv${XLEN}-unknown-${TOOL_OPT}-objdump + +TARGET := test.elf +DUMP := $(subst .elf,.dump,${TARGET}) + +ASM_SRC := $(wildcard *.S *.s) +ASM_OBJS := $(subst .S,.o,${ASM_SRC}) +ASM_FLAGS := -DCONFIG_BASE=${CONFIG_BASE} ${MARCH} +OBJDUMPFLAGS = -t -Dz -Mnumeric + +C_SRC := $(wildcard *.c) +C_OBJS := $(subst .c,.o,${C_SRC}) +C_FLAGS := -DCONFIG_BASE=${CONFIG_BASE} ${MARCH} + +LD_FLAGS := -T ${LD_FILE} + +OBJS := ${ASM_OBJS} ${C_OBJS} + +OUT_FILE := ./sim.out + +$(info =================================================================) +$(info Make variable settings....) +$(info RISCV: ${RISCV}) +$(info ASM_SRC: ${ASM_SRC}) +$(info ASM_FLAGS: ${ASM_FLAGS}) +$(info ASM_OBJS: ${ASM_OBJS}) +$(info C_SRC: ${C_SRC}) +$(info C_FLAGS: ${C_FLAGS}) +$(info C_OBJS: ${C_OBJS}) +$(info OBJS: ${OBJS}) +$(info LD_FLAGS: ${LD_FLAGS}) +$(info TARGET: ${TARGET}) +$(info DUMP: ${DUMP}) +$(info =================================================================) + +all: ${TARGET} ${DUMP} + +${TARGET} : ${OBJS} ${LD_FILE} + ${LD} ${LD_FLAGS} -o $@ ${OBJS} + +${DUMP} : ${TARGET} + ${OBJDUMP} ${OBJDUMPFLAGS} ${TARGET} > $@ + +%.o : %.S + ${ASM} -c ${ASM_FLAGS} -o $@ $< + +%.o : %.c + ${CC} -c ${C_FLAGS} -o $@ $< + +build: ${TARGET} ${DUMP} + +dump: ${DUMP} + +install: + +clean: + rm -f ${OBJS} ${TARGET} ${DUMP} ${OUT_FILE} + +run: ${TARGET} + ${RUN_TOOL} ${TARGET} -y rv32i_platform.yaml -u rv32i_isa.yaml 2>&1 | tee ${OUT_FILE} + +ddd: ${TARGET} + echo "${TARGET} -y rv32i_platform.yaml -u rv32i_isa.yaml" ; + ddd ${RUN_TOOL} + +clean_all: clean + + + + + + diff --git a/cookbook/functional_code_examples/platform_configuration/riscv_test.ld b/cookbook/functional_code_examples/platform_configuration/riscv_test.ld new file mode 100644 index 000000000..d04f359da --- /dev/null +++ b/cookbook/functional_code_examples/platform_configuration/riscv_test.ld @@ -0,0 +1,84 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +/******************************************************************************************* +/// LICENSE: +/// +/// Copyright 2021 Seagate Technology LLC and/or its Affiliates +/// +/// Licensed under the Apache License, Version 2.0 (the "License"); +/// you may not use this file except in compliance with the License. +/// You may obtain a copy of the License at +/// +/// http://www.apache.org/licenses/LICENSE-2.0 +/// +/// Unless required by applicable law or agreed to in writing, software +/// distributed under the License is distributed on an "AS IS" BASIS, +/// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +/// See the License for the specific language governing permissions and +/// limitations under the License. +********************************************************************************************/ + +/*----------------------------------------------------------------------*/ +/* Sections */ +/*----------------------------------------------------------------------*/ + +SECTIONS +{ + + /* text: test code section */ +/*. = 0x00000040; */ + . = 0x00001000; +/* + . = 0x80000000; +*/ + .rotext.init : { *(.rotext.init) } + + /* + making the symbol, reset_vector, a global, put the + reset vector at 0x80000000 + */ + . = 0x80000000; + .text.begin . : { *(.text.begin) } + + + /* data segment */ +/*. = 0x00080000; */ + .tohost ALIGN(0x1000) : { *(.tohost) } + .data : { *(.data) } + .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) } + .sdata : { + __global_pointer$ = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } + + /* bss segment */ + .sbss : { + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } + .bss : { *(.bss) } + + /* thread-local data segment */ + .tdata : + { + _tls_data = .; + *(.tdata.begin) + *(.tdata) + *(.tdata.end) + } + .tbss : + { + *(.tbss) + *(.tbss.end) + } + + __malloc_start = .; + . = . + 32768; + + /* End of uninitalized data segement */ + _end = .; + +} + diff --git a/cookbook/functional_code_examples/platform_configuration/rv32i_isa.yaml b/cookbook/functional_code_examples/platform_configuration/rv32i_isa.yaml new file mode 100644 index 000000000..68f3c85da --- /dev/null +++ b/cookbook/functional_code_examples/platform_configuration/rv32i_isa.yaml @@ -0,0 +1,3096 @@ +hart_ids: [0] +hart0: &hart0 +# ISA: RV32IMAFCNSHUZicsr_Zifencei + ISA: RV64IMAFCNSHUZicsr_Zifencei_Ssptead + User_Spec_Version: '2.3' + supported_xlen: [32] + physical_addr_sz: 32 + pmp_granularity: 5 + hw_data_misaligned_support : true +# pte_dirty_update_enable : true # TODO: look for Ssptead in ISA string + misa: + reset-val: 0x401431A5 + rv32: + accessible: true + mxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + + - mxl[1:0] in [0x1] + wr_illegal: + - unchanged + extensions: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - extensions[25:0] in [0x0000000:0x3FFFFFF] + wr_illegal: + - unchanged + mvendorid: + reset-val: 0xdeadbeef + rv32: + accessible: true + type: + ro_constant: 0xdeadbeef + rv64: + accessible: false + mtvec: + reset-val: 0x80010000 + rv32: + accessible: true + base: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - "base[29:0] bitmask [0x3FFFFFFF, 0x00000000]" + wr_illegal: + - "Unchanged" + mode: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - "mode[1:0] in [0x0,0x1]" + wr_illegal: + - "Unchanged" + sstatus: + reset-val: 0x0 + rv32: + accessible: true + uie: + implemented: false + sie: + implemented: true + upie: + implemented: false + spie: + implemented: true + spp: + implemented: true + fs: + implemented: false + xs: + implemented: true + sum: + implemented: true + mxr: + implemented: true + sd: + implemented: true + rv64: + accessible: false + vsstatus: + reset-val: 0x0 + rv32: + accessible: true + uie: + implemented: false + sie: + implemented: true + upie: + implemented: false + spie: + implemented: true + spp: + implemented: true + fs: + implemented: false + xs: + implemented: true + sum: + implemented: true + mxr: + implemented: true + sd: + implemented: true + rv64: + accessible: false + mstatus: + reset-val: 0x0 + rv32: + accessible: true + uie: + implemented: true + sie: + implemented: true + type: + wlrl: [0:1] + mie: + implemented: true + upie: + implemented: true + spie: + implemented: true + type: + wlrl: [0:1] + mpie: + implemented: true + spp: + implemented: true + type: + wlrl: [0:1] + mpp: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - mpp[1:0] in [0x0, 0x3] + wr_illegal: + - Unchanged + fs: + implemented: false + xs: + implemented: true + type: + ro_variable: true + mprv: + implemented: true + type: + wlrl: [0:1] + sum: + implemented: true + type: + wlrl: [0:1] + mxr: + implemented: true + type: + wlrl: [0:1] + tvm: + implemented: true + type: + wlrl: [0:1] + tw: + implemented: false + tsr: + implemented: true + type: + wlrl: [0:1] + sd: + implemented: true + type: + ro_variable: true + rv64: + accessible: false + + mip: + reset-val: 0 + rv32: + accessible: true + usip: + implemented: true + ssip: + implemented: true + msip: + implemented: true + type: + ro_variable: true + utip: + implemented: true + stip: + implemented: true + mtip: + implemented: true + type: + ro_variable: [0x01] + ueip: + implemented: true + seip: + implemented: true + meip: + implemented: true + type: + ro_variable: true + rv64: + accessible: false + hip: + reset-val: 0 + rv32: + accessible: true + vssip: + implemented: true + vstip: + implemented: true + vseip: + implemented: true + sgeip: + implemented: true + type: + ro_variable: true + rv64: + accessible: false + mie: + reset-val: 0 + rv32: + accessible: true + usie: + implemented: true + ssie: + implemented: true + msie: + implemented: true + type: + ro_variable: true + utie: + implemented: true + stie: + implemented: true + mtie: + implemented: true + ueie: + implemented: true + seie: + implemented: true + meie: + implemented: true + rv64: + accessible: false + hie: + reset-val: 0 + rv32: + accessible: true + vssie: + implemented: true + vstie: + implemented: true + vseie: + implemented: true + sgeie: + implemented: true + rv64: + accessible: false + mepc: + reset-val: 0x0 + rv32: + accessible: true + rv64: + accessible: false + mtval: + reset-val: 0x0 + has_illegal_inst_bits : false + rv32: + accessible: true + rv64: + accessible: false + mcause: + reset-val: 0 + rv32: + accessible: true + interrupt: + implemented: true + exception_code: + implemented: true + rv64: + accessible: false + + marchid: + rv32: + accessible: true + type: + ro_constant: 0x0 + rv64: + accessible: false + reset-val: 0x0 + mhartid: + rv32: + accessible: true + type: + ro_constant: 0x0 + rv64: + accessible: false + reset-val: 0x00 + mscratch: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mscratch[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter3: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter3[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + hpmcounter3: + rv32: + accessible: true + rv64: + accessible: false + reset-val: 0x0 + hpmcounter3h: + rv32: + accessible: true + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter4: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter4[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter4h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter4h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter5: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter5[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter6: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter6[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter7: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter7[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter8: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter8[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter9: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter9[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter10: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter10[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter11: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter11[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter12: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter12[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter13: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter13[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter14: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter14[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter15: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter15[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter16: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter16[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter17: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter17[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter18: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter18[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter19: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter19[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter20: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter20[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter21: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter21[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter22: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter22[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter23: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter23[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter24: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter24[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter25: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter25[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter26: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter26[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter27: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter27[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter28: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter28[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter29: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter29[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter30: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter30[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter31: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter31[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + + mhpmcounter3h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter3h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter5h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter5h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter6h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter6h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter7h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter7h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter8h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter8h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter9h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter9h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter10h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter10h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter11h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter11h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter12h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter12h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter13h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter13h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter14h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter14h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter15h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter15h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter16h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter16h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter17h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter17h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter18h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter18h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter19h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter19h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter20h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter20h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter21h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter21h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter22h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter22h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter23h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter23h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter24h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter24h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter25h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter25h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter26h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter26h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter27h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter27h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter28h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter28h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter29h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter29h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter30h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter30h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmcounter31h: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcounter31h[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mcountinhibit: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmcountinhibit[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent3: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent3[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent4: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent4[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent5: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent5[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent6: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent6[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent7: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent7[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent8: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent8[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent9: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent9[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent10: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent10[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent11: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent11[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent12: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent12[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent13: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent13[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent14: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent14[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent15: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent15[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent16: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent16[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent17: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent17[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent18: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent18[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent19: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent19[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent20: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent20[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent21: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent21[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent22: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent22[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent23: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent23[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent24: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent24[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent25: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent25[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent26: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent26[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent27: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent27[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent28: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent28[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent29: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent29[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent30: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent30[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mhpmevent31: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mhpmevent31[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x0 + mimpid: + rv32: + accessible: true + type: + ro_constant: 0x0 + rv64: + accessible: false + reset-val: 0 + mcounteren: + rv32: + accessible: true + rv64: + accessible: false + reset-val: 0 + pmpcfg0: + rv32: + accessible: true + pmp0cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp0cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp1cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp1cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp2cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp2cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp3cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp3cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg1: + rv32: + accessible: true + pmp4cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp4cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp5cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp5cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp6cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp6cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp7cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp7cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg2: + rv32: + accessible: true + pmp8cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp8cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp9cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp9cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp10cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp10cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp11cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp11cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg3: + rv32: + accessible: true + pmp12cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp12cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp13cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp13cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp14cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp14cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp15cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp15cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg4: + rv32: + accessible: true + pmp16cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp16cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp17cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp17cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp18cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp18cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp19cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp19cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg5: + rv32: + accessible: true + pmp20cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp20cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp21cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp21cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp22cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp22cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp23cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp23cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg6: + rv32: + accessible: true + pmp24cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp24cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp25cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp25cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp26cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp26cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp27cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp27cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg7: + rv32: + accessible: true + pmp28cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp28cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp29cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp29cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp30cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp30cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp31cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp31cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg8: + rv32: + accessible: true + pmp32cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp32cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp33cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp33cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp34cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp34cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp35cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp35cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg9: + rv32: + accessible: true + pmp36cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp36cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp37cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp37cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp38cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp38cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp39cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp39cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg10: + rv32: + accessible: true + pmp40cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp40cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp41cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp41cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp42cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp42cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp43cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp43cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg11: + rv32: + accessible: true + pmp44cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp44cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp45cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp45cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp46cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp46cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp47cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp47cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg12: + rv32: + accessible: true + pmp48cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp48cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp49cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp49cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp50cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp50cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp51cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp51cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg13: + rv32: + accessible: true + pmp52cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp52cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp53cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp53cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp54cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp54cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp55cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp55cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg14: + rv32: + accessible: true + pmp56cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp56cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp57cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp57cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp58cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp58cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp59cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp59cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpcfg15: + rv32: + accessible: true + pmp60cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp60cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp61cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp61cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp62cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp62cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + pmp63cfg: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - pmp63cfg[7:0] in [0x00:0xFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + mcycle: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mcycle[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + minstret: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - minstret[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + mcycleh: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - mcycleh[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + minstreth: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - minstreth[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr0: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr0[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0x20 + pmpaddr1: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr1[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr2: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr2[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr3: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr3[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr4: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr4[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr5: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr5[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr6: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr6[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr7: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr7[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr8: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr8[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr9: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr9[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr10: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr10[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr11: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr11[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr12: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr12[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr13: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr13[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr14: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr14[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr15: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr15[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr16: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr16[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr17: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr17[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr18: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr18[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr19: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr19[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr20: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr20[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr21: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr21[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr22: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr22[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr23: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr23[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr24: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr24[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr25: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr25[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr26: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr26[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr27: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr27[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr28: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr28[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr29: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr29[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr30: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr30[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr31: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr31[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr32: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr32[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr33: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr33[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr34: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr34[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr35: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr35[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr36: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr36[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr37: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr37[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr38: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr38[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr39: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr39[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr40: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr40[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr41: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr41[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr42: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr42[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr43: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr43[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr44: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr44[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr45: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr45[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr46: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr46[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr47: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr47[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr48: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr48[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr49: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr49[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr50: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr50[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr51: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr51[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr52: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr52[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr53: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr53[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr54: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr54[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr55: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr55[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr56: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr56[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr57: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr57[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr58: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr58[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + + pmpaddr59: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr59[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr60: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr60[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr61: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr61[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr62: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr62[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + pmpaddr63: + rv32: + accessible: true + type: + warl: + dependency_fields: [] + legal: + - pmpaddr63[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + reset-val: 0 + fcsr: + rv64: + accessible: false + rv32: + accessible: true + fflags: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - fflags[4:0] in [0x00:0x1F] + wr_illegal: + - Unchanged + frm: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - frm[2:0] in [0x0:0x7] + wr_illegal: + - Unchanged + time: + rv32: + accessible: true + type: + ro_variable: true + rv64: + accessible: false + reset-val: 0 + timeh: + rv32: + accessible: true + type: + ro_variable: true + rv64: + accessible: false + reset-val: 0 diff --git a/cookbook/functional_code_examples/platform_configuration/rv32i_platform.yaml b/cookbook/functional_code_examples/platform_configuration/rv32i_platform.yaml new file mode 100644 index 000000000..9748f523d --- /dev/null +++ b/cookbook/functional_code_examples/platform_configuration/rv32i_platform.yaml @@ -0,0 +1,15 @@ +nmi: + label: nmi_vector +reset: +# label: reset_vector +# address: 0x1000 + address: 0x80000000 +mtime: + implemented: True + address: 0x20000 + +# TODO: until we have a method for doing a memory map, +# we will keep with the original model of having 1 RAM +# block whose size can be given in MBs. +ram_size : 4 + diff --git a/cookbook/functional_code_examples/platform_configuration/test.S b/cookbook/functional_code_examples/platform_configuration/test.S new file mode 100644 index 000000000..f2d1e39d7 --- /dev/null +++ b/cookbook/functional_code_examples/platform_configuration/test.S @@ -0,0 +1,162 @@ +// vim: tabstop=2 shiftwidth=2 expandtab +// -------------------------------------------------------------------------------------------- +// File: test.S +// +// Description: +// +// Author: Bill McSpadden (bill@riscv.org) +// -------------------------------------------------------------------------------------------- + +// -------------------------------------------------------- +// Support for 32/64 bit compilation. + +#if __riscv_xlen == 64 +# define LREG ld +# define SREG sd +# define REGBYTES 8 +#else +# define LREG lw +# define SREG sw +# define REGBYTES 4 +#endif + + +// -------------------------------------------------------- +// Support for tohost/fromhost + +#define PASS_CODE 1 +#define FAIL_CODE 1337 + + +// -------------------------------------------------------- +// Following power-on reset, we start executing at _start. +// We jump to "reset_vector" +// +// .section ".text.init" + .section ".rotext.init" + .globl _start +_start: +// The following is a re-write of the "rom" code that is +// in riscv_sim.c (around lines 509-521). I want to get +// rid of that bit of code in riscv_sim.c + +// auipc t0, 0x0 + auipc x5, 0x0 +// addi a1, t0, &dtb // What is dtb??? + addi x11, x5, (8 * 4) // What is the purpose of this instruction? +// csrr a0, mhartid + csrr x10, mhartid +// LREG t0, 24(t0) + la t0, reset_vector + jr t0 + + + +// -------------------------------------------------------- + + +// .section ".text" + .section ".text.begin" + .global reset_vector // This pushed the symbol, reset_vector, to 0x80000000 +// -------------------------------------------------------- +// Initialization of the processor, starting with the +// register file. +reset_vector: + + li x1, 0 + li x2, 0 + li x3, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + +// -------------------------------------------------------- +// PMP configuration + + # configure pmp to enable all accesses + li t0, 0x1f + csrw pmpcfg0, t0 + li t0, 0xffffffff + csrw pmpaddr0, t0 + + +// -------------------------------------------------------- +// PASS: The end of the test, if successful +j_target_end_pass: + // exit code construction + li x10, PASS_CODE + la x13, tohost + sw x10, 0(x13) + la x5, j_target_end_pass + jalr x5 + j j_target_end_fail // should never be taken + +// -------------------------------------------------------- + +// -------------------------------------------------------- +// FAIL: The end of the test, if unsuccessful +j_target_end_fail: + // exit code construction + li x10, FAIL_CODE + la x13, tohost + sw x10, 0(x13) + la x5, j_target_end_fail + jalr x5 + + +// -------------------------------------------------------- +// Memory locations for specific usage. +.section ".tdata.begin" +.globl _tdata_begin +_tdata_begin: + +.section ".tdata.end" +.globl _tdata_end +_tdata_end: + +.section ".tbss.end" +.globl _tbss_end +_tbss_end: + +.section ".tohost","aw",@progbits +.align 6 +.globl tohost +tohost: .dword 0 + +.section ".fromhost","aw",@progbits +.align 6 +.globl fromhost +fromhost: .dword 0 + +.align 6 +.global timer_interrupt_flag +timer_interrupt_flag: .dword 0 + + + + diff --git a/model/main.sail b/model/main.sail index e4b1e0db5..db4ecb6d0 100644 --- a/model/main.sail +++ b/model/main.sail @@ -66,12 +66,23 @@ /* SUCH DAMAGE. */ /*=======================================================================================*/ +$include "rv_cfg_func_sigs.sail" + function main () : unit -> unit = { + + print("hello from main() in main.sail\n"); + + let reset_address : int = rv_cfg_int( "/reset/address") ; + print_int("/reset/address: 0x%x\n", reset_address); + // initialize extensions ext_init (); + + // PC = __GetSlice_int(64, elf_entry(), 0); PC = sail_zero_extend(0x1000, sizeof(xlen)); + // PC = sail_zero_extend(reset_address, sizeof(xlen)); print_bits("PC = ", PC); try { diff --git a/model/prelude.sail b/model/prelude.sail index fbf30ff7b..bdb15ab07 100644 --- a/model/prelude.sail +++ b/model/prelude.sail @@ -74,6 +74,7 @@ $include $include $include $include +$include "rv_cfg_func_sigs.sail" val string_startswith = "string_startswith" : (string, string) -> bool val string_drop = "string_drop" : (string, nat) -> string @@ -327,3 +328,7 @@ val def_spc_backwards : string -> unit function def_spc_backwards s = () val def_spc_matches_prefix : string -> option((unit, nat)) function def_spc_matches_prefix s = opt_spc_matches_prefix(s) + + + + diff --git a/model/riscv_csr_map.sail b/model/riscv_csr_map.sail index 31872d3f1..1e2fa2a60 100644 --- a/model/riscv_csr_map.sail +++ b/model/riscv_csr_map.sail @@ -116,6 +116,8 @@ mapping clause csr_name_map = 0xF11 <-> "mvendorid" mapping clause csr_name_map = 0xF12 <-> "marchid" mapping clause csr_name_map = 0xF13 <-> "mimpid" mapping clause csr_name_map = 0xF14 <-> "mhartid" +mapping clause csr_name_map = 0xFC0 <-> "xmpl_csr" // Custom CSR example +mapping clause csr_name_map = 0xFC1 <-> "xmpl_2_csr" // Custom CSR example /* machine trap setup */ mapping clause csr_name_map = 0x300 <-> "mstatus" mapping clause csr_name_map = 0x301 <-> "misa" diff --git a/model/riscv_insts_zicsr.sail b/model/riscv_insts_zicsr.sail index 08c7a19a0..3281f2186 100644 --- a/model/riscv_insts_zicsr.sail +++ b/model/riscv_insts_zicsr.sail @@ -136,6 +136,10 @@ function readCSR csr : csreg -> xlenbits = { /* trigger/debug */ (0x7a0, _) => ~(tselect), /* this indicates we don't have any trigger support */ + /* machine mode, custom extension example */ + (0xFC0, _) => xmpl_csr, // error: Xmpl_csr is not a subtype of bitvector(32, dec) + (0xFC1, _) => xmpl_csr_2.bits(), + /* supervisor mode */ (0x100, _) => lower_mstatus(mstatus).bits(), (0x102, _) => sedeleg.bits(), diff --git a/model/riscv_step.sail b/model/riscv_step.sail index 8d19ebfa9..7d6a289b7 100644 --- a/model/riscv_step.sail +++ b/model/riscv_step.sail @@ -66,10 +66,13 @@ /* SUCH DAMAGE. */ /*=======================================================================================*/ +$include "rv_cfg_func_sigs.sail" + /* The emulator fetch-execute-interrupt dispatch loop. */ /* returns whether to increment the step count in the trace */ function step(step_no : int) -> bool = { + print(__FILE__); print(__LOC__); print("entering step() function...\n"); /* for step extensions */ ext_pre_step_hook(); @@ -173,6 +176,9 @@ function init_model () -> unit = { init_sys (); /* processor */ init_vmem (); /* virtual memory */ + let isa_str : string = rv_cfg_string("hart0/ISA"); + print_string("isa_str: ", isa_str); print("\n"); + /* initialize extensions last */ ext_init (); ext_init_regs (); diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail index 668136776..33443171a 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail @@ -130,6 +130,10 @@ function is_CSR_defined (csr : csreg, p : Privilege) -> bool = /* disabled trigger/debug module */ 0x7a0 => p == Machine, + /* custom CSRs */ + 0xFC0 => p == Machine, // xmpl_csr Example custom csr + 0xFC1 => p == Machine, // xmpl_csr_2 Example custom csr + /* supervisor mode: trap setup */ 0x100 => haveSupMode() & (p == Machine | p == Supervisor), // sstatus 0x102 => haveSupMode() & haveNExt() & (p == Machine | p == Supervisor), // sedeleg diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index e1576ed6f..dd1068067 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -144,7 +144,7 @@ val sys_enable_writable_misa = {c: "sys_enable_writable_misa", ocaml: "Platform. val sys_enable_rvc = {c: "sys_enable_rvc", ocaml: "Platform.enable_rvc", _: "sys_enable_rvc"} : unit -> bool /* whether misa.{f,d} were enabled at boot */ val sys_enable_fdext = {c: "sys_enable_fdext", ocaml: "Platform.enable_fdext", _: "sys_enable_fdext"} : unit -> bool -/* whether zfinx was enabled at boot */ +/* whether zfinx was enabled at boot/* Custom CSR example */ */ val sys_enable_zfinx = {c: "sys_enable_zfinx", ocaml: "Platform.enable_zfinx", _: "sys_enable_zfinx"} : unit -> bool /* whether the N extension was enabled at boot */ val sys_enable_next = {c: "sys_enable_next", ocaml: "Platform.enable_next", _: "sys_enable_next"} : unit -> bool @@ -824,3 +824,40 @@ function read_seed_csr() -> xlenbits = { /* Writes to the seed CSR are ignored */ function write_seed_csr () -> option(xlenbits) = None() + + +/* Custom CSR example */ + +bitfield Xmpl_csr : bitvector(32, dec) = { + Rsrvd : (xlen - 1) .. (xlen - 7), + FieldWARL : (xlen - 8) .. 0 +} + +register xmpl_csr : bitvector(32, dec) + +function legalize_xmpl_csr(o : Xmpl_csr, v : bitvector(32, dec)) -> bitvector(32, dec) = { + let v = Mk_Xmpl_csr(v); + // TODO: Write a meaningful legalize function. + // Just return the register value for now + xmpl_csr +} + +bitfield Xmpl_csr_2 : xlenbits = { + Rsrvd : (xlen - 1) .. (xlen - 7), + FieldWARL : (xlen - 8) .. 0 +} +register xmpl_csr_2 : Xmpl_csr_2 + +function legalize_xmpl_csr_2(o : Xmpl_csr_2, v : bitvector(32, dec)) -> bitvector(32, dec) = { + let v = Mk_Xmpl_csr_2(v); + // TODO: Write a meaningful legalize function. + // Just return the register value for now + xmpl_csr_2.bits() +} + + + + + + + diff --git a/model/riscv_types.sail b/model/riscv_types.sail index 9b9323ee9..dcbc5a050 100644 --- a/model/riscv_types.sail +++ b/model/riscv_types.sail @@ -379,6 +379,7 @@ type csrRW = bits(2) /* read/write */ /* instruction opcode grouping */ enum uop = {RISCV_LUI, RISCV_AUIPC} /* upper immediate ops */ +enum xop = {RISCV_X_XMPL} /* custom extensions */ enum bop = {RISCV_BEQ, RISCV_BNE, RISCV_BLT, RISCV_BGE, RISCV_BLTU, RISCV_BGEU} /* branch ops */ enum iop = {RISCV_ADDI, RISCV_SLTI, RISCV_SLTIU, diff --git a/model/rv_cfg_func_sigs.sail b/model/rv_cfg_func_sigs.sail new file mode 100644 index 000000000..b4f6e5ef2 --- /dev/null +++ b/model/rv_cfg_func_sigs.sail @@ -0,0 +1,78 @@ +/*=======================================================================================*/ +/* RISCV Sail Model */ +/* */ +/* This Sail RISC-V architecture model, comprising all files and */ +/* directories except for the snapshots of the Lem and Sail libraries */ +/* in the prover_snapshots directory (which include copies of their */ +/* licences), is subject to the BSD two-clause licence below. */ +/* */ +/* Copyright (c) 2017-2021 */ +/* Prashanth Mundkur */ +/* Rishiyur S. Nikhil and Bluespec, Inc. */ +/* Jon French */ +/* Brian Campbell */ +/* Robert Norton-Wright */ +/* Alasdair Armstrong */ +/* Thomas Bauereiss */ +/* Shaked Flur */ +/* Christopher Pulte */ +/* Peter Sewell */ +/* Alexander Richardson */ +/* Hesham Almatary */ +/* Jessica Clarke */ +/* Microsoft, for contributions by Robert Norton-Wright and Nathaniel Wesley Filardo */ +/* Peter Rugg */ +/* Aril Computer Corp., for contributions by Scott Johnson */ +/* William McSpadden, RISC-V International */ +/* */ +/* All rights reserved. */ +/* */ +/* This software was developed by the above within the Rigorous */ +/* Engineering of Mainstream Systems (REMS) project, partly funded by */ +/* EPSRC grant EP/K008528/1, at the Universities of Cambridge and */ +/* Edinburgh. */ +/* */ +/* This software was developed by SRI International and the University of */ +/* Cambridge Computer Laboratory (Department of Computer Science and */ +/* Technology) under DARPA/AFRL contract FA8650-18-C-7809 ("CIFV"), and */ +/* under DARPA contract HR0011-18-C-0016 ("ECATS") as part of the DARPA */ +/* SSITH research programme. */ +/* */ +/* This project has received funding from the European Research Council */ +/* (ERC) under the European Union’s Horizon 2020 research and innovation */ +/* programme (grant agreement 789108, ELVER). */ +/* */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* 1. Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* 2. Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ +/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ +/* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ +/* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ +/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ +/* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ +/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ +/* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ +/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ +/* SUCH DAMAGE. */ +/*=======================================================================================*/ + + +/* functions for accessing RISC-V Config data */ +val rv_cfg_int = { c: "rv_cfg_s_int" } : string -> int +val rv_cfg_string = { c: "rv_cfg_s_string" } : string -> string +//val rv_cfg_bool = { c: "rv_cfg_s_bool" } : string -> int +val rv_cfg_bool = { c: "rv_cfg_s_bool" } : string -> bool + + +