things are back to working, sort of. the test, platform_configuration…

…, is executing.
riscv · Aug 3, 2022 · f9b795e · f9b795e
1 parent 84ea6fb
commit f9b795e
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Showing 7 changed files with 54 additions and 42 deletions.
diff --git a/c_emulator/cfunc.c b/c_emulator/cfunc.c
@@ -92,6 +92,11 @@ rv_cfg_build_from_file(rv_cfg_e rv_cfg_type, char * filename )
         return(0);
         }
     rv_cfg_enum2doc_a[rv_cfg_type].filename = filename;
+    rv_cfg_enum2doc_a[rv_cfg_type].e        = rv_cfg_type;
+
+    printf("%s, %d: rv_cfg file, '%s', loaded successfully as %s.\n", 
+            __FILE__, __LINE__, rv_cfg_enum2doc_a[rv_cfg_type].filename, 
+            rv_cfg_get_string(rv_cfg_enum2doc_a[rv_cfg_type].e));
 
     return (1);
     }

diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c
@@ -505,30 +505,30 @@ void init_sail_reset_vector(uint64_t entry)
 //  the Sail model setting up and executing any code.  BUT....
 //  the question is:  will the Sail model load the .elf file
 //  into the appropriate place in memory?
-//
-//#define RST_VEC_SIZE 8
-//  uint32_t reset_vec[RST_VEC_SIZE] = {
-//    0x297,                                      // auipc  t0,0x0
-//    0x28593 + (RST_VEC_SIZE * 4 << 20),         // addi   a1, t0, &dtb
-//    0xf1402573,                                 // csrr   a0, mhartid
-//    is_32bit_model() ?
-//      0x0182a283u :                             // lw     t0,24(t0)
-//      0x0182b283u,                              // ld     t0,24(t0)
-//    0x28067,                                    // jr     t0
-//    0,
-//    (uint32_t) (entry & 0xffffffff),
-//    (uint32_t) (entry >> 32)
-//  };
-//
+
+#define RST_VEC_SIZE 8
+  uint32_t reset_vec[RST_VEC_SIZE] = {
+    0x297,                                      // auipc  t0,0x0
+    0x28593 + (RST_VEC_SIZE * 4 << 20),         // addi   a1, t0, &dtb
+    0xf1402573,                                 // csrr   a0, mhartid
+    is_32bit_model() ?
+      0x0182a283u :                             // lw     t0,24(t0)
+      0x0182b283u,                              // ld     t0,24(t0)
+    0x28067,                                    // jr     t0
+    0,
+    (uint32_t) (entry & 0xffffffff),
+    (uint32_t) (entry >> 32)
+  };
+
   rv_rom_base = DEFAULT_RSTVEC;
   uint64_t addr = rv_rom_base;
-//  for (int i = 0; i < sizeof(reset_vec); i++)
-//    write_mem(addr++, (uint64_t)((char *)reset_vec)[i]);
-//
-//  if (dtb && dtb_len) {
-//    for (size_t i = 0; i < dtb_len; i++)
-//      write_mem(addr++, dtb[i]);
-//  }
+  for (int i = 0; i < sizeof(reset_vec); i++)
+    write_mem(addr++, (uint64_t)((char *)reset_vec)[i]);
+
+  if (dtb && dtb_len) {
+    for (size_t i = 0; i < dtb_len; i++)
+      write_mem(addr++, dtb[i]);
+  }
 
 #ifdef ENABLE_SPIKE
   if (dtb && dtb_len) {

diff --git a/cookbook/functional_code_examples/br_j_asm/Makefile b/cookbook/functional_code_examples/br_j_asm/Makefile
@@ -43,7 +43,9 @@ RISCV			:= /opt/riscv${XLEN}
 CONFIG_BASE		:= 0x80000000
 MARCH          	:= -march=rv32imc -mabi=ilp32
 LD_FILE			:= ./riscv_test.ld
-RUN_TOOL		:= /home/billmc/riscv/sail-riscv.git/c_emulator/riscv_sim_RV32
+#RUN_TOOL		:= /home/billmc/riscv/sail-riscv.git/c_emulator/riscv_sim_RV32
+GIT_ROOT_DIR	:= /home/billmc/riscv/sail-riscv_br_billmcspadden-riscv.git
+RUN_TOOL		:= ${GIT_ROOT_DIR}/c_emulator/riscv_sim_RV32
 
 # USER MUST SET THESE TO A PROPER SETTING
 # --------------------------------------------------------------------------------------------

diff --git a/cookbook/functional_code_examples/platform_configuration/Makefile b/cookbook/functional_code_examples/platform_configuration/Makefile
@@ -144,6 +144,9 @@ clean:
 run: ${TARGET}
 	${RUN_TOOL} ${TARGET} -y rv32i_platform.yaml -u rv32i_isa.yaml 2>&1 | tee ${OUT_FILE}
 
+#	${RUN_TOOL} ${TARGET}                                          2>&1 | tee ${OUT_FILE}
+
+
 clean_all: clean
 
 

diff --git a/cookbook/functional_code_examples/platform_configuration/riscv_test.ld b/cookbook/functional_code_examples/platform_configuration/riscv_test.ld
@@ -28,19 +28,11 @@ SECTIONS
 
   /* text: test code section */
 /*. = 0x00000040; */
-  . = 0x00001000; 
-/*
+/*. = 0x00001000; */
   . = 0x80000000;
-*/
-  .rotext.init : { *(.rotext.init) }
-
-  /* 
-  making the symbol, reset_vector, a global,  put the 
-  reset vector at 0x80000000
-  */
-  . = 0x80000000;
-  .text.begin . : { *(.text.begin) }
+  .text.init : { *(.text.init) }
 
+  .text : { *(.text) }
 
   /* data segment */
 /*. = 0x00080000; */

diff --git a/cookbook/functional_code_examples/platform_configuration/test.S b/cookbook/functional_code_examples/platform_configuration/test.S
@@ -7,6 +7,8 @@
 // Author:        Bill McSpadden ([email protected])
 // --------------------------------------------------------------------------------------------
 
+// --------------------------------------------------------
+// Support for 32/64 bit compilation.
 
 #if __riscv_xlen == 64
 # define LREG ld
@@ -18,33 +20,31 @@
 # define REGBYTES 4
 #endif
 
+
 // --------------------------------------------------------
 // Support for tohost/fromhost
 
 #define PASS_CODE       1
 #define FAIL_CODE       1337
 
 
-
-
 // --------------------------------------------------------
 // Following power-on reset, we start executing at _start.
-//  Put this code in ROM.
 //  We jump to "reset_vector"
 //
-  .section ".rotext.init"
+  .section ".text.init"
   .globl _start
 _start:
   la    x5,   reset_vector
   jr    x5
 // --------------------------------------------------------
 
+
+   .section ".text"
+
 // --------------------------------------------------------
 // Initialization of the processor, starting with the 
 //  register file.
-//  Put this code in RAM.
-  .section ".text.begin"
-  .global reset_vector    // This pushed the symbol, reset_vector, to 0x80000000
 reset_vector:
   li    x1,       0
   li    x2,       0
@@ -87,6 +87,7 @@ reset_vector:
   li    t0,       0xffffffff
   csrw  pmpaddr0, t0
 
+
 // --------------------------------------------------------
 // PASS: The end of the test,  if successful
 j_target_end_pass:
@@ -110,6 +111,7 @@ j_target_end_fail:
   la    x5,       j_target_end_fail
   jalr  x5
 
+
 // --------------------------------------------------------
 // Memory locations for specific usage.
 .section ".tdata.begin"
@@ -134,6 +136,10 @@ tohost: .dword 0
 .globl fromhost
 fromhost: .dword 0
 
+.align 6
+.global timer_interrupt_flag
+timer_interrupt_flag: .dword 0
+
 
 
 
diff --git a/model/main.sail b/model/main.sail
@@ -70,10 +70,14 @@
 val cfunc_int           = { c: "cfunc_int" }        : (string)  -> int
 
 function main () : unit -> unit = {
+
+  let reset_address : int = cfunc_int( "/reset/address") ;
+  print_int("/reset/address: 0x%x\n", reset_address);
+
   // initialize extensions
   ext_init ();
 
-  let reset_address : int = cfunc_int( "/reset/address") ;
+
 
   // PC = __GetSlice_int(64, elf_entry(), 0);
   PC = sail_zero_extend(0x1000, sizeof(xlen));