glossary.adoc

RISC-V acronyms and terms

This glossary includes definitions of terms specific to RISC-V as well as terms that are useful in understanding the architectures and technologies in use by RISC-V contributors and users.

ABI

Application Binary Interface. Abstractions and interfaces between applications and the AEE that control interactions. See 1.1. RISC-V Privileged Software Stack Terminology.

Accelerator

Either a non-programmable fixed-function unit or a core that can operate autonomously, but is specialized for certain tasks.

ACPI

Advanced Configuration and Power Interface.

ACS

Access Control Services. Follows PCI Express. A set of capabilities used to provide controls over routing of PCIe transactions.

Address field

Designated as a memory address or a processor register.

ASID

Address space identifier.

AEE

Application Execution Environment. The environment where the application runs, from bare metal to full operating system. See 1.1. RISC-V Privileged Software Stack Terminology.

AER

Advanced Error Reporting. A PCIe capability to support advanced error control and reporting.

AIA

RISC-V Advanced Interrupt Architecture. This specification builds upon the interrupt-handling functionality of the basic RISC-V ISA. See RISC-V Advanced Interrupt Architecture.

AIS 31

Information Security service for Europe and the global finance industry (for bank cards), written by BSI.

ALU

Arithmetic Logical Unit.

AMO

Atomic Memory Operation.

AP

Application Processor. Application processors can support commodity operating systems, hypervisors/VMMs and applications software workloads. The AP subsystem may contain several processing units, on-chip caches, and other controllers for interfacing with memory, accelerators, and other fixed-function logic. Multiple APs may be used within a logical system.

ASIC

Application-Specific Integrated Circuit.

ASID

Address Space IDentifier.

AT

Advanced Technology.

ATA

Advanced Technology Attachment.

ATM

Asynchronous Transfer Mode.

Atomic Layer Deposition

A layer-by-layer process that results in the deposition of thin films one atomic layer at a time in a highly controlled manner.

ATS

Address Translation Services. A PCIe protocol to support DevATC. Also called PCIe ATS.

Attestation

The process by which a relying party can assess the security posture of the confidential workload based on verifying a set of HW-rooted cryptographically-protected evidence.

ATX

Advanced Technology eXtended.

AUIPC

Add Upper Immediate to PC.

BAR

Base Address Register. Follows PCI Express. A register that is used by hardware to show the amount of system memory needed by a PCIe function and used by system software to set the base address of the allocated space.

BF

Refers to Brain Float or Brain Floating Point, used in BFLOAT16.

BFLOAT16

Brain floating point 16 bit—​a vector (V) extension representing a wide dynamic range of numeric values by using a floating radix point. See https://en.wikipedia.org/wiki/Bfloat16_floating-point_format.

BMC

Baseboard Management Controller.

BRS

Boot and Runtime Services.

BSI

German Federal Information Security service.

CAS

Compare-and-swap.

CBCFE

Cache Block Clean and Flush instruction Enable.

CBIE

Cache Block Invalidate instruction Enable.

CBO

Cache-block operation.

CBZE

Cache Block Zero instruction Enable.

CDE

Counter Delegation Enable.

CDI

Compound device identifier. A CDI is the value that represents the hardware, software and firmware combination measured by the TCB elements transitively. A CDI is the output of a DICE [R2] and is passed to the entity, which is measured by the previous TCB layer. The CDI is a secret that can be certified to use for attestation protocols.

CE

Corrected Error.

CMO

Cache-management operation.

CLIC

Core-Local Interrupt Controller. A low-latency, vectored, preemptive interrupt controller for RISC-V systems.

COFF

The Common Object File Format. Used on Unix SVR3 and by some embedded targets, although ELF is normally chosen.

Confidentail computing

A computing paradigm that protects data in use by performing computation in a hardware-based, attested Trusted Execution Environment (TEE).

CPL

Cost Per Load.

CPU Cache

Many CPUs include three kinds of caches to speed up data retrieval: an instruction cache for executable instruction fetch, a data cache for data store and fetch, and a translation lookaside buffer (TLB) for virtual-to-physical address translation for executable instructions and data.

CM

Configuration Manager.

CMOS

Complementary Metal Oxide Semiconductor.

Chemical Vapor Deposition

A chemical deposition process in which the wafer is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the final film.

Confidential application

A user-mode application or library instantiation in a TVM. The user-mode application may be supported via a trusted runtime. The user-mode library may be hosted by a surrogate process runtime.

Confidentail library

See Confidential application.

Confidential memory

Memory that is subject to access-control, confidentiality and integrity mechanisms per the threat model for use in the CoVE system. Confidential memory may also be used by nonTCB/ hosting software with appropriate TCB controls on the configuration, e.g., a separate key used for TCB and non-TCB elements.

Confidential VM

A VM instantiation of a confidential workload. Also called TEE VM (TVM).

Consistency Model

A computing system supports a specific consistency model if operations on memory follow specific rules. For example, high level languages such as C++ and Java, partially maintain the contract by translating memory operations into low-level operations while preserving memory semantics. To hold to the contract, compilers might reorder some memory instructions, and library calls such as pthread_mutex_lock(), that encapsulates the required synchronization.

Coprocessor

A unit that is attached to a RISC-V core and is sequenced by an instruction stream. It contains additional architectural state and instruction-set extensions, and possibly some limited autonomy relative to the primary RISC-V instruction stream.

CoVE

Confidential VM extension

CSR

Control and Status Register. CSRs are registers that store information. The standard RISC-V ISA sets aside a 12-bit encoding space (csr[11:0]) for up to 4,096 CSRs. By convention, the upper 4 bits of the CSR address (csr[11:8]) are used to encode the read and write accessibility of the CSRs, according to privilege level.

Custom

A register or data structure field designated for custom use. Software that is not aware of the custom use must ignore custom fields and preserve value held in these fields when writing values to other fields in the same register.

Custom extensions

Custom encodings are not used for standard extensions and are made available for vendor-specific non-standard extensions. See 1.3. RISC-V ISA Overview in Unprivileged.

CXL

Compute Express Link bus standard.

D

Debug mode. Provides access to more than M mode. This mode is used to debug implementations.

DC

Device Context. A hardware representation of state that identifies a device and the VM where the device is assigned.

DDI

Device Directory Index. A sub-field of the unique device identifier used as a index into a leaf or non-leaf DDT structure.

DDT

Device Directory Table. A radix-tree structure that is traversed by using the unique device identifier to locate the Device Context structure.

Device ID

An identification number that is up to 24-bits to identify the source of a DMA or interrupt request. For PCIe devices this is the routing identifier (RID).

DevATC

Device Address Translation Cache. An address translation cache at the device.

DIMM

Dual-In-line Memory Module. A packaging arrangement of memory devices on a socketable substrate.

DM

Debug Module.

DMA

Direct Memory Access.

DMTF

Distributed Management Task Force. Industry association for promoting systems management and interoperability.

DOM

Domain.

DRAM

Dynamic Random Access Memory.

DT

Device Tree.

Dynamic object

Another name for an ELF shared library.

EBBR

Embedded Base Boot Requirements.

ECAM

Enhanced Configuration Access Method. Follows PCI Express. A mechanism to allow addressing of Configuration Registers for PCIe functions. In addition to the PCI Express Base Specification, see the detailed requirements in this document.

ECC

Error Correcting Code.

eDRAM

Embedded Dynamic Random Access Memory (DRAM).

ECOFF

Extended Common Object File Format. Used on Alpha Digital Unix (formerly OSF/1), as well as Ultrix and Irix 4. A variant of COFF.

Execution Environment Interface.

EEW

Effective Element Width.

ELEN

Element length.

ELF

Executable and Linkable Format.

EP

Error/poisoned. Follows PCI Express. Also called Data Poisoning. EP is an error flag that accompanies data in some PCIe transactions to indicate the data is known to contain an error. Defined in PCI Express Base Specification 6.0 section 2.7.2. Unless otherwise blocked, the poison associated with the data must continue to propagate in the SoC internal interconnect.

ES

Entropy Source. An input or a measured characteristic that supplies random bits for an I/O device on a computer, usually used to supply bits that an attacker cannot know, as part of security.

Executable

A program, with instructions and symbols, and perhaps dynamic linking information. Normally produced by a linker.

Extension

An instructon set that adds customization and specialization to each base integer ISA. An extension is categorized as Standard, Custom, or Non-conforming.

FFH

Functional Fixed Hardware, as it pertains to ACPI.

FIOM

Fence of I/O implies Memory.

Flip-flop

Electronic circuitry with two stable states for storing binary data. Data that is stored in a flip-flop is changed by applying specific inputs. Both flip-flops and latches are building blocks that are used in digital computing.

FPCSR

Floating-point control and status register.

FLOPS

Floating Point Operations per Second.

FMA

Fused multiply-add.

FSM

Finite-State Machine. An abstract machine that can be in exactly one of a finite number of states at any time.

GAS

Generic Address Structure.

GE

Gate Equivalent.

GPA

Guest Physical Address. An address in the virtualized physical memory space of a virtual machine.

GSCID

Guest soft-context identifier. An identification number used by software to uniquely identify a collection of devices assigned to a virtual machine. An IOMMU might tag IOATC entries with the GSCID. Device contexts programmed with the same GSCID must also be programmed with identical second-stage page tables.

Guest

Software in a virtual machine.

HART

An abstraction of a hardware thread that captures the important aspects of a real hardware thread for the purposes of defining the RISC-V specifications. In particular, a hart is the agent that executes instructions within an execution context.

HBI

Hypervisor Binary Interface. An interface for hypervisors to connect the HEE, isolating the hypervisor from details ofthe hardware platform. See 1.1. RISC-V Privileged Software Stack Terminology.

hcounteren

Hypervisor Counter-enable register.

hedeleg

Hypervisor Trap Delegation register. Also hideleg.

HEE

Hypervisor execution environment. The environment that runs the hypervisor. See 1.1. RISC-V Privileged Software Stack Terminology.

hgatp

Hypervisor Guest Address Translation and Protection register.

Hierarchy ID

An identifier of a PCIe Hierarchy within which the Requester IDs are unique. Follows PCI Express. Also called Segment ID.

Horizontal trap

A trap that stays at the current priviledge mode when triggered.

Host Bridge

Part of a SoC that connects host CPUs and memory to PCIe root ports, RCiEP, and non-PCIe devices integrated in the SoC. The host bridge is placed between the device(s) and the platform interconnect to process DMA transactions. IO Devices may perform DMA transactions using IO Virtual Addresses (VA, GVA or GPA). The host bridge invokes the associated IOMMU to translate the IOVA to Supervisor Physical Addresses (SPA). Also called IO Bridge.

Host Software

All software elements including type-1 or type-2 HS-mode VMM and OS; U-mode user-space VMM tools; ordinary VMs hosted by the VMM that emulate devices. The hosting platform is typically a multi-tenant platform that hosts multiple mutually distrusting software owned by different tenants

HPC

High-performance Computing. HPC refers to the use of parallel processing techniques to solve complex computational problems. It enables faster data processing and simulation by leveraging multiple processors or servers.

HPET

High Precision Event Timer.

HPM

Hardware Performance Monitor.

HRET

Hypervisor Return from Trap.

HRNG

Hardware Random Number Generator. See TRNG.

hstatus

Hypervisor Status register.

htimedelta

Hypervisor Time Delta register.

htinst

Hypervisor Trap Instruction register.

htval

Hypervisor Trap Value register.

hvip

Hypervisor Interrupt register. Also hip and hie.

Hypervisor

A software entity that controls virtualization.

IALIGN

Refer to the instruction-address alignment constraint the implementation enforces. Measured in bits.

IBFD

I2c Bus Frequency Divider.

IC

Integrated Circuit.

ICF

Indentical Code Folding. ICF is an optimization to reduce output size by merging read-only sections by not only their names but by their contents. If two read-only sections happen to have the same metadata , actual contents and relocations, they are merged by ICF. It is known as an effective technique, and it usually reduces C++ program’s size by a few percent or more.

ICF

Identical COMDAT Folding.

ICU

Interrupt Consolidation Unit.

ID

Identifier.

ID Synchronization

The mechanisms by which code generated on a core (e.g., by a JIT compiler) is made visible to other cores.

IEEE 754

A technical standard for floating-point arithmetic established in 1985 by the Institute of Electrical and Electronics Engineers.

IIRC

The International Integrated Reporting Council, previously the International Integrated Reporting Committee), was formed in August 2010 and aims to create a globally accepted framework for a process that results in communications by an organization about value creation over time.

ILEN

Refers to the maximum instruction length supported by an implementation. ILEN is a multiple of IALIGN and measured in bits.

Image base

An image base is the fixed address that Windows executables or DLLs are linked against. Default image bases are 0x140000000 for executables and 0x18000000 for DLLs. For example, a executable is created, it is loaded at address 0x140000000 by the loader.

IMSIC

International Mobile Subscriber Identity Code.

IMSIC

Incoming Message-signaled Interrupt Controller.

Instruction encoding space

A number of instruction bits within which a base ISA or ISA extension is encoded. Divided into three separate spaces: Standard, Reserved, and Custom.

IOATC

IOMMU Address Translation Cache. A cache in IOMMU that caches data structures that are used for address translations.

IO Bridge

Part of a SoC that connects host CPUs and memory to PCIe root ports, RCiEP, and non-PCIe devices integrated in the SoC. The host bridge is placed between the device(s) and the platform interconnect to process DMA transactions. IO Devices may perform DMA transactions using IO Virtual Addresses (VA, GVA or GPA). The host bridge invokes the associated IOMMU to translate the IOVA to Supervisor Physical Addresses (SPA). Also called Host Bridge.

IOMMU

Input-Output Memory Management Unit. See RISC-V IOMMU Architecture Specification.

IOPMP

Input/Output Physical Memory Protection. See IOPMP Spec.

IOVA

I/O Virtual Address. Virtual address for DMA by devices.

IRC

Internet Relay Chat. A protocol is for use with text based conferencing; the simplest client being any socket program capable of connecting to the server. See Internet Relay Chat.

ISA

Instruction set architecture. Programmer visible state that represence the boundary between hardware and software. Includes operations on that state.

Instruction Set

A group of commands for a CPU in machine language that refers to all possible instructions for a CPU, or a subset of instructions to enhance its performance in specific situations.

JAL

Jump And Link instruction.

JALR

Jump And Link Register.

Latch

A circuit with two stable states that is used to store state information, known as a bi-stable multivibrator.

LCOFI

Local counter overflow interrupt.

LL/SC

Load Link/Store Conditional or Load Locked/Store conditional. See LR/SC.

LMA

Load Memory Address. The address of a section when the section is loaded. Compare with VMA.

LPI

Low Power Idle.

LR/SC

Load Reserve/Store Conditional, also LL/SC. A pair of instructions that is used in multithreading to achieve synchronization. Load-link returns the current value of a memory location, while a subsequent store-conditional to the same memory location stores a new value only if updates did not occur to that location since the load-link. Together, these implement a lock-free atomic read-modify-write operation.

LSA

Load–Store Architecture. A design that is architecturally neutral and that uses bit patterns in IEEE 754 floating-point to speed sign extension in ways that simplify the multiplexers in a CPU, by placing most-significant bits at a fixed location.

LUI

Load Upper Immediate.

M

Machine Mode. A boot mode that allows access to the most trusted code. This mode is required in all RISC-V implementations. Also called M-mode. See 1.2. Privilege Levels.

marchid

Machine Architecture ID register.

MBE

Machine Big Endian.

mcause

Machine Cause register.

mconfigptr

Machine Configuration Pointer register.

mcounteren

Machine Counter-enable register.

mvountinhibit

Machine Counter-inhibit register.

MCTP

Management Component Transport Protocol used for communication between components of a platform management system. Follows DMTF Standard.

medeleg

Machine Trap Delegation register. Also MIDELEG.

menvcfg

Machine Environment Configuration register.

mepc

Machine Exception Program register.

mip

Machine Interrupt register. Also MIE.

misa

Machine ID register.

MOPs

May-be-operations.

MCM

Multi-Chip Module.

mcyclecfg

Machine Counter Configuration register. Also minstretcfg.

mhartid

Hart ID register.

mimpid

Machine Implementation ID register.

mip

Machine Interrupt register. Also MIE.

MIPS

Microprocessor without Interlocked Pipelined Stages. A reduced instruction set computer (RISC) instruction set architecture developed by MIPS Computer Systems, now MIPS Technologies, based in the United States, that influenced later RISC architectures.

MMIO

Memory mapped I/O.

MMU

Memory Management Unit.

MMT

Memory Tracking Table.

MMWP

Machine-Mode When-no-PMP-match Policy.

MODE

A field within an instruction or instruction set that specifies the way the operand or the effective address is determined.

MPDA

Memory Proximity Domain Attributes.

MPRV

Modify PRiVilege.

MRET

Machine Return from Trap.

mscratch

Machine Scratch register.

MSCI

Memory Side Cache Information.

mseccfg

Machine Security Configuration register.

MSI

Message Signal Interrupt.

mstatus

Machine Status register. Also mstatush.

mtime

Machine Timer register. Also mtimecmp.

mtval

Machine Trap Value register.

mtvec

Machine Trap-Vector Base-Address register.

mvendorid

Machine vendor ID register.

MXLEN

Machine XLEN. A native integer width in bits.

MXL

Machine XLEN field. A field in misa to set MXLEN.

MXR

Make eXecutable Readable.

NaN

Not a number.

NAPOT

Naturally aligned power-of-2.

NIST

National Institute of STandards. This institute maintains a set of time and measurement, and cryptographic standards for the USA, including inch.

NMI

Non-maskable interrupts.

Non-ISA

Non-Standard Extension. Non-standard extensions are either custom extensions that use only custom encodings or non-conforming extensions that use any standard or reserved encoding. See 1.3. RISC-V ISA Overview in Unprivileged.

Non-prefetchable

Follows PCI Express. Defines the property of the memory space used by a device. For details, see the PCIe Base Specification. Broadly, non-prefetchable space covers any locations where reads have side effects or where writes cannot be merged.

NOP

No operation.

NTL

Non-Temporal Locality.

NUMA

Non-uniform Memory Access.

OBJ

Object.

Object file

A binary file including machine instructions, symbols, and relocation information. Normally produced by an assembler.

Object file format

The format of an object file. Typically object files and executables for a specific system are in the same format, although executables do not contain any relocation information.

OCF

Operation Code Feild. Specifies the operation to be performed.

Opcode

Operation code. Machine language instruction that specifies the operation to be performed.

OS

Operating System.

OSV

Operating System Vendor.

OS-level Sandboxing

A form of sandboxing implemented by the pointer masking proposal. There is no guarantee that sandboxed code cannot modify the pointer mask and therefore, the sandbox does not allow modifying pointer masks in user mode.

P2P

Peer-to-peer. Follows PCI Express. Transfer of data directly from one device to another. If the devices are under different PCIe Root Ports or are internal to the SoC this may involve data movement across the SoC internal interconnect.

Page fault

A type of exception raised by computer hardware when a running program accesses a memory page that is not currently mapped by the memory management unit (MMU) into the virtual address space of a process.

PASID

Process Address Space Identifier. Identifies the address space of a process. The PASID value is provided in the PASID TLP prefix of the request.

PBMT

Page-Based Memory Types.

PBMTE

Page Based Memory Types Extension.

PC

Process Control.

PCIe ATS

Peripheral Component Interconnect Express Address Translation Services. A PCIe protocol to support DevATC. Also called ATS.

PDI

Process-directory-index: a sub field of the unique process identifier used to index into a leaf or non-leaf PDT structure.

PDT

Process-directory-table: A radix tree data structure traversed using the unique Process identifier to locate the process context structure.

PE

The Portable Executable format. PE is the object file format used for Windows (specifically, Win32) object files. It is based closely on COFF, but has a few significant differences.

PEI

The Portable Executable Image format. PEI is the object file format used for Windows (specifically, Win32) executables. It is very similar to PE, but includes additional header information.

Photolithography

In microprocessor manufacturing, a process of using light to transfer a geometric pattern from a photomask (also called an optical mask) pattern parts to a photosensitive substrate on a thin film (substrate or wafer). The process can also make use of chemical photoresist on the substrate.

Platform

A System Platform is a set of features users can depend on working together that includes things such as ISA Profiles, software components, hardware system components, standardized hardware/software interfaces, and other features. Currently RISC-V has defined two Platform types: OS/A and M (naming TBD).

PLDM

Platform Level Data Model. Follows DMTF standard.

PLIC

Progressive Lossless Image Coding.

PLL

Phase-Locked Loop. A control system that generates anoutput signal whose phase is related to the phase of an input signal. PLLs are commonly used to perform clock synthesis.

PMA

Physical Memory Attributes.

PMP

Physical Memory Protection.

PPN

Physical Page Number.

PPO

Preserved Program Order. A strict sequential consistency that demands that operations be seen in the order in which they were issued.

PQC

Post-Quantum Cryptography. This standard is due to replace RSA and ECC in NIST cryptography [PQC] as well as military [NSA].

POSIX

Portable Operating System Interface.

PPO

Preserved program order. A subset of the program order that must be respected by the global memory order.

Prefetchable

Follows PCI Express. Defines the property of the memory space used by a device. For details, see the PCIe Base Specification. Broadly, non-prefetchable space covers any locations where reads have side effects or where writes cannot be merged.

PRI

Page Request Interface. A PCIe protocol that enables devices to requeprist OS memory manager services to make pages resident.

Privileged

Includes machine and supervisor mode. Privileged provides security isolation and reduces code defects because code does not have to check for illegal values. Privileged contains state, is used primarily to run applications and can be used to debug implementations. It defines CSR address space and content trap when taken increases privilege mode (say from U to S) trap when taken stays at the current privilege mode access more than even M mode. Its addresses reserved in ISA. address includes highest mode that access the CSR and if it is r/w/rw/none preserve bits already there when you change a field.

Process ID

An identification number that is up to 20-bits to identify a process. context. For PCIe devices this is the PASID.

Profile

(ISA Profile) a set of extensions (instructions, state and behaviors) that users can depend on working together. Extensions are either required, optional, unsupported, or incompatible. RISC-V has defined two Profile types: Application (RVAyy)--appropriate for Linux-class and other embedded designs with more sophisticated ISA needs—​and Micro-controller (RVMyy)--appropriate for cost-sensitive application-optimized embedded designs running bare-metal or simple RTOS environments.

PSCID

Process soft-context identifier: An identification number used by software to identify a unique address space. The IOMMU may tag IOATC entries with PSCID.

Psuedo instructions

In support of a core design goal for RISC-V ISAs—​high performance—​pseudo instructions often include special commands to the assembler. The use of pseudo instructions supports a policy of keeping the instruction set as small as possible, while supporting optimization and adding clarity to software programming. For example, the use of a pseudo instruction enables loading into memory with a 32-bit offset (called big) that is not directly available, because only 16-bit offsets are permitted.

PT

Page Table.

PTE

Page Table Entry. An entry in the data structure used by virtual memory in the operating system to store the mapping between both virtual addresses and physical addresses, that enables access data in memory.

PTEP

Parallel Telemetry Processor. A high- speed virtual processor architecture.

PTG.2

A physical random number generator class defined in AIS 31/CC.

PUD

Patch Update.

QEMU

Quick EMUlator. QEMU is a free and open-source emulator and virtualizer that can perform hardware virtualization.

QOS

Quality of Service. Defined as the minimal end-to-end performance that is guaranteed in advance by a service level agreement (SLA) to a workload.

RAS

Return-Address Stack.

RAS

Reliability, Availability, and Serviceability.

RCiEP

Root Complex Integrated Endpoint. Follows PCI Express. An internal peripheral that enumerates and behaves as specified in the PCIe standard.

RCEC

Root Complex Event Collector. A block for collecting errors and PME messages in a standard way from various internal peripherals. Follows PCI Express.

Relying party

An entity that depends on the validity of information about another entity, typically for purposes of authorization

RERI

Reliability, Availability, and Serviceability (RAS) error record register interface.

RID

Requester ID. Follows PCI Express. An identifier that uniquely identifies the requester within a PCIe Hierarchy. Needs to be extended with a Hierarchy ID to ensure it is unique across the platform.

RC

Root Comple. Follows PCI Express. Part of the SoC that includes the Host Bridge, Root Port, and RCiEP.

RD

Resource Data.

RDS

Resource Data Small.

RDL

Resource Data Large.

Register

A group of flip-flops with each flip-flop capable of storing one bit of information. The simplest register is one that consists of only flip-flops with no external gates.

Relocations

Information used by the linker to adjust section contents. Also called relocs.

Relocs

See Relocations.

Reserved

A register or data structure field that is reserved for future use. Reserved fields in data structures must be set to 0 by software. Software must ignore reserved fields in registers and preserve the value held in these fields when writing values to other fields in the same register.

RID

PCIe routing identifier. Also called PCIe RID.

RISC

Reduced Instruction Set Computer architecture. Information processing that uses any of a family of microprocessors that are designed to execute computing tasks with the simplest instructions in the shortest amount of time. RISC-based machines execute one instruction per clock cycle as opposed to CISC (Complex Instruction Set Computer) machines that can have special instructions as well as instructions that take more than one cycle to execute.

RNMI

Resumable Non-Maskable Interrupts.

RO

Read-only. Register bits are read-only and cannot be altered by software. Where explicitly defined, these bits are used to reflect changing hardware state, and as a result bit values can be observed to change at run time. If the optional feature that would Set the bits is not implemented, the bits must be hardwired to Zero

Rocket

Parameterized SoC generator written in Chisel, designed to helps tune the design under different performance, power, area constraints, and diverse technology nodes.

RoT

Root of trust (RoT) is the isolated hardware or software subsystem with an immutable ROM firmware and isolated compute and memory elements that form the Trusted Compute Base (TCB) of a TEE system. The RoT manages cryptographic keys and other security critical functions such as system lifecycle and debug authorization. The RoT provides trusted services to other software on the platform such as verified boot, key provisioning, and management, security lifecycle management, sealed storage, device management, crypto services, attestation etc. The RoT may be an integrated or discrete element

RP

Root Port. Follows PCI Express. A PCIe port in a Root Complex used to map a Hierarchy Domain using a PCI-PCI bridge.

RTC

Real-time clock.

RV

Reliability Verification. A category of physical verification that helps ensure the robustness of a design by considering the context of schematic and layout information to perform user-definable checks against various electrical and physical design rules that reduce susceptibility to premature or catastrophic electrical failures, usually over time.

RVA

Relative Virtual Address. Windows executables or DLLs are not position-independent; they are linked against a fixed address called an image base. RVAs are offsets from an image base.

RVWMO

RISC-V Weak Memory Ordering. Default memory ordering model that loads return value written by latest store to the address of the later of in-program and memory order (see specifications for list of axiomatic and operational rules).

RVC

RISC-V compression.

RW

Read-Write. Register bits are read-write and are permitted to be either set or cleared by software to the desired state. If the optional feature that is associated with the bits is not implemented, the bits are permitted to be hardwired to zero (0).

RW1C

Read-Write-1-to-clear status. Register bits that indicate status when read. A set bit indicates a status event that is Cleared by writing a 1b. Writing a 0b to RW1C bits has no effect. If the optional feature that sets the bit is not implemented, the bit must be read-only and hardwired to zero (0).

RW1S

Read-Write-1-to-set. Register bits that indicate status when read. The bit can be set by writing 1b. Writing a 0b to RW1S bits has no effect. If the optional feature that introduces the bit is not implemented, the bit must be read-only and hardwired to zero (0).

S

Supervisor mode. The boot mode that provides support for operating systems, such as Linux. Also called S-mode. See 1.2. Privilege Levels.

SAR

Sample At Reset.

satp

Supervisor Address Translation and Protection. XLEN-bit read/write register that controls supervisor-mode address translation and protection and holds the physical page number (PPN) of the root page table—​an address space identifer (ASID) that facilitates address-translation fences on a per-address-space basis, and the MODE field, which selects the current address-translation scheme.

SBBR

Server Base Boot Requirements.

SBE

Supervisor Big Endian.

SBI

System Binary Interface. SBI abstracts the interfaces that are required to run operating systems.

SBI

Supervisor Binary Interface. The interface that connects the operating system with the supervisor execution environment (SEE). See 1.1. RISC-V Privileged Software Stack Terminology.

SBSA

Server Base System Architecture.

Scala

A statically-typed, general-purpose programming language that supports both object-oriented programming and functional programming. Designed to be concise, Scala’s design aims to address criticisms of Java, and it provides language interoperability with Java so that libraries written in either language can be referenced directly in both Scala and Java code. Scala source code can be compiled to Java bytecode and run on a Java virtual machine (JVM).

scause

Supervisor Cause register.

scounteren

Supervisor Counter-enable register.

scountinhibit

Supervisor Counter Inhibit register.

SDE

Silent Data Error.

Section

Sections make up object files and executables and contain optional data and relocation information.

SEE

Supervisor Execution Environment. An environment where the operating systems run, which can be BIOS style interfaces, although it is not required. See 1.1. RISC-V Privileged Software Stack Terminology.

Segment ID

An identifier of a PCIe Hierarchy within which the Requester IDs are unique. Also called Hierarchy ID.

Segmentation fault

A failure condition caused by a memory access violation in hardware operating with memory protection. The fault process notifies the operating system (OS) that software has attempted to access a restricted area of memory.

senvcfg

Supervisor Environment Configuration register.

sepc

Supervisor Exception Program Counter register.

SEW

Selected Element Width.

SFENCE

Store fence. A store fence orders the processor execution, releative to all memory stores. See 10.2.1 Supervisor Memory-Management Fence Instruction in the Priv ISA manual.

SHA

Secure Hash Algorithms. A family of cryptographic hash functions published by the National Institute of Standards and Technology as a U.S. Federal Information Processing Standard that started with what is now known as SHA-0, a retronym used for the original (1993) 160-bit hash function published under the name "SHA".

Shared library

A library of functions that can be used by many executables without requiring a link into each executable. There are several different implementations of shared libraries, each having slightly different features.

sip

Supervisor Interrupt register. Also sie.

SLLBI

System Locality Latency and Bandwidth Information.

SMAP

Supervisor Memory Access Prevention.

SMBIOS

System Management BIOS.

SMEP

Supervisor Memory Execution Prevention.

smrnmi

Supervisor Resumable Non-Maskable Interrupts register.

SoC

System on Chip. Also referred as system-on-a-chip and system-on-chip.

SP 800 90B

Used in military and US government random security evaluations, written by NIST.

SP

Stack pointer.

SPA

Supervisor Physical Address. Physical address used to to access memory and memory-mapped resources.

SPDM

Security Protocols and Data Models. Follows DMTF Standard. A standard for authentication, attestation and key exchange to assist in providing infrastructure security enablement.

SRAM

Static Random Access Memory.

SRET

Supervisor Return from Trap.

SR-IOV

Single-Root I/O Virtualization. Follows PCI Express.

srmcfg: Supervisor Resource Management Configuration register.

sscratch

Supervisor Scratch register.

sstatus

Supervisor status register.

STCE

Supervisor TimeCmp Extension.

STD

Standard.

Standard Extension

A category of extensions that use only standard encodings, and do not conflict with each other in their uses of these encodings. See 1.3. RISC-V ISA Overview in Unprivileged.

stval

Supervisor Trap Value register.

stvec

Supervisor trap vector base register. This register contains trap vector configuration, base address, and mode.

SUM

Supervisor User Memory access

SVN

Security version number. SVN is the meta-data about the Trusted Compute Base (TCB) components that conveys the security posture of the TCB.

Symbol

A symbol is a name and an address. Each object file and executable has a list of symbols, often referred to as the symbol table. In addition, the symbol table contains additional information, such as the symbol type. Typically every global function and variable in a C program includes an associated symbol.

Target vector

A set of functions which implement support for a particular object file format.

TAP

TVM attestation payload. TAP is a block of memory in a VM that TSM uses to perform local attestation as part of promoting a VM to a TVM.

TCB

Trusted Compute Base. TCB is the hardware, software, and firmware elements that are trustedby a relying party to protect the confidentiality and integrity of the relying parties' workload data and execution against a defined adversary model. In a system with separate processing elements within a package on a socket, the TCB boundary is the package. In a multi-socket system the Hardware TCB extends across the socket-tosocket interface, and is managed as one system TCB. The software TCB may also extends across multiple sockets.

TEE

Trusted Execution Environment. TEE is a set of hardware and software mechanisms that allow attestable creation and isolated execution environment.

Tenant software

All software elements owned and deployed by a tenant in a multi-tenant hosting environment. These elements include VS-mode guest kernel and VU-mode guest user-space software.

TLB

Translation Lookaside Buffer. A memory buffer that enhances speed in retrieving a value by storing a memory address.

TLP

Transaction Layer Packet.

TRNG

True Random Number Generator. Also known as HRNG, or Hardware Random Number Generator. A device that generates random numbers from a physical process, rather than by means of an algorithm. Such devices are often based on microscopic phenomena that generate low-level, statistically random "noise" signals, like thermal noise, the photoelectric effect involving a beam splitter, and other quantum phenomena.

TSM

TEE security manager. TSM is a software module that enforces TEE security guarantees on a platform. It acts as the trusted intermediary between the VMM and the TVM.

TVM

Trap Virtual Memory.

TVM

TEE VM. See Confidential VM.

TW

Timeout Wait bit.

U

User mode. The boot mode that runs the application code. Part of Unprivileged. Also called U-mode. See 1.2. Privilege Levels.

UEC

Uncorrected Error Critical.

UED

Uncorrected Error Deferred.

UBE

User Big Endian.

UEIF

Unified Extensible Firmware Interface.

Unpriveleged

Unprivileged instructions are those that are generally usable in all privilege modes in all privileged architectures, though behavior can vary, depending on the specific privilege mode and privilege architecture.

UR

Error returns to an access made to a PCIe hierarchy.

URET

User Return from Trap.

User level sandboxing

A form of sandboxing that can be implemented by the pointer masking proposal where runtime and sandboxed code all run within the user mode and the sandboxed code was checked by the runtime to be unable to change pointer masks.

VA

Virtual Address.

vcsr

Vector Control and Status register.

vill

Virtual Type Illegal.

Virtical traps

A trap that increases privilege mode when triggered. For example, increasing from U to S.

vl

Vector Length register.

vlenb

Vector Byte Length.

VM

Virtual Machine. An efficient, isolated duplicate of a physical computer system.

VMA

Virtual Memory Allocation.

Virtual Memory Address. The address of a section when an executable is run. See also LMA.

VMM

Virtual Machine Monitor. Also referred to as hypervisor.

VS

Virtual Supervisor. Supervisor privilege in virtualization mode.

vsatp

Virtual Supervisor Address Translation and Protection register.

vscause

Virtual Supervisor Cause register.

vsepc

Virtual Supervisor Exception Program Counter register.

vsew

Vector Selected Element Width.

vstart

Vector Start Index register.

vstatus

Virtual Supervisor Status register. Also vsstatus.

vsip

Virtual Supervisor Interrupt register. Also vsie.

vsscratch

Virtual Supervisor Scratch register.

vstimecmp

Virtual Supervisor Timer register.

vstval

Virtual Supervisor Trap Value register.

vstvec

Virtual Supervisor Trap Vector Base Address register.

vtype

Vector Type register.

vxrm

Vector Fixed-Point Rounding Mode register.

WARL

Weighted Average Run Length.

WARL

Write Any Read Legal. Attribute of a register field that is defined for only a subset of bit encodings, but allows any value to be written while guaranteeing to return a legal value whenever read.

WFI

Wait for Interrupt instruction.

WLRL

Write Legal Read Legal. Check on writes, but no exception is required. The value that is read back for illegal written values is deterministic, but up to implementation.

WPRI

Write Preserve Read Ignore. Attribute of a register field that is reserved for future use.

WRS

Wait-on-Reservation-Set.

XCOFF

The eXtended Common Object File Format that is used on AIX operating systems. XCOFF is variant of COFF, with a completely different symbol table implementation.

XLEN

Register width. The word is a reference to mathematical X and an abbreviation of the word "length."

ZBT

Zero Bus Turnaround.