From 0a15a1ff630ec2fbc742b1734de82efeb41bfdd4 Mon Sep 17 00:00:00 2001 From: Thong Phan <67009134+thong-phn@users.noreply.github.com> Date: Tue, 27 Feb 2024 23:58:22 +0700 Subject: [PATCH] Change to Signed-off-by: Thong Phan <67009134+thong-phn@users.noreply.github.com> --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index c2c3502..19b7640 100644 --- a/README.md +++ b/README.md @@ -58,9 +58,9 @@ For those with little or no knowledge of digital logic design. After studying th | Resource | Author(s) | Description | Access | Date added | |---|---|---|---|---| -| **Digital Design and Computer Architecture RISC-V edition** (good starting point) | Sarah L. Harris, David M. Harris | Covers the foundational knowledge of digital logic design and segues smoothly into RISC-V Processor implementation.

Topics: Number systems and digital representation, Semiconductors and transistors, Logic gates and Digital design, C Programming, RISC-V architecture, RISC-V assembly, Memory systems, Embedded I/O systems | [Amazon book link]| 2024-01-10 | +| **Digital Design and Computer Architecture RISC-V edition** (good starting point) | Sarah L. Harris, David M. Harris | Covers the foundational knowledge of digital logic design and segues smoothly into RISC-V Processor implementation.

Topics: Number systems and digital representation, Semiconductors and transistors, Logic gates and Digital design, C Programming, RISC-V architecture, RISC-V assembly, Memory systems, Embedded I/O systems | [Amazon book link]| 2024-01-10 | | **Nand2Tetris** (optional) | Noam Nisan, Shimon Schocken | A free hands-on tutorial on building a general-purpose computer from logic gates using a hardware simulator.

Topics: Logic gates|[webpage] | 2024-01-10 | -|**learn-FPGA episode I: from blinky to RISC-V**|[BrunoLevy](https://github.com/BrunoLevy)|A beginner's introduction to digital design of a RISC-V softcore on FPGAs. Episode I gently starts from a very basic blinker in Verilog and morphs it step by step into a basic yet fully functional RISC-V SoC. It is also explained how to write programs in C and assembly for the SoC.

Topics: Digital desgin, FPGA, C Programming, RISC-V assembly
Requirement: Basic knowledge of Verilog|[GitHub]| 2024-01-10 | +|**learn-FPGA episode I: from blinky to RISC-V**|[BrunoLevy](https://github.com/BrunoLevy)|A beginner's introduction to the digital design of a RISC-V softcore on FPGAs. Episode I gently starts from a very basic blinker in Verilog and morphs it step by step into a basic yet fully functional RISC-V SoC. It also explains how to write programs in C and assembly for the SoC.

Topics: Digital design, FPGA, C Programming, RISC-V assembly
Requirement: Basic knowledge of Verilog|[GitHub]| 2024-01-10 | |**Hands-on RISC-V Processor Design**|[Rahul Behl](https://github.com/raulbehl)|This practical tutorial offers a deep dive into the world of computer architecture and processor design, with a specific focus on the RISC-V Instruction Set Architecture (ISA).

Topics: Computer architecture, Processor design, RISC-V Instruction Set Architecture (ISA), SystemVerilog, RISC-V assembly
Requirements: SystemVerilog but not necessary|[webpage] | 2024-01-10 | |**LinuxFoundationX: Building a RISC-V CPU Core** | [Steve Hoover](https://www.edx.org/bio/steve-hoover) | This free EdX course by Steve Hoover (founder of Redwood EDA) is a great way for a beginner to get started with digital logic design and basic RISC-V microarchitecture design with the help of modern, freely available open source tools.

Topics: Digital logic design, RISC-V Instruction Set Architecture (ISA), CPU microarchitecture, Transaction-Level Verilog, Makerchip online IDE| [edX Course Link] | 2024-01-10 |