Request: Configurable priority between misaligned accesses and general access traps

[billmcspadden-riscv]

This issue is a parallel issue to: riscv/sail-riscv#192

Following is the text of that issue:

Reference: Priv Spec., Table 3.7 "Synchronous exception priority in decreasing priority order."

The priority of a "load/store/AMO address misaligned" exception can be made optionally
higher or lower than other memory access exceptions. The model needs to be made
configurable to handle this option.

This option will need to be added to the RISCV-Config structure.

The solution to this problem should use the "new" YAML configuration methods that have been introduced to the
model (see PR riscv/sail-riscv#175).