From fde93582798b8ab7681e8178f6ef39a3e3e249e7 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Mon, 4 Nov 2024 15:00:04 +0500 Subject: [PATCH 1/4] add a tip for the translator use --- riscv-isac/docs/source/cgf.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/riscv-isac/docs/source/cgf.rst b/riscv-isac/docs/source/cgf.rst index 07d745143..ef6c8a5c8 100644 --- a/riscv-isac/docs/source/cgf.rst +++ b/riscv-isac/docs/source/cgf.rst @@ -647,6 +647,8 @@ syntax for the Translator: Operations can be performed on the *number_placeholder_index* to get the required value. Consider another example: + .. tip:: Use the modulus operator represented by % in python if you want to traverse over the length of the list !!! + .. code-block:: python csr_comb: From e7a1bc63a62c61255d5cbba03a3eeb7df3348570 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Mon, 4 Nov 2024 17:04:27 +0500 Subject: [PATCH 2/4] ignore the venv folder if created here for RISC_V ISAC --- .gitignore | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.gitignore b/.gitignore index 3203a4378..8857fcd25 100644 --- a/.gitignore +++ b/.gitignore @@ -9,3 +9,6 @@ *.DS_Store riscv-target/ + +#ignore venv +riscv-isac/riscv-env \ No newline at end of file From 899529230ee3173d1cfa688d63b6e2d1f9253583 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Tue, 5 Nov 2024 15:33:48 +0500 Subject: [PATCH 3/4] VM functions update, translator minor bugs removed for list expansion and load instructions added in the exception list --- riscv-isac/riscv_isac/InstructionObject.py | 33 +++++-- riscv-isac/riscv_isac/coverage.py | 81 ++++++++-------- riscv-isac/riscv_isac/plugins/c_sail.py | 36 +++++-- .../riscv_isac/plugins/translator_cgf.py | 94 ++++++++++++++----- 4 files changed, 164 insertions(+), 80 deletions(-) diff --git a/riscv-isac/riscv_isac/InstructionObject.py b/riscv-isac/riscv_isac/InstructionObject.py index 08a10601e..06f26c8f0 100644 --- a/riscv-isac/riscv_isac/InstructionObject.py +++ b/riscv-isac/riscv_isac/InstructionObject.py @@ -25,7 +25,7 @@ 'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi','bclr','bext','binv',\ 'bset','zext.h','sext.h','sext.b','zext.b','zext.w','minu','maxu','orc.b','add.uw','sh1add.uw',\ 'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8',\ - 'bclri','bexti','binvi','bseti','xperm4','xperm8','zip','unzip','gorci','fcvt.d.wu','fcvt.s.wu','fcvt.d.lu','fcvt.s.lu','c.flwsp',\ + 'bclri','bexti','binvi','bseti','fcvt.d.wu','fcvt.s.wu','fcvt.d.lu','fcvt.s.lu','c.flwsp',\ 'c.not', 'c.sext.b','c.sext.h','c.zext.b','c.zext.h','c.zext.w','sc.w','lr.w','sc.d','lr.d'] unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\ 'mulhsu','divu','remu','divuw','remuw','aes64ds','aes64dsm','aes64es',\ @@ -186,6 +186,18 @@ def evaluate_instr_vars(self, xlen, flen, arch_state, csr_regfile, instr_vars): imm_val = instr_vars.get('imm_val', None) + #update the variable for the length of the load or store: + if self.instr_name in ['ld','lw','lb','lh','sd','sw','sb','sh']: + if self.instr_name in ['ld','sd']: + instr_vars['access_len'] = 8 + if self.instr_name in ['lw','sw']: + instr_vars['access_len'] = 4 + if self.instr_name in ['lh','sh']: + instr_vars['access_len'] = 2 + if self.instr_name in ['lb','sb']: + instr_vars['access_len'] = 1 + else: + instr_vars['access_len'] = None #Update the values for the trap registers self.trap_registers_update(instr_vars,self.trap_dict) @@ -487,21 +499,24 @@ def trap_registers_update(self, instr_vars, trap_dict): instr_vars['mtval'] = trap_dict['tval'] #only update on the initialization if "scause" not in instr_vars: - instr_vars['scause'] = '0' - instr_vars['stval'] = '0' + instr_vars['scause'] = None + instr_vars['stval'] = None elif trap_dict["mode_change"].split()[2] == "S": instr_vars['scause'] = trap_dict['exc_num'] instr_vars['stval'] = trap_dict['tval'] #only update on the initialization if "mcause" not in instr_vars: - instr_vars['mcause'] = '0' - instr_vars['mtval'] = '0' + instr_vars['mcause'] = None + instr_vars['mtval'] = None + else: - instr_vars['mcause'] = '0' - instr_vars['mtval'] = '0' - instr_vars['scause'] = '0' - instr_vars['stval'] = '0' + #initialize them to None for the first time in the instr_vars + #reset them to None in case the mode change is ret + instr_vars['mcause'] = None + instr_vars['mtval'] = None + instr_vars['scause'] = None + instr_vars['stval'] = None return None diff --git a/riscv-isac/riscv_isac/coverage.py b/riscv-isac/riscv_isac/coverage.py index 9d01af5b0..d85c3ee52 100644 --- a/riscv-isac/riscv_isac/coverage.py +++ b/riscv-isac/riscv_isac/coverage.py @@ -159,7 +159,10 @@ 940: 'pmpcfg12', 941: 'pmpcfg13', 942: 'pmpcfg14', - 943: 'pmpcfg15' + 943: 'pmpcfg15', + 266: 'senvcfg', + 778: 'menvcfg', + 1863: 'mseccfg' } class cross(): @@ -571,7 +574,10 @@ def __init__ (self, xlen): "vxsat": int('009',16), "fflags":int('1',16), "frm":int('2',16), - "fcsr":int('3',16) + "fcsr":int('3',16), + "menvcfg":int('30A', 16), + "senvcfg":int('10A', 16), + "mseccfg":int('747', 16) } for i in range(16): self.csr_regs["pmpaddr"+str(i)] = int('3B0',16)+i @@ -951,7 +957,10 @@ def compute_per_line(queue, event, cgf_queue, stats_queue, cgf, xlen, flen, addr #csr regfile track for the previous instruction(old_csr_regfile) old_csr_regfile = {} for i in csr_regfile.csr_regs: - old_csr_regfile[i] = int(csr_regfile[i],16) + if isinstance(csr_regfile[i], str): + old_csr_regfile[i] = int(csr_regfile[i],16) + else: + old_csr_regfile[i] = csr_regfile[i] def old_fn_csr_comb_covpt(csr_reg): return old_csr_regfile[csr_reg] @@ -961,11 +970,11 @@ def old_fn_csr_comb_covpt(csr_reg): instr.evaluate_instr_vars(xlen, flen, arch_state, csr_regfile, instr_vars) #update the state of trap registers in csr_reg file using instr_vars - if instr_vars["mode_change"] is not None: #change the state only on the instruction - csr_regfile["mcause"] = instr_vars["mcause"] - csr_regfile["scause"] = instr_vars["scause"] - csr_regfile["mtval"] = instr_vars["mtval"] - csr_regfile["stval"] = instr_vars["stval"] + # if instr_vars["mode_change"] is not None: #change the state only on the instruction + csr_regfile["mcause"] = instr_vars["mcause"] + csr_regfile["scause"] = instr_vars["scause"] + csr_regfile["mtval"] = instr_vars["mtval"] + csr_regfile["stval"] = instr_vars["stval"] if 'rs1' in instr_vars: rs1 = instr_vars['rs1'] @@ -980,8 +989,10 @@ def old_fn_csr_comb_covpt(csr_reg): is_rd_valid = False for i in csr_regfile.csr_regs: - instr_vars[i] = int(csr_regfile[i],16) - + if isinstance(csr_regfile[i], str): + instr_vars[i] = int(csr_regfile[i],16) + else: + instr_vars[i] = csr_regfile[i] instr.iptw_update(instr_vars, iptw_dict) instr.ptw_update(instr_vars) @@ -1026,32 +1037,30 @@ def get_pte(pa, pte_addr, pgtb_addr): else: return None - def get_pte_prop(prop_name,pa, pte_addr, pgtb_addr): - pte_per = get_pte(pa, pte_addr, pgtb_addr) - if pte_per is not None: - pte_per = get_pte(pa, pte_addr, pgtb_addr) & 0x3FF - prop_name_lower = prop_name.lower() - if prop_name_lower == 'v' and (pte_per & 0x01 != 0): - return 1 - elif prop_name_lower == 'r' and (pte_per & 0x02 != 0): - return 1 - elif prop_name_lower == 'w' and (pte_per & 0x04 != 0): - return 1 - elif prop_name_lower == 'x' and (pte_per & 0x08 != 0): - return 1 - elif prop_name_lower == 'u' and (pte_per & 0x10 != 0): - return 1 - elif prop_name_lower == 'g' and (pte_per & 0x20 != 0): - return 1 - elif prop_name_lower == 'a' and (pte_per & 0x40 != 0): - return 1 - elif prop_name_lower == 'd' and (pte_per & 0x80 != 0): - return 1 - else: - return 0 - + def get_pte_prop(prop_name, pte_addr): + ''' + Function to return whether a specific Permission is given to the PTE or not + :param prop_name: an input property ., example: 'U' for U bit or 'RWX' for a combination of bits + :param pte_addr: PTE address for which we want to get the information + + :type prop_name: str + :type pte_addr: hex/int + + :return: 1 or 0 depending whether the specific (or combination of) permission/s is set or not respectively. + ''' + bitmask_dict = {'v': 0x01, 'r': 0x02, 'w': 0x04, 'x': 0x08, 'u': 0x10, 'g': 0x20, 'a': 0x40, 'd': 0x80} + + if pte_addr is not None: + # Get the permissions bit out of the pte_addr + pte_per = pte_addr & 0x3FF + + # Check each character in prop_name + for char in prop_name.lower(): + if char in bitmask_dict and (pte_per & bitmask_dict[char] == 0): + return 0 + return 1 else: - return None + return 0 globals()['get_addr'] = check_label_address globals()['get_mem_val'] = get_mem_val @@ -1059,7 +1068,6 @@ def get_pte_prop(prop_name,pa, pte_addr, pgtb_addr): globals()['get_pte_prop'] = get_pte_prop if enable : - print(instr_vars) ucovpt = [] covpt = [] csr_covpt = [] @@ -1136,7 +1144,6 @@ def get_pte_prop(prop_name,pa, pte_addr, pgtb_addr): value['rs3'][rs3] += 1 if 'op_comb' in value and len(value['op_comb']) != 0 : - for coverpoints in value['op_comb']: if eval(coverpoints, globals(), instr_vars): if cgf[cov_labels]['op_comb'][coverpoints] == 0: diff --git a/riscv-isac/riscv_isac/plugins/c_sail.py b/riscv-isac/riscv_isac/plugins/c_sail.py index a45f83842..981efc2ab 100644 --- a/riscv-isac/riscv_isac/plugins/c_sail.py +++ b/riscv-isac/riscv_isac/plugins/c_sail.py @@ -20,6 +20,7 @@ def setup(self, trace, arch): instr_pattern_c_sail_csr_reg_val = re.compile('(?PCSR|clint::tick)\s(?P[a-z0-9]+)\s<-\s(?P[0-9xABCDEF]+)(?:\s\(input:\s(?P[0-9xABCDEF]+)\))?') instr_pattern_c_sail_mem_val = re.compile('mem\[(?P[0-9xABCDEF]+)\]\s<-\s(?P[0-9xABCDEF]+)') instr_pattern_c_sail_trap = re.compile(r'trapping\sfrom\s(?P\w+\sto\s\w+)\sto\shandle\s(?P\w+.*)\shandling\sexc#(?P0x[0-9a-fA-F]+)\sat\spriv\s\w\swith\stval\s(?P0x[0-9a-fA-F]+)') + instr_pattern_c_sail_ret = re.compile(r'ret-ing\sfrom\s(?P\w+\sto\s\w+)') def extractInstruction(self, line): instr_pattern = self.instr_pattern_c_sail re_search = instr_pattern.search(line) @@ -60,6 +61,13 @@ def extractVirtualMemory(self, line): mem_r_pattern = re.compile(r'mem\[R,([0-9xABCDEF]+)\] -> 0x([0-9xABCDEF]+)') mem_x_pattern = re.compile(r'mem\[X,([0-9xABCDEF]+)\] -> 0x([0-9xABCDEF]+)') mem_depa_pattern = re.compile(r'mem\[([0-9xABCDEF]+)\]') + instr_trap_pattern = self.instr_pattern_c_sail_trap.search(line) + + #in case of a trap + if instr_trap_pattern: + trap = 1 + else: + trap = 0 match_search_mnemonic = self.instr_pattern_c_sail.search(line) depa, ieva, ieva_align, depa_align, iepa, iepa_align = None, None, None, None, None, None @@ -78,14 +86,19 @@ def extractVirtualMemory(self, line): iptw_list=(mem_r_pattern.findall(line_upper_part)) dptw_list=(mem_r_pattern.findall(line_lower_part)) + #Update the data physical address only when there is no trap else it will not be present in the log. if dptw_list is not None: - if "lw" in match_search_mnemonic.group('mnemonic') and dptw_list: - depa_list=dptw_list.pop() - depa=int(depa_list[0],16) - else: - depa_list=mem_depa_pattern.findall(line_lower_part) - if len(depa_list) != 0: + if trap == 0: + #Since, the load has the same pattern as the page table walk, skip the last one as it is a false positive. + loads_exception_list = {"lw", "ld", "lh", "lb", "lr.w", "lr.d", "lbu", "lhu", "lwu", "c.lw", "c.ld", "c.lwsp", "c.ldsp", "flw", "fld"} + if match_search_mnemonic.group('mnemonic').split()[0] in loads_exception_list and dptw_list: + depa_list=dptw_list.pop() depa=int(depa_list[0],16) + #Stores and other page table walks are normal + else: + depa_list=mem_depa_pattern.findall(line_lower_part) + if len(depa_list) != 0: + depa=int(depa_list[0],16) ieva_align = 1 if ieva is not None and ieva & 0b11 == 0 else 0 iepa_align = 1 if iepa is not None and iepa & 0b11 == 0 else 0 @@ -114,6 +127,8 @@ def extracttrapvals(self, line): instr_trap_pattern = self.instr_pattern_c_sail_trap.search(line) trap_dict = {"mode_change": None, "call_type": None, "exc_num": None, "tval": None} + #ret will tell us to delete the previous state of the cause registers + instr_ret_pattern = self.instr_pattern_c_sail_ret.search(line) if instr_trap_pattern: trap_dict["mode_change"] = instr_trap_pattern.group("mode_change") trap_dict["call_type"] = instr_trap_pattern.group("call_type") @@ -121,8 +136,13 @@ def extracttrapvals(self, line): trap_dict["tval"] = instr_trap_pattern.group("tval") self.old_trap_dict = trap_dict - #maintain the value if None - if instr_trap_pattern is None: + elif instr_ret_pattern: + #if ret_signal is 1 then clear the values of the mode_change, call_type, exc_num, tval + trap_dict = {"mode_change": None, "call_type": None, "exc_num": None, "tval": None} + self.old_trap_dict = trap_dict + + #maintain the values if None unit the new trap appears + if instr_trap_pattern is None or instr_ret_pattern is None: trap_dict = self.old_trap_dict return trap_dict diff --git a/riscv-isac/riscv_isac/plugins/translator_cgf.py b/riscv-isac/riscv_isac/plugins/translator_cgf.py index 1f10aa04d..b70e91a09 100644 --- a/riscv-isac/riscv_isac/plugins/translator_cgf.py +++ b/riscv-isac/riscv_isac/plugins/translator_cgf.py @@ -27,10 +27,12 @@ def __init__(self): self.macro_brace_resolver = re.compile(r'(\%\d+)') # self.repeat_brace_index = re.compile(r'(\*\d+)') self.list_brace_finder = re.compile(r'\{([^}]*)\}\{(\[[^\]]+\])\}') + self.list_with_index_finder = re.compile(r'\{(?:\s*\$\{[\w\d]+\}\s*,?)*\}\{\[\$[\w\d]+\]\}') self.list_index_brace_finder = re.compile(r'(\{\[.*?\]\})') self.list_index_number_finder = re.compile(r'(\<\<[^>]*\>\>\{\[[^\]]+\]\})') + self.temp_replacement_finder = re.compile(r'<>') self.placeholder_pattern = re.compile(r'<>|<>|<>|<>') - self.resolve_back_order = re.compile(r'<>|<>|<>') + self.resolve_back_order = re.compile(r'<>|<>|<>|<>') def translate_using_path(self, input_path, output_path): """Translate YAML data from the input file and dump it into the output file. @@ -173,11 +175,26 @@ def replace_macros(self, instr): Returns: str: The instruction string with macros replaced. """ + #Don't resolve the macros inside the list as they are difficult to replace back + list_with_index = self.list_with_index_finder.findall(instr) + if len(list_with_index) != 0: + for index, values in enumerate(list_with_index): + instr = instr.replace(values, f'<>') + + #Find the other macros inside the instr macros = self.macro_def_finder.findall(instr) macro_dict = {macro: f'<>' for index, macro in enumerate(macros)} instr, replacements = self.replace_using_dict(instr, macro_dict) self.replacement_dict.update(replacements) + + #replace the Temp replacement back with the actual list + temp_replacement_finds = self.temp_replacement_finder.findall(instr) + + if len(temp_replacement_finds) != 0: + for index, values in enumerate(list_with_index): + instr = instr.replace(f'<>', values) + return instr def replace_multibraces(self, instr): @@ -264,8 +281,19 @@ def replace_list_braces(self, instr): Returns: str: The instruction string with list braces and their contents replaced. """ - list_braces = self.list_brace_finder.findall(instr) + #This pattern includes all the normal pattern inside the list + list_braces_pattern_anything = self.list_brace_finder.findall(instr) + #This pattern checks the all macros pattern inside the list + list_macros_braces_pattern = re.compile(r'\{((?:\s*\$\{[\w\d]+\}\s*,?)*)\}\{(\[\$[\w\d]+\])\}') + list_braces_pattern_macros = list_macros_braces_pattern.findall(instr) + + if len(list_braces_pattern_anything) != 0: + list_braces = list_braces_pattern_anything + else: + list_braces = list_braces_pattern_macros + replacements = {} + for index, brace in enumerate(list_braces): brace_content, brace_index = brace[0], brace[1] @@ -278,7 +306,7 @@ def replace_list_braces(self, instr): # Update the replacement dictionary self.replacement_dict.update(replacements) - + # print("instr after list", instr) return instr @@ -419,12 +447,7 @@ def resolve_lists(self, instr_lst, replacement_dict, place_holder_pattern): for index, (key, val) in enumerate(replacement_dict.items()): if "LIST" in key: - try: - req_element_list.append(val[resolved_list_index[index]]) - except IndexError as e: - logging.error(f"Error: list index out of range. The index {resolved_list_index[index - 1]} is out of the size of the list {val} whose length is {len(val)}") - break - + req_element_list.append(val[resolved_list_index[0]]) #Replace the list index with No space for index, val in enumerate(req_element_list): if list_index_matches[index] in instr: @@ -433,8 +456,8 @@ def resolve_lists(self, instr_lst, replacement_dict, place_holder_pattern): temp_element_dict = {} for index, (key, val) in enumerate(replacement_dict.items()): if "LIST" in key: - temp_element_dict[key] = req_element_list[index] - instr = instr.replace(key, req_element_list[index]) + temp_element_dict[key] = req_element_list[0] + instr = instr.replace(key, req_element_list[0]) for (key, val) in replacement_dict.items(): if "NUMBER" in key: @@ -463,9 +486,15 @@ def loop_controller(self, instr, replacement_dict, place_holder_pattern): final_cov_list.append(instr) else: for curr_resolve in placeholders: + #create a req_fn_list which will help in resolving the Number placeholder req_fn_list = [placeholders[current_cov_track]] + #always include MULTI_INTER as it is not explicitly present in the instr + for value in place_holder_pattern: + if "MULTI_INTER" in value: + req_fn_list.append(value) temp_gen_cov_list = [] + #This will generate required number of coverpoints using the current instructions for instr in gen_cov_list: curr_generated_cov_list = self.calculate_coverpoints(instr, replacement_dict, place_holder_pattern, req_fn_list) temp_gen_cov_list.extend(curr_generated_cov_list) @@ -537,7 +566,7 @@ def generate_current_cov(self, instr, track_dict, replacement_dict, place_holder Returns: str: The generated coverpoint. """ - + number_pattern = re.compile(r'\d+') for key, val in replacement_dict.items(): @@ -570,18 +599,27 @@ def generate_current_cov(self, instr, track_dict, replacement_dict, place_holder list_index_pattern = self.list_index_number_finder.findall(instr) result = int(number_pattern.findall(val)[0]) -1 var = place_holder_pattern[result] - curr_index = track_dict[var][2] - - for index, val in enumerate(list_index_pattern): - internal_list__index_pattern = internal_list_index_number_finder.findall(val) - if key in internal_list__index_pattern[0][1]: - req_val = f"<<{internal_list__index_pattern[0][0]}>>{{[{curr_index}{internal_list__index_pattern[0][1].replace(key, '')}]}}" - instr = instr.replace(list_index_pattern[index], req_val) - if "MULTI_INTER" in var and "MULTI" in req_fn_list[0]: - instr = instr.replace(key, str(replacement_dict[var][curr_index])) - if req_fn_list[0] in var: - instr = instr.replace(key, str(replacement_dict[var][curr_index])) + #only replace the NUMBER Placeholder when we have the required Structure + if var in req_fn_list: + curr_index = track_dict[var][2] + multi_index_repeat_for_list = replacement_dict[var].count(replacement_dict[var][curr_index]) + multi_index_for_list = math.floor((replacement_dict[var].index(replacement_dict[var][curr_index]))/multi_index_repeat_for_list) + #replace the number placeholder in the List with the required index + for index, val in enumerate(list_index_pattern): + internal_list__index_pattern = internal_list_index_number_finder.findall(val) + if key in internal_list__index_pattern[0][1]: + if "MULTI" in var: + temp_index = multi_index_for_list + else: + temp_index = curr_index + req_val = f'<<{internal_list__index_pattern[0][0]}>>{{[{temp_index}{internal_list__index_pattern[0][1].replace(key, "")}]}}' + instr = instr.replace(list_index_pattern[index], req_val) + + if "MULTI_INTER" in var and "MULTI" in req_fn_list[0]: + instr = instr.replace(key, str(replacement_dict[var][curr_index])) + if req_fn_list[0] in var: + instr = instr.replace(key, str(replacement_dict[var][curr_index])) # Resolve back the macros for key, val in replacement_dict.items(): @@ -728,7 +766,11 @@ def list_index_resolver(self, list_indices): result_list = [] for list_index in list_indices: value_inside_index = values_finder.findall(list_index) - resolved_val = math.floor(eval(value_inside_index[0])) + macro_def_find = self.macro_def_finder.findall(value_inside_index[0]) + if macro_def_find: + resolved_val = value_inside_index[0] + else: + resolved_val = math.floor(eval(value_inside_index[0])) result_list.append(resolved_val) return result_list @@ -743,7 +785,7 @@ def Translate_cgf(input_cgf): # if __name__ == "__main__": -# defs_path = '/home/hammad/wrapper_cgf/Wrapper-cgf/config.defs' -# cgf_path = '/home/hammad/wrapper_cgf/Wrapper-cgf/output.cgf' +# defs_path = '/home/input_cgf_file.cgf' +# cgf_path = '/home/output.cgf' # trans = Translator() # trans.translate_using_path(defs_path, cgf_path) \ No newline at end of file From 22ffaddf527759635f427482ac3e231ddbc59570 Mon Sep 17 00:00:00 2001 From: MuhammadHammad001 Date: Tue, 5 Nov 2024 18:25:34 +0500 Subject: [PATCH 4/4] Revert the change for unsigned rs1 to add the previous instructions --- riscv-isac/riscv_isac/InstructionObject.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-isac/riscv_isac/InstructionObject.py b/riscv-isac/riscv_isac/InstructionObject.py index 06f26c8f0..ad4971dbb 100644 --- a/riscv-isac/riscv_isac/InstructionObject.py +++ b/riscv-isac/riscv_isac/InstructionObject.py @@ -25,7 +25,7 @@ 'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi','bclr','bext','binv',\ 'bset','zext.h','sext.h','sext.b','zext.b','zext.w','minu','maxu','orc.b','add.uw','sh1add.uw',\ 'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8',\ - 'bclri','bexti','binvi','bseti','fcvt.d.wu','fcvt.s.wu','fcvt.d.lu','fcvt.s.lu','c.flwsp',\ + 'bclri','bexti','binvi','bseti','xperm4','xperm8','zip','unzip','gorci','fcvt.d.wu','fcvt.s.wu','fcvt.d.lu','fcvt.s.lu','c.flwsp',\ 'c.not', 'c.sext.b','c.sext.h','c.zext.b','c.zext.h','c.zext.w','sc.w','lr.w','sc.d','lr.d'] unsgn_rs2 = ['bgeu', 'bltu', 'sltiu', 'sltu', 'sll', 'srl', 'sra','mulhu',\ 'mulhsu','divu','remu','divuw','remuw','aes64ds','aes64dsm','aes64es',\