From 8893700c965f265758768dca307a078059e7265d Mon Sep 17 00:00:00 2001 From: umershahidengr Date: Mon, 3 Jun 2024 21:43:53 +0500 Subject: [PATCH 1/6] Updated trap handler --- .../Makefile.Reference-sail_c_simulator | 61 + riscof_work/database.yaml | 347 ++ riscof_work/spike_simple_isa_checked.yaml | 4121 +++++++++++++++++ .../spike_simple_platform_checked.yaml | 18 + .../src/ebreak.S/dut/DUT-Spike.signature | 8 + riscof_work/src/ebreak.S/dut/my.elf | Bin 0 -> 20976 bytes riscof_work/src/ebreak.S/ref/ebreak.log | 28 + riscof_work/src/ebreak.S/ref/ref.disass | 959 ++++ riscof_work/src/ebreak.S/ref/ref.elf | Bin 0 -> 20988 bytes .../src/ecall.S/dut/DUT-Spike.signature | 8 + riscof_work/src/ecall.S/dut/my.elf | Bin 0 -> 20976 bytes .../misalign-beq-01.S/dut/DUT-Spike.signature | 69 + riscof_work/src/misalign-beq-01.S/dut/my.elf | Bin 0 -> 21512 bytes .../misalign-bge-01.S/dut/DUT-Spike.signature | 69 + riscof_work/src/misalign-bge-01.S/dut/my.elf | Bin 0 -> 21512 bytes .../dut/DUT-Spike.signature | 69 + riscof_work/src/misalign-bgeu-01.S/dut/my.elf | Bin 0 -> 25608 bytes .../misalign-blt-01.S/dut/DUT-Spike.signature | 69 + riscof_work/src/misalign-blt-01.S/dut/my.elf | Bin 0 -> 21512 bytes .../dut/DUT-Spike.signature | 69 + riscof_work/src/misalign-bltu-01.S/dut/my.elf | Bin 0 -> 21512 bytes .../misalign-bne-01.S/dut/DUT-Spike.signature | 69 + riscof_work/src/misalign-bne-01.S/dut/my.elf | Bin 0 -> 21512 bytes .../misalign-jal-01.S/dut/DUT-Spike.signature | 69 + riscof_work/src/misalign-jal-01.S/dut/my.elf | Bin 0 -> 21448 bytes .../misalign-lh-01.S/dut/DUT-Spike.signature | 69 + riscof_work/src/misalign-lh-01.S/dut/my.elf | Bin 0 -> 21364 bytes .../misalign-lhu-01.S/dut/DUT-Spike.signature | 69 + riscof_work/src/misalign-lhu-01.S/dut/my.elf | Bin 0 -> 21364 bytes .../misalign-lw-01.S/dut/DUT-Spike.signature | 71 + riscof_work/src/misalign-lw-01.S/dut/my.elf | Bin 0 -> 21416 bytes .../misalign-sh-01.S/dut/DUT-Spike.signature | 69 + riscof_work/src/misalign-sh-01.S/dut/my.elf | Bin 0 -> 21364 bytes .../misalign-sw-01.S/dut/DUT-Spike.signature | 71 + riscof_work/src/misalign-sw-01.S/dut/my.elf | Bin 0 -> 21416 bytes .../dut/DUT-Spike.signature | 69 + .../src/misalign2-jalr-01.S/dut/my.elf | Bin 0 -> 21428 bytes riscof_work/test_list.yaml | 179 + riscv-test-suite/env/arch_test.h | 337 +- 39 files changed, 6824 insertions(+), 143 deletions(-) create mode 100644 riscof_work/Makefile.Reference-sail_c_simulator create mode 100644 riscof_work/database.yaml create mode 100644 riscof_work/spike_simple_isa_checked.yaml create mode 100644 riscof_work/spike_simple_platform_checked.yaml create mode 100644 riscof_work/src/ebreak.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/ebreak.S/dut/my.elf create mode 100644 riscof_work/src/ebreak.S/ref/ebreak.log create mode 100644 riscof_work/src/ebreak.S/ref/ref.disass create mode 100755 riscof_work/src/ebreak.S/ref/ref.elf create mode 100644 riscof_work/src/ecall.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/ecall.S/dut/my.elf create mode 100644 riscof_work/src/misalign-beq-01.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/misalign-beq-01.S/dut/my.elf create mode 100644 riscof_work/src/misalign-bge-01.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/misalign-bge-01.S/dut/my.elf create mode 100644 riscof_work/src/misalign-bgeu-01.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/misalign-bgeu-01.S/dut/my.elf create mode 100644 riscof_work/src/misalign-blt-01.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/misalign-blt-01.S/dut/my.elf create mode 100644 riscof_work/src/misalign-bltu-01.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/misalign-bltu-01.S/dut/my.elf create mode 100644 riscof_work/src/misalign-bne-01.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/misalign-bne-01.S/dut/my.elf create mode 100644 riscof_work/src/misalign-jal-01.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/misalign-jal-01.S/dut/my.elf create mode 100644 riscof_work/src/misalign-lh-01.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/misalign-lh-01.S/dut/my.elf create mode 100644 riscof_work/src/misalign-lhu-01.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/misalign-lhu-01.S/dut/my.elf create mode 100644 riscof_work/src/misalign-lw-01.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/misalign-lw-01.S/dut/my.elf create mode 100644 riscof_work/src/misalign-sh-01.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/misalign-sh-01.S/dut/my.elf create mode 100644 riscof_work/src/misalign-sw-01.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/misalign-sw-01.S/dut/my.elf create mode 100644 riscof_work/src/misalign2-jalr-01.S/dut/DUT-Spike.signature create mode 100755 riscof_work/src/misalign2-jalr-01.S/dut/my.elf create mode 100644 riscof_work/test_list.yaml diff --git a/riscof_work/Makefile.Reference-sail_c_simulator b/riscof_work/Makefile.Reference-sail_c_simulator new file mode 100644 index 000000000..fc826ff1e --- /dev/null +++ b/riscof_work/Makefile.Reference-sail_c_simulator @@ -0,0 +1,61 @@ + + +.PHONY : ebreak +ebreak : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/ebreak.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/ebreak.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > ebreak.log 2>&1; + +.PHONY : ecall +ecall : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/ecall.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/ecall.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > ecall.log 2>&1; + +.PHONY : misalign-beq-01 +misalign-beq-01 : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-beq-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-beq-01.log 2>&1; + +.PHONY : misalign-bge-01 +misalign-bge-01 : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bge-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bge-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-bge-01.log 2>&1; + +.PHONY : misalign-bgeu-01 +misalign-bgeu-01 : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bgeu-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bgeu-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-bgeu-01.log 2>&1; + +.PHONY : misalign-blt-01 +misalign-blt-01 : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-blt-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-blt-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-blt-01.log 2>&1; + +.PHONY : misalign-bltu-01 +misalign-bltu-01 : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bltu-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bltu-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-bltu-01.log 2>&1; + +.PHONY : misalign-bne-01 +misalign-bne-01 : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bne-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bne-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-bne-01.log 2>&1; + +.PHONY : misalign-jal-01 +misalign-jal-01 : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-jal-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-jal-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-jal-01.log 2>&1; + +.PHONY : misalign-lh-01 +misalign-lh-01 : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-lh-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lh-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-lh-01.log 2>&1; + +.PHONY : misalign-lhu-01 +misalign-lhu-01 : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-lhu-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lhu-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-lhu-01.log 2>&1; + +.PHONY : misalign-lw-01 +misalign-lw-01 : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-lw-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lw-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-lw-01.log 2>&1; + +.PHONY : misalign-sh-01 +misalign-sh-01 : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-sh-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sh-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-sh-01.log 2>&1; + +.PHONY : misalign-sw-01 +misalign-sw-01 : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-sw-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sw-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-sw-01.log 2>&1; + +.PHONY : misalign2-jalr-01 +misalign2-jalr-01 : + @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign2-jalr-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign2-jalr-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign2-jalr-01.log 2>&1; \ No newline at end of file diff --git a/riscof_work/database.yaml b/riscof_work/database.yaml new file mode 100644 index 000000000..426d2513a --- /dev/null +++ b/riscof_work/database.yaml @@ -0,0 +1,347 @@ +# database generated on 2024-06-03 16:17 GMT +!!omap +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/ebreak.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - ebreak +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/ecall.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - ecall +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '0': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*C.*) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-beq + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + - check ISA:=regex(^[^C]+$) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-beq +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bge-01.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '0': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*C.*) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-bge + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + - check ISA:=regex(^[^C]+$) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-bge +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bgeu-01.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '0': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*C.*) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-bgeu + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + - check ISA:=regex(^[^C]+$) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-bgeu +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-blt-01.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '0': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*C.*) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-blt + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + - check ISA:=regex(^[^C]+$) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-blt +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bltu-01.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '0': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*C.*) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-bltu + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + - check ISA:=regex(^[^C]+$) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-bltu +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bne-01.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '0': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*C.*) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-bne + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + - check ISA:=regex(^[^C]+$) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-bne +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-jal-01.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '0': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*C.*) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-jal + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + - check ISA:=regex(^[^C]+$) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-jal +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lh-01.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '0': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*) + - check hw_data_misaligned_support:=True + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-lh + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + - check hw_data_misaligned_support:=False + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-lh +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lhu-01.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '0': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*) + - check hw_data_misaligned_support:=True + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-lhu + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + - check hw_data_misaligned_support:=False + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-lhu +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lw-01.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '0': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*) + - check hw_data_misaligned_support:=True + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-lw + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + - check hw_data_misaligned_support:=False + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-lw +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sh-01.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '0': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*) + - check hw_data_misaligned_support:=True + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-sh + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + - check hw_data_misaligned_support:=False + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-sh +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sw-01.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '0': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*) + - check hw_data_misaligned_support:=True + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-sw + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + - check hw_data_misaligned_support:=False + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign-sw +- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign2-jalr-01.S: + commit_id: '-' + isa: + - RV32I_Zicsr + parts: !!omap + - '0': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*C.*) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign2-jalr + - '1': + check: + - check ISA:=regex(.*32.*) + - check ISA:=regex(.*I.*Zicsr.*) + - check ISA:=regex(^[^C]+$) + define: + - def rvtest_mtrap_routine=True + - def TEST_CASE_1=True + coverage_labels: + - misalign2-jalr diff --git a/riscof_work/spike_simple_isa_checked.yaml b/riscof_work/spike_simple_isa_checked.yaml new file mode 100644 index 000000000..6e4b396eb --- /dev/null +++ b/riscof_work/spike_simple_isa_checked.yaml @@ -0,0 +1,4121 @@ +hart_ids: [0] +hart0: + ISA: RV32IMAFDCZicsr_Zifencei + physical_addr_sz: 32 + User_Spec_Version: '2.3' + supported_xlen: + - 32 + misa: + reset-val: 0x4000112D + rv32: + accessible: true + mxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - mxl[1:0] in [0x1] + wr_illegal: + - Unchanged + description: Encodes the native base integer ISA width. + shadow: + shadow_type: rw + msb: 31 + lsb: 30 + extensions: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - extensions[25:0] bitmask [0x000112D, 0x0000000] + wr_illegal: + - Unchanged + + description: Encodes the presence of the standard extensions, with + a single bit per letter of the alphabet. + shadow: + shadow_type: rw + msb: 25 + lsb: 0 + fields: + - extensions + - mxl + - + - + - 26 + - 29 + description: misa is a read-write register reporting the ISA supported by + the hart. + address: 769 + priv_mode: M + rv64: + accessible: false + Privilege_Spec_Version: '1.10' + hw_data_misaligned_support: false + pmp_granularity: 0 + custom_exceptions: + custom_interrupts: + pte_ad_hw_update: false + mtval_update: 0b11111111 + mstatus: + rv32: + accessible: true + fields: + - uie + - sie + - mie + - upie + - spie + - mpie + - spp + - mpp + - fs + - xs + - mprv + - sum + - mxr + - tvm + - tw + - tsr + - sd + - + - + - 2 + - + - 6 + - + - 9 + - 10 + - + - 23 + - 30 + uie: + implemented: false + description: Stores the state of the user mode interrupts. + shadow: + shadow_type: rw + msb: 0 + lsb: 0 + sie: + implemented: false + description: Stores the state of the supervisor mode interrupts. + shadow: + shadow_type: rw + msb: 1 + lsb: 1 + mie: + implemented: true + description: Stores the state of the machine mode interrupts. + shadow: + shadow_type: rw + msb: 3 + lsb: 3 + type: + wlrl: + - 0:1 + upie: + implemented: false + description: Stores the state of the user mode interrupts prior to + the trap. + shadow: + shadow_type: rw + msb: 4 + lsb: 4 + spie: + implemented: false + description: Stores the state of the supervisor mode interrupts prior + to the trap. + shadow: + shadow_type: rw + msb: 5 + lsb: 5 + mpie: + implemented: true + description: Stores the state of the machine mode interrupts prior + to the trap. + shadow: + shadow_type: rw + msb: 7 + lsb: 7 + type: + wlrl: + - 0:1 + spp: + implemented: false + description: Stores the previous priority mode for supervisor. + shadow: + shadow_type: rw + msb: 8 + lsb: 8 + mpp: + implemented: true + description: Stores the previous priority mode for machine. + shadow: + shadow_type: rw + msb: 12 + lsb: 11 + type: {ro_constant: 0} + fs: + implemented: true + description: Encodes the status of the floating-point unit, including + the CSR fcsr and floating-point data registers. + shadow: + shadow_type: rw + msb: 14 + lsb: 13 + type: + warl: + dependency_fields: [] + legal: + - fs[1:0] in [0x0:0x3] + wr_illegal: + - unchanged + xs: + implemented: false + description: Encodes the status of additional user-mode extensions + and associated state. + shadow: + shadow_type: rw + msb: 16 + lsb: 15 + mprv: + implemented: false + description: Modifies the privilege level at which loads and stores + execute in all privilege modes. + shadow: + shadow_type: rw + msb: 17 + lsb: 17 + sum: + implemented: false + description: Modifies the privilege with which S-mode loads and stores + access virtual memory. + shadow: + shadow_type: rw + msb: 18 + lsb: 18 + mxr: + implemented: false + description: Modifies the privilege with which loads access virtual + memory. + shadow: + shadow_type: rw + msb: 19 + lsb: 19 + tvm: + implemented: false + description: Supports intercepting supervisor virtual-memory management + operations. + shadow: + shadow_type: rw + msb: 20 + lsb: 20 + tw: + implemented: false + description: Supports intercepting the WFI instruction. + shadow: + shadow_type: rw + msb: 21 + lsb: 21 + tsr: + implemented: false + description: Supports intercepting the supervisor exception return + instruction. + shadow: + shadow_type: rw + msb: 22 + lsb: 22 + sd: + implemented: true + description: Read-only bit that summarizes whether either the FS field + or XS field signals the presence of some dirty state. + shadow: + shadow_type: rw + msb: 31 + lsb: 31 + type: + wlrl: + - 0:1 + rv64: + accessible: false + description: The mstatus register keeps track of and controls the hart’s current + operating state. + address: 768 + priv_mode: M + reset-val: 0 + mstatush: + rv32: + accessible: true + fields: + - sbe + - mbe + - gva + - mpv + - + - + - 0 + - 3 + - + - 8 + - 31 + mpv: + implemented: false + description: Stores the state of the user mode interrupts. + shadow: + shadow_type: rw + msb: 7 + lsb: 7 + gva: + implemented: false + description: Stores the state of the supervisor mode interrupts. + shadow: + shadow_type: rw + msb: 6 + lsb: 6 + mbe: + implemented: false + description: control the endianness of memory accesses other than + instruction fetches for machine mode + shadow: + shadow_type: rw + msb: 5 + lsb: 5 + sbe: + implemented: false + description: control the endianness of memory accesses other than + instruction fetches for supervisor mode + shadow: + shadow_type: rw + msb: 4 + lsb: 4 + rv64: + accessible: false + description: The mstatush register keeps track of and controls the hart’s + current operating state. + address: 768 + priv_mode: M + reset-val: 0 + mvendorid: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + ro_constant: 0 + rv64: + accessible: false + description: 32-bit read-only register providing the JEDEC manufacturer ID + of the provider of the core. + address: 3857 + priv_mode: M + reset-val: 0 + marchid: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + ro_constant: 0 + rv64: + accessible: false + description: MXLEN-bit read-only register encoding the base microarchitecture + of the hart. + address: 3858 + priv_mode: M + reset-val: 0 + mimpid: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + ro_constant: 0 + rv64: + accessible: false + description: Provides a unique encoding of the version of the processor implementation. + address: 3859 + priv_mode: M + reset-val: 0 + mhartid: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + ro_constant: 0 + rv64: + accessible: false + description: MXLEN-bit read-only register containing the integer ID of the + hardware thread running the code. + address: 3860 + priv_mode: M + reset-val: 0 + mtvec: + rv32: + accessible: true + fields: + - mode + - base + base: + implemented: true + description: Vector base address. + shadow: + shadow_type: rw + msb: 31 + lsb: 2 + type: + warl: + dependency_fields: [] + legal: + - base[29:0] bitmask [0x3FFFFFFF, 0x00000000] + wr_illegal: + - Unchanged + mode: + implemented: true + description: Vector mode. + shadow: + shadow_type: rw + msb: 1 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mode[1:0] in [0x0,0x1] + wr_illegal: + - Unchanged + rv64: + accessible: false + description: MXLEN-bit read/write register that holds trap vector configuration. + address: 773 + priv_mode: M + reset-val: 0 + mideleg: + rv32: + accessible: false + rv64: + accessible: false + description: Machine Interrupt delegation Register. + address: 771 + priv_mode: M + reset-val: 0 + medeleg: + rv32: + accessible: false + rv64: + accessible: false + description: Machine Exception delegation Register. + address: 770 + priv_mode: M + reset-val: 0 + mip: + rv32: + accessible: true + fields: + - usip + - ssip + - vssip + - msip + - utip + - stip + - vstip + - mtip + - ueip + - seip + - vseip + - meip + - sgeip + - + - + - 13 + - 31 + usip: + implemented: false + description: User Software Interrupt Pending. + shadow: + shadow_type: rw + msb: 0 + lsb: 0 + ssip: + implemented: false + description: Supervisor Software Interrupt Pending. + shadow: + shadow_type: rw + msb: 1 + lsb: 1 + vssip: + implemented: false + description: VS-level Software Interrupt Pending. + shadow: + shadow_type: rw + msb: 2 + lsb: 2 + msip: + implemented: true + description: Machine Software Interrupt Pending. + shadow: + shadow_type: rw + msb: 3 + lsb: 3 + type: + ro_variable: true + utip: + implemented: false + description: User Timer Interrupt Pending. + shadow: + shadow_type: rw + msb: 4 + lsb: 4 + stip: + implemented: false + description: Supervisor Timer Interrupt Pending. + shadow: + shadow_type: rw + msb: 5 + lsb: 5 + vstip: + implemented: false + description: VS-level Timer Interrupt Pending. + shadow: + shadow_type: rw + msb: 6 + lsb: 6 + mtip: + implemented: true + description: Machine Timer Interrupt Pending. + shadow: + shadow_type: rw + msb: 7 + lsb: 7 + type: + ro_variable: true + ueip: + implemented: false + description: User External Interrupt Pending. + shadow: + shadow_type: rw + msb: 8 + lsb: 8 + seip: + implemented: false + description: Supervisor External Interrupt Pending. + shadow: + shadow_type: rw + msb: 9 + lsb: 9 + vseip: + implemented: false + description: VS-level External Interrupt Pending. + shadow: + shadow_type: rw + msb: 10 + lsb: 10 + meip: + implemented: true + description: Machine External Interrupt Pending. + shadow: + shadow_type: rw + msb: 11 + lsb: 11 + type: + ro_variable: true + sgeip: + implemented: false + description: HS-level External Interrupt Pending. + shadow: + shadow_type: rw + msb: 12 + lsb: 12 + rv64: + accessible: false + description: The mip register is an MXLEN-bit read/write register containing + information on pending interrupts. + address: 836 + priv_mode: M + reset-val: 0 + hie: + rv32: + accessible: false + rv64: + accessible: false + description: The hie register is an HSXLEN-bit read/write register containing + interrupt enable bits. + address: 0x604 + priv_mode: H + reset-val: 0 + mie: + rv32: + accessible: true + fields: + - usie + - ssie + - vssie + - msie + - utie + - stie + - vstie + - mtie + - ueie + - seie + - vseie + - meie + - sgeie + - + - + - 13 + - 31 + usie: + implemented: false + description: User Software Interrupt enable. + shadow: + shadow_type: rw + msb: 0 + lsb: 0 + ssie: + implemented: false + description: Supervisor Software Interrupt enable. + shadow: + shadow_type: rw + msb: 1 + lsb: 1 + vssie: + implemented: false + description: VS-level Software Interrupt enable. + shadow: + shadow_type: rw + msb: 2 + lsb: 2 + msie: + implemented: true + description: Machine Software Interrupt enable. + shadow: + shadow_type: rw + msb: 3 + lsb: 3 + type: + wlrl: + - 0x0:0x1 + utie: + implemented: false + description: User Timer Interrupt enable. + shadow: + shadow_type: rw + msb: 4 + lsb: 4 + stie: + implemented: false + description: Supervisor Timer Interrupt enable. + shadow: + shadow_type: rw + msb: 5 + lsb: 5 + vstie: + implemented: false + description: VS-level Timer Interrupt enable. + shadow: + shadow_type: rw + msb: 6 + lsb: 6 + mtie: + implemented: true + description: Machine Timer Interrupt enable. + shadow: + shadow_type: rw + msb: 7 + lsb: 7 + type: + wlrl: + - 0:1 + ueie: + implemented: false + description: User External Interrupt enable. + shadow: + shadow_type: rw + msb: 8 + lsb: 8 + seie: + implemented: false + description: Supervisor External Interrupt enable. + shadow: + shadow_type: rw + msb: 9 + lsb: 9 + vseie: + implemented: false + description: VS-level External Interrupt enable. + shadow: + shadow_type: rw + msb: 10 + lsb: 10 + meie: + implemented: true + description: Machine External Interrupt enable. + shadow: + shadow_type: rw + msb: 11 + lsb: 11 + type: + wlrl: + - 0:1 + sgeie: + implemented: false + description: HS-level External Interrupt enable. + shadow: + shadow_type: rw + msb: 12 + lsb: 12 + rv64: + accessible: false + description: The mie register is an MXLEN-bit read/write register containing + interrupt enable bits. + address: 772 + priv_mode: M + reset-val: 0 + mscratch: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mscratch[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + description: The mscratch register is an MXLEN-bit read/write register dedicated + for use by machine mode. + address: 832 + priv_mode: M + reset-val: 0 + mepc: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mepc[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + description: The mepc is a warl register that must be able to hold all valid + physical and virtual addresses. + address: 0x341 + priv_mode: M + reset-val: 0 + mtval: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mtval[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + description: The mtval is a warl register that holds the address of the instruction + which caused the exception. + address: 835 + priv_mode: M + reset-val: 0 + mcause: + rv32: + accessible: true + fields: + - exception_code + - interrupt + interrupt: + implemented: true + description: Indicates whether the trap was due to an interrupt. + shadow: + shadow_type: rw + msb: 31 + lsb: 31 + type: + wlrl: + - 0x0:0x1 + exception_code: + implemented: true + description: Encodes the exception code. + shadow: + shadow_type: rw + msb: 30 + lsb: 0 + type: + wlrl: + - 0:15 + rv64: + accessible: false + description: The mcause register stores the information regarding the trap. + address: 834 + priv_mode: M + reset-val: 0 + pmpcfg0: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A0 + priv_mode: M + reset-val: 0 + pmpcfg1: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A1 + priv_mode: M + reset-val: 0 + pmpcfg2: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A2 + priv_mode: M + reset-val: 0 + pmpcfg3: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A3 + priv_mode: M + reset-val: 0 + pmpcfg4: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A4 + priv_mode: M + reset-val: 0 + pmpcfg5: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A5 + priv_mode: M + reset-val: 0 + pmpcfg6: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A6 + priv_mode: M + reset-val: 0 + pmpcfg7: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A7 + priv_mode: M + reset-val: 0 + pmpcfg8: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A8 + priv_mode: M + reset-val: 0 + pmpcfg9: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3A9 + priv_mode: M + reset-val: 0 + pmpcfg10: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3AA + priv_mode: M + reset-val: 0 + pmpcfg11: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3AB + priv_mode: M + reset-val: 0 + pmpcfg12: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3AC + priv_mode: M + reset-val: 0 + pmpcfg13: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3AD + priv_mode: M + reset-val: 0 + pmpcfg14: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3AE + priv_mode: M + reset-val: 0 + pmpcfg15: + rv32: + accessible: false + rv64: + accessible: false + description: PMP configuration register + address: 0x3AF + priv_mode: M + reset-val: 0 + pmpaddr0: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B0 + priv_mode: M + reset-val: 0 + pmpaddr1: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B1 + priv_mode: M + reset-val: 0 + pmpaddr2: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B2 + priv_mode: M + reset-val: 0 + pmpaddr3: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B3 + priv_mode: M + reset-val: 0 + pmpaddr4: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B4 + priv_mode: M + reset-val: 0 + pmpaddr5: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B5 + priv_mode: M + reset-val: 0 + pmpaddr6: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B6 + priv_mode: M + reset-val: 0 + pmpaddr7: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B7 + priv_mode: M + reset-val: 0 + pmpaddr8: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B8 + priv_mode: M + reset-val: 0 + pmpaddr9: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3B9 + priv_mode: M + reset-val: 0 + pmpaddr10: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3BA + priv_mode: M + reset-val: 0 + pmpaddr11: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3BB + priv_mode: M + reset-val: 0 + pmpaddr12: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3BC + priv_mode: M + reset-val: 0 + pmpaddr13: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3BD + priv_mode: M + reset-val: 0 + pmpaddr14: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3BE + priv_mode: M + reset-val: 0 + pmpaddr15: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3BF + priv_mode: M + reset-val: 0 + pmpaddr16: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C0 + priv_mode: M + reset-val: 0 + pmpaddr17: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C1 + priv_mode: M + reset-val: 0 + pmpaddr18: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C2 + priv_mode: M + reset-val: 0 + pmpaddr19: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C3 + priv_mode: M + reset-val: 0 + pmpaddr20: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C4 + priv_mode: M + reset-val: 0 + pmpaddr21: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C5 + priv_mode: M + reset-val: 0 + pmpaddr22: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C6 + priv_mode: M + reset-val: 0 + pmpaddr23: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C7 + priv_mode: M + reset-val: 0 + pmpaddr24: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C8 + priv_mode: M + reset-val: 0 + pmpaddr25: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3C9 + priv_mode: M + reset-val: 0 + pmpaddr26: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3CA + priv_mode: M + reset-val: 0 + pmpaddr27: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3CB + priv_mode: M + reset-val: 0 + pmpaddr28: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3CC + priv_mode: M + reset-val: 0 + pmpaddr29: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3CD + priv_mode: M + reset-val: 0 + pmpaddr30: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3CE + priv_mode: M + reset-val: 0 + pmpaddr31: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3CF + priv_mode: M + reset-val: 0 + pmpaddr32: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D0 + priv_mode: M + reset-val: 0 + pmpaddr33: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D1 + priv_mode: M + reset-val: 0 + pmpaddr34: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D2 + priv_mode: M + reset-val: 0 + pmpaddr35: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D3 + priv_mode: M + reset-val: 0 + pmpaddr36: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D4 + priv_mode: M + reset-val: 0 + pmpaddr37: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D5 + priv_mode: M + reset-val: 0 + pmpaddr38: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D6 + priv_mode: M + reset-val: 0 + pmpaddr39: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D7 + priv_mode: M + reset-val: 0 + pmpaddr40: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D8 + priv_mode: M + reset-val: 0 + pmpaddr41: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3D9 + priv_mode: M + reset-val: 0 + pmpaddr42: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3DA + priv_mode: M + reset-val: 0 + pmpaddr43: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3DB + priv_mode: M + reset-val: 0 + pmpaddr44: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3DC + priv_mode: M + reset-val: 0 + pmpaddr45: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3DD + priv_mode: M + reset-val: 0 + pmpaddr46: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3DE + priv_mode: M + reset-val: 0 + pmpaddr47: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3DF + priv_mode: M + reset-val: 0 + pmpaddr48: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E0 + priv_mode: M + reset-val: 0 + pmpaddr49: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E1 + priv_mode: M + reset-val: 0 + pmpaddr50: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E2 + priv_mode: M + reset-val: 0 + pmpaddr51: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E3 + priv_mode: M + reset-val: 0 + pmpaddr52: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E4 + priv_mode: M + reset-val: 0 + pmpaddr53: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E5 + priv_mode: M + reset-val: 0 + pmpaddr54: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E6 + priv_mode: M + reset-val: 0 + pmpaddr55: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E7 + priv_mode: M + reset-val: 0 + pmpaddr56: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E8 + priv_mode: M + reset-val: 0 + pmpaddr57: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3E9 + priv_mode: M + reset-val: 0 + pmpaddr58: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3EA + priv_mode: M + reset-val: 0 + pmpaddr59: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3EB + priv_mode: M + reset-val: 0 + pmpaddr60: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3EC + priv_mode: M + reset-val: 0 + pmpaddr61: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3ED + priv_mode: M + reset-val: 0 + pmpaddr62: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3EE + priv_mode: M + reset-val: 0 + pmpaddr63: + rv32: + accessible: false + rv64: + accessible: false + description: Physical memory protection address register + address: 0x3EF + priv_mode: M + reset-val: 0 + mcounteren: + rv32: + accessible: false + rv64: + accessible: false + description: The mcounteren is a 32-bit register that controls the availability + of the hardware performance-monitoring counters to the next-lowest privileged + mode. + address: 0x306 + priv_mode: M + reset-val: 0 + mcountinhibit: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: {ro_constant: 0} + rv64: + accessible: false + description: The mcountinhibit is a 32-bit WARL register that controls which + of the hardware performance-monitoring counters increment. + address: 0x320 + priv_mode: M + reset-val: 0 + mcycle: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mcycle[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + description: Counts the number of clock cycles executed from an arbitrary + point in time. + address: 0xB00 + priv_mode: M + reset-val: 0 + mcycleh: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - mcycleh[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + description: upper 32 bits of mcycle + address: 0xB80 + priv_mode: M + reset-val: 0 + minstret: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - minstret[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + description: Counts the number of instructions completed from an arbitrary + point in time. + address: 0xB02 + priv_mode: M + reset-val: 0 + minstreth: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: + warl: + dependency_fields: [] + legal: + - minstreth[31:0] in [0x00000000:0xFFFFFFFF] + wr_illegal: + - unchanged + rv64: + accessible: false + description: Upper 32 bits of minstret. + address: 0xB82 + priv_mode: M + reset-val: 0 + mhpmevent3: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: &id001 + ro_constant: 0 + rv64: + accessible: false + description: The mhpmevent3 is a MXLEN-bit event register which controls mhpmcounter3. + address: 0x323 + priv_mode: M + reset-val: 0 + mhpmcounter3: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter3 is a 64-bit counter. Returns lower 32 bits in + RV32I mode. + address: 0xB03 + priv_mode: M + reset-val: 0 + mhpmcounter3h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: &id002 + ro_constant: 0 + rv64: + accessible: false + description: The mhpmcounter3h returns the upper half word in RV32I systems. + address: 0xB83 + priv_mode: M + reset-val: 0 + mhpmevent4: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent4 is a MXLEN-bit event register which controls mhpmcounter4. + address: 0x324 + priv_mode: M + reset-val: 0 + mhpmcounter4: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter4 is a 64-bit counter. Returns lower 42 bits in + RV42I mode. + address: 0xB04 + priv_mode: M + reset-val: 0 + mhpmcounter4h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter4h returns the upper half word in RV42I systems. + address: 0xB84 + priv_mode: M + reset-val: 0 + mhpmevent5: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent5 is a MXLEN-bit event register which controls mhpmcounter5. + address: 0x325 + priv_mode: M + reset-val: 0 + mhpmcounter5: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter5 is a 64-bit counter. Returns lower 52 bits in + RV52I mode. + address: 0xB05 + priv_mode: M + reset-val: 0 + mhpmcounter5h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter5h returns the upper half word in RV52I systems. + address: 0xB85 + priv_mode: M + reset-val: 0 + mhpmevent6: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent6 is a MXLEN-bit event register which controls mhpmcounter6. + address: 0x326 + priv_mode: M + reset-val: 0 + mhpmcounter6: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter6 is a 64-bit counter. Returns lower 62 bits in + RV62I mode. + address: 0xB06 + priv_mode: M + reset-val: 0 + mhpmcounter6h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter6h returns the upper half word in RV62I systems. + address: 0xB86 + priv_mode: M + reset-val: 0 + mhpmevent7: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent7 is a MXLEN-bit event register which controls mhpmcounter7. + address: 0x327 + priv_mode: M + reset-val: 0 + mhpmcounter7: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter7 is a 64-bit counter. Returns lower 72 bits in + RV72I mode. + address: 0xB07 + priv_mode: M + reset-val: 0 + mhpmcounter7h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter7h returns the upper half word in RV72I systems. + address: 0xB87 + priv_mode: M + reset-val: 0 + mhpmevent8: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent8 is a MXLEN-bit event register which controls mhpmcounter8. + address: 0x328 + priv_mode: M + reset-val: 0 + mhpmcounter8: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter8 is a 64-bit counter. Returns lower 82 bits in + RV82I mode. + address: 0xB08 + priv_mode: M + reset-val: 0 + mhpmcounter8h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter8h returns the upper half word in RV82I systems. + address: 0xB88 + priv_mode: M + reset-val: 0 + mhpmevent9: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent9 is a MXLEN-bit event register which controls mhpmcounter9. + address: 0x329 + priv_mode: M + reset-val: 0 + mhpmcounter9: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter9 is a 64-bit counter. Returns lower 32 bits in + RV32I mode. + address: 0xB09 + priv_mode: M + reset-val: 0 + mhpmcounter9h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter9h returns the upper half word in RV32I systems. + address: 0xB89 + priv_mode: M + reset-val: 0 + mhpmevent10: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent10 is a MXLEN-bit event register which controls + mhpmcounter10. + address: 0x32a + priv_mode: M + reset-val: 0 + mhpmcounter10: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter10 is a 64-bit counter. Returns lower 102 bits + in RV102I mode. + address: 0xB0A + priv_mode: M + reset-val: 0 + mhpmcounter10h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter10h returns the upper half word in RV102I systems. + address: 0xB8A + priv_mode: M + reset-val: 0 + mhpmevent11: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent11 is a MXLEN-bit event register which controls + mhpmcounter11. + address: 0x32b + priv_mode: M + reset-val: 0 + mhpmcounter11: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter11 is a 64-bit counter. Returns lower 112 bits + in RV112I mode. + address: 0xB0B + priv_mode: M + reset-val: 0 + mhpmcounter11h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter11h returns the upper half word in RV112I systems. + address: 0xB8B + priv_mode: M + reset-val: 0 + mhpmevent12: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent12 is a MXLEN-bit event register which controls + mhpmcounter12. + address: 0x32c + priv_mode: M + reset-val: 0 + mhpmcounter12: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter12 is a 64-bit counter. Returns lower 122 bits + in RV122I mode. + address: 0xB0C + priv_mode: M + reset-val: 0 + mhpmcounter12h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter12h returns the upper half word in RV122I systems. + address: 0xB8C + priv_mode: M + reset-val: 0 + mhpmevent13: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent13 is a MXLEN-bit event register which controls + mhpmcounter13. + address: 0x32d + priv_mode: M + reset-val: 0 + mhpmcounter13: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter13 is a 64-bit counter. Returns lower 132 bits + in RV132I mode. + address: 0xB0D + priv_mode: M + reset-val: 0 + mhpmcounter13h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter13h returns the upper half word in RV132I systems. + address: 0xB8D + priv_mode: M + reset-val: 0 + mhpmevent14: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent14 is a MXLEN-bit event register which controls + mhpmcounter14. + address: 0x32e + priv_mode: M + reset-val: 0 + mhpmcounter14: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter14 is a 64-bit counter. Returns lower 142 bits + in RV142I mode. + address: 0xB0E + priv_mode: M + reset-val: 0 + mhpmcounter14h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter14h returns the upper half word in RV142I systems. + address: 0xB8E + priv_mode: M + reset-val: 0 + mhpmevent15: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent15 is a MXLEN-bit event register which controls + mhpmcounter15. + address: 0x32f + priv_mode: M + reset-val: 0 + mhpmcounter15: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter15 is a 64-bit counter. Returns lower 152 bits + in RV152I mode. + address: 0xB0F + priv_mode: M + reset-val: 0 + mhpmcounter15h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter15h returns the upper half word in RV152I systems. + address: 0xB8F + priv_mode: M + reset-val: 0 + mhpmevent16: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent16 is a MXLEN-bit event register which controls + mhpmcounter16. + address: 0x330 + priv_mode: M + reset-val: 0 + mhpmcounter16: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter16 is a 64-bit counter. Returns lower 162 bits + in RV162I mode. + address: 0xB10 + priv_mode: M + reset-val: 0 + mhpmcounter16h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter16h returns the upper half word in RV162I systems. + address: 0xB90 + priv_mode: M + reset-val: 0 + mhpmevent17: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent17 is a MXLEN-bit event register which controls + mhpmcounter17. + address: 0x331 + priv_mode: M + reset-val: 0 + mhpmcounter17: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter17 is a 64-bit counter. Returns lower 172 bits + in RV172I mode. + address: 0xB11 + priv_mode: M + reset-val: 0 + mhpmcounter17h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter17h returns the upper half word in RV172I systems. + address: 0xB91 + priv_mode: M + reset-val: 0 + mhpmevent18: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent18 is a MXLEN-bit event register which controls + mhpmcounter18. + address: 0x332 + priv_mode: M + reset-val: 0 + mhpmcounter18: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter18 is a 64-bit counter. Returns lower 182 bits + in RV182I mode. + address: 0xB12 + priv_mode: M + reset-val: 0 + mhpmcounter18h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter18h returns the upper half word in RV182I systems. + address: 0xB92 + priv_mode: M + reset-val: 0 + mhpmevent19: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent19 is a MXLEN-bit event register which controls + mhpmcounter19. + address: 0x333 + priv_mode: M + reset-val: 0 + mhpmcounter19: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter19 is a 64-bit counter. Returns lower 32 bits + in RV32I mode. + address: 0xB13 + priv_mode: M + reset-val: 0 + mhpmcounter19h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter19h returns the upper half word in RV32I systems. + address: 0xB93 + priv_mode: M + reset-val: 0 + mhpmevent20: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent20 is a MXLEN-bit event register which controls + mhpmcounter20. + address: 0x334 + priv_mode: M + reset-val: 0 + mhpmcounter20: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter20 is a 64-bit counter. Returns lower 202 bits + in RV202I mode. + address: 0xB14 + priv_mode: M + reset-val: 0 + mhpmcounter20h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter20h returns the upper half word in RV202I systems. + address: 0xB94 + priv_mode: M + reset-val: 0 + mhpmevent21: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent21 is a MXLEN-bit event register which controls + mhpmcounter21. + address: 0x335 + priv_mode: M + reset-val: 0 + mhpmcounter21: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter21 is a 64-bit counter. Returns lower 212 bits + in RV212I mode. + address: 0xB15 + priv_mode: M + reset-val: 0 + mhpmcounter21h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter21h returns the upper half word in RV212I systems. + address: 0xB95 + priv_mode: M + reset-val: 0 + mhpmevent22: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent22 is a MXLEN-bit event register which controls + mhpmcounter22. + address: 0x336 + priv_mode: M + reset-val: 0 + mhpmcounter22: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter22 is a 64-bit counter. Returns lower 222 bits + in RV222I mode. + address: 0xB16 + priv_mode: M + reset-val: 0 + mhpmcounter22h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter22h returns the upper half word in RV222I systems. + address: 0xB96 + priv_mode: M + reset-val: 0 + mhpmevent23: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent23 is a MXLEN-bit event register which controls + mhpmcounter23. + address: 0x337 + priv_mode: M + reset-val: 0 + mhpmcounter23: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter23 is a 64-bit counter. Returns lower 232 bits + in RV232I mode. + address: 0xB17 + priv_mode: M + reset-val: 0 + mhpmcounter23h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter23h returns the upper half word in RV232I systems. + address: 0xB97 + priv_mode: M + reset-val: 0 + mhpmevent24: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent24 is a MXLEN-bit event register which controls + mhpmcounter24. + address: 0x338 + priv_mode: M + reset-val: 0 + mhpmcounter24: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter24 is a 64-bit counter. Returns lower 242 bits + in RV242I mode. + address: 0xB18 + priv_mode: M + reset-val: 0 + mhpmcounter24h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter24h returns the upper half word in RV242I systems. + address: 0xB98 + priv_mode: M + reset-val: 0 + mhpmevent25: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent25 is a MXLEN-bit event register which controls + mhpmcounter25. + address: 0x339 + priv_mode: M + reset-val: 0 + mhpmcounter25: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter25 is a 64-bit counter. Returns lower 252 bits + in RV252I mode. + address: 0xB19 + priv_mode: M + reset-val: 0 + mhpmcounter25h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter25h returns the upper half word in RV252I systems. + address: 0xB99 + priv_mode: M + reset-val: 0 + mhpmevent26: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent26 is a MXLEN-bit event register which controls + mhpmcounter26. + address: 0x33a + priv_mode: M + reset-val: 0 + mhpmcounter26: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter26 is a 64-bit counter. Returns lower 262 bits + in RV262I mode. + address: 0xB1A + priv_mode: M + reset-val: 0 + mhpmcounter26h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter26h returns the upper half word in RV262I systems. + address: 0xB9A + priv_mode: M + reset-val: 0 + mhpmevent27: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent27 is a MXLEN-bit event register which controls + mhpmcounter27. + address: 0x33b + priv_mode: M + reset-val: 0 + mhpmcounter27: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter27 is a 64-bit counter. Returns lower 272 bits + in RV272I mode. + address: 0xB1B + priv_mode: M + reset-val: 0 + mhpmcounter27h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter27h returns the upper half word in RV272I systems. + address: 0xB9B + priv_mode: M + reset-val: 0 + mhpmevent28: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent28 is a MXLEN-bit event register which controls + mhpmcounter28. + address: 0x33c + priv_mode: M + reset-val: 0 + mhpmcounter28: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter28 is a 64-bit counter. Returns lower 282 bits + in RV282I mode. + address: 0xB1C + priv_mode: M + reset-val: 0 + mhpmcounter28h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter28h returns the upper half word in RV282I systems. + address: 0xB9C + priv_mode: M + reset-val: 0 + mhpmevent29: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent29 is a MXLEN-bit event register which controls + mhpmcounter29. + address: 0x33d + priv_mode: M + reset-val: 0 + mhpmcounter29: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter29 is a 64-bit counter. Returns lower 32 bits + in RV32I mode. + address: 0xB1D + priv_mode: M + reset-val: 0 + mhpmcounter29h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter29h returns the upper half word in RV32I systems. + address: 0xB9D + priv_mode: M + reset-val: 0 + mhpmevent30: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent30 is a MXLEN-bit event register which controls + mhpmcounter30. + address: 0x33e + priv_mode: M + reset-val: 0 + mhpmcounter30: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter30 is a 64-bit counter. Returns lower 302 bits + in RV302I mode. + address: 0xB1E + priv_mode: M + reset-val: 0 + mhpmcounter30h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter30h returns the upper half word in RV302I systems. + address: 0xB9E + priv_mode: M + reset-val: 0 + mhpmevent31: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmevent31 is a MXLEN-bit event register which controls + mhpmcounter31. + address: 0x33f + priv_mode: M + reset-val: 0 + mhpmcounter31: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id001 + rv64: + accessible: false + description: The mhpmcounter31 is a 64-bit counter. Returns lower 312 bits + in RV312I mode. + address: 0xB1F + priv_mode: M + reset-val: 0 + mhpmcounter31h: + rv32: + accessible: true + fields: [] + shadow: + shadow_type: rw + msb: 31 + lsb: 0 + type: *id002 + rv64: + accessible: false + description: The mhpmcounter31h returns the upper half word in RV312I systems. + address: 0xB9F + priv_mode: M + reset-val: 0 + sedeleg: + rv32: + accessible: false + rv64: + accessible: false + description: sedeleg + address: 258 + priv_mode: S + reset-val: 0 + sideleg: + rv32: + accessible: false + rv64: + accessible: false + description: sideleg + priv_mode: S + address: 259 + reset-val: 0 + fflags: + rv32: + accessible: false + rv64: + accessible: false + description: 32-bit register to hold floating point accrued exceptions. + address: 001 + priv_mode: U + reset-val: 0 + frm: + rv32: + accessible: false + rv64: + accessible: false + description: 32-bit register to hold Floating-Point Dynamic Rounding Mode. + address: 002 + priv_mode: U + reset-val: 0 + fcsr: + rv32: + accessible: false + rv64: + accessible: false + description: 32-bit register to hold Floating-Point Control and Status Register. + address: 003 + priv_mode: U + reset-val: 0 + cycle: + rv32: + accessible: false + rv64: + accessible: false + description: Captures the number of cycles executed from an arbitrary point + in time. + priv_mode: U + address: 0xC00 + reset-val: 0 + cycleh: + rv32: + accessible: false + rv64: + accessible: false + description: Upper 32-bits of the mcycle counter; only for rv32. + address: 0xC80 + priv_mode: U + reset-val: 0 + time: + rv32: + accessible: false + rv64: + accessible: false + description: Timer for RDTIME instruction and RTC in the processor. + priv_mode: U + address: 0xC01 + reset-val: 0 + timeh: + rv32: + accessible: false + rv64: + accessible: false + description: Upper 32-bits of the Timer for RDTIME instruction and RTC in + the processor; only for rv32. + address: 0xC81 + priv_mode: U + reset-val: 0 + instret: + rv32: + accessible: false + rv64: + accessible: false + description: Captures the number of instructions executed from an arbitrary + point in time. + priv_mode: U + address: 0xC02 + reset-val: 0 + instreth: + rv32: + accessible: false + rv64: + accessible: false + description: Upper 32-bits of the minstret counter; only for rv32. + address: 0xC82 + priv_mode: U + reset-val: 0 + hpmcounter3: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter3 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC03 + hpmcounter4: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter4 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC04 + hpmcounter5: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter5 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC05 + hpmcounter6: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter6 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC06 + hpmcounter7: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter7 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC07 + hpmcounter8: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter8 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC08 + hpmcounter9: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter9 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC09 + hpmcounter10: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter10 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC0A + hpmcounter11: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter11 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC0B + hpmcounter12: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter12 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC0C + hpmcounter13: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter13 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC0D + hpmcounter14: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter14 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC0E + hpmcounter15: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter15 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC0F + hpmcounter16: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter16 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC10 + hpmcounter17: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter17 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC11 + hpmcounter18: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter18 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC12 + hpmcounter19: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter19 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC13 + hpmcounter20: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter20 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC14 + hpmcounter21: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter21 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC15 + hpmcounter22: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter22 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC16 + hpmcounter23: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter23 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC17 + hpmcounter24: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter24 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC18 + hpmcounter25: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter25 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC19 + hpmcounter26: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter26 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC1A + hpmcounter27: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter27 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC1B + hpmcounter28: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter28 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC1C + hpmcounter29: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter29 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC1D + hpmcounter30: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter30 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC1E + hpmcounter31: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter31 is a 64-bit counter. Returns lower 32 bits in + RV32UI mode. + address: 0xC1F + hpmcounter3h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter3h returns the upper half word in RV32I systems. + address: 0xC83 + hpmcounter4h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter4h returns the upper half word in RV32I systems. + address: 0xC84 + hpmcounter5h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter5h returns the upper half word in RV32I systems. + address: 0xC85 + hpmcounter6h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter6h returns the upper half word in RV32I systems. + address: 0xC86 + hpmcounter7h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter7h returns the upper half word in RV32I systems. + address: 0xC87 + hpmcounter8h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter8h returns the upper half word in RV32I systems. + address: 0xC88 + hpmcounter9h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter9h returns the upper half word in RV32I systems. + address: 0xC89 + hpmcounter10h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter10h returns the upper half word in RV32I systems. + address: 0xC8A + hpmcounter11h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter11h returns the upper half word in RV32I systems. + address: 0xC8B + hpmcounter12h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter12h returns the upper half word in RV32I systems. + address: 0xC8C + hpmcounter13h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter13h returns the upper half word in RV32I systems. + address: 0xC8D + hpmcounter14h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter14h returns the upper half word in RV32I systems. + address: 0xC8E + hpmcounter15h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter15h returns the upper half word in RV32I systems. + address: 0xC8F + hpmcounter16h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter16h returns the upper half word in RV32I systems. + address: 0xC90 + hpmcounter17h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter17h returns the upper half word in RV32I systems. + address: 0xC91 + hpmcounter18h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter18h returns the upper half word in RV32I systems. + address: 0xC92 + hpmcounter19h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter19h returns the upper half word in RV32I systems. + address: 0xC93 + hpmcounter20h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter20h returns the upper half word in RV32I systems. + address: 0xC94 + hpmcounter21h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter21h returns the upper half word in RV32I systems. + address: 0xC95 + hpmcounter22h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter22h returns the upper half word in RV32I systems. + address: 0xC96 + hpmcounter23h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter23h returns the upper half word in RV32I systems. + address: 0xC97 + hpmcounter24h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter24h returns the upper half word in RV32I systems. + address: 0xC98 + hpmcounter25h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter25h returns the upper half word in RV32I systems. + address: 0xC99 + hpmcounter26h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter26h returns the upper half word in RV32I systems. + address: 0xC9A + hpmcounter27h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter27h returns the upper half word in RV32I systems. + address: 0xC9B + hpmcounter28h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter28h returns the upper half word in RV32I systems. + address: 0xC9C + hpmcounter29h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter29h returns the upper half word in RV32I systems. + address: 0xC9D + hpmcounter30h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter30h returns the upper half word in RV32I systems. + address: 0xC9E + hpmcounter31h: + rv32: + accessible: false + rv64: + accessible: false + priv_mode: U + reset-val: 0 + description: The hpmcounter31h returns the upper half word in RV32I systems. + address: 0xC9F + sstatus: + rv32: + accessible: false + rv64: + accessible: false + description: The sstatus register keeps track of the processor’s current operating + state. + address: 0x100 + priv_mode: S + reset-val: 0 + sie: + rv32: + accessible: false + rv64: + accessible: false + description: The sie register is an SXLEN-bit read/write register containing + interrupt enable bits. + address: 0x104 + priv_mode: S + reset-val: 0 + sip: + rv32: + accessible: false + rv64: + accessible: false + description: The sip register is an SXLEN-bit read/write register containing + interrupt pending bits. + address: 0x144 + priv_mode: S + reset-val: 0 + sscratch: + rv32: + accessible: false + rv64: + accessible: false + description: The sscratch register is an MXLEN-bit read/write register dedicated + for use by machine mode. + address: 0x140 + priv_mode: S + reset-val: 0 + sepc: + rv32: + accessible: false + rv64: + accessible: false + description: The sepc is a warl register that must be able to hold all valid + physical and virtual addresses. + address: 0x141 + priv_mode: S + reset-val: 0 + stval: + rv32: + accessible: false + rv64: + accessible: false + description: The stval is a warl register that holds the address of the instruction + which caused the exception. + address: 0x143 + priv_mode: S + reset-val: 0 + scause: + rv32: + accessible: false + rv64: + accessible: false + description: The scause register stores the information regarding the trap. + address: 0x142 + priv_mode: S + reset-val: 0 + stvec: + rv32: + accessible: false + rv64: + accessible: false + description: SXLEN-bit read/write register that holds trap vector configuration. + address: 0x105 + priv_mode: S + reset-val: 0 + satp: + rv32: + accessible: false + rv64: + accessible: false + description: SXLEN-bit register which controls supervisor-mode address translation + and protection + address: 0x180 + priv_mode: S + reset-val: 0 + ustatus: + rv32: + accessible: false + rv64: + accessible: false + description: The ustatus register keeps track of the processor’s current operating + state. + address: 0x000 + priv_mode: U + reset-val: 0 + uie: + rv32: + accessible: false + rv64: + accessible: false + description: The uie register is an UXLEN-bit read/write register containing + interrupt enable bits. + address: 0x004 + priv_mode: U + reset-val: 0 + uip: + rv32: + accessible: false + rv64: + accessible: false + description: The uip register is an UXLEN-bit read/write register containing + interrupt pending bits. + address: 0x044 + priv_mode: U + reset-val: 0 + uscratch: + rv32: + accessible: false + rv64: + accessible: false + description: The uscratch register is an UXLEN-bit read/write register dedicated + for use by machine mode. + address: 0x040 + priv_mode: U + reset-val: 0 + uepc: + rv32: + accessible: false + rv64: + accessible: false + description: The uepc is a warl register that must be able to hold all valid + physical and virtual addresses. + address: 0x041 + priv_mode: U + reset-val: 0 + utval: + rv32: + accessible: false + rv64: + accessible: false + description: The utval is a warl register that holds the address of the instruction + which caused the exception. + address: 0x043 + priv_mode: U + reset-val: 0 + ucause: + rv32: + accessible: false + rv64: + accessible: false + description: The ucause register stores the information regarding the trap. + address: 0x042 + priv_mode: U + reset-val: 0 + utvec: + rv32: + accessible: false + rv64: + accessible: false + description: UXLEN-bit read/write register that holds trap vector configuration. + address: 0x005 + priv_mode: U + reset-val: 0 + scounteren: + rv32: + accessible: false + rv64: + accessible: false + description: The scounteren is a 32-bit register that controls the availability + of the hardware performance-monitoring counters to the next-lowest privileged + mode. + address: 0x106 + priv_mode: S + reset-val: 0 + hstatus: + rv32: + accessible: false + rv64: + accessible: false + description: The hstatus register keeps track of and controls the hart’s current + operating state. + address: 1536 + priv_mode: H + reset-val: 0 + hideleg: + rv32: + accessible: false + rv64: + accessible: false + description: Hypervisor Interrupt delegation Register. + address: 1539 + priv_mode: H + reset-val: 0 + hedeleg: + rv32: + accessible: false + rv64: + accessible: false + description: Hypervisor Exception delegation Register. + address: 1538 + priv_mode: H + reset-val: 0 + hip: + rv32: + accessible: false + rv64: + accessible: false + description: The hip register is an HXLEN-bit read/write register containing + information on pending interrupts. + address: 1604 + priv_mode: H + reset-val: 0 + hvip: + rv32: + accessible: false + rv64: + accessible: false + description: The hvip register is an HSXLEN-bit read/write register that a + hypervisor can write to indicate virtual interrupts intended for VS-mode. + address: 1605 + priv_mode: H + reset-val: 0 + hgeip: + rv32: + accessible: false + rv64: + accessible: false + description: The hgeip register is an HSXLEN-bit read-only register that indicates + pending guest external interrupts for this hart. + address: 0xE12 + priv_mode: H + reset-val: 0 + hgeie: + rv32: + accessible: false + rv64: + accessible: false + description: The hgeie register is an HSXLEN-bit read/write register that + contains enable bits for the guest external interrupts at this hart. + address: 0x607 + priv_mode: H + reset-val: 0 + htval: + rv32: + accessible: false + rv64: + accessible: false + description: The htval is a warl register that holds the address of the instruction + which caused the exception. + address: 0x643 + priv_mode: H + reset-val: 0 + htinst: + rv32: + accessible: false + rv64: + accessible: false + description: The htinst is a warl register that need only be able to hold + the values that the implementation may automatically write to it on a + trap. + address: 0x64A + priv_mode: H + reset-val: 0 + mtval2: + rv32: + accessible: false + rv64: + accessible: false + description: When a trap is taken into M-mode, mtval2 is written with additional + exception-specific information to assist software in handling the trap. + address: 0x34B + priv_mode: M + reset-val: 0 + mtinst: + rv32: + accessible: false + rv64: + accessible: false + description: The mtinst is a warl register that need only be able to hold + the values that the implementation may automatically write to it on a + trap. + address: 0x34A + priv_mode: M + reset-val: 0 + hgatp: + rv32: + accessible: false + rv64: + accessible: false + description: HSXLEN-bit register which controls G-stage address translation + and protection + address: 0x680 + priv_mode: H + reset-val: 0 + hcounteren: + rv32: + accessible: false + rv64: + accessible: false + description: The hcounteren is a 32-bit register that controls the availability + of the hardware performance-monitoring counters to the next-lowest privileged + mode. + address: 0x606 + priv_mode: H + reset-val: 0 + htimedelta: + rv32: + accessible: false + rv64: + accessible: false + description: The htimedelta CSR is a read/write register that contains the + delta between the value of the time CSR and the value returned in VS-mode + or VU-mode. + priv_mode: H + address: 0x605 + reset-val: 0 + htimedeltah: + rv32: + accessible: false + rv64: + accessible: false + description: Upper 32-bits of htimedelta + address: 0x615 + priv_mode: H + reset-val: 0 + vsstatus: + rv32: + accessible: false + rv64: + accessible: false + description: The vsstatus register keeps track of the processor’s current + operating state. + address: 0x200 + priv_mode: S + reset-val: 0 + vsie: + rv32: + accessible: false + rv64: + accessible: false + description: The vsie register is an VSXLEN-bit read/write register containing + interrupt enable bits. + address: 0x204 + priv_mode: S + reset-val: 0 + vsip: + rv32: + accessible: false + rv64: + accessible: false + description: The vsip register is an VSXLEN-bit read/write register containing + interrupt pending bits. + address: 0x244 + priv_mode: S + reset-val: 0 + vsscratch: + rv32: + accessible: false + rv64: + accessible: false + description: The vsscratch register is an VSXLEN-bit read/write register dedicated + for use by machine mode. + address: 0x240 + priv_mode: S + reset-val: 0 + vsepc: + rv32: + accessible: false + rv64: + accessible: false + description: The vsepc is a warl register that must be able to hold all valid + physical and virtual addresses. + address: 0x241 + priv_mode: S + reset-val: 0 + vstval: + rv32: + accessible: false + rv64: + accessible: false + description: The vstval is a warl register that holds the address of the instruction + which caused the exception. + address: 0x243 + priv_mode: S + reset-val: 0 + vscause: + rv32: + accessible: false + rv64: + accessible: false + description: The scause register stores the information regarding the trap. + address: 0x242 + priv_mode: S + reset-val: 0 + vstvec: + rv32: + accessible: false + rv64: + accessible: false + description: SXLEN-bit read/write register that holds trap vector configuration. + address: 0x205 + priv_mode: S + reset-val: 0 + vsatp: + rv32: + accessible: false + rv64: + accessible: false + description: VSXLEN-bit register which controls supervisor-mode address translation + and protection + address: 0x280 + priv_mode: S + reset-val: 0 + vxsat: + rv32: + accessible: false + rv64: + accessible: false + description: The vxsat register records the overflow saturation condition + of P and V instructions. + address: 9 + priv_mode: U + reset-val: 0 + mnscratch: + rv32: + accessible: false + rv64: + accessible: false + description: |- + The mnscratch CSR holds an MXLEN-bit read-write register which enables the NMI trap + handler to save and restore the context that was interrupted. + address: 0x740 + priv_mode: M + reset-val: 0 + mnepc: + rv32: + accessible: false + rv64: + accessible: false + description: |- + The mnepc CSR is an MXLEN-bit read-write register which on entry to the NMI trap handler holds + the PC of the instruction that took the interrupt. + + The low bit of mnepc (mnepc[0]) is always zero. On implementations that support only + IALIGN=32, the two low bits (mnepc[1:0]) are always zero. + + If an implementation allows IALIGN to be either 16 or 32 (by changing CSR misa, for example), + then, whenever IALIGN=32, bit mnepc[1] is masked on reads so that it appears to be 0. This + masking occurs also for the implicit read by the MRET instruction. Though masked, mnepc[1] + remains writable when IALIGN=32. + + mnepc is a WARL register that must be able to hold all valid virtual addresses. It need not be + capable of holding all possible invalid addresses. Prior to writing mnepc, implementations may + convert an invalid address into some other invalid address that mnepc is capable of holding. + address: 0x741 + priv_mode: M + reset-val: 0 + mncause: + rv32: + accessible: false + rv64: + accessible: false + description: |- + The mncause CSR holds the reason for the NMI, with bit MXLEN-1 set to 1, + and the NMI cause encoded in the least-significant bits or zero if NMI causes are not supported. + address: 0x742 + priv_mode: M + reset-val: 2147483648 + mnstatus: + rv32: + accessible: false + rv64: + accessible: false + description: |2- + + The mnstatus CSR holds a two-bit field, MNPP, which on entry to the trap handler holds the + privilege mode of the interrupted context, encoded in the same manner as mstatus.MPP. It also + + holds a one-bit field, MNPV, which on entry to the trap handler holds the virtualization mode of + the interrupted context, encoded in the same manner as mstatus.MPV. + mnstatus also holds the NMIE bit. When NMIE=1, nonmaskable interrupts are enabled. When + NMIE=0, all interrupts are disabled. + When NMIE=0, the hart behaves as though mstatus.MPRV were clear, regardless of the current + setting of mstatus.MPRV. + + Upon reset, NMIE contains the value 0. + address: 0x744 + priv_mode: M + reset-val: 0 diff --git a/riscof_work/spike_simple_platform_checked.yaml b/riscof_work/spike_simple_platform_checked.yaml new file mode 100644 index 000000000..83f665106 --- /dev/null +++ b/riscof_work/spike_simple_platform_checked.yaml @@ -0,0 +1,18 @@ +mtime: + implemented: true + address: 0xbff8 +mtimecmp: + implemented: true + address: 0x4000 +nmi: + label: nmi_vector +reset: + label: reset_vector +mtval_condition_writes: + implemented: false +scause_non_standard: + implemented: false +stval_condition_writes: + implemented: false +zicbo_cache_block_sz: + implemented: false diff --git a/riscof_work/src/ebreak.S/dut/DUT-Spike.signature b/riscof_work/src/ebreak.S/dut/DUT-Spike.signature new file mode 100644 index 000000000..6cd1e67e4 --- /dev/null +++ b/riscof_work/src/ebreak.S/dut/DUT-Spike.signature @@ -0,0 +1,8 @@ +6f5ca309 +00000000 +11111111 +000008d3 +00000003 +0000003c +0000003c +6f5ca309 diff --git a/riscof_work/src/ebreak.S/dut/my.elf b/riscof_work/src/ebreak.S/dut/my.elf new file mode 100755 index 0000000000000000000000000000000000000000..407f6ae114e2a4693db1a952c53193ddc24a2fb4 GIT binary patch literal 20976 zcmeI44Qw0b8ONW?*=<@%Nw}n+Au*iWb%;f29aN!dnzJN)NVN!!+rcOp_v|EY;}3k7 zH0}7f&dJ0iCbe8kOIsj}vQvV0c}WHg;MJM-}|s% zO3Rppgv9QZUO&(8dET#k?zz|Ji{txSmt8Li0y(9O#>pnV5yri3WO5_%g*}uXx>Uh-$rxCI0WhU57zt7Zlu0ZUo#2xDjw8;6}iWfExif0$*JOX3Ip9D3XLBFI3eku~A->t1qXS|CVuU9~nQ~F693?Nzxn8N45)r#K&aZwjTCJg#5ogCh2d`M;;LZ zYtE4IqYbd{5c0>*ko0%xBRhn^+E2*1{l~EH6!QQ6grqm2kL(lz-Dk;Ibr0;jg#7zw zNqP(V$Sxs}{FID4?uGqPA^*XrB)tuNBQ;5DJ8q^E$Ks^l1`i+6iar!tfUVKC7n1uNb-Ul!rZ(lbh<4pNcnP zZxNI`y=78WHAxLuQtySkrx3m7qlgENT|sV3t&~58JRi8$+>_+1o+M?Nw`zO=HAq{IkrKxG z76{iFhkirGL?hN*1=&J|_nWQR|5UH zAog3#_fo-tUENgOI4(CdNqy%A>p_V zkzyuy}sw*0z9`s9&a$c4k{ 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+ --trace-output + -l --inst-limit + -x --enable-zfinx + --enable-writable-fiom + --enable-svinval + --enable-zcb diff --git a/riscof_work/src/ebreak.S/ref/ref.disass b/riscof_work/src/ebreak.S/ref/ref.disass new file mode 100644 index 000000000..8009f5fc4 --- /dev/null +++ b/riscof_work/src/ebreak.S/ref/ref.disass @@ -0,0 +1,959 @@ + +ref.elf: file format elf32-littleriscv + + +Disassembly of section .text.init: + +80000000 : +80000000: 00002317 auipc t1,0x2 +80000004: 00030313 mv t1,t1 +80000008: 00000013 nop +8000000c: 00000013 nop +80000010: 00000013 nop +80000014: 00000013 nop +80000018: 00000013 nop +8000001c: 00000013 nop + +80000020 : +80000020: 34031473 csrrw s0,mscratch,t1 +80000024: 1c832823 sw s0,464(t1) # 800021d0 + +80000028 : +80000028: 00000393 li t2,0 +8000002c: 1a732c23 sw t2,440(t1) + +80000030 : +80000030: 30502473 csrr s0,mtvec +80000034: 1c832423 sw s0,456(t1) +80000038: 00347393 and t2,s0,3 +8000003c: 1b032483 lw s1,432(t1) +80000040: eac48493 add s1,s1,-340 +80000044: 0074e3b3 or t2,s1,t2 +80000048: 1c732023 sw t2,448(t1) +8000004c: 30539073 csrw mtvec,t2 +80000050: 30502573 csrr a0,mtvec +80000054: 08750863 beq a0,t2,800000e4 +80000058: 30541073 csrw mtvec,s0 +8000005c: 04040663 beqz s0,800000a8 +80000060: 1c832023 sw s0,448(t1) + +80000064 : +80000064: ffc47393 and t2,s0,-4 +80000068: 15438413 add s0,t2,340 + +8000006c : +8000006c: 0003a583 lw a1,0(t2) +80000070: 00b32023 sw a1,0(t1) +80000074: 0004a503 lw a0,0(s1) +80000078: 00a3a023 sw a0,0(t2) +8000007c: 0003a583 lw a1,0(t2) +80000080: 00a59a63 bne a1,a0,80000094 +80000084: 00438393 add t2,t2,4 +80000088: 00430313 add t1,t1,4 +8000008c: 00448493 add s1,s1,4 +80000090: fc741ee3 bne s0,t2,8000006c + +80000094 : +80000094: 00000013 nop +80000098: 34002373 csrr t1,mscratch +8000009c: 1a732423 sw t2,424(t1) +800000a0: 1a932823 sw s1,432(t1) +800000a4: 04740063 beq s0,t2,800000e4 + +800000a8 : +800000a8: 00000013 nop +800000ac: 00000013 nop +800000b0: 00000013 nop +800000b4: 00000013 nop +800000b8: 00000013 nop +800000bc: 00000013 nop +800000c0: 00000597 auipc a1,0x0 +800000c4: 1c458593 add a1,a1,452 # 80000284 +800000c8: 00000013 nop +800000cc: 00000013 nop +800000d0: 00000013 nop +800000d4: 00000013 nop +800000d8: 00000013 nop +800000dc: 00000013 nop +800000e0: 00058067 jr a1 + +800000e4 : +800000e4: 7d5c0837 lui a6,0x7d5c0 +800000e8: ddb80813 add a6,a6,-549 # 7d5bfddb +800000ec: 00785893 srl a7,a6,0x7 +800000f0: 01985793 srl a5,a6,0x19 +800000f4: 00f8e8b3 or a7,a7,a5 +800000f8: 0078d913 srl s2,a7,0x7 +800000fc: 0198d793 srl a5,a7,0x19 +80000100: 00f96933 or s2,s2,a5 +80000104: 00795993 srl s3,s2,0x7 +80000108: 01995793 srl a5,s2,0x19 +8000010c: 00f9e9b3 or s3,s3,a5 +80000110: 0079da13 srl s4,s3,0x7 +80000114: 0199d793 srl a5,s3,0x19 +80000118: 00fa6a33 or s4,s4,a5 +8000011c: 007a5a93 srl s5,s4,0x7 +80000120: 019a5793 srl a5,s4,0x19 +80000124: 00faeab3 or s5,s5,a5 +80000128: 007adb13 srl s6,s5,0x7 +8000012c: 019ad793 srl a5,s5,0x19 +80000130: 00fb6b33 or s6,s6,a5 +80000134: 007b5b93 srl s7,s6,0x7 +80000138: 019b5793 srl a5,s6,0x19 +8000013c: 00fbebb3 or s7,s7,a5 +80000140: 007bdc13 srl s8,s7,0x7 +80000144: 019bd793 srl a5,s7,0x19 +80000148: 00fc6c33 or s8,s8,a5 +8000014c: 007c5c93 srl s9,s8,0x7 +80000150: 019c5793 srl a5,s8,0x19 +80000154: 00fcecb3 or s9,s9,a5 +80000158: 007cdd13 srl s10,s9,0x7 +8000015c: 019cd793 srl a5,s9,0x19 +80000160: 00fd6d33 or s10,s10,a5 +80000164: 007d5d93 srl s11,s10,0x7 +80000168: 019d5793 srl a5,s10,0x19 +8000016c: 00fdedb3 or s11,s11,a5 +80000170: 007dde13 srl t3,s11,0x7 +80000174: 019dd793 srl a5,s11,0x19 +80000178: 00fe6e33 or t3,t3,a5 +8000017c: 007e5e93 srl t4,t3,0x7 +80000180: 019e5793 srl a5,t3,0x19 +80000184: 00feeeb3 or t4,t4,a5 +80000188: 007edf13 srl t5,t4,0x7 +8000018c: 019ed793 srl a5,t4,0x19 +80000190: 00ff6f33 or t5,t5,a5 +80000194: feedc0b7 lui ra,0xfeedc +80000198: ead08093 add ra,ra,-339 # feedbead <_end+0x7eed8d7d> +8000019c: 0070d113 srl sp,ra,0x7 +800001a0: 0190d793 srl a5,ra,0x19 +800001a4: 00f16133 or sp,sp,a5 +800001a8: 00715193 srl gp,sp,0x7 +800001ac: 01915793 srl a5,sp,0x19 +800001b0: 00f1e1b3 or gp,gp,a5 +800001b4: 0071d213 srl tp,gp,0x7 +800001b8: 0191d793 srl a5,gp,0x19 +800001bc: 00f26233 or tp,tp,a5 +800001c0: 00725293 srl t0,tp,0x7 +800001c4: 01925793 srl a5,tp,0x19 +800001c8: 00f2e2b3 or t0,t0,a5 +800001cc: 0072d313 srl t1,t0,0x7 +800001d0: 0192d793 srl a5,t0,0x19 +800001d4: 00f36333 or t1,t1,a5 +800001d8: 00735393 srl t2,t1,0x7 +800001dc: 01935793 srl a5,t1,0x19 +800001e0: 00f3e3b3 or t2,t2,a5 +800001e4: 0073d413 srl s0,t2,0x7 +800001e8: 0193d793 srl a5,t2,0x19 +800001ec: 00f46433 or s0,s0,a5 +800001f0: 00745493 srl s1,s0,0x7 +800001f4: 01945793 srl a5,s0,0x19 +800001f8: 00f4e4b3 or s1,s1,a5 +800001fc: 0074d513 srl a0,s1,0x7 +80000200: 0194d793 srl a5,s1,0x19 +80000204: 00f56533 or a0,a0,a5 +80000208: 00755593 srl a1,a0,0x7 +8000020c: 01955793 srl a5,a0,0x19 +80000210: 00f5e5b3 or a1,a1,a5 +80000214: 0075d613 srl a2,a1,0x7 +80000218: 0195d793 srl a5,a1,0x19 +8000021c: 00f66633 or a2,a2,a5 +80000220: 00765693 srl a3,a2,0x7 +80000224: 01965793 srl a5,a2,0x19 +80000228: 00f6e6b3 or a3,a3,a5 + +8000022c : +8000022c: 00000013 nop +80000230: 00000013 nop +80000234: 00000013 nop +80000238: 00000013 nop +8000023c: 00000013 nop +80000240: 00003097 auipc ra,0x3 +80000244: ed408093 add ra,ra,-300 # 80003114 +80000248: 00000013 nop +8000024c: 00000013 nop +80000250: 00000013 nop +80000254: 00000013 nop +80000258: 00000013 nop +8000025c: 00000013 nop +80000260: 11111137 lui sp,0x11111 +80000264: 11110113 add sp,sp,273 # 11111111 +80000268: 00100073 ebreak +8000026c: 00000013 nop +80000270: 00000013 nop +80000274: 0000a023 sw zero,0(ra) +80000278: 0020a223 sw sp,4(ra) + +8000027c : +8000027c: 00000113 li sp,0 +80000280: 00000073 ecall + +80000284 : +80000284: 34002373 csrr t1,mscratch + +80000288 : +80000288: 1b832383 lw t2,440(t1) + +8000028c : +8000028c: 1d032503 lw a0,464(t1) +80000290: 34051073 csrw mscratch,a0 + +80000294 : +80000294: 1c832483 lw s1,456(t1) +80000298: 305493f3 csrrw t2,mtvec,s1 +8000029c: ffc4f493 and s1,s1,-4 +800002a0: ffc3f393 and t2,t2,-4 +800002a4: 02749063 bne s1,t2,800002c4 + +800002a8 : +800002a8: 00030493 mv s1,t1 +800002ac: 1a832403 lw s0,424(t1) + +800002b0 : +800002b0: 0004a583 lw a1,0(s1) +800002b4: 00b3a023 sw a1,0(t2) +800002b8: 00438393 add t2,t2,4 +800002bc: 00448493 add s1,s1,4 +800002c0: fe83c8e3 blt t2,s0,800002b0 + +800002c4 : +800002c4: 6880006f j 8000094c + +800002c8 : +800002c8: 17812483 lw s1,376(sp) +800002cc: 18012303 lw t1,384(sp) +800002d0: 00930333 add t1,t1,s1 +800002d4: bad0e337 lui t1,0xbad0e +800002d8: ad030313 add t1,t1,-1328 # bad0dad0 <_end+0x3ad0a9a0> +800002dc: fe64ae23 sw t1,-4(s1) +800002e0: 66c0006f j 8000094c +800002e4: 00000013 nop +800002e8: 00000013 nop +800002ec: 00000013 nop +800002f0: 00000013 nop +800002f4: 00000013 nop +800002f8: 00000013 nop +800002fc: 00000013 nop + +80000300 : +80000300: 0800006f j 80000380 +80000304: 0880006f j 8000038c +80000308: 0900006f j 80000398 +8000030c: 0980006f j 800003a4 +80000310: 0a00006f j 800003b0 +80000314: 0a80006f j 800003bc +80000318: 0b00006f j 800003c8 +8000031c: 0b80006f j 800003d4 +80000320: 0c00006f j 800003e0 +80000324: 0c80006f j 800003ec +80000328: 0d00006f j 800003f8 +8000032c: 0d80006f j 80000404 +80000330: 0e00006f j 80000410 +80000334: 0e80006f j 8000041c +80000338: 0f00006f j 80000428 +8000033c: 0f80006f j 80000434 +80000340: 1600006f j 800004a0 +80000344: 15c0006f j 800004a0 +80000348: 1580006f j 800004a0 +8000034c: 1540006f j 800004a0 +80000350: 1500006f j 800004a0 +80000354: 14c0006f j 800004a0 +80000358: 1480006f j 800004a0 +8000035c: 1440006f j 800004a0 +80000360: 1400006f j 800004a0 +80000364: 13c0006f j 800004a0 +80000368: 1380006f j 800004a0 +8000036c: 1340006f j 800004a0 +80000370: 1300006f j 800004a0 +80000374: 12c0006f j 800004a0 +80000378: 1280006f j 800004a0 +8000037c: 1240006f j 800004a0 + +80000380 : +80000380: 34011173 csrrw sp,mscratch,sp +80000384: 1eb12823 sw a1,496(sp) +80000388: 0b8005ef jal a1,80000440 +8000038c: 34011173 csrrw sp,mscratch,sp +80000390: 1eb12823 sw a1,496(sp) +80000394: 0ac005ef jal a1,80000440 +80000398: 34011173 csrrw sp,mscratch,sp +8000039c: 1eb12823 sw a1,496(sp) +800003a0: 0a0005ef jal a1,80000440 +800003a4: 34011173 csrrw sp,mscratch,sp +800003a8: 1eb12823 sw a1,496(sp) +800003ac: 094005ef jal a1,80000440 +800003b0: 34011173 csrrw sp,mscratch,sp +800003b4: 1eb12823 sw a1,496(sp) +800003b8: 088005ef jal a1,80000440 +800003bc: 34011173 csrrw sp,mscratch,sp +800003c0: 1eb12823 sw a1,496(sp) +800003c4: 07c005ef jal a1,80000440 +800003c8: 34011173 csrrw sp,mscratch,sp +800003cc: 1eb12823 sw a1,496(sp) +800003d0: 070005ef jal a1,80000440 +800003d4: 34011173 csrrw sp,mscratch,sp +800003d8: 1eb12823 sw a1,496(sp) +800003dc: 064005ef jal a1,80000440 +800003e0: 34011173 csrrw sp,mscratch,sp +800003e4: 1eb12823 sw a1,496(sp) +800003e8: 058005ef jal a1,80000440 +800003ec: 34011173 csrrw sp,mscratch,sp +800003f0: 1eb12823 sw a1,496(sp) +800003f4: 04c005ef jal a1,80000440 +800003f8: 34011173 csrrw sp,mscratch,sp +800003fc: 1eb12823 sw a1,496(sp) +80000400: 040005ef jal a1,80000440 +80000404: 34011173 csrrw sp,mscratch,sp +80000408: 1eb12823 sw a1,496(sp) +8000040c: 034005ef jal a1,80000440 +80000410: 34011173 csrrw sp,mscratch,sp +80000414: 1eb12823 sw a1,496(sp) +80000418: 028005ef jal a1,80000440 +8000041c: 34011173 csrrw sp,mscratch,sp +80000420: 1eb12823 sw a1,496(sp) +80000424: 01c005ef jal a1,80000440 +80000428: 34011173 csrrw sp,mscratch,sp +8000042c: 1eb12823 sw a1,496(sp) +80000430: 010005ef jal a1,80000440 +80000434: 34011173 csrrw sp,mscratch,sp +80000438: 1eb12823 sw a1,496(sp) +8000043c: 004005ef jal a1,80000440 + +80000440 : +80000440: 1ea12623 sw a0,492(sp) +80000444: 34011573 csrrw a0,mscratch,sp +80000448: 1ea12a23 sw a0,500(sp) +8000044c: 1b012503 lw a0,432(sp) +80000450: 00050067 jr a0 + +80000454 : +80000454: 1e912423 sw s1,488(sp) +80000458: 1e812223 sw s0,484(sp) +8000045c: 1e712023 sw t2,480(sp) +80000460: 1c612e23 sw t1,476(sp) + +80000464 : +80000464: 34202573 csrr a0,mcause +80000468: 800014b7 lui s1,0x80001 +8000046c: ffc48493 add s1,s1,-4 # 80000ffc +80000470: 00a4f4b3 and s1,s1,a0 +80000474: ff848493 add s1,s1,-8 +80000478: 00049663 bnez s1,80000484 +8000047c: 1f412383 lw t2,500(sp) +80000480: 48038663 beqz t2,8000090c + +80000484 : +80000484: 01000393 li t2,16 +80000488: 02055e63 bgez a0,800004c4 + +8000048c : +8000048c: 00151413 sll s0,a0,0x1 +80000490: ff240413 add s0,s0,-14 +80000494: 04045063 bgez s0,800004d4 +80000498: 00c00393 li t2,12 +8000049c: 0380006f j 800004d4 + +800004a0 : +800004a0: 00000317 auipc t1,0x0 +800004a4: e2430313 add t1,t1,-476 # 800002c4 +800004a8: 00000013 nop +800004ac: 00000013 nop +800004b0: 00000013 nop +800004b4: 00000013 nop +800004b8: 00000013 nop +800004bc: 00000013 nop +800004c0: 00030067 jr t1 + +800004c4 : +800004c4: 30102373 csrr t1,misa +800004c8: 01831313 sll t1,t1,0x18 +800004cc: 00035463 bgez t1,800004d4 +800004d0: 01800393 li t2,24 + +800004d4 : +800004d4: 19812303 lw t1,408(sp) +800004d8: 007304b3 add s1,t1,t2 +800004dc: 18912c23 sw s1,408(sp) +800004e0: 17812403 lw s0,376(sp) +800004e4: 40830333 sub t1,t1,s0 +800004e8: 17812403 lw s0,376(sp) +800004ec: 00830333 add t1,t1,s0 +800004f0: 1c012403 lw s0,448(sp) + +800004f4 : +800004f4: 408585b3 sub a1,a1,s0 +800004f8: 00459593 sll a1,a1,0x4 +800004fc: 0075e5b3 or a1,a1,t2 +80000500: 00358593 add a1,a1,3 +80000504: 00b32023 sw a1,0(t1) + +80000508 : +80000508: 00a32223 sw a0,4(t1) +8000050c: 14054c63 bltz a0,80000664 + +80000510 : +80000510: 300025f3 csrr a1,mstatus +80000514: 00e59413 sll s0,a1,0xe +80000518: 00045463 bgez s0,80000520 +8000051c: 39012583 lw a1,912(sp) +80000520: 00b5d493 srl s1,a1,0xb +80000524: 0034f493 and s1,s1,3 +80000528: 00148493 add s1,s1,1 +8000052c: 0044f493 and s1,s1,4 +80000530: 05d00593 li a1,93 +80000534: 0095d5b3 srl a1,a1,s1 +80000538: 0015f593 and a1,a1,1 +8000053c: f60582e3 beqz a1,800004a0 +80000540: 1f800593 li a1,504 +80000544: 0014f413 and s0,s1,1 +80000548: 008595b3 sll a1,a1,s0 +8000054c: 01d49413 sll s0,s1,0x1d +80000550: 41f45413 sra s0,s0,0x1f +80000554: fff44413 not s0,s0 +80000558: 0085f4b3 and s1,a1,s0 + +8000055c : +8000055c: 002484b3 add s1,s1,sp +80000560: 341023f3 csrr t2,mepc +80000564: 1884a403 lw s0,392(s1) +80000568: 1904a583 lw a1,400(s1) +8000056c: 008585b3 add a1,a1,s0 +80000570: 00b3f463 bgeu t2,a1,80000578 +80000574: 0283f663 bgeu t2,s0,800005a0 + +80000578 : +80000578: 1584a403 lw s0,344(s1) +8000057c: 1604a583 lw a1,352(s1) +80000580: 008585b3 add a1,a1,s0 +80000584: 00b3f463 bgeu t2,a1,8000058c +80000588: 0083fc63 bgeu t2,s0,800005a0 + +8000058c : +8000058c: 1684a403 lw s0,360(s1) +80000590: 1704a583 lw a1,368(s1) +80000594: 008585b3 add a1,a1,s0 +80000598: ceb3f6e3 bgeu t2,a1,80000284 +8000059c: ce83e4e3 bltu t2,s0,80000284 + +800005a0 : +800005a0: 40838433 sub s0,t2,s0 + +800005a4 : +800005a4: 00832423 sw s0,8(t1) + +800005a8 : +800005a8: ffc3f593 and a1,t2,-4 +800005ac: 00858593 add a1,a1,8 +800005b0: 34159073 csrw mepc,a1 +800005b4: 343023f3 csrr t2,mtval + +800005b8 : +800005b8: 00f57513 and a0,a0,15 +800005bc: 0000b437 lui s0,0xb +800005c0: 0fb40413 add s0,s0,251 # b0fb +800005c4: 00a45433 srl s0,s0,a0 +800005c8: 01f41413 sll s0,s0,0x1f +800005cc: 04045c63 bgez s0,80000624 + +800005d0 : +800005d0: 1884a403 lw s0,392(s1) +800005d4: 1904a583 lw a1,400(s1) +800005d8: 008585b3 add a1,a1,s0 +800005dc: 00b3f463 bgeu t2,a1,800005e4 +800005e0: 0483f063 bgeu t2,s0,80000620 + +800005e4 : +800005e4: 1784a403 lw s0,376(s1) +800005e8: 1804a583 lw a1,384(s1) +800005ec: 008585b3 add a1,a1,s0 +800005f0: 00b3f463 bgeu t2,a1,800005f8 +800005f4: 0283f663 bgeu t2,s0,80000620 + +800005f8 : +800005f8: 1584a403 lw s0,344(s1) +800005fc: 1604a583 lw a1,352(s1) +80000600: 008585b3 add a1,a1,s0 +80000604: 00b3f463 bgeu t2,a1,8000060c +80000608: 0083fc63 bgeu t2,s0,80000620 + +8000060c : +8000060c: 1684a403 lw s0,360(s1) +80000610: 1704a583 lw a1,368(s1) +80000614: 008585b3 add a1,a1,s0 +80000618: c6b3f6e3 bgeu t2,a1,80000284 +8000061c: c683e4e3 bltu t2,s0,80000284 + +80000620 : +80000620: 40838433 sub s0,t2,s0 + +80000624 : +80000624: 00832623 sw s0,12(t1) + +80000628 : +80000628: 19812483 lw s1,408(sp) +8000062c: 17812383 lw t2,376(sp) +80000630: 18012303 lw t1,384(sp) +80000634: 00730333 add t1,t1,t2 +80000638: c49366e3 bltu t1,s1,80000284 +8000063c: 10000393 li t2,256 +80000640: 0400006f j 80000680 + +80000644 : +80000644: 1dc12303 lw t1,476(sp) +80000648: 1e012383 lw t2,480(sp) +8000064c: 1e412403 lw s0,484(sp) +80000650: 1e812483 lw s1,488(sp) +80000654: 1ec12503 lw a0,492(sp) +80000658: 1f012583 lw a1,496(sp) +8000065c: 1f412103 lw sp,500(sp) +80000660: 30200073 mret + +80000664 : +80000664: 00100413 li s0,1 +80000668: 00f57393 and t2,a0,15 +8000066c: 00741433 sll s0,s0,t2 +80000670: 304434f3 csrrc s1,mie,s0 +80000674: 344434f3 csrrc s1,mip,s0 + +80000678 : +80000678: 00932423 sw s1,8(t1) +8000067c: 00000393 li t2,0 + +80000680 : +80000680: 00000417 auipc s0,0x0 +80000684: 03c40413 add s0,s0,60 # 800006bc +80000688: 00740433 add s0,s0,t2 +8000068c: 00351393 sll t2,a0,0x3 +80000690: 00740433 add s0,s0,t2 +80000694: ff847413 and s0,s0,-8 +80000698: 00042403 lw s0,0(s0) + +8000069c : +8000069c: c20406e3 beqz s0,800002c8 +800006a0: 01f41393 sll t2,s0,0x1f +800006a4: 0003d863 bgez t2,800006b4 +800006a8: 00145413 srl s0,s0,0x1 +800006ac: f8850ce3 beq a0,s0,80000644 +800006b0: c19ff06f j 800002c8 + +800006b4 : +800006b4: 00040067 jr s0 + +800006b8 : + ... +800006c0: 0001 .2byte 0x1 +800006c2: 0000 .2byte 0x0 +800006c4: 0000 .2byte 0x0 +800006c6: 0000 .2byte 0x0 +800006c8: 0001 .2byte 0x1 +800006ca: 0000 .2byte 0x0 +800006cc: 0000 .2byte 0x0 +800006ce: 0000 .2byte 0x0 +800006d0: 08b8 .2byte 0x8b8 +800006d2: 8000 .2byte 0x8000 + ... +800006e0: 0001 .2byte 0x1 +800006e2: 0000 .2byte 0x0 +800006e4: 0000 .2byte 0x0 +800006e6: 0000 .2byte 0x0 +800006e8: 0001 .2byte 0x1 +800006ea: 0000 .2byte 0x0 +800006ec: 0000 .2byte 0x0 +800006ee: 0000 .2byte 0x0 +800006f0: 08c0 .2byte 0x8c0 +800006f2: 8000 .2byte 0x8000 + ... +80000700: 0001 .2byte 0x1 +80000702: 0000 .2byte 0x0 +80000704: 0000 .2byte 0x0 +80000706: 0000 .2byte 0x0 +80000708: 0001 .2byte 0x1 +8000070a: 0000 .2byte 0x0 +8000070c: 0000 .2byte 0x0 +8000070e: 0000 .2byte 0x0 +80000710: 08c8 .2byte 0x8c8 +80000712: 8000 .2byte 0x8000 +80000714: 0000 .2byte 0x0 +80000716: 0000 .2byte 0x0 +80000718: 0001 .2byte 0x1 +8000071a: 0000 .2byte 0x0 +8000071c: 0000 .2byte 0x0 +8000071e: 0000 .2byte 0x0 +80000720: 0001 .2byte 0x1 +80000722: 0000 .2byte 0x0 +80000724: 0000 .2byte 0x0 +80000726: 0000 .2byte 0x0 +80000728: 0001 .2byte 0x1 +8000072a: 0000 .2byte 0x0 +8000072c: 0000 .2byte 0x0 +8000072e: 0000 .2byte 0x0 +80000730: 0001 .2byte 0x1 + ... + +800007b8 : +800007b8: 0001 .2byte 0x1 +800007ba: 0000 .2byte 0x0 +800007bc: 0000 .2byte 0x0 +800007be: 0000 .2byte 0x0 +800007c0: 00000003 lb zero,0(zero) # 0 +800007c4: 0000 .2byte 0x0 +800007c6: 0000 .2byte 0x0 +800007c8: 0005 .2byte 0x5 +800007ca: 0000 .2byte 0x0 +800007cc: 0000 .2byte 0x0 +800007ce: 0000 .2byte 0x0 +800007d0: 00000007 .4byte 0x7 +800007d4: 0000 .2byte 0x0 +800007d6: 0000 .2byte 0x0 +800007d8: 0009 .2byte 0x9 +800007da: 0000 .2byte 0x0 +800007dc: 0000 .2byte 0x0 +800007de: 0000 .2byte 0x0 +800007e0: 0000000b .4byte 0xb +800007e4: 0000 .2byte 0x0 +800007e6: 0000 .2byte 0x0 +800007e8: 000d .2byte 0xd +800007ea: 0000 .2byte 0x0 +800007ec: 0000 .2byte 0x0 +800007ee: 0000 .2byte 0x0 +800007f0: 0000000f fence unknown,unknown +800007f4: 0000 .2byte 0x0 +800007f6: 0000 .2byte 0x0 +800007f8: 0011 .2byte 0x11 +800007fa: 0000 .2byte 0x0 +800007fc: 0000 .2byte 0x0 +800007fe: 0000 .2byte 0x0 +80000800: 00000013 nop +80000804: 0000 .2byte 0x0 +80000806: 0000 .2byte 0x0 +80000808: 0015 .2byte 0x15 +8000080a: 0000 .2byte 0x0 +8000080c: 0000 .2byte 0x0 +8000080e: 0000 .2byte 0x0 +80000810: 00000017 auipc zero,0x0 +80000814: 0000 .2byte 0x0 +80000816: 0000 .2byte 0x0 +80000818: 0019 .2byte 0x19 +8000081a: 0000 .2byte 0x0 +8000081c: 0000 .2byte 0x0 +8000081e: 0000 .2byte 0x0 +80000820: 0000001b .4byte 0x1b +80000824: 0000 .2byte 0x0 +80000826: 0000 .2byte 0x0 +80000828: 001d .2byte 0x1d +8000082a: 0000 .2byte 0x0 +8000082c: 0000 .2byte 0x0 +8000082e: 0000 .2byte 0x0 +80000830: 001f 0000 0000 .byte 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00 + ... + +800008b8 : +800008b8: 9cdff06f j 80000284 +800008bc: d89ff06f j 80000644 + +800008c0 : +800008c0: 9c5ff06f j 80000284 +800008c4: d81ff06f j 80000644 + +800008c8 : +800008c8: 9bdff06f j 80000284 +800008cc: 00832623 sw s0,12(t1) +800008d0: d75ff06f j 80000644 + +800008d4 : +800008d4: 9b1ff06f j 80000284 +800008d8: d6dff06f j 80000644 + +800008dc : +800008dc: 9a9ff06f j 80000284 +800008e0: d65ff06f j 80000644 + +800008e4 : +800008e4: 9a1ff06f j 80000284 +800008e8: 00832623 sw s0,12(t1) +800008ec: d59ff06f j 80000644 + +800008f0 : +800008f0: 995ff06f j 80000284 +800008f4: d51ff06f j 80000644 + +800008f8 : +800008f8: 98dff06f j 80000284 +800008fc: d49ff06f j 80000644 + +80000900 : +80000900: 985ff06f j 80000284 +80000904: 00832623 sw s0,12(t1) +80000908: d3dff06f j 80000644 + +8000090c : +8000090c: ff550493 add s1,a0,-11 +80000910: 00048c63 beqz s1,80000928 +80000914: 35012583 lw a1,848(sp) +80000918: 0003d463 bgez t2,80000920 + +8000091c : +8000091c: 54812583 lw a1,1352(sp) + +80000920 : +80000920: 15812483 lw s1,344(sp) +80000924: 40b484b3 sub s1,s1,a1 + +80000928 : +80000928: 341023f3 csrr t2,mepc +8000092c: 009383b3 add t2,t2,s1 +80000930: 1dc12303 lw t1,476(sp) +80000934: 1e412403 lw s0,484(sp) +80000938: 1e812483 lw s1,488(sp) +8000093c: 1ec12503 lw a0,492(sp) +80000940: 1f012583 lw a1,496(sp) +80000944: 1f412103 lw sp,500(sp) +80000948: 00438067 jr 4(t2) + +8000094c : +8000094c: 00100093 li ra,1 +80000950: 00000397 auipc t2,0x0 +80000954: 6a13a823 sw ra,1712(t2) # 80001000 +80000958: ff9ff06f j 80000950 +8000095c: 00100093 li ra,1 +80000960: 00000397 auipc t2,0x0 +80000964: 6a13a023 sw ra,1696(t2) # 80001000 +80000968: ff9ff06f j 80000960 + ... + +Disassembly of section .tohost: + +80001000 : + ... + +80001100 : + ... + +Disassembly of section .data: + +80002000 : +80002000: 0000006f j 80002000 +80002004: 0000006f j 80002004 +80002008: 0000006f j 80002008 +8000200c: 0000006f j 8000200c +80002010: 0000006f j 80002010 +80002014: 0000006f j 80002014 +80002018: 0000006f j 80002018 +8000201c: 0000006f j 8000201c +80002020: 0000006f j 80002020 +80002024: 0000006f j 80002024 +80002028: 0000006f j 80002028 +8000202c: 0000006f j 8000202c +80002030: 0000006f j 80002030 +80002034: 0000006f j 80002034 +80002038: 0000006f j 80002038 +8000203c: 0000006f j 8000203c +80002040: 0000006f j 80002040 +80002044: 0000006f j 80002044 +80002048: 0000006f j 80002048 +8000204c: 0000006f j 8000204c +80002050: 0000006f j 80002050 +80002054: 0000006f j 80002054 +80002058: 0000006f j 80002058 +8000205c: 0000006f j 8000205c +80002060: 0000006f j 80002060 +80002064: 0000006f j 80002064 +80002068: 0000006f j 80002068 +8000206c: 0000006f j 8000206c +80002070: 0000006f j 80002070 +80002074: 0000006f j 80002074 +80002078: 0000006f j 80002078 +8000207c: 0000006f j 8000207c +80002080: 0000006f j 80002080 +80002084: 0000006f j 80002084 +80002088: 0000006f j 80002088 +8000208c: 0000006f j 8000208c +80002090: 0000006f j 80002090 +80002094: 0000006f j 80002094 +80002098: 0000006f j 80002098 +8000209c: 0000006f j 8000209c +800020a0: 0000006f j 800020a0 +800020a4: 0000006f j 800020a4 +800020a8: 0000006f j 800020a8 +800020ac: 0000006f j 800020ac +800020b0: 0000006f j 800020b0 +800020b4: 0000006f j 800020b4 +800020b8: 0000006f j 800020b8 +800020bc: 0000006f j 800020bc +800020c0: 0000006f j 800020c0 +800020c4: 0000006f j 800020c4 +800020c8: 0000006f j 800020c8 +800020cc: 0000006f j 800020cc +800020d0: 0000006f j 800020d0 +800020d4: 0000006f j 800020d4 +800020d8: 0000006f j 800020d8 +800020dc: 0000006f j 800020dc +800020e0: 0000006f j 800020e0 +800020e4: 0000006f j 800020e4 +800020e8: 0000006f j 800020e8 +800020ec: 0000006f j 800020ec +800020f0: 0000006f j 800020f0 +800020f4: 0000006f j 800020f4 +800020f8: 0000006f j 800020f8 +800020fc: 0000006f j 800020fc +80002100: 0000006f j 80002100 +80002104: 0000006f j 80002104 +80002108: 0000006f j 80002108 +8000210c: 0000006f j 8000210c +80002110: 0000006f j 80002110 +80002114: 0000006f j 80002114 +80002118: 0000006f j 80002118 +8000211c: 0000006f j 8000211c +80002120: 0000006f j 80002120 +80002124: 0000006f j 80002124 +80002128: 0000006f j 80002128 +8000212c: 0000006f j 8000212c +80002130: 0000006f j 80002130 +80002134: 0000006f j 80002134 +80002138: 0000006f j 80002138 +8000213c: 0000006f j 8000213c +80002140: 0000006f j 80002140 +80002144: 0000006f j 80002144 +80002148: 0000006f j 80002148 +8000214c: 0000006f j 8000214c +80002150: 0000006f j 80002150 +80002154: 0000006f j 80002154 + +80002158 : +80002158: 022c .2byte 0x22c +8000215a: 8000 .2byte 0x8000 +8000215c: 0000 .2byte 0x0 + ... + +80002160 : +80002160: 0050 .2byte 0x50 +80002162: 0000 .2byte 0x0 +80002164: 0000 .2byte 0x0 + ... + +80002168 : +80002168: 21f8 .2byte 0x21f8 +8000216a: 8000 .2byte 0x8000 +8000216c: 0000 .2byte 0x0 + ... + +80002170 : +80002170: 0e08 .2byte 0xe08 +80002172: 0000 .2byte 0x0 +80002174: 0000 .2byte 0x0 + ... + +80002178 : +80002178: 3110 .2byte 0x3110 +8000217a: 8000 .2byte 0x8000 +8000217c: 0000 .2byte 0x0 + ... + +80002180 : +80002180: 0020 .2byte 0x20 +80002182: 0000 .2byte 0x0 +80002184: 0000 .2byte 0x0 + ... + +80002188 : +80002188: 022c .2byte 0x22c +8000218a: 8000 .2byte 0x8000 +8000218c: 0000 .2byte 0x0 + ... + +80002190 : +80002190: 0050 .2byte 0x50 +80002192: 0000 .2byte 0x0 +80002194: 0000 .2byte 0x0 + ... + +80002198 : +80002198: 311c .2byte 0x311c +8000219a: 8000 .2byte 0x8000 +8000219c: 0000 .2byte 0x0 + ... + +800021a0 : + ... + +800021a8 : + ... + +800021b0 : +800021b0: 0454 .2byte 0x454 +800021b2: 8000 .2byte 0x8000 +800021b4: 0000 .2byte 0x0 + ... + +800021b8 : + ... + +800021c0 : + ... + +800021c8 : + ... + +800021d0 : + ... + +800021d8 : +800021d8: deadbeef jal t4,7ffdd7c2 +800021dc: deadbeef jal t4,7ffdd7c6 +800021e0: deadbeef jal t4,7ffdd7ca +800021e4: deadbeef jal t4,7ffdd7ce +800021e8: deadbeef jal t4,7ffdd7d2 +800021ec: deadbeef jal t4,7ffdd7d6 +800021f0: deadbeef jal t4,7ffdd7da +800021f4: deadbeef jal t4,7ffdd7de + +800021f8 : + ... + +80003000 : +80003000: 0080 .2byte 0x80 + ... + +80003100 : +80003100: 0004 .2byte 0x4 + ... + +80003110 : +80003110: a309 .2byte 0xa309 +80003112: 6f5c .2byte 0x6f5c + +80003114 : +80003114: deadbeef jal t4,7ffde6fe +80003118: deadbeef jal t4,7ffde702 + +8000311c : +8000311c: deadbeef jal t4,7ffde706 +80003120: deadbeef jal t4,7ffde70a +80003124: deadbeef jal t4,7ffde70e +80003128: deadbeef jal t4,7ffde712 + +8000312c : +8000312c: a309 .2byte 0xa309 +8000312e: 6f5c .2byte 0x6f5c + +Disassembly of section .riscv.attributes: + +00000000 <.riscv.attributes>: + 0: 2641 .2byte 0x2641 + 2: 0000 .2byte 0x0 + 4: 7200 .2byte 0x7200 + 6: 7369 .2byte 0x7369 + 8: 01007663 bgeu zero,a6,14 + c: 001c .2byte 0x1c + e: 0000 .2byte 0x0 + 10: 7205 .2byte 0x7205 + 12: 3376 .2byte 0x3376 + 14: 6932 .2byte 0x6932 + 16: 7032 .2byte 0x7032 + 18: 5f31 .2byte 0x5f31 + 1a: 697a .2byte 0x697a + 1c: 32727363 bgeu tp,t2,342 + 20: 3070 .2byte 0x3070 + 22: 0800 .2byte 0x800 + 24: 0a01 .2byte 0xa01 + 26: 0b Address 0x26 is out of bounds. + diff --git a/riscof_work/src/ebreak.S/ref/ref.elf b/riscof_work/src/ebreak.S/ref/ref.elf new file mode 100755 index 0000000000000000000000000000000000000000..ea816bec326dad515b7736a858de6ed7ba417bd9 GIT binary patch literal 20988 zcmeI44Qw0b8ONW?Ic-`BBwW(ZkQ&bII>aKk4y({K%~=vYq*{c=?Ftl(dv+7I@dv(3 zns$6#=VStjNiEmX(iRA#Y!wnykvmaM3av|l1K}vf+j;! z#^31lAo`ZAdLUU}vwx*&)bXnKPa$HpoS9%Z{a#bo!Mgt{B338aekR=FM!=1L8v!>0 zZUo#2xDjw8;6}iWfExif0&WD{2z+%Bm?0BMqDT^kyiirE#RhpnuGYYZe)(E;w(4v3 z%RaE$Kslc{$LJkAo*&jo_Nuk&rZ&Giuhp+qbXBO8VZSoT1^ZSZf9y0#Z$Tg0 zDg;)aA!B(r?2iih56@gMKeqW1e?55OV)0*GRaGSkRaGh;^f+zge&o{6y(Hm5kZPan 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+/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/ecall.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/ecall.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - ecall + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/ecall.S +/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-beq-01.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - misalign-beq + - misalign-beq + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S +/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bge-01.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bge-01.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - misalign-bge + - misalign-bge + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bge-01.S +/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bgeu-01.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bgeu-01.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - misalign-bgeu + - misalign-bgeu + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bgeu-01.S +/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-blt-01.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-blt-01.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - misalign-blt + - misalign-blt + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-blt-01.S +/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bltu-01.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bltu-01.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - misalign-bltu + - misalign-bltu + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bltu-01.S +/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bne-01.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bne-01.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - misalign-bne + - misalign-bne + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bne-01.S +/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-jal-01.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-jal-01.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - misalign-jal + - misalign-jal + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-jal-01.S +/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lh-01.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-lh-01.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - misalign-lh + - misalign-lh + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lh-01.S +/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lhu-01.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-lhu-01.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - misalign-lhu + - misalign-lhu + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lhu-01.S +/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lw-01.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-lw-01.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - misalign-lw + - misalign-lw + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lw-01.S +/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sh-01.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-sh-01.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - misalign-sh + - misalign-sh + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sh-01.S +/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sw-01.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-sw-01.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - misalign-sw + - misalign-sw + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sw-01.S +/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign2-jalr-01.S: + commit_id: '-' + work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign2-jalr-01.S + macros: + - rvtest_mtrap_routine=True + - TEST_CASE_1=True + - XLEN=32 + isa: RV32I_Zicsr + coverage_labels: + - misalign2-jalr + - misalign2-jalr + test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign2-jalr-01.S diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h index f754d65e6..6d573c113 100644 --- a/riscv-test-suite/env/arch_test.h +++ b/riscv-test-suite/env/arch_test.h @@ -1,8 +1,16 @@ +// ***DELETEME** note to self +// this version adds instret counts to the signature +// this version modifies the LA macro to skip generation if rd=x0 (or X0) +// this version detects ECALL cause even in CLIC mode + // ----------- // Copyright (c) 2020-2023. RISC-V International. All rights reserved. // SPDX-License-Identifier: BSD-3-Clause // ----------- + //******************************************************************************** + //********** FIXME: these comments are now completely out of order**************** + //******************************************************************************** // This file is divided into the following sections: // RV Arch Test Constants @@ -37,15 +45,15 @@ // (Data section) - align to 4K boundary // RVTEST_DATA_BEGIN //************************************** -//*****(Ld/St test data is here)******** +//*****(trap handler data is here)****** //************************************** // //************************************** -//*****(trap handler data is here)****** +//*****(Ld/St test data is here)******** //************************************** // -// rvtest_trap_sig: [global trap signature start (shared by all modes) inited to mtrap_sigptr] **FIXME: needs VA=PA -// RVTEST_TRAP_SAVEAREA [handler sv area(m, ms, or msv) temp reg save, CSRs, tramp table, ptrs] +// rvtest_trap_sig: [ptr toglobal trap signature start (shared by all modes) inited to mtrap_sigptr] **FIXME: needs VA=PA +// RVTEST_TRAP_SAVEAREA [handler sv area(m, ms, or msv) temp reg save, CSRs, tramp table, ptrs] // rvtest_data_begin: [input data (shared by all modes)] // RVTEST_DATA_END // rvtest_data_end: @@ -203,12 +211,14 @@ #define GOTO_M_OP ecall #endif -//this is a valid global pte entry with all permissions. IF at the root entry, it forms an identity map. -#define RVTEST_PTE_IDENT_MAP .fill 4096/REGWIDTH, REGWIDTH, (PTE_G | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V) -#define RVTEST_PTE_NOACC_MAP .fill 4096/REGWIDTH, REGWIDTH, (PTE_G | PTE_U ) +//this is pte entry permision bits for all permissions. +#define RVTEST_ALLPERMS ( PTE_G | PTE_U | PTE_X | PTE_W | PTE_R | PTE_V) +//this is pte entry permision bits for no permissions. +#define RVTEST_NOACC ( PTE_G | PTE_U ) //_ADDR_SZ_ is a global variable extracted from YAML; set a default if it isn't defined -// This should be the MAX(phy_addr_size, VADDR_SZ) from YAML, where VADDR_SZ is derived from SATP.mode at reset +// This should be the MAX(phy_addr_size, VADDR_SZ) from YAML, +// where VADDR_SZ is derived from SATP.mode at reset #ifndef _ADDR_SZ_ #if XLEN==64 #define _ADDR_SZ_ 57 @@ -217,6 +227,25 @@ #endif #endif +// this is the position of the last level PPN in each root page table PTE + #define ROOT_PPN_LSB 10 + #if XLEN==32 + #define PPN_SZ 10 + #define LVLS 2 + #else + #define PPN_SZ 9 + #define LVLS ((_ADDR_SZ_-4)/PPN_SZ) + #endif + +// this defines a page of PTEs at top level (depending on _ADDR_SZ_) with named permissions +// for the largest size page and a common base (which is set to zero for identify mapping) +#define RVTEST_PTE_IDENT_MAP(PGBASE,LVLS,PERMS) ;\ + .set ppn, 0 ;\ + .rept (4096 >> REGWIDTH) ;\ + .fill 1, REGWIDTH, (PGBASE | (ppn<<(10+(LVLS-1)*PPN_SZ)) | PERMS) ;\ + .set ppn, (ppn+1) ;\ + .endr ;\ + // define a bunch of XLEN dependent constants #if XLEN==32 #define SREG sw @@ -242,15 +271,12 @@ #define FLREG fld #define FSREG fsd #define FREGWIDTH 8 -#elif FLEN==16 - #define FLREG flh - #define FSREG fsh - #define FREGWIDTH 2 -#else +#elif FLEN==128 #define FLREG flq #define FSREG fsq #define FREGWIDTH 16 #endif + #if ZFINX==1 #define FLREG ld #define FSREG sd @@ -455,14 +481,15 @@ /**** fixed length LA macro; alignment and rvc/norvc unknown before execution ****/ #define LA(reg,val) ;\ + .ifnc(reg, X0) ;\ .option push ;\ .option rvc ;\ .align UNROLLSZ ;\ .option norvc ;\ la reg,val ;\ .align UNROLLSZ ;\ - .option pop - + .option pop ;\ + .endif #define ADDI(dst, src, imm) /* helper*/ ;\ .if ((imm<=2048) & (imm>=-2048)) ;\ addi dst, src, imm ;\ @@ -475,41 +502,52 @@ /**** initialize regs, just to make sure you catch any errors ****/ /*****************************************************************/ +.macro DBLSHIFT7 dstreg, oldreg + srli \dstreg\(), \oldreg\(), 7 + srli x15 , \oldreg\(), XLEN-7 + or \dstreg\(), \dstreg\(), x15 +.endm /* init regs, to ensure you catch any errors */ .macro RVTEST_INIT_GPRS - LI (x1, (0xFEEDBEADFEEDBEAD & MASK)) - LI (x2, (0xFF76DF56FF76DF56 & MASK)) - LI (x3, (0x7FBB6FAB7FBB6FAB & MASK)) - LI (x4, (0xBFDDB7D5BFDDB7D5 & MASK)) - LI (x5, (0xDFEEDBEADFEEDBEA & MASK)) - LI (x6, (0x6FF76DF56FF76DF5 & MASK)) - LI (x7, (0xB7FBB6FAB7FBB6FA & MASK)) - LI (x8, (0x5BFDDB7D5BFDDB7D & MASK)) - LI (x9, (0xADFEEDBEADFEEDBE & MASK)) - LI (x10, (0x56FF76DF56FF76DF & MASK)) - LI (x11, (0xAB7FBB6FAB7FBB6F & MASK)) - LI (x12, (0xD5BFDDB7D5BFDDB7 & MASK)) - LI (x13, (0xEADFEEDBEADFEEDB & MASK)) - LI (x14, (0xF56FF76DF56FF76D & MASK)) - LI (x15, (0xFAB7FBB6FAB7FBB6 & MASK)) #ifndef RVTEST_E LI (x16, (0x7D5BFDDB7D5BFDDB & MASK)) - LI (x17, (0xBEADFEEDBEADFEED & MASK)) - LI (x18, (0xDF56FF76DF56FF76 & MASK)) - LI (x19, (0x6FAB7FBB6FAB7FBB & MASK)) - LI (x20, (0xB7D5BFDDB7D5BFDD & MASK)) - LI (x21, (0xDBEADFEEDBEADFEE & MASK)) - LI (x22, (0x6DF56FF76DF56FF7 & MASK)) - LI (x23, (0xB6FAB7FBB6FAB7FB & MASK)) - LI (x24, (0xDB7D5BFDDB7D5BFD & MASK)) - LI (x25, (0xEDBEADFEEDBEADFE & MASK)) - LI (x26, (0x76DF56FF76DF56FF & MASK)) - LI (x27, (0xBB6FAB7FBB6FAB7F & MASK)) - LI (x28, (0xDDB7D5BFDDB7D5BF & MASK)) - LI (x29, (0xEEDBEADFEEDBEADF & MASK)) - LI (x30, (0xF76DF56FF76DF56F & MASK)) - LI (x31, (0xFBB6FAB7FBB6FAB7 & MASK)) + DBLSHIFT7 x17, x16 + DBLSHIFT7 x18, x17 + DBLSHIFT7 x19, x18 + DBLSHIFT7 x20, x19 + DBLSHIFT7 x21, x20 + DBLSHIFT7 x22, x21 + DBLSHIFT7 x23, x22 + DBLSHIFT7 x24, x23 + DBLSHIFT7 x25, x24 + DBLSHIFT7 x26, x25 + DBLSHIFT7 x27, x26 + DBLSHIFT7 x28, x27 + DBLSHIFT7 x29, x28 + DBLSHIFT7 x30, x29 #endif + LI (x1, (0xFEEDBEADFEEDBEAD & MASK)) + DBLSHIFT7 x2, x1 + DBLSHIFT7 x3, x2 + DBLSHIFT7 x4, x3 + DBLSHIFT7 x5, x4 + DBLSHIFT7 x6, x5 + DBLSHIFT7 x7, x6 + DBLSHIFT7 x8, x7 + DBLSHIFT7 x9, x8 + DBLSHIFT7 x10, x9 + DBLSHIFT7 x11, x10 + DBLSHIFT7 x12, x11 + DBLSHIFT7 x13, x12 + +#ifdef RVTEST_ENAB_INSTRET_CNT + csrr x14, CSR_MSCRATCH + csrr x15, CSR_MINSTRET + SREG x15, tramp_sz+4*8(x14) // this replaces initial canary val w/ instret counter val + + DBLSHIFT7 x14, x13 + LI (x15, (0xFAB7FBB6FAB7FBB6 & MASK)) +#endif .endm /******************************************************************************/ /**** this is a helper macro that conditionally instantiates the macros ****/ @@ -630,7 +668,7 @@ //**** NOTE: Only be use for debug! Xregs containing addresses won't be relocated ****// //////////////////////////////////////////////////////////////////////////////////////// -#define RVTEST_SAVE_GPRSM(_BR, _LBL, ...) ;\ +#define RVTEST_SAVE_GPRS(_BR, _LBL, ...) ;\ .option push ;\ .option norvc ;\ .set __SV_MASK__, -1 /* default to save all */ ;\ @@ -736,55 +774,6 @@ .option pop ;\ #endif -/********************* REQUIRED FOR NEW TESTS *************************/ -/**** new macro encapsulating RVMODEL_DATA_BEGIN (signature area) ****/ -/**** defining rvtest_sig_begin: label to enabling direct stores ****/ -/**** into the signature area to be properly relocated ****/ -/**********************************************************************/ -#define RVTEST_SIG_BEGIN ;\ -.global rvtest_sig_begin /* defines beginning of signature area */ ;\ - RVMODEL_DATA_BEGIN /* model specific stuff */ ;\ -sig_begin_canary: ;\ -CANARY ;\ -rvtest_sig_begin: - -// Tests allocate normal signature space here, then define -// the mtrap_sigptr: label to separate normal and trap -// signature space, then allocate trap signature space - -/********************* REQUIRED FOR NEW TESTS *************************/ -/**** new macro definong start of trap signature area ****/ -/**** defining rvtest_sig_end: label to enabling direct stores ****/ -/**** into the signature area to be properLY relocated ****/ -/**********************************************************************/ -#define RVTEST_TSIG_BEGIN ;\ -.global rvtest_tsig_begin /* defines beginning of trap sig area */ ;\ - ;\ -tsig_begin_canary: ;\ - CANARY ;\ - mtrap_sigptr: .fill 3*(XLEN/32),4,0xdeadbeef ;\ - tsig_end_canary: ;\ - CANARY - -/********************* REQUIRED FOR NEW TESTS *************************/ -/**** new macro encapsulating RVMODEL_SIG_END (signature area) ****/ -/**** defining rvtest_sig_end: label to enabling direct stores ****/ -/**** into the signature area to be properLY relocated ****/ -/**********************************************************************/ -#define RVTEST_SIG_END ;\ -.global rvtest_sig_end /* defines beginning of trap sig area */ ;\ - ;\ -#ifdef rvtest_gpr_save ;\ -gpr_save: ;\ - .fill 32*(XLEN/32),4,0xdeadbeef ;\ -#endif ;\ - ;\ -sig_end_canary: ;\ - CANARY ;\ - CANARY /* add one extra word of guardband */ ;\ -rvtest_sig_end: ;\ -RVMODEL_DATA_END /* model specific stuff */ - /***********************************************************************************/ /**** At end of test, this code is entered. It sets a register x2 to 0 and by ****/ @@ -1177,8 +1166,9 @@ common_\__MODE__\()entry: //spcl case handling for ECALL in GOTO_MMODE mode,) ****tests can't use ECALL T2=0**** spcl_\__MODE__\()2mmode_test: csrr T5, CSR_XCAUSE - addi T4, T5, -8 // is cause 8..11? Mmode should avoid ECALL 0 - andi T4, T4, -4 // NOTE: cause 10 is RSVD. Sail will diverge, but buggy anyway + LI(T4,(1<<(XLEN-1))+(1<<12 - 1<<2)) // make a mask of int bit and cause(11:2). This + and T4, T4, T5 // Keep int bit and cause[11:2] NOTE: cause 10 is RSVD. Sail will diverge, but buggy anyway + addi T4, T4, -8 // map cause 8..11 to 0. Mmode should avoid ECALL 0 bnez T4, \__MODE__\()trapsig_ptr_upd // no, not in special mode, just continue LREG T2, trap_sv_off+7*REGWIDTH(sp) // get test x2 (which is sp, which has been saved in the trap_sv area beqz T2, rtn2mmode // spcl code 0 in T2 means spcl ECALL goto_mmode, just rtn after ECALL @@ -1275,26 +1265,26 @@ common_\__MODE__\()excpt_handler: //******************************************************************************** // calculate the delta between trap mode and handler mode sv areas & add to sp // This code calculates this table: (H-ext is determined by Vtrap_routine variable - - // +-------+-------+-------+-------+---------+ - // | Hndlr | vMPP | M.GVA | H-ext | sv area | + // lglmsk(vMPP,H,GVA)=(1x1,x01)=0x5D + // +-------+------+-------+-------+---------+ + // | Hndlr | vMPP | H-ext | M.GVA | sv area | // | Mode | =3 | | | delta | // +-------+------+-------+-------+---------+ // | M | 0 | 1 | 1 | 2 | - // | M | 0 | 0 | x | 1 | - // | M | 1 | 0 | x | 0 | - // | M | x | 1 | 0 | illegal | - // | M | 1 | 1 | x | illegal | + // | M | 0 | x | 0 | 1 | + // | M | 1 | x | 0 | 0 | + // | M | x | 0 | 1 | illegal | + // | M | 1 | x | 1 | illegal | // +-------+------+-------+-------+---------+ - // | | | H.GVA | H-ext | sv area | + // | | | H-ext | H.GVA | sv area | // +-------+------+-------+-------+---------+ // | S/HS | 0* | 1 | 1 | 1 | - // | S/HS | 0* | 0 | 1 | 0 | - // | S/HS | 0* | * | 0 | 0 | + // | S/HS | 0* | 1 | 0 | 0 | + // | S/HS | 0* | 0 | * | 0 | // +-------+------+-------+-------+---------+ - // | | | noGVA | H-ext | sv area | | + // | | | H-ext | noGVA | sv area | // +-------+------+-------+-------+---------+ - // | VS | 0* | - | 1* | 0 | + // | VS | 0* | 1* | -* | 0 | // +-------+------+-------+-------+---------+ // where vMPP is // +-------+-------+-------+-------+------+ @@ -1317,50 +1307,47 @@ common_\__MODE__\()excpt_handler: //******************************************************************************** // create an index from these values: vMPP, x.GVA , H-ext - // where vMPP = m.PRV ? svedMPP : m.MPP & svedMPP + // where vMPP = m.PRV ? svedMPP : m.MPP .ifc \__MODE__ , M csrr T6, CSR_MSTATUS - LREG T4, mpp_sv_off(sp) /* saved MPP, overwritten if MPRV=1 */ // extract MPRV into bit0. Note that only Mmode cares; all other modes can have garbage slli T3, T6, XLEN-MPRV_LSB-1 /* put MPRV into sign bit & test */ bge T3, x0, 1f - and T4, T4, T6 /* MPP=11 if MPRV=0, so AND w/ prevMPP */ + LREG T6, mpp_sv_off(sp) /* saved MPP, overwritten if MPRV=1 */ 1: - // FIXME: add code here to end test if MPRV=1 & MPP<3 - // e.g. rt justify, extract, add mprv, end if <4 -// now convert 2 bit xMPP field into a single bit 2 - srli T4, T4, MPP_LSB /* now cvt MPP (in its natural position)*/ +// create a mask in T4[2:0] with (xMPP==3, H-ext, GVA) + srli T4, T6, MPP_LSB /* now cvt MPP (in its natural position)*/ andi T4, T4, 3 /* to a single bit in bit2 iff ==3 */ addi T4, T4, 1 andi T4, T4, 4 -// extract GVA into bit 1 +// extract GVA into bit 0 #if (rvtest_vtrap_routine) #if (XLEN==32) csrr T3, CSR_MSTATUSH /* get CSR with GVA bit, but only H-ext */ - srli T3, T3, GVA_LSB-1 /* reposition RV32 mstatush into bit1 */ + srli T3, T3, GVA_LSB /* reposition RV32 mstatush into bit1 */ #else - srli T3, T6, GVA_LSB-1+32 /* reposition RV32 mstatus into bit1 */ + srli T3, T4, GVA_LSB+32 /* reposition RV32 mstatus into bit1 */ #endif - andi T3, T3, 1<<1 + andi T3, T3, 1 or T4, T4, T3 /* extract GVA in bit1, insert into msk */ // put H-extension implemented into bit 0 ori T4, T4, 1 /* set LSB if H-ext present */ //****FIXME: this doesn't work if misa.H is RW but set to zero ****/ #endif // chk for illegal combination - LI( T6, 0x3B) /*lgl msk(vMPP,GVA,H)= 011,00x,10x=0x3B */ + LI( T6, 0x5D) /*lglmsk(vMPP,H,GVA)=(1x1,011,0x0)=0x5D */ srl T6, T6, T4 - andi T6, T6, 1 - beq T6, x0, rvtest_\__MODE__\()endtest /* illegal combination */ + andi T6, T6, 1 /* extract lgl bit val & end test if 0 */ + beq T6, x0, rvtest_\__MODE__\()endtest //determine sv offset multiplier LI( T6, sv_area_sz) - andi T3, T4, 2 - srli T3, T3, 1 /* extract GVA & move to bito cases */ - srl T6, T6, T3 /* mul by 2 if GVAelse mul by 1 */ - slli T3, T4, XLEN-3 - srai T3, T3, XLEN-1 /* sg ext vMPP, user it to clr delta */ - and T6, T6, T3 + andi T3, T4, 1 /* GVA indicates *2 or sll of 1 */ + sll T6, T6, T3 /* mul by 2 if GVA else mul by 1 */ + slli T3, T4, XLEN-3 /* but mul by 0 if bit2 (vMPP==3) == 1 */ + srai T3, T3, XLEN-1 /* make 0s msk if vMMP==3 bit =1 */ + xori T3, T3, -1 + and T4, T6, T3 .else // do it again, but from VS or HS mode .ifc \__MODE__ , S @@ -1890,6 +1877,8 @@ rvtest_\__MODE__\()end: rvtest_init: //instantiate prologs here INSTANTIATE_MODE_MACRO RVTEST_TRAP_PROLOG +rvtest_entrypoint: + RVMODEL_BOOT RVTEST_INIT_GPRS // 0xF0E1D2C3B4A59687 rvtest_code_begin: .option pop @@ -1901,7 +1890,7 @@ rvtest_\__MODE__\()end: /**** So the test is here ****/ /**** the below is instantiated at the end of the actual test ****/ /************************************************************************************/ - +/* ----------------> test inserted here <---------------- */ /**************************************************************************************/ /**** RVTEST_CODE_END macro defines end of test code: saves regs, transitions to ****/ /**** Mmode, & instantiates epilog using RVTEST_TRAP_EPILOG() macros. Test code ****/ @@ -1922,6 +1911,13 @@ rvtest_\__MODE__\()end: #endif RVTEST_GOTO_MMODE // if only Mmode used by tests, this has no effect cleanup_epilogs: // jump here to quit, will restore state for each mode +#ifdef RVTEST_ENAB_INSTRET_CNT + csrr x15, CSR_MINSTRET + csrr x14, CSR_MSCRATCH + LREG x13, tramp_sz+4*8(x14) // initial instret point stored here + sub x15, x15, x13 // calc instret delta + SREG x13, tramp_sz+4*8(x14) //put it back in the signature +#endif //restore xTVEC, trampoline, regs for each mode in opposite order that they were saved #ifdef rvtest_mtrap_routine @@ -1949,14 +1945,10 @@ rvtest_\__MODE__\()end: INSTANTIATE_MODE_MACRO RVTEST_TRAP_HANDLER exit_cleanup: // *** RVMODEL_HALT MUST follow this***, then data - +RVMODEL_HALT .option pop .endm // end of RVTEST_CODE_END -/************************************************************************************/ -/**** RVTEST_CODE_END macros must fall thru or jump to an RVMODEL_HALT macro here ***/ -/************************************************************************************/ - /*===================================data section starts here========================*/ /************************************************************************************/ @@ -1987,29 +1979,88 @@ rvtest_\__MODE__\()end: rvtest_data_begin: .endm +/************************************************************************************/ +/* ----------------> test data inserted here <---------------- */ +/************************************************************************************/ + /************************************************************************************/ /**************** RVTEST_DATA_END macro; defines global label rvtest_data_end ****/ /************************************************************************************/ .macro RVTEST_DATA_END .global rvtest_data_end - #ifndef rvtest_mtrap_routine - mtrap_sigptr: - .fill 2,4,0xdeadbeef - #endif /**** create identity mapped page tables here if mmu is present ****/ .align 12 #ifndef RVTEST_NO_IDENTY_MAP #ifdef rvtest_strap_routine +//this is a valid global pte entry w/ all permissions. IF at root level, it forms an identity map. rvtest_Sroot_pg_tbl: - RVTEST_PTE_IDENT_MAP - + RVTEST_PTE_IDENT_MAP(0,LVLS,RVTEST_ALLPERMS) + #ifdef rvtest_vtrap_routine - rvtest_Vroot_pg_tbl: - RVTEST_PTE_IDENT_MAP + rvtest_Vroot_pg_tbl: + RVTEST_PTE_IDENT_MAP(0,LVLS,RVTEST_ALLPERMS) #endif #endif #endif rvtest_data_end: .endm + +/********************* REQUIRED FOR NEW TESTS *************************/ +/**** new macro encapsulating RVMODEL_DATA_BEGIN (signature area) ****/ +/**** defining rvtest_sig_begin: label to enabling direct stores ****/ +/**** into the signature area to be properly relocated ****/ +/**********************************************************************/ +.macro RVTEST_SIG_BEGIN +.global rvtest_sig_begin /* defines beginning of signature area */ + RVMODEL_DATA_BEGIN /* model specific stuff */ +sig_begin_canary: +CANARY +rvtest_sig_begin: +.endm + +// Tests allocate normal signature space here, then define +// the mtrap_sigptr: label to separate normal and trap +// signature space, then allocate trap signature space + +/********************* REQUIRED FOR NEW TESTS *************************/ +/**** new macro defining start of trap signature area ****/ +/**** defining rvtest_sig_end: label to enabling direct stores ****/ +/**** into the signature area to be properLY relocated ****/ +/**********************************************************************/ +//.macro RVTEST_TSIG_BEGIN +.macro RVTEST_SIG_END +.global rvtest_tsig_begin /* defines beginning of trap sig area */ + +tsig_begin_canary: + CANARY +mtrap_sigptr: + #ifndef rvtest_mtrap_routine /* install dummy or dflt trap sig area */ + .fill 3*(XLEN/32),4,0xdeadbeef + #else + .fill 64*(XLEN/32),4,0xdeadbeef + #endif +tsig_end_canary: + CANARY +//.endm + +/********************* REQUIRED FOR NEW TESTS *************************/ +/**** new macro encapsulating RVMODEL_SIG_END (signature area) ****/ +/**** defining rvtest_sig_end: label to enabling direct stores ****/ +/**** into the signature area to be properLY relocated ****/ +/**********************************************************************/ +//.macro RVTEST_SIG_END +.global rvtest_sig_end /* defines beginning of trap sig area */ + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef +#endif + +sig_end_canary: + CANARY + CANARY /* add one extra word of guardband */ +rvtest_sig_end: +RVMODEL_DATA_END /* model specific stuff */ +.endm \ No newline at end of file From e48de2b55e68517c505e767df516024a0af181fb Mon Sep 17 00:00:00 2001 From: umershahidengr Date: Mon, 3 Jun 2024 21:44:10 +0500 Subject: [PATCH 2/6] Updated trap handler --- .../Makefile.Reference-sail_c_simulator | 61 - riscof_work/database.yaml | 347 -- riscof_work/spike_simple_isa_checked.yaml | 4121 ----------------- .../spike_simple_platform_checked.yaml | 18 - .../src/ebreak.S/dut/DUT-Spike.signature | 8 - riscof_work/src/ebreak.S/dut/my.elf | Bin 20976 -> 0 bytes riscof_work/src/ebreak.S/ref/ebreak.log | 28 - riscof_work/src/ebreak.S/ref/ref.disass | 959 ---- riscof_work/src/ebreak.S/ref/ref.elf | Bin 20988 -> 0 bytes .../src/ecall.S/dut/DUT-Spike.signature | 8 - riscof_work/src/ecall.S/dut/my.elf | Bin 20976 -> 0 bytes .../misalign-beq-01.S/dut/DUT-Spike.signature | 69 - riscof_work/src/misalign-beq-01.S/dut/my.elf | Bin 21512 -> 0 bytes .../misalign-bge-01.S/dut/DUT-Spike.signature | 69 - riscof_work/src/misalign-bge-01.S/dut/my.elf | Bin 21512 -> 0 bytes .../dut/DUT-Spike.signature | 69 - riscof_work/src/misalign-bgeu-01.S/dut/my.elf | Bin 25608 -> 0 bytes .../misalign-blt-01.S/dut/DUT-Spike.signature | 69 - riscof_work/src/misalign-blt-01.S/dut/my.elf | Bin 21512 -> 0 bytes .../dut/DUT-Spike.signature | 69 - riscof_work/src/misalign-bltu-01.S/dut/my.elf | Bin 21512 -> 0 bytes .../misalign-bne-01.S/dut/DUT-Spike.signature | 69 - riscof_work/src/misalign-bne-01.S/dut/my.elf | Bin 21512 -> 0 bytes .../misalign-jal-01.S/dut/DUT-Spike.signature | 69 - riscof_work/src/misalign-jal-01.S/dut/my.elf | Bin 21448 -> 0 bytes .../misalign-lh-01.S/dut/DUT-Spike.signature | 69 - riscof_work/src/misalign-lh-01.S/dut/my.elf | Bin 21364 -> 0 bytes .../misalign-lhu-01.S/dut/DUT-Spike.signature | 69 - riscof_work/src/misalign-lhu-01.S/dut/my.elf | Bin 21364 -> 0 bytes .../misalign-lw-01.S/dut/DUT-Spike.signature | 71 - riscof_work/src/misalign-lw-01.S/dut/my.elf | Bin 21416 -> 0 bytes .../misalign-sh-01.S/dut/DUT-Spike.signature | 69 - riscof_work/src/misalign-sh-01.S/dut/my.elf | Bin 21364 -> 0 bytes .../misalign-sw-01.S/dut/DUT-Spike.signature | 71 - riscof_work/src/misalign-sw-01.S/dut/my.elf | Bin 21416 -> 0 bytes .../dut/DUT-Spike.signature | 69 - .../src/misalign2-jalr-01.S/dut/my.elf | Bin 21428 -> 0 bytes riscof_work/test_list.yaml | 179 - 38 files changed, 6630 deletions(-) delete mode 100644 riscof_work/Makefile.Reference-sail_c_simulator delete mode 100644 riscof_work/database.yaml delete mode 100644 riscof_work/spike_simple_isa_checked.yaml delete mode 100644 riscof_work/spike_simple_platform_checked.yaml delete mode 100644 riscof_work/src/ebreak.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/ebreak.S/dut/my.elf delete mode 100644 riscof_work/src/ebreak.S/ref/ebreak.log delete mode 100644 riscof_work/src/ebreak.S/ref/ref.disass delete mode 100755 riscof_work/src/ebreak.S/ref/ref.elf delete mode 100644 riscof_work/src/ecall.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/ecall.S/dut/my.elf delete mode 100644 riscof_work/src/misalign-beq-01.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/misalign-beq-01.S/dut/my.elf delete mode 100644 riscof_work/src/misalign-bge-01.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/misalign-bge-01.S/dut/my.elf delete mode 100644 riscof_work/src/misalign-bgeu-01.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/misalign-bgeu-01.S/dut/my.elf delete mode 100644 riscof_work/src/misalign-blt-01.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/misalign-blt-01.S/dut/my.elf delete mode 100644 riscof_work/src/misalign-bltu-01.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/misalign-bltu-01.S/dut/my.elf delete mode 100644 riscof_work/src/misalign-bne-01.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/misalign-bne-01.S/dut/my.elf delete mode 100644 riscof_work/src/misalign-jal-01.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/misalign-jal-01.S/dut/my.elf delete mode 100644 riscof_work/src/misalign-lh-01.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/misalign-lh-01.S/dut/my.elf delete mode 100644 riscof_work/src/misalign-lhu-01.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/misalign-lhu-01.S/dut/my.elf delete mode 100644 riscof_work/src/misalign-lw-01.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/misalign-lw-01.S/dut/my.elf delete mode 100644 riscof_work/src/misalign-sh-01.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/misalign-sh-01.S/dut/my.elf delete mode 100644 riscof_work/src/misalign-sw-01.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/misalign-sw-01.S/dut/my.elf delete mode 100644 riscof_work/src/misalign2-jalr-01.S/dut/DUT-Spike.signature delete mode 100755 riscof_work/src/misalign2-jalr-01.S/dut/my.elf delete mode 100644 riscof_work/test_list.yaml diff --git a/riscof_work/Makefile.Reference-sail_c_simulator b/riscof_work/Makefile.Reference-sail_c_simulator deleted file mode 100644 index fc826ff1e..000000000 --- a/riscof_work/Makefile.Reference-sail_c_simulator +++ /dev/null @@ -1,61 +0,0 @@ - - -.PHONY : ebreak -ebreak : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/ebreak.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/ebreak.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > ebreak.log 2>&1; - -.PHONY : ecall -ecall : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/ecall.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/ecall.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > ecall.log 2>&1; - -.PHONY : misalign-beq-01 -misalign-beq-01 : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-beq-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-beq-01.log 2>&1; - -.PHONY : misalign-bge-01 -misalign-bge-01 : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bge-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bge-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-bge-01.log 2>&1; - -.PHONY : misalign-bgeu-01 -misalign-bgeu-01 : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bgeu-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bgeu-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-bgeu-01.log 2>&1; - -.PHONY : misalign-blt-01 -misalign-blt-01 : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-blt-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-blt-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-blt-01.log 2>&1; - -.PHONY : misalign-bltu-01 -misalign-bltu-01 : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bltu-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bltu-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-bltu-01.log 2>&1; - -.PHONY : misalign-bne-01 -misalign-bne-01 : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bne-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bne-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-bne-01.log 2>&1; - -.PHONY : misalign-jal-01 -misalign-jal-01 : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-jal-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-jal-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-jal-01.log 2>&1; - -.PHONY : misalign-lh-01 -misalign-lh-01 : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-lh-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lh-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-lh-01.log 2>&1; - -.PHONY : misalign-lhu-01 -misalign-lhu-01 : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-lhu-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lhu-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-lhu-01.log 2>&1; - -.PHONY : misalign-lw-01 -misalign-lw-01 : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-lw-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lw-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-lw-01.log 2>&1; - -.PHONY : misalign-sh-01 -misalign-sh-01 : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-sh-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sh-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-sh-01.log 2>&1; - -.PHONY : misalign-sw-01 -misalign-sw-01 : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-sw-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sw-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign-sw-01.log 2>&1; - -.PHONY : misalign2-jalr-01 -misalign2-jalr-01 : - @cd /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign2-jalr-01.S/ref;riscv32-unknown-elf-gcc -march=rv32i_zicsr -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/user/Tools/riscof-plugins/sail_cSim/env/link.ld -I /home/user/Tools/riscof-plugins/sail_cSim/env/ -I /home/user/Work/Tests/riscv-test-suite/env -mabi=ilp32 /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign2-jalr-01.S -o ref.elf -Drvtest_mtrap_routine=True -DTEST_CASE_1=True -DXLEN=32;riscv32-unknown-elf-objdump -D ref.elf > ref.disass;riscv_sim_RV32 -i -v --enable-pmp --test-signature=Reference-sail_c_simulator.signature ref.elf > misalign2-jalr-01.log 2>&1; \ No newline at end of file diff --git a/riscof_work/database.yaml b/riscof_work/database.yaml deleted file mode 100644 index 426d2513a..000000000 --- a/riscof_work/database.yaml +++ /dev/null @@ -1,347 +0,0 @@ -# database generated on 2024-06-03 16:17 GMT -!!omap -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/ebreak.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - ebreak -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/ecall.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - ecall -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-beq - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-beq -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bge-01.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bge - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bge -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bgeu-01.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bgeu - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bgeu -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-blt-01.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-blt - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-blt -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bltu-01.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bltu - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bltu -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bne-01.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bne - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-bne -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-jal-01.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-jal - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-jal -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lh-01.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lh - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lh -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lhu-01.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lhu - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lhu -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lw-01.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lw - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-lw -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sh-01.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sh - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sh -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sw-01.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*) - - check hw_data_misaligned_support:=True - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sw - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check hw_data_misaligned_support:=False - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign-sw -- /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign2-jalr-01.S: - commit_id: '-' - isa: - - RV32I_Zicsr - parts: !!omap - - '0': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*C.*) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign2-jalr - - '1': - check: - - check ISA:=regex(.*32.*) - - check ISA:=regex(.*I.*Zicsr.*) - - check ISA:=regex(^[^C]+$) - define: - - def rvtest_mtrap_routine=True - - def TEST_CASE_1=True - coverage_labels: - - misalign2-jalr diff --git a/riscof_work/spike_simple_isa_checked.yaml b/riscof_work/spike_simple_isa_checked.yaml deleted file mode 100644 index 6e4b396eb..000000000 --- a/riscof_work/spike_simple_isa_checked.yaml +++ /dev/null @@ -1,4121 +0,0 @@ -hart_ids: [0] -hart0: - ISA: RV32IMAFDCZicsr_Zifencei - physical_addr_sz: 32 - User_Spec_Version: '2.3' - supported_xlen: - - 32 - misa: - reset-val: 0x4000112D - rv32: - accessible: true - mxl: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - mxl[1:0] in [0x1] - wr_illegal: - - Unchanged - description: Encodes the native base integer ISA width. - shadow: - shadow_type: rw - msb: 31 - lsb: 30 - extensions: - implemented: true - type: - warl: - dependency_fields: [] - legal: - - extensions[25:0] bitmask [0x000112D, 0x0000000] - wr_illegal: - - Unchanged - - description: Encodes the presence of the standard extensions, with - a single bit per letter of the alphabet. - shadow: - shadow_type: rw - msb: 25 - lsb: 0 - fields: - - extensions - - mxl - - - - - - 26 - - 29 - description: misa is a read-write register reporting the ISA supported by - the hart. - address: 769 - priv_mode: M - rv64: - accessible: false - Privilege_Spec_Version: '1.10' - hw_data_misaligned_support: false - pmp_granularity: 0 - custom_exceptions: - custom_interrupts: - pte_ad_hw_update: false - mtval_update: 0b11111111 - mstatus: - rv32: - accessible: true - fields: - - uie - - sie - - mie - - upie - - spie - - mpie - - spp - - mpp - - fs - - xs - - mprv - - sum - - mxr - - tvm - - tw - - tsr - - sd - - - - - - 2 - - - - 6 - - - - 9 - - 10 - - - - 23 - - 30 - uie: - implemented: false - description: Stores the state of the user mode interrupts. - shadow: - shadow_type: rw - msb: 0 - lsb: 0 - sie: - implemented: false - description: Stores the state of the supervisor mode interrupts. - shadow: - shadow_type: rw - msb: 1 - lsb: 1 - mie: - implemented: true - description: Stores the state of the machine mode interrupts. - shadow: - shadow_type: rw - msb: 3 - lsb: 3 - type: - wlrl: - - 0:1 - upie: - implemented: false - description: Stores the state of the user mode interrupts prior to - the trap. - shadow: - shadow_type: rw - msb: 4 - lsb: 4 - spie: - implemented: false - description: Stores the state of the supervisor mode interrupts prior - to the trap. - shadow: - shadow_type: rw - msb: 5 - lsb: 5 - mpie: - implemented: true - description: Stores the state of the machine mode interrupts prior - to the trap. - shadow: - shadow_type: rw - msb: 7 - lsb: 7 - type: - wlrl: - - 0:1 - spp: - implemented: false - description: Stores the previous priority mode for supervisor. - shadow: - shadow_type: rw - msb: 8 - lsb: 8 - mpp: - implemented: true - description: Stores the previous priority mode for machine. - shadow: - shadow_type: rw - msb: 12 - lsb: 11 - type: {ro_constant: 0} - fs: - implemented: true - description: Encodes the status of the floating-point unit, including - the CSR fcsr and floating-point data registers. - shadow: - shadow_type: rw - msb: 14 - lsb: 13 - type: - warl: - dependency_fields: [] - legal: - - fs[1:0] in [0x0:0x3] - wr_illegal: - - unchanged - xs: - implemented: false - description: Encodes the status of additional user-mode extensions - and associated state. - shadow: - shadow_type: rw - msb: 16 - lsb: 15 - mprv: - implemented: false - description: Modifies the privilege level at which loads and stores - execute in all privilege modes. - shadow: - shadow_type: rw - msb: 17 - lsb: 17 - sum: - implemented: false - description: Modifies the privilege with which S-mode loads and stores - access virtual memory. - shadow: - shadow_type: rw - msb: 18 - lsb: 18 - mxr: - implemented: false - description: Modifies the privilege with which loads access virtual - memory. - shadow: - shadow_type: rw - msb: 19 - lsb: 19 - tvm: - implemented: false - description: Supports intercepting supervisor virtual-memory management - operations. - shadow: - shadow_type: rw - msb: 20 - lsb: 20 - tw: - implemented: false - description: Supports intercepting the WFI instruction. - shadow: - shadow_type: rw - msb: 21 - lsb: 21 - tsr: - implemented: false - description: Supports intercepting the supervisor exception return - instruction. - shadow: - shadow_type: rw - msb: 22 - lsb: 22 - sd: - implemented: true - description: Read-only bit that summarizes whether either the FS field - or XS field signals the presence of some dirty state. - shadow: - shadow_type: rw - msb: 31 - lsb: 31 - type: - wlrl: - - 0:1 - rv64: - accessible: false - description: The mstatus register keeps track of and controls the hart’s current - operating state. - address: 768 - priv_mode: M - reset-val: 0 - mstatush: - rv32: - accessible: true - fields: - - sbe - - mbe - - gva - - mpv - - - - - - 0 - - 3 - - - - 8 - - 31 - mpv: - implemented: false - description: Stores the state of the user mode interrupts. - shadow: - shadow_type: rw - msb: 7 - lsb: 7 - gva: - implemented: false - description: Stores the state of the supervisor mode interrupts. - shadow: - shadow_type: rw - msb: 6 - lsb: 6 - mbe: - implemented: false - description: control the endianness of memory accesses other than - instruction fetches for machine mode - shadow: - shadow_type: rw - msb: 5 - lsb: 5 - sbe: - implemented: false - description: control the endianness of memory accesses other than - instruction fetches for supervisor mode - shadow: - shadow_type: rw - msb: 4 - lsb: 4 - rv64: - accessible: false - description: The mstatush register keeps track of and controls the hart’s - current operating state. - address: 768 - priv_mode: M - reset-val: 0 - mvendorid: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: - ro_constant: 0 - rv64: - accessible: false - description: 32-bit read-only register providing the JEDEC manufacturer ID - of the provider of the core. - address: 3857 - priv_mode: M - reset-val: 0 - marchid: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: - ro_constant: 0 - rv64: - accessible: false - description: MXLEN-bit read-only register encoding the base microarchitecture - of the hart. - address: 3858 - priv_mode: M - reset-val: 0 - mimpid: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: - ro_constant: 0 - rv64: - accessible: false - description: Provides a unique encoding of the version of the processor implementation. - address: 3859 - priv_mode: M - reset-val: 0 - mhartid: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: - ro_constant: 0 - rv64: - accessible: false - description: MXLEN-bit read-only register containing the integer ID of the - hardware thread running the code. - address: 3860 - priv_mode: M - reset-val: 0 - mtvec: - rv32: - accessible: true - fields: - - mode - - base - base: - implemented: true - description: Vector base address. - shadow: - shadow_type: rw - msb: 31 - lsb: 2 - type: - warl: - dependency_fields: [] - legal: - - base[29:0] bitmask [0x3FFFFFFF, 0x00000000] - wr_illegal: - - Unchanged - mode: - implemented: true - description: Vector mode. - shadow: - shadow_type: rw - msb: 1 - lsb: 0 - type: - warl: - dependency_fields: [] - legal: - - mode[1:0] in [0x0,0x1] - wr_illegal: - - Unchanged - rv64: - accessible: false - description: MXLEN-bit read/write register that holds trap vector configuration. - address: 773 - priv_mode: M - reset-val: 0 - mideleg: - rv32: - accessible: false - rv64: - accessible: false - description: Machine Interrupt delegation Register. - address: 771 - priv_mode: M - reset-val: 0 - medeleg: - rv32: - accessible: false - rv64: - accessible: false - description: Machine Exception delegation Register. - address: 770 - priv_mode: M - reset-val: 0 - mip: - rv32: - accessible: true - fields: - - usip - - ssip - - vssip - - msip - - utip - - stip - - vstip - - mtip - - ueip - - seip - - vseip - - meip - - sgeip - - - - - - 13 - - 31 - usip: - implemented: false - description: User Software Interrupt Pending. - shadow: - shadow_type: rw - msb: 0 - lsb: 0 - ssip: - implemented: false - description: Supervisor Software Interrupt Pending. - shadow: - shadow_type: rw - msb: 1 - lsb: 1 - vssip: - implemented: false - description: VS-level Software Interrupt Pending. - shadow: - shadow_type: rw - msb: 2 - lsb: 2 - msip: - implemented: true - description: Machine Software Interrupt Pending. - shadow: - shadow_type: rw - msb: 3 - lsb: 3 - type: - ro_variable: true - utip: - implemented: false - description: User Timer Interrupt Pending. - shadow: - shadow_type: rw - msb: 4 - lsb: 4 - stip: - implemented: false - description: Supervisor Timer Interrupt Pending. - shadow: - shadow_type: rw - msb: 5 - lsb: 5 - vstip: - implemented: false - description: VS-level Timer Interrupt Pending. - shadow: - shadow_type: rw - msb: 6 - lsb: 6 - mtip: - implemented: true - description: Machine Timer Interrupt Pending. - shadow: - shadow_type: rw - msb: 7 - lsb: 7 - type: - ro_variable: true - ueip: - implemented: false - description: User External Interrupt Pending. - shadow: - shadow_type: rw - msb: 8 - lsb: 8 - seip: - implemented: false - description: Supervisor External Interrupt Pending. - shadow: - shadow_type: rw - msb: 9 - lsb: 9 - vseip: - implemented: false - description: VS-level External Interrupt Pending. - shadow: - shadow_type: rw - msb: 10 - lsb: 10 - meip: - implemented: true - description: Machine External Interrupt Pending. - shadow: - shadow_type: rw - msb: 11 - lsb: 11 - type: - ro_variable: true - sgeip: - implemented: false - description: HS-level External Interrupt Pending. - shadow: - shadow_type: rw - msb: 12 - lsb: 12 - rv64: - accessible: false - description: The mip register is an MXLEN-bit read/write register containing - information on pending interrupts. - address: 836 - priv_mode: M - reset-val: 0 - hie: - rv32: - accessible: false - rv64: - accessible: false - description: The hie register is an HSXLEN-bit read/write register containing - interrupt enable bits. - address: 0x604 - priv_mode: H - reset-val: 0 - mie: - rv32: - accessible: true - fields: - - usie - - ssie - - vssie - - msie - - utie - - stie - - vstie - - mtie - - ueie - - seie - - vseie - - meie - - sgeie - - - - - - 13 - - 31 - usie: - implemented: false - description: User Software Interrupt enable. - shadow: - shadow_type: rw - msb: 0 - lsb: 0 - ssie: - implemented: false - description: Supervisor Software Interrupt enable. - shadow: - shadow_type: rw - msb: 1 - lsb: 1 - vssie: - implemented: false - description: VS-level Software Interrupt enable. - shadow: - shadow_type: rw - msb: 2 - lsb: 2 - msie: - implemented: true - description: Machine Software Interrupt enable. - shadow: - shadow_type: rw - msb: 3 - lsb: 3 - type: - wlrl: - - 0x0:0x1 - utie: - implemented: false - description: User Timer Interrupt enable. - shadow: - shadow_type: rw - msb: 4 - lsb: 4 - stie: - implemented: false - description: Supervisor Timer Interrupt enable. - shadow: - shadow_type: rw - msb: 5 - lsb: 5 - vstie: - implemented: false - description: VS-level Timer Interrupt enable. - shadow: - shadow_type: rw - msb: 6 - lsb: 6 - mtie: - implemented: true - description: Machine Timer Interrupt enable. - shadow: - shadow_type: rw - msb: 7 - lsb: 7 - type: - wlrl: - - 0:1 - ueie: - implemented: false - description: User External Interrupt enable. - shadow: - shadow_type: rw - msb: 8 - lsb: 8 - seie: - implemented: false - description: Supervisor External Interrupt enable. - shadow: - shadow_type: rw - msb: 9 - lsb: 9 - vseie: - implemented: false - description: VS-level External Interrupt enable. - shadow: - shadow_type: rw - msb: 10 - lsb: 10 - meie: - implemented: true - description: Machine External Interrupt enable. - shadow: - shadow_type: rw - msb: 11 - lsb: 11 - type: - wlrl: - - 0:1 - sgeie: - implemented: false - description: HS-level External Interrupt enable. - shadow: - shadow_type: rw - msb: 12 - lsb: 12 - rv64: - accessible: false - description: The mie register is an MXLEN-bit read/write register containing - interrupt enable bits. - address: 772 - priv_mode: M - reset-val: 0 - mscratch: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: - warl: - dependency_fields: [] - legal: - - mscratch[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - rv64: - accessible: false - description: The mscratch register is an MXLEN-bit read/write register dedicated - for use by machine mode. - address: 832 - priv_mode: M - reset-val: 0 - mepc: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: - warl: - dependency_fields: [] - legal: - - mepc[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - rv64: - accessible: false - description: The mepc is a warl register that must be able to hold all valid - physical and virtual addresses. - address: 0x341 - priv_mode: M - reset-val: 0 - mtval: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: - warl: - dependency_fields: [] - legal: - - mtval[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - rv64: - accessible: false - description: The mtval is a warl register that holds the address of the instruction - which caused the exception. - address: 835 - priv_mode: M - reset-val: 0 - mcause: - rv32: - accessible: true - fields: - - exception_code - - interrupt - interrupt: - implemented: true - description: Indicates whether the trap was due to an interrupt. - shadow: - shadow_type: rw - msb: 31 - lsb: 31 - type: - wlrl: - - 0x0:0x1 - exception_code: - implemented: true - description: Encodes the exception code. - shadow: - shadow_type: rw - msb: 30 - lsb: 0 - type: - wlrl: - - 0:15 - rv64: - accessible: false - description: The mcause register stores the information regarding the trap. - address: 834 - priv_mode: M - reset-val: 0 - pmpcfg0: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3A0 - priv_mode: M - reset-val: 0 - pmpcfg1: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3A1 - priv_mode: M - reset-val: 0 - pmpcfg2: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3A2 - priv_mode: M - reset-val: 0 - pmpcfg3: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3A3 - priv_mode: M - reset-val: 0 - pmpcfg4: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3A4 - priv_mode: M - reset-val: 0 - pmpcfg5: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3A5 - priv_mode: M - reset-val: 0 - pmpcfg6: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3A6 - priv_mode: M - reset-val: 0 - pmpcfg7: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3A7 - priv_mode: M - reset-val: 0 - pmpcfg8: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3A8 - priv_mode: M - reset-val: 0 - pmpcfg9: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3A9 - priv_mode: M - reset-val: 0 - pmpcfg10: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3AA - priv_mode: M - reset-val: 0 - pmpcfg11: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3AB - priv_mode: M - reset-val: 0 - pmpcfg12: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3AC - priv_mode: M - reset-val: 0 - pmpcfg13: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3AD - priv_mode: M - reset-val: 0 - pmpcfg14: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3AE - priv_mode: M - reset-val: 0 - pmpcfg15: - rv32: - accessible: false - rv64: - accessible: false - description: PMP configuration register - address: 0x3AF - priv_mode: M - reset-val: 0 - pmpaddr0: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3B0 - priv_mode: M - reset-val: 0 - pmpaddr1: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3B1 - priv_mode: M - reset-val: 0 - pmpaddr2: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3B2 - priv_mode: M - reset-val: 0 - pmpaddr3: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3B3 - priv_mode: M - reset-val: 0 - pmpaddr4: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3B4 - priv_mode: M - reset-val: 0 - pmpaddr5: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3B5 - priv_mode: M - reset-val: 0 - pmpaddr6: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3B6 - priv_mode: M - reset-val: 0 - pmpaddr7: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3B7 - priv_mode: M - reset-val: 0 - pmpaddr8: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3B8 - priv_mode: M - reset-val: 0 - pmpaddr9: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3B9 - priv_mode: M - reset-val: 0 - pmpaddr10: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3BA - priv_mode: M - reset-val: 0 - pmpaddr11: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3BB - priv_mode: M - reset-val: 0 - pmpaddr12: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3BC - priv_mode: M - reset-val: 0 - pmpaddr13: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3BD - priv_mode: M - reset-val: 0 - pmpaddr14: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3BE - priv_mode: M - reset-val: 0 - pmpaddr15: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3BF - priv_mode: M - reset-val: 0 - pmpaddr16: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3C0 - priv_mode: M - reset-val: 0 - pmpaddr17: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3C1 - priv_mode: M - reset-val: 0 - pmpaddr18: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3C2 - priv_mode: M - reset-val: 0 - pmpaddr19: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3C3 - priv_mode: M - reset-val: 0 - pmpaddr20: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3C4 - priv_mode: M - reset-val: 0 - pmpaddr21: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3C5 - priv_mode: M - reset-val: 0 - pmpaddr22: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3C6 - priv_mode: M - reset-val: 0 - pmpaddr23: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3C7 - priv_mode: M - reset-val: 0 - pmpaddr24: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3C8 - priv_mode: M - reset-val: 0 - pmpaddr25: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3C9 - priv_mode: M - reset-val: 0 - pmpaddr26: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3CA - priv_mode: M - reset-val: 0 - pmpaddr27: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3CB - priv_mode: M - reset-val: 0 - pmpaddr28: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3CC - priv_mode: M - reset-val: 0 - pmpaddr29: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3CD - priv_mode: M - reset-val: 0 - pmpaddr30: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3CE - priv_mode: M - reset-val: 0 - pmpaddr31: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3CF - priv_mode: M - reset-val: 0 - pmpaddr32: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3D0 - priv_mode: M - reset-val: 0 - pmpaddr33: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3D1 - priv_mode: M - reset-val: 0 - pmpaddr34: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3D2 - priv_mode: M - reset-val: 0 - pmpaddr35: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3D3 - priv_mode: M - reset-val: 0 - pmpaddr36: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3D4 - priv_mode: M - reset-val: 0 - pmpaddr37: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3D5 - priv_mode: M - reset-val: 0 - pmpaddr38: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3D6 - priv_mode: M - reset-val: 0 - pmpaddr39: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3D7 - priv_mode: M - reset-val: 0 - pmpaddr40: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3D8 - priv_mode: M - reset-val: 0 - pmpaddr41: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3D9 - priv_mode: M - reset-val: 0 - pmpaddr42: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3DA - priv_mode: M - reset-val: 0 - pmpaddr43: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3DB - priv_mode: M - reset-val: 0 - pmpaddr44: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3DC - priv_mode: M - reset-val: 0 - pmpaddr45: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3DD - priv_mode: M - reset-val: 0 - pmpaddr46: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3DE - priv_mode: M - reset-val: 0 - pmpaddr47: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3DF - priv_mode: M - reset-val: 0 - pmpaddr48: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3E0 - priv_mode: M - reset-val: 0 - pmpaddr49: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3E1 - priv_mode: M - reset-val: 0 - pmpaddr50: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3E2 - priv_mode: M - reset-val: 0 - pmpaddr51: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3E3 - priv_mode: M - reset-val: 0 - pmpaddr52: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3E4 - priv_mode: M - reset-val: 0 - pmpaddr53: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3E5 - priv_mode: M - reset-val: 0 - pmpaddr54: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3E6 - priv_mode: M - reset-val: 0 - pmpaddr55: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3E7 - priv_mode: M - reset-val: 0 - pmpaddr56: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3E8 - priv_mode: M - reset-val: 0 - pmpaddr57: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3E9 - priv_mode: M - reset-val: 0 - pmpaddr58: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3EA - priv_mode: M - reset-val: 0 - pmpaddr59: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3EB - priv_mode: M - reset-val: 0 - pmpaddr60: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3EC - priv_mode: M - reset-val: 0 - pmpaddr61: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3ED - priv_mode: M - reset-val: 0 - pmpaddr62: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3EE - priv_mode: M - reset-val: 0 - pmpaddr63: - rv32: - accessible: false - rv64: - accessible: false - description: Physical memory protection address register - address: 0x3EF - priv_mode: M - reset-val: 0 - mcounteren: - rv32: - accessible: false - rv64: - accessible: false - description: The mcounteren is a 32-bit register that controls the availability - of the hardware performance-monitoring counters to the next-lowest privileged - mode. - address: 0x306 - priv_mode: M - reset-val: 0 - mcountinhibit: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: {ro_constant: 0} - rv64: - accessible: false - description: The mcountinhibit is a 32-bit WARL register that controls which - of the hardware performance-monitoring counters increment. - address: 0x320 - priv_mode: M - reset-val: 0 - mcycle: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: - warl: - dependency_fields: [] - legal: - - mcycle[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - rv64: - accessible: false - description: Counts the number of clock cycles executed from an arbitrary - point in time. - address: 0xB00 - priv_mode: M - reset-val: 0 - mcycleh: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: - warl: - dependency_fields: [] - legal: - - mcycleh[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - rv64: - accessible: false - description: upper 32 bits of mcycle - address: 0xB80 - priv_mode: M - reset-val: 0 - minstret: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: - warl: - dependency_fields: [] - legal: - - minstret[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - rv64: - accessible: false - description: Counts the number of instructions completed from an arbitrary - point in time. - address: 0xB02 - priv_mode: M - reset-val: 0 - minstreth: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: - warl: - dependency_fields: [] - legal: - - minstreth[31:0] in [0x00000000:0xFFFFFFFF] - wr_illegal: - - unchanged - rv64: - accessible: false - description: Upper 32 bits of minstret. - address: 0xB82 - priv_mode: M - reset-val: 0 - mhpmevent3: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: &id001 - ro_constant: 0 - rv64: - accessible: false - description: The mhpmevent3 is a MXLEN-bit event register which controls mhpmcounter3. - address: 0x323 - priv_mode: M - reset-val: 0 - mhpmcounter3: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter3 is a 64-bit counter. Returns lower 32 bits in - RV32I mode. - address: 0xB03 - priv_mode: M - reset-val: 0 - mhpmcounter3h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: &id002 - ro_constant: 0 - rv64: - accessible: false - description: The mhpmcounter3h returns the upper half word in RV32I systems. - address: 0xB83 - priv_mode: M - reset-val: 0 - mhpmevent4: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent4 is a MXLEN-bit event register which controls mhpmcounter4. - address: 0x324 - priv_mode: M - reset-val: 0 - mhpmcounter4: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter4 is a 64-bit counter. Returns lower 42 bits in - RV42I mode. - address: 0xB04 - priv_mode: M - reset-val: 0 - mhpmcounter4h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter4h returns the upper half word in RV42I systems. - address: 0xB84 - priv_mode: M - reset-val: 0 - mhpmevent5: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent5 is a MXLEN-bit event register which controls mhpmcounter5. - address: 0x325 - priv_mode: M - reset-val: 0 - mhpmcounter5: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter5 is a 64-bit counter. Returns lower 52 bits in - RV52I mode. - address: 0xB05 - priv_mode: M - reset-val: 0 - mhpmcounter5h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter5h returns the upper half word in RV52I systems. - address: 0xB85 - priv_mode: M - reset-val: 0 - mhpmevent6: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent6 is a MXLEN-bit event register which controls mhpmcounter6. - address: 0x326 - priv_mode: M - reset-val: 0 - mhpmcounter6: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter6 is a 64-bit counter. Returns lower 62 bits in - RV62I mode. - address: 0xB06 - priv_mode: M - reset-val: 0 - mhpmcounter6h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter6h returns the upper half word in RV62I systems. - address: 0xB86 - priv_mode: M - reset-val: 0 - mhpmevent7: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent7 is a MXLEN-bit event register which controls mhpmcounter7. - address: 0x327 - priv_mode: M - reset-val: 0 - mhpmcounter7: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter7 is a 64-bit counter. Returns lower 72 bits in - RV72I mode. - address: 0xB07 - priv_mode: M - reset-val: 0 - mhpmcounter7h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter7h returns the upper half word in RV72I systems. - address: 0xB87 - priv_mode: M - reset-val: 0 - mhpmevent8: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent8 is a MXLEN-bit event register which controls mhpmcounter8. - address: 0x328 - priv_mode: M - reset-val: 0 - mhpmcounter8: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter8 is a 64-bit counter. Returns lower 82 bits in - RV82I mode. - address: 0xB08 - priv_mode: M - reset-val: 0 - mhpmcounter8h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter8h returns the upper half word in RV82I systems. - address: 0xB88 - priv_mode: M - reset-val: 0 - mhpmevent9: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent9 is a MXLEN-bit event register which controls mhpmcounter9. - address: 0x329 - priv_mode: M - reset-val: 0 - mhpmcounter9: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter9 is a 64-bit counter. Returns lower 32 bits in - RV32I mode. - address: 0xB09 - priv_mode: M - reset-val: 0 - mhpmcounter9h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter9h returns the upper half word in RV32I systems. - address: 0xB89 - priv_mode: M - reset-val: 0 - mhpmevent10: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent10 is a MXLEN-bit event register which controls - mhpmcounter10. - address: 0x32a - priv_mode: M - reset-val: 0 - mhpmcounter10: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter10 is a 64-bit counter. Returns lower 102 bits - in RV102I mode. - address: 0xB0A - priv_mode: M - reset-val: 0 - mhpmcounter10h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter10h returns the upper half word in RV102I systems. - address: 0xB8A - priv_mode: M - reset-val: 0 - mhpmevent11: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent11 is a MXLEN-bit event register which controls - mhpmcounter11. - address: 0x32b - priv_mode: M - reset-val: 0 - mhpmcounter11: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter11 is a 64-bit counter. Returns lower 112 bits - in RV112I mode. - address: 0xB0B - priv_mode: M - reset-val: 0 - mhpmcounter11h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter11h returns the upper half word in RV112I systems. - address: 0xB8B - priv_mode: M - reset-val: 0 - mhpmevent12: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent12 is a MXLEN-bit event register which controls - mhpmcounter12. - address: 0x32c - priv_mode: M - reset-val: 0 - mhpmcounter12: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter12 is a 64-bit counter. Returns lower 122 bits - in RV122I mode. - address: 0xB0C - priv_mode: M - reset-val: 0 - mhpmcounter12h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter12h returns the upper half word in RV122I systems. - address: 0xB8C - priv_mode: M - reset-val: 0 - mhpmevent13: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent13 is a MXLEN-bit event register which controls - mhpmcounter13. - address: 0x32d - priv_mode: M - reset-val: 0 - mhpmcounter13: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter13 is a 64-bit counter. Returns lower 132 bits - in RV132I mode. - address: 0xB0D - priv_mode: M - reset-val: 0 - mhpmcounter13h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter13h returns the upper half word in RV132I systems. - address: 0xB8D - priv_mode: M - reset-val: 0 - mhpmevent14: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent14 is a MXLEN-bit event register which controls - mhpmcounter14. - address: 0x32e - priv_mode: M - reset-val: 0 - mhpmcounter14: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter14 is a 64-bit counter. Returns lower 142 bits - in RV142I mode. - address: 0xB0E - priv_mode: M - reset-val: 0 - mhpmcounter14h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter14h returns the upper half word in RV142I systems. - address: 0xB8E - priv_mode: M - reset-val: 0 - mhpmevent15: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent15 is a MXLEN-bit event register which controls - mhpmcounter15. - address: 0x32f - priv_mode: M - reset-val: 0 - mhpmcounter15: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter15 is a 64-bit counter. Returns lower 152 bits - in RV152I mode. - address: 0xB0F - priv_mode: M - reset-val: 0 - mhpmcounter15h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter15h returns the upper half word in RV152I systems. - address: 0xB8F - priv_mode: M - reset-val: 0 - mhpmevent16: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent16 is a MXLEN-bit event register which controls - mhpmcounter16. - address: 0x330 - priv_mode: M - reset-val: 0 - mhpmcounter16: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter16 is a 64-bit counter. Returns lower 162 bits - in RV162I mode. - address: 0xB10 - priv_mode: M - reset-val: 0 - mhpmcounter16h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter16h returns the upper half word in RV162I systems. - address: 0xB90 - priv_mode: M - reset-val: 0 - mhpmevent17: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent17 is a MXLEN-bit event register which controls - mhpmcounter17. - address: 0x331 - priv_mode: M - reset-val: 0 - mhpmcounter17: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter17 is a 64-bit counter. Returns lower 172 bits - in RV172I mode. - address: 0xB11 - priv_mode: M - reset-val: 0 - mhpmcounter17h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter17h returns the upper half word in RV172I systems. - address: 0xB91 - priv_mode: M - reset-val: 0 - mhpmevent18: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent18 is a MXLEN-bit event register which controls - mhpmcounter18. - address: 0x332 - priv_mode: M - reset-val: 0 - mhpmcounter18: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter18 is a 64-bit counter. Returns lower 182 bits - in RV182I mode. - address: 0xB12 - priv_mode: M - reset-val: 0 - mhpmcounter18h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter18h returns the upper half word in RV182I systems. - address: 0xB92 - priv_mode: M - reset-val: 0 - mhpmevent19: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent19 is a MXLEN-bit event register which controls - mhpmcounter19. - address: 0x333 - priv_mode: M - reset-val: 0 - mhpmcounter19: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter19 is a 64-bit counter. Returns lower 32 bits - in RV32I mode. - address: 0xB13 - priv_mode: M - reset-val: 0 - mhpmcounter19h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter19h returns the upper half word in RV32I systems. - address: 0xB93 - priv_mode: M - reset-val: 0 - mhpmevent20: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent20 is a MXLEN-bit event register which controls - mhpmcounter20. - address: 0x334 - priv_mode: M - reset-val: 0 - mhpmcounter20: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter20 is a 64-bit counter. Returns lower 202 bits - in RV202I mode. - address: 0xB14 - priv_mode: M - reset-val: 0 - mhpmcounter20h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter20h returns the upper half word in RV202I systems. - address: 0xB94 - priv_mode: M - reset-val: 0 - mhpmevent21: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent21 is a MXLEN-bit event register which controls - mhpmcounter21. - address: 0x335 - priv_mode: M - reset-val: 0 - mhpmcounter21: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter21 is a 64-bit counter. Returns lower 212 bits - in RV212I mode. - address: 0xB15 - priv_mode: M - reset-val: 0 - mhpmcounter21h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter21h returns the upper half word in RV212I systems. - address: 0xB95 - priv_mode: M - reset-val: 0 - mhpmevent22: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent22 is a MXLEN-bit event register which controls - mhpmcounter22. - address: 0x336 - priv_mode: M - reset-val: 0 - mhpmcounter22: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter22 is a 64-bit counter. Returns lower 222 bits - in RV222I mode. - address: 0xB16 - priv_mode: M - reset-val: 0 - mhpmcounter22h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter22h returns the upper half word in RV222I systems. - address: 0xB96 - priv_mode: M - reset-val: 0 - mhpmevent23: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent23 is a MXLEN-bit event register which controls - mhpmcounter23. - address: 0x337 - priv_mode: M - reset-val: 0 - mhpmcounter23: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter23 is a 64-bit counter. Returns lower 232 bits - in RV232I mode. - address: 0xB17 - priv_mode: M - reset-val: 0 - mhpmcounter23h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter23h returns the upper half word in RV232I systems. - address: 0xB97 - priv_mode: M - reset-val: 0 - mhpmevent24: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent24 is a MXLEN-bit event register which controls - mhpmcounter24. - address: 0x338 - priv_mode: M - reset-val: 0 - mhpmcounter24: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter24 is a 64-bit counter. Returns lower 242 bits - in RV242I mode. - address: 0xB18 - priv_mode: M - reset-val: 0 - mhpmcounter24h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter24h returns the upper half word in RV242I systems. - address: 0xB98 - priv_mode: M - reset-val: 0 - mhpmevent25: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent25 is a MXLEN-bit event register which controls - mhpmcounter25. - address: 0x339 - priv_mode: M - reset-val: 0 - mhpmcounter25: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter25 is a 64-bit counter. Returns lower 252 bits - in RV252I mode. - address: 0xB19 - priv_mode: M - reset-val: 0 - mhpmcounter25h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter25h returns the upper half word in RV252I systems. - address: 0xB99 - priv_mode: M - reset-val: 0 - mhpmevent26: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent26 is a MXLEN-bit event register which controls - mhpmcounter26. - address: 0x33a - priv_mode: M - reset-val: 0 - mhpmcounter26: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter26 is a 64-bit counter. Returns lower 262 bits - in RV262I mode. - address: 0xB1A - priv_mode: M - reset-val: 0 - mhpmcounter26h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter26h returns the upper half word in RV262I systems. - address: 0xB9A - priv_mode: M - reset-val: 0 - mhpmevent27: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent27 is a MXLEN-bit event register which controls - mhpmcounter27. - address: 0x33b - priv_mode: M - reset-val: 0 - mhpmcounter27: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter27 is a 64-bit counter. Returns lower 272 bits - in RV272I mode. - address: 0xB1B - priv_mode: M - reset-val: 0 - mhpmcounter27h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter27h returns the upper half word in RV272I systems. - address: 0xB9B - priv_mode: M - reset-val: 0 - mhpmevent28: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent28 is a MXLEN-bit event register which controls - mhpmcounter28. - address: 0x33c - priv_mode: M - reset-val: 0 - mhpmcounter28: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter28 is a 64-bit counter. Returns lower 282 bits - in RV282I mode. - address: 0xB1C - priv_mode: M - reset-val: 0 - mhpmcounter28h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter28h returns the upper half word in RV282I systems. - address: 0xB9C - priv_mode: M - reset-val: 0 - mhpmevent29: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent29 is a MXLEN-bit event register which controls - mhpmcounter29. - address: 0x33d - priv_mode: M - reset-val: 0 - mhpmcounter29: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter29 is a 64-bit counter. Returns lower 32 bits - in RV32I mode. - address: 0xB1D - priv_mode: M - reset-val: 0 - mhpmcounter29h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter29h returns the upper half word in RV32I systems. - address: 0xB9D - priv_mode: M - reset-val: 0 - mhpmevent30: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent30 is a MXLEN-bit event register which controls - mhpmcounter30. - address: 0x33e - priv_mode: M - reset-val: 0 - mhpmcounter30: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter30 is a 64-bit counter. Returns lower 302 bits - in RV302I mode. - address: 0xB1E - priv_mode: M - reset-val: 0 - mhpmcounter30h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter30h returns the upper half word in RV302I systems. - address: 0xB9E - priv_mode: M - reset-val: 0 - mhpmevent31: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmevent31 is a MXLEN-bit event register which controls - mhpmcounter31. - address: 0x33f - priv_mode: M - reset-val: 0 - mhpmcounter31: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id001 - rv64: - accessible: false - description: The mhpmcounter31 is a 64-bit counter. Returns lower 312 bits - in RV312I mode. - address: 0xB1F - priv_mode: M - reset-val: 0 - mhpmcounter31h: - rv32: - accessible: true - fields: [] - shadow: - shadow_type: rw - msb: 31 - lsb: 0 - type: *id002 - rv64: - accessible: false - description: The mhpmcounter31h returns the upper half word in RV312I systems. - address: 0xB9F - priv_mode: M - reset-val: 0 - sedeleg: - rv32: - accessible: false - rv64: - accessible: false - description: sedeleg - address: 258 - priv_mode: S - reset-val: 0 - sideleg: - rv32: - accessible: false - rv64: - accessible: false - description: sideleg - priv_mode: S - address: 259 - reset-val: 0 - fflags: - rv32: - accessible: false - rv64: - accessible: false - description: 32-bit register to hold floating point accrued exceptions. - address: 001 - priv_mode: U - reset-val: 0 - frm: - rv32: - accessible: false - rv64: - accessible: false - description: 32-bit register to hold Floating-Point Dynamic Rounding Mode. - address: 002 - priv_mode: U - reset-val: 0 - fcsr: - rv32: - accessible: false - rv64: - accessible: false - description: 32-bit register to hold Floating-Point Control and Status Register. - address: 003 - priv_mode: U - reset-val: 0 - cycle: - rv32: - accessible: false - rv64: - accessible: false - description: Captures the number of cycles executed from an arbitrary point - in time. - priv_mode: U - address: 0xC00 - reset-val: 0 - cycleh: - rv32: - accessible: false - rv64: - accessible: false - description: Upper 32-bits of the mcycle counter; only for rv32. - address: 0xC80 - priv_mode: U - reset-val: 0 - time: - rv32: - accessible: false - rv64: - accessible: false - description: Timer for RDTIME instruction and RTC in the processor. - priv_mode: U - address: 0xC01 - reset-val: 0 - timeh: - rv32: - accessible: false - rv64: - accessible: false - description: Upper 32-bits of the Timer for RDTIME instruction and RTC in - the processor; only for rv32. - address: 0xC81 - priv_mode: U - reset-val: 0 - instret: - rv32: - accessible: false - rv64: - accessible: false - description: Captures the number of instructions executed from an arbitrary - point in time. - priv_mode: U - address: 0xC02 - reset-val: 0 - instreth: - rv32: - accessible: false - rv64: - accessible: false - description: Upper 32-bits of the minstret counter; only for rv32. - address: 0xC82 - priv_mode: U - reset-val: 0 - hpmcounter3: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter3 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC03 - hpmcounter4: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter4 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC04 - hpmcounter5: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter5 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC05 - hpmcounter6: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter6 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC06 - hpmcounter7: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter7 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC07 - hpmcounter8: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter8 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC08 - hpmcounter9: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter9 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC09 - hpmcounter10: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter10 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC0A - hpmcounter11: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter11 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC0B - hpmcounter12: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter12 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC0C - hpmcounter13: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter13 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC0D - hpmcounter14: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter14 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC0E - hpmcounter15: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter15 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC0F - hpmcounter16: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter16 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC10 - hpmcounter17: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter17 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC11 - hpmcounter18: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter18 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC12 - hpmcounter19: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter19 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC13 - hpmcounter20: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter20 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC14 - hpmcounter21: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter21 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC15 - hpmcounter22: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter22 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC16 - hpmcounter23: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter23 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC17 - hpmcounter24: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter24 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC18 - hpmcounter25: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter25 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC19 - hpmcounter26: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter26 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC1A - hpmcounter27: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter27 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC1B - hpmcounter28: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter28 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC1C - hpmcounter29: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter29 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC1D - hpmcounter30: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter30 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC1E - hpmcounter31: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter31 is a 64-bit counter. Returns lower 32 bits in - RV32UI mode. - address: 0xC1F - hpmcounter3h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter3h returns the upper half word in RV32I systems. - address: 0xC83 - hpmcounter4h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter4h returns the upper half word in RV32I systems. - address: 0xC84 - hpmcounter5h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter5h returns the upper half word in RV32I systems. - address: 0xC85 - hpmcounter6h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter6h returns the upper half word in RV32I systems. - address: 0xC86 - hpmcounter7h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter7h returns the upper half word in RV32I systems. - address: 0xC87 - hpmcounter8h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter8h returns the upper half word in RV32I systems. - address: 0xC88 - hpmcounter9h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter9h returns the upper half word in RV32I systems. - address: 0xC89 - hpmcounter10h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter10h returns the upper half word in RV32I systems. - address: 0xC8A - hpmcounter11h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter11h returns the upper half word in RV32I systems. - address: 0xC8B - hpmcounter12h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter12h returns the upper half word in RV32I systems. - address: 0xC8C - hpmcounter13h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter13h returns the upper half word in RV32I systems. - address: 0xC8D - hpmcounter14h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter14h returns the upper half word in RV32I systems. - address: 0xC8E - hpmcounter15h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter15h returns the upper half word in RV32I systems. - address: 0xC8F - hpmcounter16h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter16h returns the upper half word in RV32I systems. - address: 0xC90 - hpmcounter17h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter17h returns the upper half word in RV32I systems. - address: 0xC91 - hpmcounter18h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter18h returns the upper half word in RV32I systems. - address: 0xC92 - hpmcounter19h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter19h returns the upper half word in RV32I systems. - address: 0xC93 - hpmcounter20h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter20h returns the upper half word in RV32I systems. - address: 0xC94 - hpmcounter21h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter21h returns the upper half word in RV32I systems. - address: 0xC95 - hpmcounter22h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter22h returns the upper half word in RV32I systems. - address: 0xC96 - hpmcounter23h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter23h returns the upper half word in RV32I systems. - address: 0xC97 - hpmcounter24h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter24h returns the upper half word in RV32I systems. - address: 0xC98 - hpmcounter25h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter25h returns the upper half word in RV32I systems. - address: 0xC99 - hpmcounter26h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter26h returns the upper half word in RV32I systems. - address: 0xC9A - hpmcounter27h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter27h returns the upper half word in RV32I systems. - address: 0xC9B - hpmcounter28h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter28h returns the upper half word in RV32I systems. - address: 0xC9C - hpmcounter29h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter29h returns the upper half word in RV32I systems. - address: 0xC9D - hpmcounter30h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter30h returns the upper half word in RV32I systems. - address: 0xC9E - hpmcounter31h: - rv32: - accessible: false - rv64: - accessible: false - priv_mode: U - reset-val: 0 - description: The hpmcounter31h returns the upper half word in RV32I systems. - address: 0xC9F - sstatus: - rv32: - accessible: false - rv64: - accessible: false - description: The sstatus register keeps track of the processor’s current operating - state. - address: 0x100 - priv_mode: S - reset-val: 0 - sie: - rv32: - accessible: false - rv64: - accessible: false - description: The sie register is an SXLEN-bit read/write register containing - interrupt enable bits. - address: 0x104 - priv_mode: S - reset-val: 0 - sip: - rv32: - accessible: false - rv64: - accessible: false - description: The sip register is an SXLEN-bit read/write register containing - interrupt pending bits. - address: 0x144 - priv_mode: S - reset-val: 0 - sscratch: - rv32: - accessible: false - rv64: - accessible: false - description: The sscratch register is an MXLEN-bit read/write register dedicated - for use by machine mode. - address: 0x140 - priv_mode: S - reset-val: 0 - sepc: - rv32: - accessible: false - rv64: - accessible: false - description: The sepc is a warl register that must be able to hold all valid - physical and virtual addresses. - address: 0x141 - priv_mode: S - reset-val: 0 - stval: - rv32: - accessible: false - rv64: - accessible: false - description: The stval is a warl register that holds the address of the instruction - which caused the exception. - address: 0x143 - priv_mode: S - reset-val: 0 - scause: - rv32: - accessible: false - rv64: - accessible: false - description: The scause register stores the information regarding the trap. - address: 0x142 - priv_mode: S - reset-val: 0 - stvec: - rv32: - accessible: false - rv64: - accessible: false - description: SXLEN-bit read/write register that holds trap vector configuration. - address: 0x105 - priv_mode: S - reset-val: 0 - satp: - rv32: - accessible: false - rv64: - accessible: false - description: SXLEN-bit register which controls supervisor-mode address translation - and protection - address: 0x180 - priv_mode: S - reset-val: 0 - ustatus: - rv32: - accessible: false - rv64: - accessible: false - description: The ustatus register keeps track of the processor’s current operating - state. - address: 0x000 - priv_mode: U - reset-val: 0 - uie: - rv32: - accessible: false - rv64: - accessible: false - description: The uie register is an UXLEN-bit read/write register containing - interrupt enable bits. - address: 0x004 - priv_mode: U - reset-val: 0 - uip: - rv32: - accessible: false - rv64: - accessible: false - description: The uip register is an UXLEN-bit read/write register containing - interrupt pending bits. - address: 0x044 - priv_mode: U - reset-val: 0 - uscratch: - rv32: - accessible: false - rv64: - accessible: false - description: The uscratch register is an UXLEN-bit read/write register dedicated - for use by machine mode. - address: 0x040 - priv_mode: U - reset-val: 0 - uepc: - rv32: - accessible: false - rv64: - accessible: false - description: The uepc is a warl register that must be able to hold all valid - physical and virtual addresses. - address: 0x041 - priv_mode: U - reset-val: 0 - utval: - rv32: - accessible: false - rv64: - accessible: false - description: The utval is a warl register that holds the address of the instruction - which caused the exception. - address: 0x043 - priv_mode: U - reset-val: 0 - ucause: - rv32: - accessible: false - rv64: - accessible: false - description: The ucause register stores the information regarding the trap. - address: 0x042 - priv_mode: U - reset-val: 0 - utvec: - rv32: - accessible: false - rv64: - accessible: false - description: UXLEN-bit read/write register that holds trap vector configuration. - address: 0x005 - priv_mode: U - reset-val: 0 - scounteren: - rv32: - accessible: false - rv64: - accessible: false - description: The scounteren is a 32-bit register that controls the availability - of the hardware performance-monitoring counters to the next-lowest privileged - mode. - address: 0x106 - priv_mode: S - reset-val: 0 - hstatus: - rv32: - accessible: false - rv64: - accessible: false - description: The hstatus register keeps track of and controls the hart’s current - operating state. - address: 1536 - priv_mode: H - reset-val: 0 - hideleg: - rv32: - accessible: false - rv64: - accessible: false - description: Hypervisor Interrupt delegation Register. - address: 1539 - priv_mode: H - reset-val: 0 - hedeleg: - rv32: - accessible: false - rv64: - accessible: false - description: Hypervisor Exception delegation Register. - address: 1538 - priv_mode: H - reset-val: 0 - hip: - rv32: - accessible: false - rv64: - accessible: false - description: The hip register is an HXLEN-bit read/write register containing - information on pending interrupts. - address: 1604 - priv_mode: H - reset-val: 0 - hvip: - rv32: - accessible: false - rv64: - accessible: false - description: The hvip register is an HSXLEN-bit read/write register that a - hypervisor can write to indicate virtual interrupts intended for VS-mode. - address: 1605 - priv_mode: H - reset-val: 0 - hgeip: - rv32: - accessible: false - rv64: - accessible: false - description: The hgeip register is an HSXLEN-bit read-only register that indicates - pending guest external interrupts for this hart. - address: 0xE12 - priv_mode: H - reset-val: 0 - hgeie: - rv32: - accessible: false - rv64: - accessible: false - description: The hgeie register is an HSXLEN-bit read/write register that - contains enable bits for the guest external interrupts at this hart. - address: 0x607 - priv_mode: H - reset-val: 0 - htval: - rv32: - accessible: false - rv64: - accessible: false - description: The htval is a warl register that holds the address of the instruction - which caused the exception. - address: 0x643 - priv_mode: H - reset-val: 0 - htinst: - rv32: - accessible: false - rv64: - accessible: false - description: The htinst is a warl register that need only be able to hold - the values that the implementation may automatically write to it on a - trap. - address: 0x64A - priv_mode: H - reset-val: 0 - mtval2: - rv32: - accessible: false - rv64: - accessible: false - description: When a trap is taken into M-mode, mtval2 is written with additional - exception-specific information to assist software in handling the trap. - address: 0x34B - priv_mode: M - reset-val: 0 - mtinst: - rv32: - accessible: false - rv64: - accessible: false - description: The mtinst is a warl register that need only be able to hold - the values that the implementation may automatically write to it on a - trap. - address: 0x34A - priv_mode: M - reset-val: 0 - hgatp: - rv32: - accessible: false - rv64: - accessible: false - description: HSXLEN-bit register which controls G-stage address translation - and protection - address: 0x680 - priv_mode: H - reset-val: 0 - hcounteren: - rv32: - accessible: false - rv64: - accessible: false - description: The hcounteren is a 32-bit register that controls the availability - of the hardware performance-monitoring counters to the next-lowest privileged - mode. - address: 0x606 - priv_mode: H - reset-val: 0 - htimedelta: - rv32: - accessible: false - rv64: - accessible: false - description: The htimedelta CSR is a read/write register that contains the - delta between the value of the time CSR and the value returned in VS-mode - or VU-mode. - priv_mode: H - address: 0x605 - reset-val: 0 - htimedeltah: - rv32: - accessible: false - rv64: - accessible: false - description: Upper 32-bits of htimedelta - address: 0x615 - priv_mode: H - reset-val: 0 - vsstatus: - rv32: - accessible: false - rv64: - accessible: false - description: The vsstatus register keeps track of the processor’s current - operating state. - address: 0x200 - priv_mode: S - reset-val: 0 - vsie: - rv32: - accessible: false - rv64: - accessible: false - description: The vsie register is an VSXLEN-bit read/write register containing - interrupt enable bits. - address: 0x204 - priv_mode: S - reset-val: 0 - vsip: - rv32: - accessible: false - rv64: - accessible: false - description: The vsip register is an VSXLEN-bit read/write register containing - interrupt pending bits. - address: 0x244 - priv_mode: S - reset-val: 0 - vsscratch: - rv32: - accessible: false - rv64: - accessible: false - description: The vsscratch register is an VSXLEN-bit read/write register dedicated - for use by machine mode. - address: 0x240 - priv_mode: S - reset-val: 0 - vsepc: - rv32: - accessible: false - rv64: - accessible: false - description: The vsepc is a warl register that must be able to hold all valid - physical and virtual addresses. - address: 0x241 - priv_mode: S - reset-val: 0 - vstval: - rv32: - accessible: false - rv64: - accessible: false - description: The vstval is a warl register that holds the address of the instruction - which caused the exception. - address: 0x243 - priv_mode: S - reset-val: 0 - vscause: - rv32: - accessible: false - rv64: - accessible: false - description: The scause register stores the information regarding the trap. - address: 0x242 - priv_mode: S - reset-val: 0 - vstvec: - rv32: - accessible: false - rv64: - accessible: false - description: SXLEN-bit read/write register that holds trap vector configuration. - address: 0x205 - priv_mode: S - reset-val: 0 - vsatp: - rv32: - accessible: false - rv64: - accessible: false - description: VSXLEN-bit register which controls supervisor-mode address translation - and protection - address: 0x280 - priv_mode: S - reset-val: 0 - vxsat: - rv32: - accessible: false - rv64: - accessible: false - description: The vxsat register records the overflow saturation condition - of P and V instructions. - address: 9 - priv_mode: U - reset-val: 0 - mnscratch: - rv32: - accessible: false - rv64: - accessible: false - description: |- - The mnscratch CSR holds an MXLEN-bit read-write register which enables the NMI trap - handler to save and restore the context that was interrupted. - address: 0x740 - priv_mode: M - reset-val: 0 - mnepc: - rv32: - accessible: false - rv64: - accessible: false - description: |- - The mnepc CSR is an MXLEN-bit read-write register which on entry to the NMI trap handler holds - the PC of the instruction that took the interrupt. - - The low bit of mnepc (mnepc[0]) is always zero. On implementations that support only - IALIGN=32, the two low bits (mnepc[1:0]) are always zero. - - If an implementation allows IALIGN to be either 16 or 32 (by changing CSR misa, for example), - then, whenever IALIGN=32, bit mnepc[1] is masked on reads so that it appears to be 0. This - masking occurs also for the implicit read by the MRET instruction. Though masked, mnepc[1] - remains writable when IALIGN=32. - - mnepc is a WARL register that must be able to hold all valid virtual addresses. It need not be - capable of holding all possible invalid addresses. Prior to writing mnepc, implementations may - convert an invalid address into some other invalid address that mnepc is capable of holding. - address: 0x741 - priv_mode: M - reset-val: 0 - mncause: - rv32: - accessible: false - rv64: - accessible: false - description: |- - The mncause CSR holds the reason for the NMI, with bit MXLEN-1 set to 1, - and the NMI cause encoded in the least-significant bits or zero if NMI causes are not supported. - address: 0x742 - priv_mode: M - reset-val: 2147483648 - mnstatus: - rv32: - accessible: false - rv64: - accessible: false - description: |2- - - The mnstatus CSR holds a two-bit field, MNPP, which on entry to the trap handler holds the - privilege mode of the interrupted context, encoded in the same manner as mstatus.MPP. It also - - holds a one-bit field, MNPV, which on entry to the trap handler holds the virtualization mode of - the interrupted context, encoded in the same manner as mstatus.MPV. - mnstatus also holds the NMIE bit. When NMIE=1, nonmaskable interrupts are enabled. When - NMIE=0, all interrupts are disabled. - When NMIE=0, the hart behaves as though mstatus.MPRV were clear, regardless of the current - setting of mstatus.MPRV. - - Upon reset, NMIE contains the value 0. - address: 0x744 - priv_mode: M - reset-val: 0 diff --git a/riscof_work/spike_simple_platform_checked.yaml b/riscof_work/spike_simple_platform_checked.yaml deleted file mode 100644 index 83f665106..000000000 --- a/riscof_work/spike_simple_platform_checked.yaml +++ /dev/null @@ -1,18 +0,0 @@ -mtime: - implemented: true - address: 0xbff8 -mtimecmp: - implemented: true - address: 0x4000 -nmi: - label: nmi_vector -reset: - label: reset_vector -mtval_condition_writes: - implemented: false -scause_non_standard: - implemented: false -stval_condition_writes: - implemented: false -zicbo_cache_block_sz: - implemented: false diff --git a/riscof_work/src/ebreak.S/dut/DUT-Spike.signature b/riscof_work/src/ebreak.S/dut/DUT-Spike.signature deleted file mode 100644 index 6cd1e67e4..000000000 --- a/riscof_work/src/ebreak.S/dut/DUT-Spike.signature +++ /dev/null @@ -1,8 +0,0 @@ -6f5ca309 -00000000 -11111111 -000008d3 -00000003 -0000003c -0000003c -6f5ca309 diff --git a/riscof_work/src/ebreak.S/dut/my.elf b/riscof_work/src/ebreak.S/dut/my.elf deleted file mode 100755 index 407f6ae114e2a4693db1a952c53193ddc24a2fb4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 20976 zcmeI44Qw0b8ONW?*=<@%Nw}n+Au*iWb%;f29aN!dnzJN)NVN!!+rcOp_v|EY;}3k7 zH0}7f&dJ0iCbe8kOIsj}vQvV0c}WHg;MJM-}|s% zO3Rppgv9QZUO&(8dET#k?zz|Ji{txSmt8Li0y(9O#>pnV5yri3WO5_%g*}uXx>Uh-$rxCI0WhU57zt7Zlu0ZUo#2xDjw8;6}iWfExif0$*JOX3Ip9D3XLBFI3eku~A->t1qXS|CVuU9~nQ~F693?Nzxn8N45)r#K&aZwjTCJg#5ogCh2d`M;;LZ zYtE4IqYbd{5c0>*ko0%xBRhn^+E2*1{l~EH6!QQ6grqm2kL(lz-Dk;Ibr0;jg#7zw zNqP(V$Sxs}{FID4?uGqPA^*XrB)tuNBQ;5DJ8q^E$Ks^l1`i+6iar!tfUVKC7n1uNb-Ul!rZ(lbh<4pNcnP zZxNI`y=78WHAxLuQtySkrx3m7qlgENT|sV3t&~58JRi8$+>_+1o+M?Nw`zO=HAq{IkrKxG z76{iFhkirGL?hN*1=&J|_nWQR|5UH zAog3#_fo-tUENgOI4(CdNqy%A>p_V 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- --trace-output - -l --inst-limit - -x --enable-zfinx - --enable-writable-fiom - --enable-svinval - --enable-zcb diff --git a/riscof_work/src/ebreak.S/ref/ref.disass b/riscof_work/src/ebreak.S/ref/ref.disass deleted file mode 100644 index 8009f5fc4..000000000 --- a/riscof_work/src/ebreak.S/ref/ref.disass +++ /dev/null @@ -1,959 +0,0 @@ - -ref.elf: file format elf32-littleriscv - - -Disassembly of section .text.init: - -80000000 : -80000000: 00002317 auipc t1,0x2 -80000004: 00030313 mv t1,t1 -80000008: 00000013 nop -8000000c: 00000013 nop -80000010: 00000013 nop -80000014: 00000013 nop -80000018: 00000013 nop -8000001c: 00000013 nop - -80000020 : -80000020: 34031473 csrrw s0,mscratch,t1 -80000024: 1c832823 sw s0,464(t1) # 800021d0 - -80000028 : -80000028: 00000393 li t2,0 -8000002c: 1a732c23 sw t2,440(t1) - -80000030 : -80000030: 30502473 csrr s0,mtvec -80000034: 1c832423 sw s0,456(t1) -80000038: 00347393 and t2,s0,3 -8000003c: 1b032483 lw s1,432(t1) -80000040: eac48493 add s1,s1,-340 -80000044: 0074e3b3 or t2,s1,t2 -80000048: 1c732023 sw t2,448(t1) -8000004c: 30539073 csrw mtvec,t2 -80000050: 30502573 csrr a0,mtvec -80000054: 08750863 beq a0,t2,800000e4 -80000058: 30541073 csrw mtvec,s0 -8000005c: 04040663 beqz s0,800000a8 -80000060: 1c832023 sw s0,448(t1) - -80000064 : -80000064: ffc47393 and t2,s0,-4 -80000068: 15438413 add s0,t2,340 - -8000006c : -8000006c: 0003a583 lw a1,0(t2) -80000070: 00b32023 sw a1,0(t1) -80000074: 0004a503 lw a0,0(s1) -80000078: 00a3a023 sw a0,0(t2) -8000007c: 0003a583 lw a1,0(t2) -80000080: 00a59a63 bne a1,a0,80000094 -80000084: 00438393 add t2,t2,4 -80000088: 00430313 add t1,t1,4 -8000008c: 00448493 add s1,s1,4 -80000090: fc741ee3 bne s0,t2,8000006c - -80000094 : -80000094: 00000013 nop -80000098: 34002373 csrr t1,mscratch -8000009c: 1a732423 sw t2,424(t1) -800000a0: 1a932823 sw s1,432(t1) -800000a4: 04740063 beq s0,t2,800000e4 - -800000a8 : -800000a8: 00000013 nop -800000ac: 00000013 nop -800000b0: 00000013 nop -800000b4: 00000013 nop -800000b8: 00000013 nop -800000bc: 00000013 nop -800000c0: 00000597 auipc a1,0x0 -800000c4: 1c458593 add a1,a1,452 # 80000284 -800000c8: 00000013 nop -800000cc: 00000013 nop -800000d0: 00000013 nop -800000d4: 00000013 nop -800000d8: 00000013 nop -800000dc: 00000013 nop -800000e0: 00058067 jr a1 - -800000e4 : -800000e4: 7d5c0837 lui a6,0x7d5c0 -800000e8: ddb80813 add a6,a6,-549 # 7d5bfddb -800000ec: 00785893 srl a7,a6,0x7 -800000f0: 01985793 srl a5,a6,0x19 -800000f4: 00f8e8b3 or a7,a7,a5 -800000f8: 0078d913 srl s2,a7,0x7 -800000fc: 0198d793 srl a5,a7,0x19 -80000100: 00f96933 or s2,s2,a5 -80000104: 00795993 srl s3,s2,0x7 -80000108: 01995793 srl a5,s2,0x19 -8000010c: 00f9e9b3 or s3,s3,a5 -80000110: 0079da13 srl s4,s3,0x7 -80000114: 0199d793 srl a5,s3,0x19 -80000118: 00fa6a33 or s4,s4,a5 -8000011c: 007a5a93 srl s5,s4,0x7 -80000120: 019a5793 srl a5,s4,0x19 -80000124: 00faeab3 or s5,s5,a5 -80000128: 007adb13 srl s6,s5,0x7 -8000012c: 019ad793 srl a5,s5,0x19 -80000130: 00fb6b33 or s6,s6,a5 -80000134: 007b5b93 srl s7,s6,0x7 -80000138: 019b5793 srl a5,s6,0x19 -8000013c: 00fbebb3 or s7,s7,a5 -80000140: 007bdc13 srl s8,s7,0x7 -80000144: 019bd793 srl a5,s7,0x19 -80000148: 00fc6c33 or s8,s8,a5 -8000014c: 007c5c93 srl s9,s8,0x7 -80000150: 019c5793 srl a5,s8,0x19 -80000154: 00fcecb3 or s9,s9,a5 -80000158: 007cdd13 srl s10,s9,0x7 -8000015c: 019cd793 srl a5,s9,0x19 -80000160: 00fd6d33 or s10,s10,a5 -80000164: 007d5d93 srl s11,s10,0x7 -80000168: 019d5793 srl a5,s10,0x19 -8000016c: 00fdedb3 or s11,s11,a5 -80000170: 007dde13 srl t3,s11,0x7 -80000174: 019dd793 srl a5,s11,0x19 -80000178: 00fe6e33 or t3,t3,a5 -8000017c: 007e5e93 srl t4,t3,0x7 -80000180: 019e5793 srl a5,t3,0x19 -80000184: 00feeeb3 or t4,t4,a5 -80000188: 007edf13 srl t5,t4,0x7 -8000018c: 019ed793 srl a5,t4,0x19 -80000190: 00ff6f33 or t5,t5,a5 -80000194: feedc0b7 lui ra,0xfeedc -80000198: ead08093 add ra,ra,-339 # feedbead <_end+0x7eed8d7d> -8000019c: 0070d113 srl sp,ra,0x7 -800001a0: 0190d793 srl a5,ra,0x19 -800001a4: 00f16133 or sp,sp,a5 -800001a8: 00715193 srl gp,sp,0x7 -800001ac: 01915793 srl a5,sp,0x19 -800001b0: 00f1e1b3 or gp,gp,a5 -800001b4: 0071d213 srl tp,gp,0x7 -800001b8: 0191d793 srl a5,gp,0x19 -800001bc: 00f26233 or tp,tp,a5 -800001c0: 00725293 srl t0,tp,0x7 -800001c4: 01925793 srl a5,tp,0x19 -800001c8: 00f2e2b3 or t0,t0,a5 -800001cc: 0072d313 srl t1,t0,0x7 -800001d0: 0192d793 srl a5,t0,0x19 -800001d4: 00f36333 or t1,t1,a5 -800001d8: 00735393 srl t2,t1,0x7 -800001dc: 01935793 srl a5,t1,0x19 -800001e0: 00f3e3b3 or t2,t2,a5 -800001e4: 0073d413 srl s0,t2,0x7 -800001e8: 0193d793 srl a5,t2,0x19 -800001ec: 00f46433 or s0,s0,a5 -800001f0: 00745493 srl s1,s0,0x7 -800001f4: 01945793 srl a5,s0,0x19 -800001f8: 00f4e4b3 or s1,s1,a5 -800001fc: 0074d513 srl a0,s1,0x7 -80000200: 0194d793 srl a5,s1,0x19 -80000204: 00f56533 or a0,a0,a5 -80000208: 00755593 srl a1,a0,0x7 -8000020c: 01955793 srl a5,a0,0x19 -80000210: 00f5e5b3 or a1,a1,a5 -80000214: 0075d613 srl a2,a1,0x7 -80000218: 0195d793 srl a5,a1,0x19 -8000021c: 00f66633 or a2,a2,a5 -80000220: 00765693 srl a3,a2,0x7 -80000224: 01965793 srl a5,a2,0x19 -80000228: 00f6e6b3 or a3,a3,a5 - -8000022c : -8000022c: 00000013 nop -80000230: 00000013 nop -80000234: 00000013 nop -80000238: 00000013 nop -8000023c: 00000013 nop -80000240: 00003097 auipc ra,0x3 -80000244: ed408093 add ra,ra,-300 # 80003114 -80000248: 00000013 nop -8000024c: 00000013 nop -80000250: 00000013 nop -80000254: 00000013 nop -80000258: 00000013 nop -8000025c: 00000013 nop -80000260: 11111137 lui sp,0x11111 -80000264: 11110113 add sp,sp,273 # 11111111 -80000268: 00100073 ebreak -8000026c: 00000013 nop -80000270: 00000013 nop -80000274: 0000a023 sw zero,0(ra) -80000278: 0020a223 sw sp,4(ra) - -8000027c : -8000027c: 00000113 li sp,0 -80000280: 00000073 ecall - -80000284 : -80000284: 34002373 csrr t1,mscratch - -80000288 : -80000288: 1b832383 lw t2,440(t1) - -8000028c : -8000028c: 1d032503 lw a0,464(t1) -80000290: 34051073 csrw mscratch,a0 - -80000294 : -80000294: 1c832483 lw s1,456(t1) -80000298: 305493f3 csrrw t2,mtvec,s1 -8000029c: ffc4f493 and s1,s1,-4 -800002a0: ffc3f393 and t2,t2,-4 -800002a4: 02749063 bne s1,t2,800002c4 - -800002a8 : -800002a8: 00030493 mv s1,t1 -800002ac: 1a832403 lw s0,424(t1) - -800002b0 : -800002b0: 0004a583 lw a1,0(s1) -800002b4: 00b3a023 sw a1,0(t2) -800002b8: 00438393 add t2,t2,4 -800002bc: 00448493 add s1,s1,4 -800002c0: fe83c8e3 blt t2,s0,800002b0 - -800002c4 : -800002c4: 6880006f j 8000094c - -800002c8 : -800002c8: 17812483 lw s1,376(sp) -800002cc: 18012303 lw t1,384(sp) -800002d0: 00930333 add t1,t1,s1 -800002d4: bad0e337 lui t1,0xbad0e -800002d8: ad030313 add t1,t1,-1328 # bad0dad0 <_end+0x3ad0a9a0> -800002dc: fe64ae23 sw t1,-4(s1) -800002e0: 66c0006f j 8000094c -800002e4: 00000013 nop -800002e8: 00000013 nop -800002ec: 00000013 nop -800002f0: 00000013 nop -800002f4: 00000013 nop -800002f8: 00000013 nop -800002fc: 00000013 nop - -80000300 : -80000300: 0800006f j 80000380 -80000304: 0880006f j 8000038c -80000308: 0900006f j 80000398 -8000030c: 0980006f j 800003a4 -80000310: 0a00006f j 800003b0 -80000314: 0a80006f j 800003bc -80000318: 0b00006f j 800003c8 -8000031c: 0b80006f j 800003d4 -80000320: 0c00006f j 800003e0 -80000324: 0c80006f j 800003ec -80000328: 0d00006f j 800003f8 -8000032c: 0d80006f j 80000404 -80000330: 0e00006f j 80000410 -80000334: 0e80006f j 8000041c -80000338: 0f00006f j 80000428 -8000033c: 0f80006f j 80000434 -80000340: 1600006f j 800004a0 -80000344: 15c0006f j 800004a0 -80000348: 1580006f j 800004a0 -8000034c: 1540006f j 800004a0 -80000350: 1500006f j 800004a0 -80000354: 14c0006f j 800004a0 -80000358: 1480006f j 800004a0 -8000035c: 1440006f j 800004a0 -80000360: 1400006f j 800004a0 -80000364: 13c0006f j 800004a0 -80000368: 1380006f j 800004a0 -8000036c: 1340006f j 800004a0 -80000370: 1300006f j 800004a0 -80000374: 12c0006f j 800004a0 -80000378: 1280006f j 800004a0 -8000037c: 1240006f j 800004a0 - -80000380 : -80000380: 34011173 csrrw sp,mscratch,sp -80000384: 1eb12823 sw a1,496(sp) -80000388: 0b8005ef jal a1,80000440 -8000038c: 34011173 csrrw sp,mscratch,sp -80000390: 1eb12823 sw a1,496(sp) -80000394: 0ac005ef jal a1,80000440 -80000398: 34011173 csrrw sp,mscratch,sp -8000039c: 1eb12823 sw a1,496(sp) -800003a0: 0a0005ef jal a1,80000440 -800003a4: 34011173 csrrw sp,mscratch,sp -800003a8: 1eb12823 sw a1,496(sp) -800003ac: 094005ef jal a1,80000440 -800003b0: 34011173 csrrw sp,mscratch,sp -800003b4: 1eb12823 sw a1,496(sp) -800003b8: 088005ef jal a1,80000440 -800003bc: 34011173 csrrw sp,mscratch,sp -800003c0: 1eb12823 sw a1,496(sp) -800003c4: 07c005ef jal a1,80000440 -800003c8: 34011173 csrrw sp,mscratch,sp -800003cc: 1eb12823 sw a1,496(sp) -800003d0: 070005ef jal a1,80000440 -800003d4: 34011173 csrrw sp,mscratch,sp -800003d8: 1eb12823 sw a1,496(sp) -800003dc: 064005ef jal a1,80000440 -800003e0: 34011173 csrrw sp,mscratch,sp -800003e4: 1eb12823 sw a1,496(sp) -800003e8: 058005ef jal a1,80000440 -800003ec: 34011173 csrrw sp,mscratch,sp -800003f0: 1eb12823 sw a1,496(sp) -800003f4: 04c005ef jal a1,80000440 -800003f8: 34011173 csrrw sp,mscratch,sp -800003fc: 1eb12823 sw a1,496(sp) -80000400: 040005ef jal a1,80000440 -80000404: 34011173 csrrw sp,mscratch,sp -80000408: 1eb12823 sw a1,496(sp) -8000040c: 034005ef jal a1,80000440 -80000410: 34011173 csrrw sp,mscratch,sp -80000414: 1eb12823 sw a1,496(sp) -80000418: 028005ef jal a1,80000440 -8000041c: 34011173 csrrw sp,mscratch,sp -80000420: 1eb12823 sw a1,496(sp) -80000424: 01c005ef jal a1,80000440 -80000428: 34011173 csrrw sp,mscratch,sp -8000042c: 1eb12823 sw a1,496(sp) -80000430: 010005ef jal a1,80000440 -80000434: 34011173 csrrw sp,mscratch,sp -80000438: 1eb12823 sw a1,496(sp) -8000043c: 004005ef jal a1,80000440 - -80000440 : -80000440: 1ea12623 sw a0,492(sp) -80000444: 34011573 csrrw a0,mscratch,sp -80000448: 1ea12a23 sw a0,500(sp) -8000044c: 1b012503 lw a0,432(sp) -80000450: 00050067 jr a0 - -80000454 : -80000454: 1e912423 sw s1,488(sp) -80000458: 1e812223 sw s0,484(sp) -8000045c: 1e712023 sw t2,480(sp) -80000460: 1c612e23 sw t1,476(sp) - -80000464 : -80000464: 34202573 csrr a0,mcause -80000468: 800014b7 lui s1,0x80001 -8000046c: ffc48493 add s1,s1,-4 # 80000ffc -80000470: 00a4f4b3 and s1,s1,a0 -80000474: ff848493 add s1,s1,-8 -80000478: 00049663 bnez s1,80000484 -8000047c: 1f412383 lw t2,500(sp) -80000480: 48038663 beqz t2,8000090c - -80000484 : -80000484: 01000393 li t2,16 -80000488: 02055e63 bgez a0,800004c4 - -8000048c : -8000048c: 00151413 sll s0,a0,0x1 -80000490: ff240413 add s0,s0,-14 -80000494: 04045063 bgez s0,800004d4 -80000498: 00c00393 li t2,12 -8000049c: 0380006f j 800004d4 - -800004a0 : -800004a0: 00000317 auipc t1,0x0 -800004a4: e2430313 add t1,t1,-476 # 800002c4 -800004a8: 00000013 nop -800004ac: 00000013 nop -800004b0: 00000013 nop -800004b4: 00000013 nop -800004b8: 00000013 nop -800004bc: 00000013 nop -800004c0: 00030067 jr t1 - -800004c4 : -800004c4: 30102373 csrr t1,misa -800004c8: 01831313 sll t1,t1,0x18 -800004cc: 00035463 bgez t1,800004d4 -800004d0: 01800393 li t2,24 - -800004d4 : -800004d4: 19812303 lw t1,408(sp) -800004d8: 007304b3 add s1,t1,t2 -800004dc: 18912c23 sw s1,408(sp) -800004e0: 17812403 lw s0,376(sp) -800004e4: 40830333 sub t1,t1,s0 -800004e8: 17812403 lw s0,376(sp) -800004ec: 00830333 add t1,t1,s0 -800004f0: 1c012403 lw s0,448(sp) - -800004f4 : -800004f4: 408585b3 sub a1,a1,s0 -800004f8: 00459593 sll a1,a1,0x4 -800004fc: 0075e5b3 or a1,a1,t2 -80000500: 00358593 add a1,a1,3 -80000504: 00b32023 sw a1,0(t1) - -80000508 : -80000508: 00a32223 sw a0,4(t1) -8000050c: 14054c63 bltz a0,80000664 - -80000510 : -80000510: 300025f3 csrr a1,mstatus -80000514: 00e59413 sll s0,a1,0xe -80000518: 00045463 bgez s0,80000520 -8000051c: 39012583 lw a1,912(sp) -80000520: 00b5d493 srl s1,a1,0xb -80000524: 0034f493 and s1,s1,3 -80000528: 00148493 add s1,s1,1 -8000052c: 0044f493 and s1,s1,4 -80000530: 05d00593 li a1,93 -80000534: 0095d5b3 srl a1,a1,s1 -80000538: 0015f593 and a1,a1,1 -8000053c: f60582e3 beqz a1,800004a0 -80000540: 1f800593 li a1,504 -80000544: 0014f413 and s0,s1,1 -80000548: 008595b3 sll a1,a1,s0 -8000054c: 01d49413 sll s0,s1,0x1d -80000550: 41f45413 sra s0,s0,0x1f -80000554: fff44413 not s0,s0 -80000558: 0085f4b3 and s1,a1,s0 - -8000055c : -8000055c: 002484b3 add s1,s1,sp -80000560: 341023f3 csrr t2,mepc -80000564: 1884a403 lw s0,392(s1) -80000568: 1904a583 lw a1,400(s1) -8000056c: 008585b3 add a1,a1,s0 -80000570: 00b3f463 bgeu t2,a1,80000578 -80000574: 0283f663 bgeu t2,s0,800005a0 - -80000578 : -80000578: 1584a403 lw s0,344(s1) -8000057c: 1604a583 lw a1,352(s1) -80000580: 008585b3 add a1,a1,s0 -80000584: 00b3f463 bgeu t2,a1,8000058c -80000588: 0083fc63 bgeu t2,s0,800005a0 - -8000058c : -8000058c: 1684a403 lw s0,360(s1) -80000590: 1704a583 lw a1,368(s1) -80000594: 008585b3 add a1,a1,s0 -80000598: ceb3f6e3 bgeu t2,a1,80000284 -8000059c: ce83e4e3 bltu t2,s0,80000284 - -800005a0 : -800005a0: 40838433 sub s0,t2,s0 - -800005a4 : -800005a4: 00832423 sw s0,8(t1) - -800005a8 : -800005a8: ffc3f593 and a1,t2,-4 -800005ac: 00858593 add a1,a1,8 -800005b0: 34159073 csrw mepc,a1 -800005b4: 343023f3 csrr t2,mtval - -800005b8 : -800005b8: 00f57513 and a0,a0,15 -800005bc: 0000b437 lui s0,0xb -800005c0: 0fb40413 add s0,s0,251 # b0fb -800005c4: 00a45433 srl s0,s0,a0 -800005c8: 01f41413 sll s0,s0,0x1f -800005cc: 04045c63 bgez s0,80000624 - -800005d0 : -800005d0: 1884a403 lw s0,392(s1) -800005d4: 1904a583 lw a1,400(s1) -800005d8: 008585b3 add a1,a1,s0 -800005dc: 00b3f463 bgeu t2,a1,800005e4 -800005e0: 0483f063 bgeu t2,s0,80000620 - -800005e4 : -800005e4: 1784a403 lw s0,376(s1) -800005e8: 1804a583 lw a1,384(s1) -800005ec: 008585b3 add a1,a1,s0 -800005f0: 00b3f463 bgeu t2,a1,800005f8 -800005f4: 0283f663 bgeu t2,s0,80000620 - -800005f8 : -800005f8: 1584a403 lw s0,344(s1) -800005fc: 1604a583 lw a1,352(s1) -80000600: 008585b3 add a1,a1,s0 -80000604: 00b3f463 bgeu t2,a1,8000060c -80000608: 0083fc63 bgeu t2,s0,80000620 - -8000060c : -8000060c: 1684a403 lw s0,360(s1) -80000610: 1704a583 lw a1,368(s1) -80000614: 008585b3 add a1,a1,s0 -80000618: c6b3f6e3 bgeu t2,a1,80000284 -8000061c: c683e4e3 bltu t2,s0,80000284 - -80000620 : -80000620: 40838433 sub s0,t2,s0 - -80000624 : -80000624: 00832623 sw s0,12(t1) - -80000628 : -80000628: 19812483 lw s1,408(sp) -8000062c: 17812383 lw t2,376(sp) -80000630: 18012303 lw t1,384(sp) -80000634: 00730333 add t1,t1,t2 -80000638: c49366e3 bltu t1,s1,80000284 -8000063c: 10000393 li t2,256 -80000640: 0400006f j 80000680 - -80000644 : -80000644: 1dc12303 lw t1,476(sp) -80000648: 1e012383 lw t2,480(sp) -8000064c: 1e412403 lw s0,484(sp) -80000650: 1e812483 lw s1,488(sp) -80000654: 1ec12503 lw a0,492(sp) -80000658: 1f012583 lw a1,496(sp) -8000065c: 1f412103 lw sp,500(sp) -80000660: 30200073 mret - -80000664 : -80000664: 00100413 li s0,1 -80000668: 00f57393 and t2,a0,15 -8000066c: 00741433 sll s0,s0,t2 -80000670: 304434f3 csrrc s1,mie,s0 -80000674: 344434f3 csrrc s1,mip,s0 - -80000678 : -80000678: 00932423 sw s1,8(t1) -8000067c: 00000393 li t2,0 - -80000680 : -80000680: 00000417 auipc s0,0x0 -80000684: 03c40413 add s0,s0,60 # 800006bc -80000688: 00740433 add s0,s0,t2 -8000068c: 00351393 sll t2,a0,0x3 -80000690: 00740433 add s0,s0,t2 -80000694: ff847413 and s0,s0,-8 -80000698: 00042403 lw s0,0(s0) - -8000069c : -8000069c: c20406e3 beqz s0,800002c8 -800006a0: 01f41393 sll t2,s0,0x1f -800006a4: 0003d863 bgez t2,800006b4 -800006a8: 00145413 srl s0,s0,0x1 -800006ac: f8850ce3 beq a0,s0,80000644 -800006b0: c19ff06f j 800002c8 - -800006b4 : -800006b4: 00040067 jr s0 - -800006b8 : - ... -800006c0: 0001 .2byte 0x1 -800006c2: 0000 .2byte 0x0 -800006c4: 0000 .2byte 0x0 -800006c6: 0000 .2byte 0x0 -800006c8: 0001 .2byte 0x1 -800006ca: 0000 .2byte 0x0 -800006cc: 0000 .2byte 0x0 -800006ce: 0000 .2byte 0x0 -800006d0: 08b8 .2byte 0x8b8 -800006d2: 8000 .2byte 0x8000 - ... -800006e0: 0001 .2byte 0x1 -800006e2: 0000 .2byte 0x0 -800006e4: 0000 .2byte 0x0 -800006e6: 0000 .2byte 0x0 -800006e8: 0001 .2byte 0x1 -800006ea: 0000 .2byte 0x0 -800006ec: 0000 .2byte 0x0 -800006ee: 0000 .2byte 0x0 -800006f0: 08c0 .2byte 0x8c0 -800006f2: 8000 .2byte 0x8000 - ... -80000700: 0001 .2byte 0x1 -80000702: 0000 .2byte 0x0 -80000704: 0000 .2byte 0x0 -80000706: 0000 .2byte 0x0 -80000708: 0001 .2byte 0x1 -8000070a: 0000 .2byte 0x0 -8000070c: 0000 .2byte 0x0 -8000070e: 0000 .2byte 0x0 -80000710: 08c8 .2byte 0x8c8 -80000712: 8000 .2byte 0x8000 -80000714: 0000 .2byte 0x0 -80000716: 0000 .2byte 0x0 -80000718: 0001 .2byte 0x1 -8000071a: 0000 .2byte 0x0 -8000071c: 0000 .2byte 0x0 -8000071e: 0000 .2byte 0x0 -80000720: 0001 .2byte 0x1 -80000722: 0000 .2byte 0x0 -80000724: 0000 .2byte 0x0 -80000726: 0000 .2byte 0x0 -80000728: 0001 .2byte 0x1 -8000072a: 0000 .2byte 0x0 -8000072c: 0000 .2byte 0x0 -8000072e: 0000 .2byte 0x0 -80000730: 0001 .2byte 0x1 - ... - -800007b8 : -800007b8: 0001 .2byte 0x1 -800007ba: 0000 .2byte 0x0 -800007bc: 0000 .2byte 0x0 -800007be: 0000 .2byte 0x0 -800007c0: 00000003 lb zero,0(zero) # 0 -800007c4: 0000 .2byte 0x0 -800007c6: 0000 .2byte 0x0 -800007c8: 0005 .2byte 0x5 -800007ca: 0000 .2byte 0x0 -800007cc: 0000 .2byte 0x0 -800007ce: 0000 .2byte 0x0 -800007d0: 00000007 .4byte 0x7 -800007d4: 0000 .2byte 0x0 -800007d6: 0000 .2byte 0x0 -800007d8: 0009 .2byte 0x9 -800007da: 0000 .2byte 0x0 -800007dc: 0000 .2byte 0x0 -800007de: 0000 .2byte 0x0 -800007e0: 0000000b .4byte 0xb -800007e4: 0000 .2byte 0x0 -800007e6: 0000 .2byte 0x0 -800007e8: 000d .2byte 0xd -800007ea: 0000 .2byte 0x0 -800007ec: 0000 .2byte 0x0 -800007ee: 0000 .2byte 0x0 -800007f0: 0000000f fence unknown,unknown -800007f4: 0000 .2byte 0x0 -800007f6: 0000 .2byte 0x0 -800007f8: 0011 .2byte 0x11 -800007fa: 0000 .2byte 0x0 -800007fc: 0000 .2byte 0x0 -800007fe: 0000 .2byte 0x0 -80000800: 00000013 nop -80000804: 0000 .2byte 0x0 -80000806: 0000 .2byte 0x0 -80000808: 0015 .2byte 0x15 -8000080a: 0000 .2byte 0x0 -8000080c: 0000 .2byte 0x0 -8000080e: 0000 .2byte 0x0 -80000810: 00000017 auipc zero,0x0 -80000814: 0000 .2byte 0x0 -80000816: 0000 .2byte 0x0 -80000818: 0019 .2byte 0x19 -8000081a: 0000 .2byte 0x0 -8000081c: 0000 .2byte 0x0 -8000081e: 0000 .2byte 0x0 -80000820: 0000001b .4byte 0x1b -80000824: 0000 .2byte 0x0 -80000826: 0000 .2byte 0x0 -80000828: 001d .2byte 0x1d -8000082a: 0000 .2byte 0x0 -8000082c: 0000 .2byte 0x0 -8000082e: 0000 .2byte 0x0 -80000830: 001f 0000 0000 .byte 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00 - ... - -800008b8 : -800008b8: 9cdff06f j 80000284 -800008bc: d89ff06f j 80000644 - -800008c0 : -800008c0: 9c5ff06f j 80000284 -800008c4: d81ff06f j 80000644 - -800008c8 : -800008c8: 9bdff06f j 80000284 -800008cc: 00832623 sw s0,12(t1) -800008d0: d75ff06f j 80000644 - -800008d4 : -800008d4: 9b1ff06f j 80000284 -800008d8: d6dff06f j 80000644 - -800008dc : -800008dc: 9a9ff06f j 80000284 -800008e0: d65ff06f j 80000644 - -800008e4 : -800008e4: 9a1ff06f j 80000284 -800008e8: 00832623 sw s0,12(t1) -800008ec: d59ff06f j 80000644 - -800008f0 : -800008f0: 995ff06f j 80000284 -800008f4: d51ff06f j 80000644 - -800008f8 : -800008f8: 98dff06f j 80000284 -800008fc: d49ff06f j 80000644 - -80000900 : -80000900: 985ff06f j 80000284 -80000904: 00832623 sw s0,12(t1) -80000908: d3dff06f j 80000644 - -8000090c : -8000090c: ff550493 add s1,a0,-11 -80000910: 00048c63 beqz s1,80000928 -80000914: 35012583 lw a1,848(sp) -80000918: 0003d463 bgez t2,80000920 - -8000091c : -8000091c: 54812583 lw a1,1352(sp) - -80000920 : -80000920: 15812483 lw s1,344(sp) -80000924: 40b484b3 sub s1,s1,a1 - -80000928 : -80000928: 341023f3 csrr t2,mepc -8000092c: 009383b3 add t2,t2,s1 -80000930: 1dc12303 lw t1,476(sp) -80000934: 1e412403 lw s0,484(sp) -80000938: 1e812483 lw s1,488(sp) -8000093c: 1ec12503 lw a0,492(sp) -80000940: 1f012583 lw a1,496(sp) -80000944: 1f412103 lw sp,500(sp) -80000948: 00438067 jr 4(t2) - -8000094c : -8000094c: 00100093 li ra,1 -80000950: 00000397 auipc t2,0x0 -80000954: 6a13a823 sw ra,1712(t2) # 80001000 -80000958: ff9ff06f j 80000950 -8000095c: 00100093 li ra,1 -80000960: 00000397 auipc t2,0x0 -80000964: 6a13a023 sw ra,1696(t2) # 80001000 -80000968: ff9ff06f j 80000960 - ... - -Disassembly of section .tohost: - -80001000 : - ... - -80001100 : - ... - -Disassembly of section .data: - -80002000 : -80002000: 0000006f j 80002000 -80002004: 0000006f j 80002004 -80002008: 0000006f j 80002008 -8000200c: 0000006f j 8000200c -80002010: 0000006f j 80002010 -80002014: 0000006f j 80002014 -80002018: 0000006f j 80002018 -8000201c: 0000006f j 8000201c -80002020: 0000006f j 80002020 -80002024: 0000006f j 80002024 -80002028: 0000006f j 80002028 -8000202c: 0000006f j 8000202c -80002030: 0000006f j 80002030 -80002034: 0000006f j 80002034 -80002038: 0000006f j 80002038 -8000203c: 0000006f j 8000203c -80002040: 0000006f j 80002040 -80002044: 0000006f j 80002044 -80002048: 0000006f j 80002048 -8000204c: 0000006f j 8000204c -80002050: 0000006f j 80002050 -80002054: 0000006f j 80002054 -80002058: 0000006f j 80002058 -8000205c: 0000006f j 8000205c -80002060: 0000006f j 80002060 -80002064: 0000006f j 80002064 -80002068: 0000006f j 80002068 -8000206c: 0000006f j 8000206c -80002070: 0000006f j 80002070 -80002074: 0000006f j 80002074 -80002078: 0000006f j 80002078 -8000207c: 0000006f j 8000207c -80002080: 0000006f j 80002080 -80002084: 0000006f j 80002084 -80002088: 0000006f j 80002088 -8000208c: 0000006f j 8000208c -80002090: 0000006f j 80002090 -80002094: 0000006f j 80002094 -80002098: 0000006f j 80002098 -8000209c: 0000006f j 8000209c -800020a0: 0000006f j 800020a0 -800020a4: 0000006f j 800020a4 -800020a8: 0000006f j 800020a8 -800020ac: 0000006f j 800020ac -800020b0: 0000006f j 800020b0 -800020b4: 0000006f j 800020b4 -800020b8: 0000006f j 800020b8 -800020bc: 0000006f j 800020bc -800020c0: 0000006f j 800020c0 -800020c4: 0000006f j 800020c4 -800020c8: 0000006f j 800020c8 -800020cc: 0000006f j 800020cc -800020d0: 0000006f j 800020d0 -800020d4: 0000006f j 800020d4 -800020d8: 0000006f j 800020d8 -800020dc: 0000006f j 800020dc -800020e0: 0000006f j 800020e0 -800020e4: 0000006f j 800020e4 -800020e8: 0000006f j 800020e8 -800020ec: 0000006f j 800020ec -800020f0: 0000006f j 800020f0 -800020f4: 0000006f j 800020f4 -800020f8: 0000006f j 800020f8 -800020fc: 0000006f j 800020fc -80002100: 0000006f j 80002100 -80002104: 0000006f j 80002104 -80002108: 0000006f j 80002108 -8000210c: 0000006f j 8000210c -80002110: 0000006f j 80002110 -80002114: 0000006f j 80002114 -80002118: 0000006f j 80002118 -8000211c: 0000006f j 8000211c -80002120: 0000006f j 80002120 -80002124: 0000006f j 80002124 -80002128: 0000006f j 80002128 -8000212c: 0000006f j 8000212c -80002130: 0000006f j 80002130 -80002134: 0000006f j 80002134 -80002138: 0000006f j 80002138 -8000213c: 0000006f j 8000213c -80002140: 0000006f j 80002140 -80002144: 0000006f j 80002144 -80002148: 0000006f j 80002148 -8000214c: 0000006f j 8000214c -80002150: 0000006f j 80002150 -80002154: 0000006f j 80002154 - -80002158 : -80002158: 022c .2byte 0x22c -8000215a: 8000 .2byte 0x8000 -8000215c: 0000 .2byte 0x0 - ... - -80002160 : -80002160: 0050 .2byte 0x50 -80002162: 0000 .2byte 0x0 -80002164: 0000 .2byte 0x0 - ... - -80002168 : -80002168: 21f8 .2byte 0x21f8 -8000216a: 8000 .2byte 0x8000 -8000216c: 0000 .2byte 0x0 - ... - -80002170 : -80002170: 0e08 .2byte 0xe08 -80002172: 0000 .2byte 0x0 -80002174: 0000 .2byte 0x0 - ... - -80002178 : -80002178: 3110 .2byte 0x3110 -8000217a: 8000 .2byte 0x8000 -8000217c: 0000 .2byte 0x0 - ... - -80002180 : -80002180: 0020 .2byte 0x20 -80002182: 0000 .2byte 0x0 -80002184: 0000 .2byte 0x0 - ... - -80002188 : -80002188: 022c .2byte 0x22c -8000218a: 8000 .2byte 0x8000 -8000218c: 0000 .2byte 0x0 - ... - -80002190 : -80002190: 0050 .2byte 0x50 -80002192: 0000 .2byte 0x0 -80002194: 0000 .2byte 0x0 - ... - -80002198 : -80002198: 311c .2byte 0x311c -8000219a: 8000 .2byte 0x8000 -8000219c: 0000 .2byte 0x0 - ... - -800021a0 : - ... - -800021a8 : - ... - -800021b0 : -800021b0: 0454 .2byte 0x454 -800021b2: 8000 .2byte 0x8000 -800021b4: 0000 .2byte 0x0 - ... - -800021b8 : - ... - -800021c0 : - ... - -800021c8 : - ... - -800021d0 : - ... - -800021d8 : -800021d8: deadbeef jal t4,7ffdd7c2 -800021dc: deadbeef jal t4,7ffdd7c6 -800021e0: deadbeef jal t4,7ffdd7ca -800021e4: deadbeef jal t4,7ffdd7ce -800021e8: deadbeef jal t4,7ffdd7d2 -800021ec: deadbeef jal t4,7ffdd7d6 -800021f0: deadbeef jal t4,7ffdd7da -800021f4: deadbeef jal t4,7ffdd7de - -800021f8 : - ... - -80003000 : -80003000: 0080 .2byte 0x80 - ... - -80003100 : -80003100: 0004 .2byte 0x4 - ... - -80003110 : -80003110: a309 .2byte 0xa309 -80003112: 6f5c .2byte 0x6f5c - -80003114 : -80003114: deadbeef jal t4,7ffde6fe -80003118: deadbeef jal t4,7ffde702 - -8000311c : -8000311c: deadbeef jal t4,7ffde706 -80003120: deadbeef jal t4,7ffde70a -80003124: deadbeef jal t4,7ffde70e -80003128: deadbeef jal t4,7ffde712 - -8000312c : -8000312c: a309 .2byte 0xa309 -8000312e: 6f5c .2byte 0x6f5c - -Disassembly of section .riscv.attributes: - -00000000 <.riscv.attributes>: - 0: 2641 .2byte 0x2641 - 2: 0000 .2byte 0x0 - 4: 7200 .2byte 0x7200 - 6: 7369 .2byte 0x7369 - 8: 01007663 bgeu zero,a6,14 - c: 001c .2byte 0x1c - e: 0000 .2byte 0x0 - 10: 7205 .2byte 0x7205 - 12: 3376 .2byte 0x3376 - 14: 6932 .2byte 0x6932 - 16: 7032 .2byte 0x7032 - 18: 5f31 .2byte 0x5f31 - 1a: 697a .2byte 0x697a - 1c: 32727363 bgeu tp,t2,342 - 20: 3070 .2byte 0x3070 - 22: 0800 .2byte 0x800 - 24: 0a01 .2byte 0xa01 - 26: 0b Address 0x26 is out of bounds. - diff --git a/riscof_work/src/ebreak.S/ref/ref.elf b/riscof_work/src/ebreak.S/ref/ref.elf deleted file mode 100755 index ea816bec326dad515b7736a858de6ed7ba417bd9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 20988 zcmeI44Qw0b8ONW?Ic-`BBwW(ZkQ&bII>aKk4y({K%~=vYq*{c=?Ftl(dv+7I@dv(3 zns$6#=VStjNiEmX(iRA#Y!wnykvmaM3av|l1K}vf+j;! z#^31lAo`ZAdLUU}vwx*&)bXnKPa$HpoS9%Z{a#bo!Mgt{B338aekR=FM!=1L8v!>0 zZUo#2xDjw8;6}iWfExif0&WD{2z+%Bm?0BMqDT^kyiirE#RhpnuGYYZe)(E;w(4v3 z%RaE$Kslc{$LJkAo*&jo_Nuk&rZ&Giuhp+qbXBO8VZSoT1^ZSZf9y0#Z$Tg0 zDg;)aA!B(r?2iih56@gMKeqW1e?55OV)0*GRaGSkRaGh;^f+zge&o{6y(Hm5kZPan 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-/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/ecall.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/ecall.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - ecall - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/ecall.S -/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-beq-01.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - misalign-beq - - misalign-beq - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S -/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bge-01.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bge-01.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - misalign-bge - - misalign-bge - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bge-01.S -/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bgeu-01.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bgeu-01.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - misalign-bgeu - - misalign-bgeu - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bgeu-01.S -/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-blt-01.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-blt-01.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - misalign-blt - - misalign-blt - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-blt-01.S -/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bltu-01.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bltu-01.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - misalign-bltu - - misalign-bltu - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bltu-01.S -/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bne-01.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-bne-01.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - misalign-bne - - misalign-bne - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-bne-01.S -/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-jal-01.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-jal-01.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - misalign-jal - - misalign-jal - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-jal-01.S -/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lh-01.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-lh-01.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - misalign-lh - - misalign-lh - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lh-01.S -/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lhu-01.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-lhu-01.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - misalign-lhu - - misalign-lhu - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lhu-01.S -/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lw-01.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-lw-01.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - misalign-lw - - misalign-lw - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-lw-01.S -/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sh-01.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-sh-01.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - misalign-sh - - misalign-sh - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sh-01.S -/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sw-01.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign-sw-01.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - misalign-sw - - misalign-sw - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign-sw-01.S -/home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign2-jalr-01.S: - commit_id: '-' - work_dir: /home/user/Work/New_Repo/riscv-arch-test/riscof_work/src/misalign2-jalr-01.S - macros: - - rvtest_mtrap_routine=True - - TEST_CASE_1=True - - XLEN=32 - isa: RV32I_Zicsr - coverage_labels: - - misalign2-jalr - - misalign2-jalr - test_path: /home/user/Work/Tests/riscv-test-suite/rv32i_m/privilege/src/misalign2-jalr-01.S From 1df2288f3dda9298c70e5e22b0429e30eb0f9bc1 Mon Sep 17 00:00:00 2001 From: umershahidengr Date: Sun, 9 Jun 2024 08:28:33 +0500 Subject: [PATCH 3/6] Updated Changelog file --- CHANGELOG.md | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 5cfe4c8ae..d59ad06af 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,4 +1,9 @@ # CHANGELOG +## [3.9.2] - 2024-06-09 +- converted one of the CANARY words to a delta instret count (there is a variable that will enable that...) +- converted CODE/DATA/SIG_BEGIN/END to include all the little incidental code, so the tests template improves +- minor bug fixes to the trap handler in the cases of traps delegated to S-mode with virtualization enabled. + ## [3.9.1] - 2024-05-24 - Split rv32i_m/F/fnmadd_b15.S, fnmsub_b15.S, fmadd_b15.S, fmsub_b15.S into multiple smaller tests - Split each _b15 file into 50 files consists of 768 (128*6) tests From 8399425356a2000a6d0de25a4d08c01acb24537f Mon Sep 17 00:00:00 2001 From: umershahidengr Date: Sun, 9 Jun 2024 08:35:26 +0500 Subject: [PATCH 4/6] Removed RVMODEL_HALT from exit_cleanup macro as RVMODEL_HALT is already called in every test file --- riscv-test-suite/env/arch_test.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-test-suite/env/arch_test.h b/riscv-test-suite/env/arch_test.h index 6d573c113..ae8ff7aa1 100644 --- a/riscv-test-suite/env/arch_test.h +++ b/riscv-test-suite/env/arch_test.h @@ -1945,7 +1945,7 @@ rvtest_\__MODE__\()end: INSTANTIATE_MODE_MACRO RVTEST_TRAP_HANDLER exit_cleanup: // *** RVMODEL_HALT MUST follow this***, then data -RVMODEL_HALT +//RVMODEL_HALT .option pop .endm // end of RVTEST_CODE_END @@ -2063,4 +2063,4 @@ CANARY CANARY /* add one extra word of guardband */ rvtest_sig_end: RVMODEL_DATA_END /* model specific stuff */ -.endm \ No newline at end of file +.endm From 00b4ee4a1956b63ffe411370c2c8c96d10e25131 Mon Sep 17 00:00:00 2001 From: umershahidengr Date: Mon, 1 Jul 2024 21:26:55 +0500 Subject: [PATCH 5/6] Removed ChangeLog entry --- CHANGELOG.md | 4 ---- 1 file changed, 4 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index d59ad06af..d00f02520 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,8 +1,4 @@ # CHANGELOG -## [3.9.2] - 2024-06-09 -- converted one of the CANARY words to a delta instret count (there is a variable that will enable that...) -- converted CODE/DATA/SIG_BEGIN/END to include all the little incidental code, so the tests template improves -- minor bug fixes to the trap handler in the cases of traps delegated to S-mode with virtualization enabled. ## [3.9.1] - 2024-05-24 - Split rv32i_m/F/fnmadd_b15.S, fnmsub_b15.S, fmadd_b15.S, fmsub_b15.S into multiple smaller tests From 58056777dcb40b3ecfe67d78ba4bc39dec1a243f Mon Sep 17 00:00:00 2001 From: umershahidengr Date: Mon, 1 Jul 2024 21:30:44 +0500 Subject: [PATCH 6/6] Removed ChangeLog entry (extra line) --- CHANGELOG.md | 1 - 1 file changed, 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index d00f02520..5cfe4c8ae 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,4 @@ # CHANGELOG - ## [3.9.1] - 2024-05-24 - Split rv32i_m/F/fnmadd_b15.S, fnmsub_b15.S, fmadd_b15.S, fmsub_b15.S into multiple smaller tests - Split each _b15 file into 50 files consists of 768 (128*6) tests