diff --git a/CHANGELOG.md b/CHANGELOG.md
index 6f76e7864..f2075807a 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,8 @@
 # CHANGELOG
 
+## [3.8.13] - 2024-04-13
+- Fixed missing `F` and `Zfh` ISA identifiers in `Zfh/flh-align-01` RVTEST_CASE macro.
+
 ## [3.8.12] - 2024-03-26
 Corrected missing RV64 strings in RVTEST_CASE macros for Zfh fcvt.h.l and similar tests
 
diff --git a/riscv-test-suite/rv32i_m/Zfh/src/flh-align-01.S b/riscv-test-suite/rv32i_m/Zfh/src/flh-align-01.S
index 638799f9b..a3459cadf 100644
--- a/riscv-test-suite/rv32i_m/Zfh/src/flh-align-01.S
+++ b/riscv-test-suite/rv32i_m/Zfh/src/flh-align-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*);def TEST_CASE_1=True;",flh-align)
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",flh-align)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)