From 2d25eafe37ecf9c11754ec65f6beff668342382d Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sat, 23 Sep 2023 10:41:55 -0500 Subject: [PATCH 1/9] add test macro for c.mop --- riscv-test-suite/env/test_macros.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h index 6426d92f8..1ea30757d 100644 --- a/riscv-test-suite/env/test_macros.h +++ b/riscv-test-suite/env/test_macros.h @@ -615,6 +615,13 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg) inst imm_val ;\ ) +//Tests c.mop.* instructions +#define TEST_CMOP_OP(inst, destreg, imm_val, swreg, testreg, offset) \ + TEST_CASE(testreg, destreg, imm_val, swreg, offset, \ + mv destreg, swreg; \ + inst; \ + ) + //Tests for instructions with register-immediate operand and update the saturation flag #define TEST_PKIMM_OP( inst, destreg, reg, correctval, val, imm, flagreg, swreg, offset, testreg) \ TEST_CASE(testreg, destreg, correctval, swreg, offset, \ From 4b4aa3df024a468a678773f7c440bfbf3bcab7f7 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sat, 23 Sep 2023 10:42:15 -0500 Subject: [PATCH 2/9] add cgf for zcmop --- coverage/zcmop.cgf | 71 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 coverage/zcmop.cgf diff --git a/coverage/zcmop.cgf b/coverage/zcmop.cgf new file mode 100644 index 000000000..b48f3274c --- /dev/null +++ b/coverage/zcmop.cgf @@ -0,0 +1,71 @@ +c.mop.0: + config: + - check ISA:=regex(.*C.*Zcmop.*) + mnemonics: + c.mop.0: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.1: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.1: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.2: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.2: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.3: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.3: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.4: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.4: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.5: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.5: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.6: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.6: + val_comb: + abstract_comb: + <<: *cbimm_val_walking + +c.mop.7: + config: + - check ISA:=regex(.*C.*Zcmop.*) + opcode: + c.mop.7: + val_comb: + abstract_comb: + <<: *cbimm_val_walking From 00d25881eaf3a2765b2e94f2de3167a291095eec Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sat, 23 Sep 2023 10:42:38 -0500 Subject: [PATCH 3/9] add rv32i tests for c.mop.* --- .../rv32i_m/Zcmop/src/c.mop.0-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.1-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.2-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.3-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.4-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.5-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.6-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.7-01.S | 122 ++++++++++++++++++ 8 files changed, 976 insertions(+) create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.0-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.6-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.0-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.0-01.S new file mode 100644 index 000000000..e32912aa6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.0-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:35:30 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.0 instruction of the RISC-V RV32CZcmop extension for the c.mop.0 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.0) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.0; immval:0x15 +TEST_CMOP_OP(c.mop.0, x1, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.0; immval:0x1 +TEST_CMOP_OP(c.mop.0, x1, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.0; immval:0x2 +TEST_CMOP_OP(c.mop.0, x1, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.0; immval:0x1f +TEST_CMOP_OP(c.mop.0, x1, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.0; immval:0x4 +TEST_CMOP_OP(c.mop.0, x1, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.0; immval:0x8 +TEST_CMOP_OP(c.mop.0, x1, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.0; immval:0x10 +TEST_CMOP_OP(c.mop.0, x1, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S new file mode 100644 index 000000000..4f8da5be7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:35:30 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.1 instruction of the RISC-V RV32CZcmop extension for the c.mop.1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.1) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.1; immval:0x15 +TEST_CMOP_OP(c.mop.1, x3, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.1; immval:0x1 +TEST_CMOP_OP(c.mop.1, x3, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.1; immval:0x2 +TEST_CMOP_OP(c.mop.1, x3, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.1; immval:0x1f +TEST_CMOP_OP(c.mop.1, x3, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.1; immval:0x4 +TEST_CMOP_OP(c.mop.1, x3, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.1; immval:0x8 +TEST_CMOP_OP(c.mop.1, x3, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.1; immval:0x10 +TEST_CMOP_OP(c.mop.1, x3, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.2-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.2-01.S new file mode 100644 index 000000000..4b94a9592 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.2-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:35:30 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.2 instruction of the RISC-V RV32CZcmop extension for the c.mop.2 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.2) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.2; immval:0x15 +TEST_CMOP_OP(c.mop.2, x5, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.2; immval:0x1 +TEST_CMOP_OP(c.mop.2, x5, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.2; immval:0x2 +TEST_CMOP_OP(c.mop.2, x5, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.2; immval:0x1f +TEST_CMOP_OP(c.mop.2, x5, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.2; immval:0x4 +TEST_CMOP_OP(c.mop.2, x5, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.2; immval:0x8 +TEST_CMOP_OP(c.mop.2, x5, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.2; immval:0x10 +TEST_CMOP_OP(c.mop.2, x5, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S new file mode 100644 index 000000000..4c6420093 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:35:30 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.3 instruction of the RISC-V RV32CZcmop extension for the c.mop.3 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.3) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.3; immval:0x15 +TEST_CMOP_OP(c.mop.3, x7, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.3; immval:0x1 +TEST_CMOP_OP(c.mop.3, x7, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.3; immval:0x2 +TEST_CMOP_OP(c.mop.3, x7, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.3; immval:0x1f +TEST_CMOP_OP(c.mop.3, x7, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.3; immval:0x4 +TEST_CMOP_OP(c.mop.3, x7, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.3; immval:0x8 +TEST_CMOP_OP(c.mop.3, x7, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.3; immval:0x10 +TEST_CMOP_OP(c.mop.3, x7, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.4-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.4-01.S new file mode 100644 index 000000000..24ba823f9 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.4-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:35:30 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.4 instruction of the RISC-V RV32CZcmop extension for the c.mop.4 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.4) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.4; immval:0x15 +TEST_CMOP_OP(c.mop.4, x9, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.4; immval:0x1 +TEST_CMOP_OP(c.mop.4, x9, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.4; immval:0x2 +TEST_CMOP_OP(c.mop.4, x9, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.4; immval:0x1f +TEST_CMOP_OP(c.mop.4, x9, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.4; immval:0x4 +TEST_CMOP_OP(c.mop.4, x9, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.4; immval:0x8 +TEST_CMOP_OP(c.mop.4, x9, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.4; immval:0x10 +TEST_CMOP_OP(c.mop.4, x9, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S new file mode 100644 index 000000000..e483f41b7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:35:30 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.5 instruction of the RISC-V RV32CZcmop extension for the c.mop.5 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.5) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.5; immval:0x15 +TEST_CMOP_OP(c.mop.5, x11, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.5; immval:0x1 +TEST_CMOP_OP(c.mop.5, x11, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.5; immval:0x2 +TEST_CMOP_OP(c.mop.5, x11, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.5; immval:0x1f +TEST_CMOP_OP(c.mop.5, x11, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.5; immval:0x4 +TEST_CMOP_OP(c.mop.5, x11, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.5; immval:0x8 +TEST_CMOP_OP(c.mop.5, x11, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.5; immval:0x10 +TEST_CMOP_OP(c.mop.5, x11, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.6-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.6-01.S new file mode 100644 index 000000000..cf2de5ba5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.6-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:35:30 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.6 instruction of the RISC-V RV32CZcmop extension for the c.mop.6 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.6) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.6; immval:0x15 +TEST_CMOP_OP(c.mop.6, x13, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.6; immval:0x1 +TEST_CMOP_OP(c.mop.6, x13, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.6; immval:0x2 +TEST_CMOP_OP(c.mop.6, x13, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.6; immval:0x1f +TEST_CMOP_OP(c.mop.6, x13, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.6; immval:0x4 +TEST_CMOP_OP(c.mop.6, x13, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.6; immval:0x8 +TEST_CMOP_OP(c.mop.6, x13, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.6; immval:0x10 +TEST_CMOP_OP(c.mop.6, x13, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S new file mode 100644 index 000000000..6fb168bff --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:35:30 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.7 instruction of the RISC-V RV32CZcmop extension for the c.mop.7 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.7) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.7; immval:0x15 +TEST_CMOP_OP(c.mop.7, x15, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.7; immval:0x1 +TEST_CMOP_OP(c.mop.7, x15, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.7; immval:0x2 +TEST_CMOP_OP(c.mop.7, x15, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.7; immval:0x1f +TEST_CMOP_OP(c.mop.7, x15, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.7; immval:0x4 +TEST_CMOP_OP(c.mop.7, x15, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.7; immval:0x8 +TEST_CMOP_OP(c.mop.7, x15, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.7; immval:0x10 +TEST_CMOP_OP(c.mop.7, x15, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END From 2f242d4cca9c3c3b48f0671aad00561c4b242954 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sat, 23 Sep 2023 10:42:48 -0500 Subject: [PATCH 4/9] add rv64i tests for c.mop.* --- .../rv64i_m/Zcmop/src/c.mop.0-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.1-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.2-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.3-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.4-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.5-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.6-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.7-01.S | 122 ++++++++++++++++++ 8 files changed, 976 insertions(+) create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.0-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.2-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.4-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.6-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.0-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.0-01.S new file mode 100644 index 000000000..6bb9fcccd --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.0-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:34:58 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.0 instruction of the RISC-V RV64CZcmop extension for the c.mop.0 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.0) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.0; immval:0x15 +TEST_CMOP_OP(c.mop.0, x1, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.0; immval:0x1 +TEST_CMOP_OP(c.mop.0, x1, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.0; immval:0x2 +TEST_CMOP_OP(c.mop.0, x1, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.0; immval:0x1f +TEST_CMOP_OP(c.mop.0, x1, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.0; immval:0x4 +TEST_CMOP_OP(c.mop.0, x1, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.0; immval:0x8 +TEST_CMOP_OP(c.mop.0, x1, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.0; immval:0x10 +TEST_CMOP_OP(c.mop.0, x1, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S new file mode 100644 index 000000000..418a9c264 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:34:58 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.1 instruction of the RISC-V RV64CZcmop extension for the c.mop.1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.1) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.1; immval:0x15 +TEST_CMOP_OP(c.mop.1, x3, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.1; immval:0x1 +TEST_CMOP_OP(c.mop.1, x3, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.1; immval:0x2 +TEST_CMOP_OP(c.mop.1, x3, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.1; immval:0x1f +TEST_CMOP_OP(c.mop.1, x3, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.1; immval:0x4 +TEST_CMOP_OP(c.mop.1, x3, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.1; immval:0x8 +TEST_CMOP_OP(c.mop.1, x3, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.1; immval:0x10 +TEST_CMOP_OP(c.mop.1, x3, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.2-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.2-01.S new file mode 100644 index 000000000..b5e00bca1 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.2-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:34:58 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.2 instruction of the RISC-V RV64CZcmop extension for the c.mop.2 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.2) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.2; immval:0x15 +TEST_CMOP_OP(c.mop.2, x5, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.2; immval:0x1 +TEST_CMOP_OP(c.mop.2, x5, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.2; immval:0x2 +TEST_CMOP_OP(c.mop.2, x5, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.2; immval:0x1f +TEST_CMOP_OP(c.mop.2, x5, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.2; immval:0x4 +TEST_CMOP_OP(c.mop.2, x5, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.2; immval:0x8 +TEST_CMOP_OP(c.mop.2, x5, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.2; immval:0x10 +TEST_CMOP_OP(c.mop.2, x5, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S new file mode 100644 index 000000000..fdb3cd523 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:34:58 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.3 instruction of the RISC-V RV64CZcmop extension for the c.mop.3 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.3) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.3; immval:0x15 +TEST_CMOP_OP(c.mop.3, x7, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.3; immval:0x1 +TEST_CMOP_OP(c.mop.3, x7, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.3; immval:0x2 +TEST_CMOP_OP(c.mop.3, x7, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.3; immval:0x1f +TEST_CMOP_OP(c.mop.3, x7, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.3; immval:0x4 +TEST_CMOP_OP(c.mop.3, x7, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.3; immval:0x8 +TEST_CMOP_OP(c.mop.3, x7, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.3; immval:0x10 +TEST_CMOP_OP(c.mop.3, x7, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.4-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.4-01.S new file mode 100644 index 000000000..8b57047dc --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.4-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:34:58 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.4 instruction of the RISC-V RV64CZcmop extension for the c.mop.4 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.4) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.4; immval:0x15 +TEST_CMOP_OP(c.mop.4, x9, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.4; immval:0x1 +TEST_CMOP_OP(c.mop.4, x9, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.4; immval:0x2 +TEST_CMOP_OP(c.mop.4, x9, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.4; immval:0x1f +TEST_CMOP_OP(c.mop.4, x9, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.4; immval:0x4 +TEST_CMOP_OP(c.mop.4, x9, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.4; immval:0x8 +TEST_CMOP_OP(c.mop.4, x9, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.4; immval:0x10 +TEST_CMOP_OP(c.mop.4, x9, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S new file mode 100644 index 000000000..aaaf97509 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:34:58 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.5 instruction of the RISC-V RV64CZcmop extension for the c.mop.5 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.5) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.5; immval:0x15 +TEST_CMOP_OP(c.mop.5, x11, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.5; immval:0x1 +TEST_CMOP_OP(c.mop.5, x11, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.5; immval:0x2 +TEST_CMOP_OP(c.mop.5, x11, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.5; immval:0x1f +TEST_CMOP_OP(c.mop.5, x11, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.5; immval:0x4 +TEST_CMOP_OP(c.mop.5, x11, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.5; immval:0x8 +TEST_CMOP_OP(c.mop.5, x11, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.5; immval:0x10 +TEST_CMOP_OP(c.mop.5, x11, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.6-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.6-01.S new file mode 100644 index 000000000..ae6eb575c --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.6-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:34:58 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.6 instruction of the RISC-V RV64CZcmop extension for the c.mop.6 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.6) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.6; immval:0x15 +TEST_CMOP_OP(c.mop.6, x13, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.6; immval:0x1 +TEST_CMOP_OP(c.mop.6, x13, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.6; immval:0x2 +TEST_CMOP_OP(c.mop.6, x13, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.6; immval:0x1f +TEST_CMOP_OP(c.mop.6, x13, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.6; immval:0x4 +TEST_CMOP_OP(c.mop.6, x13, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.6; immval:0x8 +TEST_CMOP_OP(c.mop.6, x13, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.6; immval:0x10 +TEST_CMOP_OP(c.mop.6, x13, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S new file mode 100644 index 000000000..283ddedcf --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Sat Sep 23 15:34:58 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.7 instruction of the RISC-V RV64CZcmop extension for the c.mop.7 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.7) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.7; immval:0x15 +TEST_CMOP_OP(c.mop.7, x15, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.7; immval:0x1 +TEST_CMOP_OP(c.mop.7, x15, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.7; immval:0x2 +TEST_CMOP_OP(c.mop.7, x15, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.7; immval:0x1f +TEST_CMOP_OP(c.mop.7, x15, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.7; immval:0x4 +TEST_CMOP_OP(c.mop.7, x15, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.7; immval:0x8 +TEST_CMOP_OP(c.mop.7, x15, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.7; immval:0x10 +TEST_CMOP_OP(c.mop.7, x15, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END From 76b78d13cb6dc0c56b434a965707639f81b19e79 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sat, 23 Sep 2023 10:45:16 -0500 Subject: [PATCH 5/9] update changelog --- CHANGELOG.md | 3 +++ riscv-test-suite/rv32i_m/Zcmop/src/c.mop.0-01.S | 4 ++-- riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S | 4 ++-- riscv-test-suite/rv32i_m/Zcmop/src/c.mop.2-01.S | 4 ++-- riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S | 4 ++-- riscv-test-suite/rv32i_m/Zcmop/src/c.mop.4-01.S | 4 ++-- riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S | 4 ++-- riscv-test-suite/rv32i_m/Zcmop/src/c.mop.6-01.S | 4 ++-- riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S | 4 ++-- riscv-test-suite/rv64i_m/Zcmop/src/c.mop.0-01.S | 4 ++-- riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S | 4 ++-- riscv-test-suite/rv64i_m/Zcmop/src/c.mop.2-01.S | 4 ++-- riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S | 4 ++-- riscv-test-suite/rv64i_m/Zcmop/src/c.mop.4-01.S | 4 ++-- riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S | 4 ++-- riscv-test-suite/rv64i_m/Zcmop/src/c.mop.6-01.S | 4 ++-- riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S | 4 ++-- 17 files changed, 35 insertions(+), 32 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 7d682b8bb..461b68dd0 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,8 @@ # CHANGELOG +## [3.7.2] - 2023-09-23 +- Updated the Zcmop extension + ## [3.7.0] - 2023-05-16 - Updated the LI macro - Make Trap handler compatible for RV32E diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.0-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.0-01.S index e32912aa6..aeb18683e 100644 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.0-01.S +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.0-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:35:30 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 32 \ // --randomize \ diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S index 4f8da5be7..b525c36aa 100644 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:35:30 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 32 \ // --randomize \ diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.2-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.2-01.S index 4b94a9592..05d806a96 100644 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.2-01.S +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.2-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:35:30 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 32 \ // --randomize \ diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S index 4c6420093..ef4966b6c 100644 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:35:30 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 32 \ // --randomize \ diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.4-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.4-01.S index 24ba823f9..3dbf5532b 100644 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.4-01.S +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.4-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:35:30 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 32 \ // --randomize \ diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S index e483f41b7..eca260ada 100644 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:35:30 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 32 \ // --randomize \ diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.6-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.6-01.S index cf2de5ba5..a8fc1c12a 100644 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.6-01.S +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.6-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:35:30 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 32 \ // --randomize \ diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S index 6fb168bff..8b37caef3 100644 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:35:30 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 32 \ // --randomize \ diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.0-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.0-01.S index 6bb9fcccd..51bda0eff 100644 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.0-01.S +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.0-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:34:58 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 64 \ // --randomize \ diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S index 418a9c264..9d14de682 100644 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:34:58 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 64 \ // --randomize \ diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.2-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.2-01.S index b5e00bca1..a68feb1bf 100644 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.2-01.S +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.2-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:34:58 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 64 \ // --randomize \ diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S index fdb3cd523..960bfcbad 100644 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:34:58 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 64 \ // --randomize \ diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.4-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.4-01.S index 8b57047dc..093e87b5b 100644 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.4-01.S +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.4-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:34:58 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 64 \ // --randomize \ diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S index aaaf97509..d774816c7 100644 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:34:58 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 64 \ // --randomize \ diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.6-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.6-01.S index ae6eb575c..9cbd894ca 100644 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.6-01.S +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.6-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:34:58 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 64 \ // --randomize \ diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S index 283ddedcf..848f32b8d 100644 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S @@ -4,8 +4,8 @@ // version : 0.11.1 // timestamp : Sat Sep 23 15:34:58 2023 GMT // usage : riscv_ctg \ -// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ +// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ \ // -- xlen 64 \ // --randomize \ From 45cb2994787367953488ce26c16bb8e8867117bd Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Mon, 16 Oct 2023 17:37:42 -0500 Subject: [PATCH 6/9] renaming files to update mnemonic --- .../rv64i_m/Zcmop/src/c.mop.0-01.S | 122 ------------------ .../rv64i_m/Zcmop/src/c.mop.1-01.S | 122 ------------------ .../rv64i_m/Zcmop/src/c.mop.2-01.S | 122 ------------------ .../rv64i_m/Zcmop/src/c.mop.3-01.S | 122 ------------------ .../rv64i_m/Zcmop/src/c.mop.4-01.S | 122 ------------------ .../rv64i_m/Zcmop/src/c.mop.5-01.S | 122 ------------------ .../rv64i_m/Zcmop/src/c.mop.6-01.S | 122 ------------------ .../rv64i_m/Zcmop/src/c.mop.7-01.S | 122 ------------------ 8 files changed, 976 deletions(-) delete mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.0-01.S delete mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S delete mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.2-01.S delete mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S delete mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.4-01.S delete mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S delete mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.6-01.S delete mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.0-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.0-01.S deleted file mode 100644 index 51bda0eff..000000000 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.0-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:34:58 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 64 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.0 instruction of the RISC-V RV64CZcmop extension for the c.mop.0 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.0) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.0; immval:0x15 -TEST_CMOP_OP(c.mop.0, x1, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.0; immval:0x1 -TEST_CMOP_OP(c.mop.0, x1, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.0; immval:0x2 -TEST_CMOP_OP(c.mop.0, x1, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.0; immval:0x1f -TEST_CMOP_OP(c.mop.0, x1, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.0; immval:0x4 -TEST_CMOP_OP(c.mop.0, x1, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.0; immval:0x8 -TEST_CMOP_OP(c.mop.0, x1, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.0; immval:0x10 -TEST_CMOP_OP(c.mop.0, x1, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S deleted file mode 100644 index 9d14de682..000000000 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:34:58 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 64 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.1 instruction of the RISC-V RV64CZcmop extension for the c.mop.1 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.1) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.1; immval:0x15 -TEST_CMOP_OP(c.mop.1, x3, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.1; immval:0x1 -TEST_CMOP_OP(c.mop.1, x3, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.1; immval:0x2 -TEST_CMOP_OP(c.mop.1, x3, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.1; immval:0x1f -TEST_CMOP_OP(c.mop.1, x3, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.1; immval:0x4 -TEST_CMOP_OP(c.mop.1, x3, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.1; immval:0x8 -TEST_CMOP_OP(c.mop.1, x3, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.1; immval:0x10 -TEST_CMOP_OP(c.mop.1, x3, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.2-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.2-01.S deleted file mode 100644 index a68feb1bf..000000000 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.2-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:34:58 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 64 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.2 instruction of the RISC-V RV64CZcmop extension for the c.mop.2 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.2) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.2; immval:0x15 -TEST_CMOP_OP(c.mop.2, x5, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.2; immval:0x1 -TEST_CMOP_OP(c.mop.2, x5, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.2; immval:0x2 -TEST_CMOP_OP(c.mop.2, x5, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.2; immval:0x1f -TEST_CMOP_OP(c.mop.2, x5, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.2; immval:0x4 -TEST_CMOP_OP(c.mop.2, x5, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.2; immval:0x8 -TEST_CMOP_OP(c.mop.2, x5, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.2; immval:0x10 -TEST_CMOP_OP(c.mop.2, x5, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S deleted file mode 100644 index 960bfcbad..000000000 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:34:58 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 64 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.3 instruction of the RISC-V RV64CZcmop extension for the c.mop.3 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.3) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.3; immval:0x15 -TEST_CMOP_OP(c.mop.3, x7, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.3; immval:0x1 -TEST_CMOP_OP(c.mop.3, x7, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.3; immval:0x2 -TEST_CMOP_OP(c.mop.3, x7, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.3; immval:0x1f -TEST_CMOP_OP(c.mop.3, x7, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.3; immval:0x4 -TEST_CMOP_OP(c.mop.3, x7, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.3; immval:0x8 -TEST_CMOP_OP(c.mop.3, x7, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.3; immval:0x10 -TEST_CMOP_OP(c.mop.3, x7, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.4-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.4-01.S deleted file mode 100644 index 093e87b5b..000000000 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.4-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:34:58 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 64 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.4 instruction of the RISC-V RV64CZcmop extension for the c.mop.4 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.4) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.4; immval:0x15 -TEST_CMOP_OP(c.mop.4, x9, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.4; immval:0x1 -TEST_CMOP_OP(c.mop.4, x9, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.4; immval:0x2 -TEST_CMOP_OP(c.mop.4, x9, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.4; immval:0x1f -TEST_CMOP_OP(c.mop.4, x9, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.4; immval:0x4 -TEST_CMOP_OP(c.mop.4, x9, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.4; immval:0x8 -TEST_CMOP_OP(c.mop.4, x9, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.4; immval:0x10 -TEST_CMOP_OP(c.mop.4, x9, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S deleted file mode 100644 index d774816c7..000000000 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:34:58 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 64 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.5 instruction of the RISC-V RV64CZcmop extension for the c.mop.5 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.5) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.5; immval:0x15 -TEST_CMOP_OP(c.mop.5, x11, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.5; immval:0x1 -TEST_CMOP_OP(c.mop.5, x11, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.5; immval:0x2 -TEST_CMOP_OP(c.mop.5, x11, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.5; immval:0x1f -TEST_CMOP_OP(c.mop.5, x11, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.5; immval:0x4 -TEST_CMOP_OP(c.mop.5, x11, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.5; immval:0x8 -TEST_CMOP_OP(c.mop.5, x11, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.5; immval:0x10 -TEST_CMOP_OP(c.mop.5, x11, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.6-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.6-01.S deleted file mode 100644 index 9cbd894ca..000000000 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.6-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:34:58 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 64 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.6 instruction of the RISC-V RV64CZcmop extension for the c.mop.6 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.6) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.6; immval:0x15 -TEST_CMOP_OP(c.mop.6, x13, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.6; immval:0x1 -TEST_CMOP_OP(c.mop.6, x13, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.6; immval:0x2 -TEST_CMOP_OP(c.mop.6, x13, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.6; immval:0x1f -TEST_CMOP_OP(c.mop.6, x13, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.6; immval:0x4 -TEST_CMOP_OP(c.mop.6, x13, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.6; immval:0x8 -TEST_CMOP_OP(c.mop.6, x13, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.6; immval:0x10 -TEST_CMOP_OP(c.mop.6, x13, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S deleted file mode 100644 index 848f32b8d..000000000 --- a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:34:58 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 64 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.7 instruction of the RISC-V RV64CZcmop extension for the c.mop.7 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV64ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.7) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.7; immval:0x15 -TEST_CMOP_OP(c.mop.7, x15, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.7; immval:0x1 -TEST_CMOP_OP(c.mop.7, x15, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.7; immval:0x2 -TEST_CMOP_OP(c.mop.7, x15, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.7; immval:0x1f -TEST_CMOP_OP(c.mop.7, x15, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.7; immval:0x4 -TEST_CMOP_OP(c.mop.7, x15, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.7; immval:0x8 -TEST_CMOP_OP(c.mop.7, x15, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.7; immval:0x10 -TEST_CMOP_OP(c.mop.7, x15, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END From 7e6fac03f7000167e383f85903aa515e1c19b823 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Mon, 16 Oct 2023 17:40:13 -0500 Subject: [PATCH 7/9] renaming files to update mnemonic --- .../rv32i_m/Zcmop/src/c.mop.0-01.S | 122 ------------------ .../rv32i_m/Zcmop/src/c.mop.1-01.S | 122 ------------------ .../rv32i_m/Zcmop/src/c.mop.2-01.S | 122 ------------------ .../rv32i_m/Zcmop/src/c.mop.3-01.S | 122 ------------------ .../rv32i_m/Zcmop/src/c.mop.4-01.S | 122 ------------------ .../rv32i_m/Zcmop/src/c.mop.5-01.S | 122 ------------------ .../rv32i_m/Zcmop/src/c.mop.6-01.S | 122 ------------------ .../rv32i_m/Zcmop/src/c.mop.7-01.S | 122 ------------------ 8 files changed, 976 deletions(-) delete mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.0-01.S delete mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S delete mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.2-01.S delete mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S delete mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.4-01.S delete mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S delete mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.6-01.S delete mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.0-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.0-01.S deleted file mode 100644 index aeb18683e..000000000 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.0-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:35:30 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 32 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.0 instruction of the RISC-V RV32CZcmop extension for the c.mop.0 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.0) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.0; immval:0x15 -TEST_CMOP_OP(c.mop.0, x1, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.0; immval:0x1 -TEST_CMOP_OP(c.mop.0, x1, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.0; immval:0x2 -TEST_CMOP_OP(c.mop.0, x1, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.0; immval:0x1f -TEST_CMOP_OP(c.mop.0, x1, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.0; immval:0x4 -TEST_CMOP_OP(c.mop.0, x1, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.0; immval:0x8 -TEST_CMOP_OP(c.mop.0, x1, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.0; immval:0x10 -TEST_CMOP_OP(c.mop.0, x1, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S deleted file mode 100644 index b525c36aa..000000000 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:35:30 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 32 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.1 instruction of the RISC-V RV32CZcmop extension for the c.mop.1 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.1) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.1; immval:0x15 -TEST_CMOP_OP(c.mop.1, x3, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.1; immval:0x1 -TEST_CMOP_OP(c.mop.1, x3, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.1; immval:0x2 -TEST_CMOP_OP(c.mop.1, x3, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.1; immval:0x1f -TEST_CMOP_OP(c.mop.1, x3, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.1; immval:0x4 -TEST_CMOP_OP(c.mop.1, x3, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.1; immval:0x8 -TEST_CMOP_OP(c.mop.1, x3, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.1; immval:0x10 -TEST_CMOP_OP(c.mop.1, x3, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.2-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.2-01.S deleted file mode 100644 index 05d806a96..000000000 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.2-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:35:30 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 32 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.2 instruction of the RISC-V RV32CZcmop extension for the c.mop.2 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.2) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.2; immval:0x15 -TEST_CMOP_OP(c.mop.2, x5, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.2; immval:0x1 -TEST_CMOP_OP(c.mop.2, x5, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.2; immval:0x2 -TEST_CMOP_OP(c.mop.2, x5, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.2; immval:0x1f -TEST_CMOP_OP(c.mop.2, x5, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.2; immval:0x4 -TEST_CMOP_OP(c.mop.2, x5, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.2; immval:0x8 -TEST_CMOP_OP(c.mop.2, x5, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.2; immval:0x10 -TEST_CMOP_OP(c.mop.2, x5, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S deleted file mode 100644 index ef4966b6c..000000000 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:35:30 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 32 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.3 instruction of the RISC-V RV32CZcmop extension for the c.mop.3 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.3) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.3; immval:0x15 -TEST_CMOP_OP(c.mop.3, x7, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.3; immval:0x1 -TEST_CMOP_OP(c.mop.3, x7, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.3; immval:0x2 -TEST_CMOP_OP(c.mop.3, x7, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.3; immval:0x1f -TEST_CMOP_OP(c.mop.3, x7, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.3; immval:0x4 -TEST_CMOP_OP(c.mop.3, x7, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.3; immval:0x8 -TEST_CMOP_OP(c.mop.3, x7, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.3; immval:0x10 -TEST_CMOP_OP(c.mop.3, x7, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.4-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.4-01.S deleted file mode 100644 index 3dbf5532b..000000000 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.4-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:35:30 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 32 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.4 instruction of the RISC-V RV32CZcmop extension for the c.mop.4 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.4) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.4; immval:0x15 -TEST_CMOP_OP(c.mop.4, x9, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.4; immval:0x1 -TEST_CMOP_OP(c.mop.4, x9, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.4; immval:0x2 -TEST_CMOP_OP(c.mop.4, x9, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.4; immval:0x1f -TEST_CMOP_OP(c.mop.4, x9, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.4; immval:0x4 -TEST_CMOP_OP(c.mop.4, x9, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.4; immval:0x8 -TEST_CMOP_OP(c.mop.4, x9, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.4; immval:0x10 -TEST_CMOP_OP(c.mop.4, x9, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S deleted file mode 100644 index eca260ada..000000000 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:35:30 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 32 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.5 instruction of the RISC-V RV32CZcmop extension for the c.mop.5 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.5) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.5; immval:0x15 -TEST_CMOP_OP(c.mop.5, x11, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.5; immval:0x1 -TEST_CMOP_OP(c.mop.5, x11, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.5; immval:0x2 -TEST_CMOP_OP(c.mop.5, x11, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.5; immval:0x1f -TEST_CMOP_OP(c.mop.5, x11, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.5; immval:0x4 -TEST_CMOP_OP(c.mop.5, x11, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.5; immval:0x8 -TEST_CMOP_OP(c.mop.5, x11, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.5; immval:0x10 -TEST_CMOP_OP(c.mop.5, x11, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.6-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.6-01.S deleted file mode 100644 index a8fc1c12a..000000000 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.6-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:35:30 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 32 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.6 instruction of the RISC-V RV32CZcmop extension for the c.mop.6 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.6) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.6; immval:0x15 -TEST_CMOP_OP(c.mop.6, x13, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.6; immval:0x1 -TEST_CMOP_OP(c.mop.6, x13, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.6; immval:0x2 -TEST_CMOP_OP(c.mop.6, x13, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.6; immval:0x1f -TEST_CMOP_OP(c.mop.6, x13, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.6; immval:0x4 -TEST_CMOP_OP(c.mop.6, x13, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.6; immval:0x8 -TEST_CMOP_OP(c.mop.6, x13, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.6; immval:0x10 -TEST_CMOP_OP(c.mop.6, x13, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S deleted file mode 100644 index 8b37caef3..000000000 --- a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S +++ /dev/null @@ -1,122 +0,0 @@ - -// ----------- -// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) -// version : 0.11.1 -// timestamp : Sat Sep 23 15:35:30 2023 GMT -// usage : riscv_ctg \ -// -- cgf // --cgf /riscv-ctg/sample_cgfs/dataset.cgf \ -// --cgf /riscv-ctg/sample_cgfs/zcmop.cgf \ - \ -// -- xlen 32 \ -// --randomize \ -// ----------- -// -// ----------- -// Copyright (c) 2020. RISC-V International. All rights reserved. -// SPDX-License-Identifier: BSD-3-Clause -// ----------- -// -// This assembly file tests the c.mop.7 instruction of the RISC-V RV32CZcmop extension for the c.mop.7 covergroup. -// -#include "model_test.h" -#include "arch_test.h" -RVTEST_ISA("RV32ICZcmop") - -.section .text.init -.globl rvtest_entry_point -rvtest_entry_point: -RVMODEL_BOOT -RVTEST_CODE_BEGIN - -#ifdef TEST_CASE_1 - -RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.7) - -RVTEST_SIGBASE(x1,signature_x1_1) - -inst_0: -// imm_val == 21, -// opcode:c.mop.7; immval:0x15 -TEST_CMOP_OP(c.mop.7, x15, 0x15, x1, x2, 0*XLEN/8) - -inst_1: -// imm_val == 1, -// opcode:c.mop.7; immval:0x1 -TEST_CMOP_OP(c.mop.7, x15, 0x1, x1, x2, 1*XLEN/8) - -inst_2: -// imm_val == -2, -// opcode:c.mop.7; immval:0x2 -TEST_CMOP_OP(c.mop.7, x15, 0x2, x1, x2, 2*XLEN/8) - -inst_3: -// imm_val == 31, -// opcode:c.mop.7; immval:0x1f -TEST_CMOP_OP(c.mop.7, x15, 0x1f, x1, x2, 3*XLEN/8) - -inst_4: -// imm_val == 4, -// opcode:c.mop.7; immval:0x4 -TEST_CMOP_OP(c.mop.7, x15, 0x4, x1, x2, 4*XLEN/8) - -inst_5: -// imm_val == 8, -// opcode:c.mop.7; immval:0x8 -TEST_CMOP_OP(c.mop.7, x15, 0x8, x1, x2, 5*XLEN/8) - -inst_6: -// imm_val == 16, -// opcode:c.mop.7; immval:0x10 -TEST_CMOP_OP(c.mop.7, x15, 0x10, x1, x2, 6*XLEN/8) -#endif - - -RVTEST_CODE_END -RVMODEL_HALT - -RVTEST_DATA_BEGIN -.align 4 -rvtest_data: -.word 0xbabecafe -.word 0xabecafeb -.word 0xbecafeba -.word 0xecafebab -RVTEST_DATA_END - -RVMODEL_DATA_BEGIN -rvtest_sig_begin: -sig_begin_canary: -CANARY; - - - -signature_x1_0: - .fill 0*((XLEN/8)/4),4,0xdeadbeef - - -signature_x1_1: - .fill 7*((XLEN/8)/4),4,0xdeadbeef - -#ifdef rvtest_mtrap_routine -tsig_begin_canary: -CANARY; - -mtrap_sigptr: - .fill 64*XLEN/32,4,0xdeadbeef - -tsig_end_canary: -CANARY; -#endif - -#ifdef rvtest_gpr_save - -gpr_save: - .fill 32*XLEN/32,4,0xdeadbeef - -#endif - - -sig_end_canary: -CANARY; -rvtest_sig_end: -RVMODEL_DATA_END From 2ae56a328e89c63b7a3aa1bebfba6063b56e592d Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Tue, 17 Oct 2023 11:03:31 -0500 Subject: [PATCH 8/9] update zcmop mnemonic --- coverage/zcmop.cgf | 32 ++--- .../rv32i_m/Zcmop/src/c.mop.1-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.11-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.13-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.15-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.3-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.5-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.7-01.S | 122 ++++++++++++++++++ .../rv32i_m/Zcmop/src/c.mop.9-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.1-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.11-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.13-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.15-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.3-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.5-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.7-01.S | 122 ++++++++++++++++++ .../rv64i_m/Zcmop/src/c.mop.9-01.S | 122 ++++++++++++++++++ 17 files changed, 1968 insertions(+), 16 deletions(-) create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.11-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.13-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.15-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zcmop/src/c.mop.9-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.11-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.13-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.15-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S create mode 100644 riscv-test-suite/rv64i_m/Zcmop/src/c.mop.9-01.S diff --git a/coverage/zcmop.cgf b/coverage/zcmop.cgf index b48f3274c..99329886a 100644 --- a/coverage/zcmop.cgf +++ b/coverage/zcmop.cgf @@ -1,71 +1,71 @@ -c.mop.0: +c.mop.1: config: - check ISA:=regex(.*C.*Zcmop.*) mnemonics: - c.mop.0: + c.mop.1: val_comb: abstract_comb: <<: *cbimm_val_walking -c.mop.1: +c.mop.3: config: - check ISA:=regex(.*C.*Zcmop.*) opcode: - c.mop.1: + c.mop.3: val_comb: abstract_comb: <<: *cbimm_val_walking -c.mop.2: +c.mop.5: config: - check ISA:=regex(.*C.*Zcmop.*) opcode: - c.mop.2: + c.mop.5: val_comb: abstract_comb: <<: *cbimm_val_walking -c.mop.3: +c.mop.7: config: - check ISA:=regex(.*C.*Zcmop.*) opcode: - c.mop.3: + c.mop.7: val_comb: abstract_comb: <<: *cbimm_val_walking -c.mop.4: +c.mop.9: config: - check ISA:=regex(.*C.*Zcmop.*) opcode: - c.mop.4: + c.mop.9: val_comb: abstract_comb: <<: *cbimm_val_walking -c.mop.5: +c.mop.11: config: - check ISA:=regex(.*C.*Zcmop.*) opcode: - c.mop.5: + c.mop.11: val_comb: abstract_comb: <<: *cbimm_val_walking -c.mop.6: +c.mop.13: config: - check ISA:=regex(.*C.*Zcmop.*) opcode: - c.mop.6: + c.mop.13: val_comb: abstract_comb: <<: *cbimm_val_walking -c.mop.7: +c.mop.15: config: - check ISA:=regex(.*C.*Zcmop.*) opcode: - c.mop.7: + c.mop.15: val_comb: abstract_comb: <<: *cbimm_val_walking diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S new file mode 100644 index 000000000..6c0cd0e44 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.1-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:40:56 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.1 instruction of the RISC-V RV32CZcmop extension for the c.mop.1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.1) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.1; immval:0x15 +TEST_CMOP_OP(c.mop.1, x1, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.1; immval:0x1 +TEST_CMOP_OP(c.mop.1, x1, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.1; immval:0x2 +TEST_CMOP_OP(c.mop.1, x1, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.1; immval:0x1f +TEST_CMOP_OP(c.mop.1, x1, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.1; immval:0x4 +TEST_CMOP_OP(c.mop.1, x1, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.1; immval:0x8 +TEST_CMOP_OP(c.mop.1, x1, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.1; immval:0x10 +TEST_CMOP_OP(c.mop.1, x1, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.11-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.11-01.S new file mode 100644 index 000000000..11d2dd818 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.11-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:40:56 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.11 instruction of the RISC-V RV32CZcmop extension for the c.mop.11 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.11) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.11; immval:0x15 +TEST_CMOP_OP(c.mop.11, x11, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.11; immval:0x1 +TEST_CMOP_OP(c.mop.11, x11, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.11; immval:0x2 +TEST_CMOP_OP(c.mop.11, x11, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.11; immval:0x1f +TEST_CMOP_OP(c.mop.11, x11, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.11; immval:0x4 +TEST_CMOP_OP(c.mop.11, x11, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.11; immval:0x8 +TEST_CMOP_OP(c.mop.11, x11, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.11; immval:0x10 +TEST_CMOP_OP(c.mop.11, x11, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.13-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.13-01.S new file mode 100644 index 000000000..d3d0fabd4 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.13-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:40:56 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.13 instruction of the RISC-V RV32CZcmop extension for the c.mop.13 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.13) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.13; immval:0x15 +TEST_CMOP_OP(c.mop.13, x13, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.13; immval:0x1 +TEST_CMOP_OP(c.mop.13, x13, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.13; immval:0x2 +TEST_CMOP_OP(c.mop.13, x13, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.13; immval:0x1f +TEST_CMOP_OP(c.mop.13, x13, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.13; immval:0x4 +TEST_CMOP_OP(c.mop.13, x13, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.13; immval:0x8 +TEST_CMOP_OP(c.mop.13, x13, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.13; immval:0x10 +TEST_CMOP_OP(c.mop.13, x13, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.15-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.15-01.S new file mode 100644 index 000000000..629520815 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.15-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:40:56 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.15 instruction of the RISC-V RV32CZcmop extension for the c.mop.15 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.15) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.15; immval:0x15 +TEST_CMOP_OP(c.mop.15, x15, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.15; immval:0x1 +TEST_CMOP_OP(c.mop.15, x15, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.15; immval:0x2 +TEST_CMOP_OP(c.mop.15, x15, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.15; immval:0x1f +TEST_CMOP_OP(c.mop.15, x15, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.15; immval:0x4 +TEST_CMOP_OP(c.mop.15, x15, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.15; immval:0x8 +TEST_CMOP_OP(c.mop.15, x15, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.15; immval:0x10 +TEST_CMOP_OP(c.mop.15, x15, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S new file mode 100644 index 000000000..10db333a7 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.3-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:40:56 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.3 instruction of the RISC-V RV32CZcmop extension for the c.mop.3 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.3) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.3; immval:0x15 +TEST_CMOP_OP(c.mop.3, x3, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.3; immval:0x1 +TEST_CMOP_OP(c.mop.3, x3, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.3; immval:0x2 +TEST_CMOP_OP(c.mop.3, x3, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.3; immval:0x1f +TEST_CMOP_OP(c.mop.3, x3, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.3; immval:0x4 +TEST_CMOP_OP(c.mop.3, x3, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.3; immval:0x8 +TEST_CMOP_OP(c.mop.3, x3, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.3; immval:0x10 +TEST_CMOP_OP(c.mop.3, x3, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S new file mode 100644 index 000000000..40df1f3cc --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.5-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:40:56 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.5 instruction of the RISC-V RV32CZcmop extension for the c.mop.5 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.5) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.5; immval:0x15 +TEST_CMOP_OP(c.mop.5, x5, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.5; immval:0x1 +TEST_CMOP_OP(c.mop.5, x5, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.5; immval:0x2 +TEST_CMOP_OP(c.mop.5, x5, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.5; immval:0x1f +TEST_CMOP_OP(c.mop.5, x5, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.5; immval:0x4 +TEST_CMOP_OP(c.mop.5, x5, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.5; immval:0x8 +TEST_CMOP_OP(c.mop.5, x5, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.5; immval:0x10 +TEST_CMOP_OP(c.mop.5, x5, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S new file mode 100644 index 000000000..3fed4f825 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.7-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:40:56 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.7 instruction of the RISC-V RV32CZcmop extension for the c.mop.7 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.7) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.7; immval:0x15 +TEST_CMOP_OP(c.mop.7, x7, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.7; immval:0x1 +TEST_CMOP_OP(c.mop.7, x7, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.7; immval:0x2 +TEST_CMOP_OP(c.mop.7, x7, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.7; immval:0x1f +TEST_CMOP_OP(c.mop.7, x7, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.7; immval:0x4 +TEST_CMOP_OP(c.mop.7, x7, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.7; immval:0x8 +TEST_CMOP_OP(c.mop.7, x7, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.7; immval:0x10 +TEST_CMOP_OP(c.mop.7, x7, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.9-01.S b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.9-01.S new file mode 100644 index 000000000..702d6894c --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zcmop/src/c.mop.9-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:40:56 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.9 instruction of the RISC-V RV32CZcmop extension for the c.mop.9 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.9) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.9; immval:0x15 +TEST_CMOP_OP(c.mop.9, x9, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.9; immval:0x1 +TEST_CMOP_OP(c.mop.9, x9, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.9; immval:0x2 +TEST_CMOP_OP(c.mop.9, x9, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.9; immval:0x1f +TEST_CMOP_OP(c.mop.9, x9, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.9; immval:0x4 +TEST_CMOP_OP(c.mop.9, x9, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.9; immval:0x8 +TEST_CMOP_OP(c.mop.9, x9, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.9; immval:0x10 +TEST_CMOP_OP(c.mop.9, x9, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S new file mode 100644 index 000000000..40c4a3467 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.1-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:27:26 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.1 instruction of the RISC-V RV64CZcmop extension for the c.mop.1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.1) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.1; immval:0x15 +TEST_CMOP_OP(c.mop.1, x1, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.1; immval:0x1 +TEST_CMOP_OP(c.mop.1, x1, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.1; immval:0x2 +TEST_CMOP_OP(c.mop.1, x1, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.1; immval:0x1f +TEST_CMOP_OP(c.mop.1, x1, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.1; immval:0x4 +TEST_CMOP_OP(c.mop.1, x1, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.1; immval:0x8 +TEST_CMOP_OP(c.mop.1, x1, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.1; immval:0x10 +TEST_CMOP_OP(c.mop.1, x1, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.11-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.11-01.S new file mode 100644 index 000000000..9a79a4790 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.11-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:27:26 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.11 instruction of the RISC-V RV64CZcmop extension for the c.mop.11 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.11) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.11; immval:0x15 +TEST_CMOP_OP(c.mop.11, x11, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.11; immval:0x1 +TEST_CMOP_OP(c.mop.11, x11, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.11; immval:0x2 +TEST_CMOP_OP(c.mop.11, x11, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.11; immval:0x1f +TEST_CMOP_OP(c.mop.11, x11, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.11; immval:0x4 +TEST_CMOP_OP(c.mop.11, x11, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.11; immval:0x8 +TEST_CMOP_OP(c.mop.11, x11, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.11; immval:0x10 +TEST_CMOP_OP(c.mop.11, x11, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.13-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.13-01.S new file mode 100644 index 000000000..c2740d626 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.13-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:27:26 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.13 instruction of the RISC-V RV64CZcmop extension for the c.mop.13 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.13) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.13; immval:0x15 +TEST_CMOP_OP(c.mop.13, x13, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.13; immval:0x1 +TEST_CMOP_OP(c.mop.13, x13, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.13; immval:0x2 +TEST_CMOP_OP(c.mop.13, x13, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.13; immval:0x1f +TEST_CMOP_OP(c.mop.13, x13, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.13; immval:0x4 +TEST_CMOP_OP(c.mop.13, x13, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.13; immval:0x8 +TEST_CMOP_OP(c.mop.13, x13, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.13; immval:0x10 +TEST_CMOP_OP(c.mop.13, x13, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.15-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.15-01.S new file mode 100644 index 000000000..7f85f40c3 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.15-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:27:26 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.15 instruction of the RISC-V RV64CZcmop extension for the c.mop.15 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.15) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.15; immval:0x15 +TEST_CMOP_OP(c.mop.15, x15, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.15; immval:0x1 +TEST_CMOP_OP(c.mop.15, x15, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.15; immval:0x2 +TEST_CMOP_OP(c.mop.15, x15, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.15; immval:0x1f +TEST_CMOP_OP(c.mop.15, x15, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.15; immval:0x4 +TEST_CMOP_OP(c.mop.15, x15, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.15; immval:0x8 +TEST_CMOP_OP(c.mop.15, x15, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.15; immval:0x10 +TEST_CMOP_OP(c.mop.15, x15, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S new file mode 100644 index 000000000..59c199168 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.3-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:27:26 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.3 instruction of the RISC-V RV64CZcmop extension for the c.mop.3 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.3) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.3; immval:0x15 +TEST_CMOP_OP(c.mop.3, x3, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.3; immval:0x1 +TEST_CMOP_OP(c.mop.3, x3, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.3; immval:0x2 +TEST_CMOP_OP(c.mop.3, x3, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.3; immval:0x1f +TEST_CMOP_OP(c.mop.3, x3, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.3; immval:0x4 +TEST_CMOP_OP(c.mop.3, x3, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.3; immval:0x8 +TEST_CMOP_OP(c.mop.3, x3, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.3; immval:0x10 +TEST_CMOP_OP(c.mop.3, x3, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S new file mode 100644 index 000000000..8a53f2ce7 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.5-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:27:26 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.5 instruction of the RISC-V RV64CZcmop extension for the c.mop.5 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.5) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.5; immval:0x15 +TEST_CMOP_OP(c.mop.5, x5, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.5; immval:0x1 +TEST_CMOP_OP(c.mop.5, x5, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.5; immval:0x2 +TEST_CMOP_OP(c.mop.5, x5, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.5; immval:0x1f +TEST_CMOP_OP(c.mop.5, x5, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.5; immval:0x4 +TEST_CMOP_OP(c.mop.5, x5, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.5; immval:0x8 +TEST_CMOP_OP(c.mop.5, x5, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.5; immval:0x10 +TEST_CMOP_OP(c.mop.5, x5, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S new file mode 100644 index 000000000..ef847585f --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.7-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:27:26 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.7 instruction of the RISC-V RV64CZcmop extension for the c.mop.7 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.7) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.7; immval:0x15 +TEST_CMOP_OP(c.mop.7, x7, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.7; immval:0x1 +TEST_CMOP_OP(c.mop.7, x7, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.7; immval:0x2 +TEST_CMOP_OP(c.mop.7, x7, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.7; immval:0x1f +TEST_CMOP_OP(c.mop.7, x7, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.7; immval:0x4 +TEST_CMOP_OP(c.mop.7, x7, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.7; immval:0x8 +TEST_CMOP_OP(c.mop.7, x7, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.7; immval:0x10 +TEST_CMOP_OP(c.mop.7, x7, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.9-01.S b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.9-01.S new file mode 100644 index 000000000..0e51f14cb --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zcmop/src/c.mop.9-01.S @@ -0,0 +1,122 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Mon Oct 16 22:27:26 2023 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/vedvyas/rvi-code-forks/riscv-ctg/sample_cgfs/zcmop.cgf \ + \ +// -- xlen 64 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.mop.9 instruction of the RISC-V RV64CZcmop extension for the c.mop.9 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV64ICZcmop") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*C.*Zcmop.*);def TEST_CASE_1=True;",c.mop.9) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// imm_val == 21, +// opcode:c.mop.9; immval:0x15 +TEST_CMOP_OP(c.mop.9, x9, 0x15, x1, x2, 0*XLEN/8) + +inst_1: +// imm_val == 1, +// opcode:c.mop.9; immval:0x1 +TEST_CMOP_OP(c.mop.9, x9, 0x1, x1, x2, 1*XLEN/8) + +inst_2: +// imm_val == -2, +// opcode:c.mop.9; immval:0x2 +TEST_CMOP_OP(c.mop.9, x9, 0x2, x1, x2, 2*XLEN/8) + +inst_3: +// imm_val == 31, +// opcode:c.mop.9; immval:0x1f +TEST_CMOP_OP(c.mop.9, x9, 0x1f, x1, x2, 3*XLEN/8) + +inst_4: +// imm_val == 4, +// opcode:c.mop.9; immval:0x4 +TEST_CMOP_OP(c.mop.9, x9, 0x4, x1, x2, 4*XLEN/8) + +inst_5: +// imm_val == 8, +// opcode:c.mop.9; immval:0x8 +TEST_CMOP_OP(c.mop.9, x9, 0x8, x1, x2, 5*XLEN/8) + +inst_6: +// imm_val == 16, +// opcode:c.mop.9; immval:0x10 +TEST_CMOP_OP(c.mop.9, x9, 0x10, x1, x2, 6*XLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 7*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END From 7cf18f277bcfe77181a85be6f2816ba42d4bac14 Mon Sep 17 00:00:00 2001 From: Umer Shahid Date: Tue, 7 May 2024 17:35:49 +0500 Subject: [PATCH 9/9] Update CHANGELOG.md Updated Changelog file to remove versioning issues Signed-off-by: Umer Shahid --- CHANGELOG.md | 242 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 241 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 461b68dd0..6ece28712 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,14 +1,254 @@ # CHANGELOG -## [3.7.2] - 2023-09-23 +## [3.8.20] - 2024-05-08 - Updated the Zcmop extension +## [3.8.19] - 2024-05-08 +- Add support for unratified Svadu extension + +## [3.8.18] - 2024-05-08 +- Add Zacas ISA extension support. + +## [3.8.17] - 2024-05-03 +- Add Zfa support. +- +## [3.8.16] - 2024-04-26 +- Split rv32i_m/F/fnmadd_b15.S, fnmsub_b15.S, fmadd_b15.S, fmsub_b15.S into multiple smaller tests + +## [3.8.15] - 2024-04-20 +Corrected missing 32 string in RVTEST_CASE macros for Zcb rv32i_m/C/clh-01.S + +## [3.8.14] - 2024-04-16 +Add missing `Zfh` ISA in RVTEST_CASE for `Zfh` fdiv related tests + +## [3.8.13] - 2024-04-13 +- Fixed missing `F` and `Zfh` ISA identifiers in `Zfh/flh-align-01` RVTEST_CASE macro. + + +## [3.8.12] - 2024-03-26 +Corrected missing RV64 strings in RVTEST_CASE macros for Zfh fcvt.h.l and similar tests + +## [3.8.11] - 2024-03-26 +- Added test suites for Zfh extensions. +- Introduced half word and half width in Nan boxing functionality to accomdate Zfh extensions. +- Added test suites for Zfinx extensions. + +## [3.8.10] -- 2024-03-24 +- Updated TEST_JALR_OP in test_macros.h +- The macro no longer works when rd = x0 in versions of GCC newer than 2023.12.20 +- riscof throws a message /home/jstine/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S:72: Error: illegal operands `la x0,5b' +- The TEST_JALR_OP macro invokes LA, which does not like x0 as an operand +- replacing LA(rd, 5b) with auipc rd, 0 in test_macros.h solves the compiler issue and produces similar code but without a bunch of preceeding nops + + +## [3.8.9] -- 2024-01-12 +- Fixed Check ISA fields to include 32/64 in Zicond tests. Note that the riscv-ctg CGFs have not been updated. + +## [3.8.8] -- 2024-01-04 +- Fixed macros to allow assembling tests with LLVM. + +## [3.8.7] -- 2024-01-02 +- Update satp initialization macro + +## [3.8.6] -- 2023-12-24 +- Fixed check ISA fields to include 32/64 in Zca and CMO tests. Note that the riscv-ctg CGFs have not been updated. +- Fixed check ISA fields in rv32e_m/B/src/ror-01 and rori-01 that listed I instead of E. Again, CGF has not been updated. + +## [3.8.5] -- 2023-12-23 +- Renamed rv32e_unratified to rv32e_m because the E extension has been ratified January 2023 +- Copied missing ebreak.S and ecall.S tests from rv32i_m/privilege to rv32e_m/privilege and update ISA for E + +## [3.8.3] - 2023-11-30 +- Add Zicond ISA extension support + +## [3.8.4] - 2023-11-30 + +- Added test suites for `zcb` from code size reduction extension. +- Added test macro for instructions with single operand. + +## [3.8.2.3] -- 2013-11-19 +-Fixed typo in regex in 3.8.2.2 + +## [3.8.2.2] -- 2013-11-17 +- Restored *RV32 Check ISA attributes to RV32IM test cases where they were dropped in 3.8.2. Missed these on 3.8.2.1. + +## [3.8.2.1] -- 2013-11-15 +- Restored *RV64 Check ISA attributes to RV64IM test cases where they were dropped in 3.8.2. Similar to 3.7.5 + +## [3.8.2] - 2023-11-14 +- Added "most negative number divided by -1" case for RV64IM and RV32IM in remw, divw, div and rem tests + +## [3.8.1] - 2023-11-01 +- Updated trap handler to avoid using mstatush when used for Priv Arch 1.11 +- Updated GOTO_Lower_Mode macro to adjust the save area when switching to Umode. + +## [3.8.0] - 2023-10-26 +- Updated trap handler to handle delegated exceptions in S-mode for both bare and virtual modes. +- Added Hypervisor mode support in Trap handler +- Updated the save area within the trap handler file. +- Improved CSR Rename macro for code clarity. + +## [3.7.5] - 2023-10-11 +Add missing check ISA fields in recently modified div and amo tests + +## [3.7.4] - 2023-10-04 +- Fix typos in CONTRIBUTION.md + +## [3.7.3] - 2023-09-29 +- Added test RV32i_m/div-01.S and RV64i_m/div-01.S tests. +- Added tests for resolving missing coverage issue of harcoded registers[issue #306](https://github.com/riscv-non-isa/riscv-arch-test/issues/306) +## [3.7.2] - 2023-08-16 +- Added RV32E_Privilege,RV32E_B and RV32E_Fencei tests with cgf files + +## [3.7.2] - 2023-09-27 +- Modified macros to allow assembling tests with LLVM 18+ + +## [3.7.1] - 2023-08-03 +- Add ACTs for Atomic Extension excluding Lr/Sc Instructions. +- Added Test macro for the execution of atomic instructions. + +## [3.7.1] - 2023-07-30 +- Add support for unratified Svadu extension + +## [3.8.20] - 2024-05-08 +- Add Zimop extension. +- +## [3.8.19] - 2024-05-08 +- Add support for unratified Svadu extension + +## [3.8.18] - 2024-05-08 +- Add Zacas ISA extension support. + +## [3.8.17] - 2024-05-03 +- Add Zfa support. +- +## [3.8.16] - 2024-04-26 +- Split rv32i_m/F/fnmadd_b15.S, fnmsub_b15.S, fmadd_b15.S, fmsub_b15.S into multiple smaller tests + +## [3.8.15] - 2024-04-20 +Corrected missing 32 string in RVTEST_CASE macros for Zcb rv32i_m/C/clh-01.S + +## [3.8.14] - 2024-04-16 +Add missing `Zfh` ISA in RVTEST_CASE for `Zfh` fdiv related tests + +## [3.8.13] - 2024-04-13 +- Fixed missing `F` and `Zfh` ISA identifiers in `Zfh/flh-align-01` RVTEST_CASE macro. + + +## [3.8.12] - 2024-03-26 +Corrected missing RV64 strings in RVTEST_CASE macros for Zfh fcvt.h.l and similar tests + +## [3.8.11] - 2024-03-26 +- Added test suites for Zfh extensions. +- Introduced half word and half width in Nan boxing functionality to accomdate Zfh extensions. +- Added test suites for Zfinx extensions. + +## [3.8.10] -- 2024-03-24 +- Updated TEST_JALR_OP in test_macros.h +- The macro no longer works when rd = x0 in versions of GCC newer than 2023.12.20 +- riscof throws a message /home/jstine/cvw/addins/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S:72: Error: illegal operands `la x0,5b' +- The TEST_JALR_OP macro invokes LA, which does not like x0 as an operand +- replacing LA(rd, 5b) with auipc rd, 0 in test_macros.h solves the compiler issue and produces similar code but without a bunch of preceeding nops + + +## [3.8.9] -- 2024-01-12 +- Fixed Check ISA fields to include 32/64 in Zicond tests. Note that the riscv-ctg CGFs have not been updated. + +## [3.8.8] -- 2024-01-04 +- Fixed macros to allow assembling tests with LLVM. + +## [3.8.7] -- 2024-01-02 +- Update satp initialization macro + +## [3.8.6] -- 2023-12-24 +- Fixed check ISA fields to include 32/64 in Zca and CMO tests. Note that the riscv-ctg CGFs have not been updated. +- Fixed check ISA fields in rv32e_m/B/src/ror-01 and rori-01 that listed I instead of E. Again, CGF has not been updated. + +## [3.8.5] -- 2023-12-23 +- Renamed rv32e_unratified to rv32e_m because the E extension has been ratified January 2023 +- Copied missing ebreak.S and ecall.S tests from rv32i_m/privilege to rv32e_m/privilege and update ISA for E + +## [3.8.3] - 2023-11-30 +- Add Zicond ISA extension support + +## [3.8.4] - 2023-11-30 + +- Added test suites for `zcb` from code size reduction extension. +- Added test macro for instructions with single operand. + +## [3.8.2.3] -- 2013-11-19 +-Fixed typo in regex in 3.8.2.2 + +## [3.8.2.2] -- 2013-11-17 +- Restored *RV32 Check ISA attributes to RV32IM test cases where they were dropped in 3.8.2. Missed these on 3.8.2.1. + +## [3.8.2.1] -- 2013-11-15 +- Restored *RV64 Check ISA attributes to RV64IM test cases where they were dropped in 3.8.2. Similar to 3.7.5 + +## [3.8.2] - 2023-11-14 +- Added "most negative number divided by -1" case for RV64IM and RV32IM in remw, divw, div and rem tests + +## [3.8.1] - 2023-11-01 +- Updated trap handler to avoid using mstatush when used for Priv Arch 1.11 +- Updated GOTO_Lower_Mode macro to adjust the save area when switching to Umode. + +## [3.8.0] - 2023-10-26 +- Updated trap handler to handle delegated exceptions in S-mode for both bare and virtual modes. +- Added Hypervisor mode support in Trap handler +- Updated the save area within the trap handler file. +- Improved CSR Rename macro for code clarity. + +## [3.7.5] - 2023-10-11 +Add missing check ISA fields in recently modified div and amo tests + +## [3.7.4] - 2023-10-04 +- Fix typos in CONTRIBUTION.md + +## [3.7.3] - 2023-09-29 +- Added test RV32i_m/div-01.S and RV64i_m/div-01.S tests. +- Added tests for resolving missing coverage issue of harcoded registers[issue #306](https://github.com/riscv-non-isa/riscv-arch-test/issues/306) +## [3.7.2] - 2023-08-16 +- Added RV32E_Privilege,RV32E_B and RV32E_Fencei tests with cgf files + +## [3.7.2] - 2023-09-27 +- Modified macros to allow assembling tests with LLVM 18+ + +## [3.7.1] - 2023-08-03 +- Add ACTs for Atomic Extension excluding Lr/Sc Instructions. +- Added Test macro for the execution of atomic instructions. + +## [3.7.1] - 2023-07-30 +- Add support for unratified Svadu extension + +## [3.7.0] - 2023-05-16 +- Updated the LI macro +- Make Trap handler compatible for RV32E +- Remove the warning messages [issue #336](https://github.com/riscv-non-isa/riscv-arch-test/issues/336) +- Added Macros for testing Virtual Memory in Sv32 mode. + +## [3.6.8] - 2023-06-22 +- Fix broken hyperlink in README + +## [3.6.7] - 2023-06-22 +- Specify new optional model macro RVMODEL_MTVEC_ALIGN to define new macro MTVEC_ALIGN in arch_test.h for issue #351 + +## [3.6.6] - 2023-06-17 +- Removed stale zext.h-01.S test case superseded by zext.h_64-01.S + +## [3.7.1] - 2023-07-22 +- Added test case for division if most negative number by -1 +- Solved the [issue #300](https://github.com/riscv-non-isa/riscv-arch-test/issues/300) + + ## [3.7.0] - 2023-05-16 - Updated the LI macro - Make Trap handler compatible for RV32E - Remove the warning messages [issue #336](https://github.com/riscv-non-isa/riscv-arch-test/issues/336) - Added Macros for testing Virtual Memory in Sv32 mode. +## [3.6.9] - 2023-06-25 +- Add support for Zicboz extension + ## [3.6.8] - 2023-06-22 - Fix broken hyperlink in README