From 8af9fabba4c4f25f56e35852de238fbd04399650 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sat, 29 Jul 2023 12:45:25 -0500 Subject: [PATCH 1/6] menvcfg encodings --- riscv-test-suite/env/encoding.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/riscv-test-suite/env/encoding.h b/riscv-test-suite/env/encoding.h index 1ee1285be..eae8cd330 100755 --- a/riscv-test-suite/env/encoding.h +++ b/riscv-test-suite/env/encoding.h @@ -131,6 +131,18 @@ #define SIP_SSIP MIP_SSIP #define SIP_STIP MIP_STIP +#define MENVCFG_FIOM 0x00000001 +#define MENVCFG_CBIE 0x00000030 +#define MENVCFG_CBCFE 0x00000040 +#define MENVCFG_CBZE 0x00000080 +#define MENVCFG_HADE 0x2000000000000000 +#define MENVCFG_PBMTE 0x4000000000000000 +#define MENVCFG_STCE 0x8000000000000000 + +#define MENVCFGH_HADE 0x20000000 +#define MENVCFGH_PBMTE 0x40000000 +#define MENVCFGH_STCE 0x80000000 + #define PRV_U 0 #define PRV_S 1 #define PRV_H 2 From a7a4ea0052135d295c8cc5e27c8e09efba9bb0dc Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sat, 29 Jul 2023 12:45:36 -0500 Subject: [PATCH 2/6] svadu test --- CHANGELOG.md | 3 + coverage/rv32_svadu.cgf | 8 ++ coverage/rv64_svadu.cgf | 17 ++++ .../rv32i_m/Svadu/src/svadu_sv32.S | 78 +++++++++++++++++++ .../rv64i_m/Svadu/src/svadu_sv39.S | 77 ++++++++++++++++++ .../rv64i_m/Svadu/src/svadu_sv48.S | 77 ++++++++++++++++++ .../rv64i_m/Svadu/src/svadu_sv57.S | 77 ++++++++++++++++++ 7 files changed, 337 insertions(+) create mode 100644 coverage/rv32_svadu.cgf create mode 100644 coverage/rv64_svadu.cgf create mode 100644 riscv-test-suite/rv32i_m/Svadu/src/svadu_sv32.S create mode 100644 riscv-test-suite/rv64i_m/Svadu/src/svadu_sv39.S create mode 100644 riscv-test-suite/rv64i_m/Svadu/src/svadu_sv48.S create mode 100644 riscv-test-suite/rv64i_m/Svadu/src/svadu_sv57.S diff --git a/CHANGELOG.md b/CHANGELOG.md index 7d682b8bb..a70f71cbf 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,8 @@ # CHANGELOG +## [3.7.1] - 2023-07-30 +- Add support for unratified Svadu extension + ## [3.7.0] - 2023-05-16 - Updated the LI macro - Make Trap handler compatible for RV32E diff --git a/coverage/rv32_svadu.cgf b/coverage/rv32_svadu.cgf new file mode 100644 index 000000000..a2a379f3f --- /dev/null +++ b/coverage/rv32_svadu.cgf @@ -0,0 +1,8 @@ + +svadu_sv32: + config: + - check ISA:=regex(.*I.*Svadu.*) + opcode: + nop: 0 + + diff --git a/coverage/rv64_svadu.cgf b/coverage/rv64_svadu.cgf new file mode 100644 index 000000000..4b57ece9e --- /dev/null +++ b/coverage/rv64_svadu.cgf @@ -0,0 +1,17 @@ +svadu_sv39: + config: + - check ISA:=regex(.*I.*Svadu.*) + opcode: + nop: 0 + +svadu_sv48: + config: + - check ISA:=regex(.*I.*Svadu.*) + opcode: + nop: 0 + +svadu_sv57: + config: + - check ISA:=regex(.*I.*Svadu.*) + opcode: + nop: 0 diff --git a/riscv-test-suite/rv32i_m/Svadu/src/svadu_sv32.S b/riscv-test-suite/rv32i_m/Svadu/src/svadu_sv32.S new file mode 100644 index 000000000..823df8bdf --- /dev/null +++ b/riscv-test-suite/rv32i_m/Svadu/src/svadu_sv32.S @@ -0,0 +1,78 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the Svadu extension +// +#include "model_test.h" +#include "arch_test.h" + +# Test Virtual Machine (TVM) used by program. +RVTEST_ISA("RV32I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv32) + + RVTEST_SIGBASE(x1, signature_x1_0) + + # enable pmp to cover 4 GiB address space + li t0, -1 + csrw pmpaddr0, t0 + li t0, PMP_TOR | PMP_X | PMP_W | PMP_R + csrw pmpcfg0, t0 + + # ID map the page_4k + la t1, page_4k + mv t2, t1 + PTE_SETUP_SV32(t1, PTE_V, t0, s2, t2, 1) + + # enable virtual memory in Sv32 mode + SATP_SETUP(t0, t1, SATP32_MODE) + + # test svadu + TEST_SVADU(x1, s2, page_4k, offset, 0x31a, MENVCFGH_HADE) + + RVMODEL_HALT + +#endif +RVTEST_CODE_END + +RVTEST_DATA_BEGIN + .align 12 + page_4k: + .fill 4096/REGWIDTH, REGWIDTH, 0 +RVTEST_DATA_END + + .align 12 +rvtest_Sroot_pg_tbl: + .fill 4096/REGWIDTH, REGWIDTH, 0 + +# Output data section. +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_x1_0: + .fill 128*(XLEN/32),4,0xdeadbeef + +mtrap_sigptr: + .fill 128*4, 4, 0xdeadbeef + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32), 4, 0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv39.S b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv39.S new file mode 100644 index 000000000..e1f53e8bf --- /dev/null +++ b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv39.S @@ -0,0 +1,77 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the Svadu extension +// +#include "model_test.h" +#include "arch_test.h" + +# Test Virtual Machine (TVM) used by program. +RVTEST_ISA("RV64I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv39) + + RVTEST_SIGBASE(x1, signature_x1_0) + + # enable pmp to cover 4 GiB address space + li t0, -1 + csrw pmpaddr0, t0 + li t0, PMP_TOR | PMP_X | PMP_W | PMP_R + csrw pmpcfg0, t0 + + # ID map the page_4k + la t1, page_4k + mv t2, t1 + PTE_SETUP_SV39(t1, PTE_V, t0, s2, t2, 2) + + # enable virtual memory in Sv32 mode + SATP_SETUP(t0, t1, ((SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39)) + + # test svadu + TEST_SVADU(x1, s2, page_4k, offset, 0x30a, MENVCFG_HADE) + + RVMODEL_HALT +#endif +RVTEST_CODE_END + +RVTEST_DATA_BEGIN + .align 12 + page_4k: + .fill 4096/REGWIDTH, REGWIDTH, 0 +RVTEST_DATA_END + + .align 12 +rvtest_Sroot_pg_tbl: + .fill 4096/REGWIDTH, REGWIDTH, 0 + +# Output data section. +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_x1_0: + .fill 64*(XLEN/32),4,0xdeadbeef + +mtrap_sigptr: + .fill 128*4, 4, 0xdeadbeef + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32), 4, 0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv48.S b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv48.S new file mode 100644 index 000000000..1cd356e16 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv48.S @@ -0,0 +1,77 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the Svadu extension +// +#include "model_test.h" +#include "arch_test.h" + +# Test Virtual Machine (TVM) used by program. +RVTEST_ISA("RV64I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv48) + + RVTEST_SIGBASE(x1, signature_x1_0) + + # enable pmp to cover 4 GiB address space + li t0, -1 + csrw pmpaddr0, t0 + li t0, PMP_TOR | PMP_X | PMP_W | PMP_R + csrw pmpcfg0, t0 + + # ID map the page_4k + la t1, page_4k + mv t2, t1 + PTE_SETUP_SV48(t1, PTE_V, t0, s2, t2, 3) + + # enable virtual memory in Sv32 mode + SATP_SETUP(t0, t1, ((SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV48)) + + # test svadu + TEST_SVADU(x1, s2, page_4k, offset, 0x30a, MENVCFG_HADE) + + RVMODEL_HALT +#endif +RVTEST_CODE_END + +RVTEST_DATA_BEGIN + .align 12 + page_4k: + .fill 4096/REGWIDTH, REGWIDTH, 0 +RVTEST_DATA_END + + .align 12 +rvtest_Sroot_pg_tbl: + .fill 4096/REGWIDTH, REGWIDTH, 0 + +# Output data section. +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_x1_0: + .fill 64*(XLEN/32),4,0xdeadbeef + +mtrap_sigptr: + .fill 128*4, 4, 0xdeadbeef + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32), 4, 0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv57.S b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv57.S new file mode 100644 index 000000000..38ff9f9ec --- /dev/null +++ b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv57.S @@ -0,0 +1,77 @@ +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the Svadu extension +// +#include "model_test.h" +#include "arch_test.h" + +# Test Virtual Machine (TVM) used by program. +RVTEST_ISA("RV64I_Zicsr") + +# Test code region +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv57) + + RVTEST_SIGBASE(x1, signature_x1_0) + + # enable pmp to cover 4 GiB address space + li t0, -1 + csrw pmpaddr0, t0 + li t0, PMP_TOR | PMP_X | PMP_W | PMP_R + csrw pmpcfg0, t0 + + # ID map the page_4k + la t1, page_4k + mv t2, t1 + PTE_SETUP_SV57(t1, PTE_V, t0, s2, t2, 4) + + # enable virtual memory in Sv32 mode + SATP_SETUP(t0, t1, ((SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV57)) + + # test svadu + TEST_SVADU(x1, s2, page_4k, offset, 0x30a, MENVCFG_HADE) + + RVMODEL_HALT +#endif +RVTEST_CODE_END + +RVTEST_DATA_BEGIN + .align 12 + page_4k: + .fill 4096/REGWIDTH, REGWIDTH, 0 +RVTEST_DATA_END + + .align 12 +rvtest_Sroot_pg_tbl: + .fill 4096/REGWIDTH, REGWIDTH, 0 + +# Output data section. +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_x1_0: + .fill 64*(XLEN/32),4,0xdeadbeef + +mtrap_sigptr: + .fill 128*4, 4, 0xdeadbeef + +#ifdef rvtest_gpr_save +gpr_save: + .fill 32*(XLEN/32), 4, 0xdeadbeef +#endif + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END From 78db16db059a1c3804f890a56f76bca0907f429a Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Thu, 3 Aug 2023 17:13:27 -0500 Subject: [PATCH 3/6] add svadu test macros --- riscv-test-suite/env/test_macros.h | 185 +++++++++++++++++++++++++---- 1 file changed, 164 insertions(+), 21 deletions(-) diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h index 6426d92f8..fd44eb166 100644 --- a/riscv-test-suite/env/test_macros.h +++ b/riscv-test-suite/env/test_macros.h @@ -17,23 +17,74 @@ //****NOTE: label `rvtest_Sroot_pg_tbl` must be declared after RVTEST_DATA_END // in the test aligned at 4kiB (use .align 12) - -#define PTE_SETUP_RV32(_PAR, _PR, _TR0, _TR1, VA, level) ;\ - srli _PAR, _PAR, 12 ;\ - slli _PAR, _PAR, 10 ;\ - or _PAR, _PAR, _PR ;\ - .if (level==1) ;\ - LA(_TR1, rvtest_Sroot_pg_tbl) ;\ - .set vpn, ((VA>>22)&0x3FF)<<2 ;\ - .endif ;\ - .if (level==0) ;\ - LA(_TR1, rvtest_slvl1_pg_tbl) ;\ - .set vpn, ((VA>>12)&0x3FF)<<2 ;\ - .endif ;\ - LI(_TR0, vpn) ;\ - add _TR1, _TR1, _TR0 ;\ +#define PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + srli _VAR, _VAR, (RISCV_PGLEVEL_BITS * level + RISCV_PGSHIFT) ;\ + srli _PAR, _PAR, (RISCV_PGLEVEL_BITS * level + RISCV_PGSHIFT) ;\ + slli _PAR, _PAR, (RISCV_PGLEVEL_BITS * level + RISCV_PGSHIFT) ;\ + LI(_TR0, ((1 << RISCV_PGLEVEL_BITS) - 1)) ;\ + and _VAR, _VAR, _TR0 ;\ + slli _VAR, _VAR, ((XLEN >> 5)+1) ;\ + add _TR1, _TR1, _VAR ;\ + srli _PAR, _PAR, 12 ;\ + slli _PAR, _PAR, 10 ;\ + or _PAR, _PAR, _PR ;\ SREG _PAR, 0(_TR1); +#define PTE_SETUP_SV32(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + .endif ;\ + PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) + +#define PTE_SETUP_SV39(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + .if (level==2) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + .endif ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_slvl2_pg_tbl) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + .endif ;\ + PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) + +#define PTE_SETUP_SV48(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + .if (level==3) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + .endif ;\ + .if (level==2) ;\ + LA(_TR1, rvtest_slvl3_pg_tbl) ;\ + .endif ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_slvl2_pg_tbl) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + .endif ;\ + PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) + +#define PTE_SETUP_SV57(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + .if (level==4) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + .endif ;\ + .if (level==3) ;\ + LA(_TR1, rvtest_slvl4_pg_tbl) ;\ + .endif ;\ + .if (level==2) ;\ + LA(_TR1, rvtest_slvl3_pg_tbl) ;\ + .endif ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_slvl2_pg_tbl) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + .endif ;\ + PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) + + #define PTE_PERMUPD_RV32(_PR, _TR0, _TR1, VA, level) ;\ .if (level==1) ;\ LA(_TR1, rvtest_Sroot_pg_tbl) ;\ @@ -51,12 +102,12 @@ or _TR0, _TR0, _PR ;\ SREG _TR0, 0(_TR1) ;\ -#define SATP_SETUP_SV32 ;\ - LA(t6, rvtest_Sroot_pg_tbl) ;\ - LI(t5, SATP32_MODE) ;\ - srli t6, t6, 12 ;\ - or t6, t6, t5 ;\ - csrw satp, t6 ;\ +#define SATP_SETUP(_TR0, _TR1, MODE);\ + LA(_TR0, rvtest_Sroot_pg_tbl) ;\ + LI(_TR1, MODE) ;\ + srli _TR0, _TR0, 12 ;\ + or _TR0, _TR0, _TR1 ;\ + csrw satp, _TR0 ;\ #define NAN_BOXED(__val__,__width__,__max__) ;\ .if __width__ == 32 ;\ @@ -933,6 +984,98 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg) sub x1,x1,tempreg ;\ RVTEST_SIGUPD(swreg,x1,offset) +#define TEST_SVADU(swreg, PTE_ADDR, VA, offset, menvcfgaddr, hade_bit) \ + sfence.vma ;\ + la t0, VA ;\ + li t2, PTE_X | PTE_W | PTE_R ;\ +1: ;\ + LREG t1, (PTE_ADDR) ;\ + andi t1, t1, ~(PTE_X | PTE_W | PTE_R | PTE_V) ;\ + or t1, t1, t2 ;\ + SREG t1, (PTE_ADDR) ;\ + sfence.vma ;\ + ;\ + li t1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\ + csrs mstatus, t1 ;\ + ;\ + .align 2 ;\ + SREG x0, (t0) ;\ + unimp ;\ + ;\ + li t1, MSTATUS_MPRV ;\ + csrc mstatus, t1 ;\ + ;\ + beqz t2, 2f ;\ + addi t2, t2, -1 ;\ + li t1, PTE_W | PTE_R | PTE_V ;\ + bne t2, t1, 1b ;\ + addi t2, t2, -1 ;\ + j 1b ;\ +2: ;\ + li t0, MSTATUS_MPRV ;\ + csrc mstatus, t0 ;\ + LREG t0, (PTE_ADDR) ;\ + and t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\ + RVTEST_SIGUPD(x1,t0,offset) ;\ + ;\ + LREG t0, (PTE_ADDR) ;\ + andi t0, t0, ~(PTE_X | PTE_W | PTE_R | PTE_V | PTE_A | PTE_D | PTE_V) ;\ + ori t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A ;\ + SREG t0, (PTE_ADDR) ;\ + sfence.vma ;\ + ;\ + la t0, VA ;\ + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\ + csrs mstatus, a1 ;\ + ;\ + .align 2 ;\ + SREG x0, (t0) ;\ + unimp ;\ + ;\ + li t0, MSTATUS_MPRV ;\ + csrc mstatus, t0 ;\ + ;\ + LREG t0, (PTE_ADDR) ;\ + and t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\ + RVTEST_SIGUPD(x1,t0,offset) ;\ + ;\ + LREG t0, (PTE_ADDR) ;\ + andi t0, t0, ~(PTE_X | PTE_W | PTE_R | PTE_V | PTE_A | PTE_D | PTE_V) ;\ + ori t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\ + SREG t0, (PTE_ADDR) ;\ + sfence.vma ;\ + la t0, VA ;\ + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\ + csrs mstatus, a1 ;\ + ;\ + SREG x0, (t0) ;\ + j 3f ;\ + unimp ;\ +3: ;\ + LREG t0, (PTE_ADDR) ;\ + andi t0, t0, ~(PTE_D) ;\ + SREG t0, (PTE_ADDR) ;\ + sfence.vma ;\ + ;\ + li t0, hade_bit ;\ + csrs menvcfgaddr, t0 ;\ + ;\ + la t0, VA ;\ + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\ + csrs mstatus, a1 ;\ + ;\ + .align 2 ;\ + SREG x0, (t0) ;\ + j 4f ;\ + unimp ;\ +4: ;\ + li t0, MSTATUS_MPRV ;\ + csrc mstatus, t0 ;\ + ;\ + LREG t0, (PTE_ADDR) ;\ + and t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\ + RVTEST_SIGUPD(x1,t0,offset) + //--------------------------------- Migration aliases ------------------------------------------ #ifdef RV_COMPLIANCE_RV32M From e0e57ece4792a2e970dbaa4dad2ceaf1bc93a1d0 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Thu, 3 Aug 2023 18:15:29 -0500 Subject: [PATCH 4/6] make PMP setup a common macro --- coverage/rv32_svadu.cgf | 4 ++-- coverage/rv64_svadu.cgf | 12 +++++----- riscv-test-suite/env/encoding.h | 4 ++-- riscv-test-suite/env/test_macros.h | 24 +++++++++++++++++-- .../rv32i_m/Svadu/src/svadu_sv32.S | 18 +++++++------- .../rv64i_m/Svadu/src/svadu_sv39.S | 20 +++++++--------- .../rv64i_m/Svadu/src/svadu_sv48.S | 20 +++++++--------- .../rv64i_m/Svadu/src/svadu_sv57.S | 20 +++++++--------- 8 files changed, 67 insertions(+), 55 deletions(-) diff --git a/coverage/rv32_svadu.cgf b/coverage/rv32_svadu.cgf index a2a379f3f..eee9cee6f 100644 --- a/coverage/rv32_svadu.cgf +++ b/coverage/rv32_svadu.cgf @@ -1,7 +1,7 @@ -svadu_sv32: +svhad_sv32: config: - - check ISA:=regex(.*I.*Svadu.*) + - check ISA:=regex(.*I.*Svhad.*) opcode: nop: 0 diff --git a/coverage/rv64_svadu.cgf b/coverage/rv64_svadu.cgf index 4b57ece9e..6514eebfe 100644 --- a/coverage/rv64_svadu.cgf +++ b/coverage/rv64_svadu.cgf @@ -1,17 +1,17 @@ -svadu_sv39: +svhad_sv39: config: - - check ISA:=regex(.*I.*Svadu.*) + - check ISA:=regex(.*I.*Svhad.*) opcode: nop: 0 -svadu_sv48: +svhad_sv48: config: - - check ISA:=regex(.*I.*Svadu.*) + - check ISA:=regex(.*I.*Svhad.*) opcode: nop: 0 -svadu_sv57: +svhad_sv57: config: - - check ISA:=regex(.*I.*Svadu.*) + - check ISA:=regex(.*I.*Svhad.*) opcode: nop: 0 diff --git a/riscv-test-suite/env/encoding.h b/riscv-test-suite/env/encoding.h index eae8cd330..1dbe6853a 100755 --- a/riscv-test-suite/env/encoding.h +++ b/riscv-test-suite/env/encoding.h @@ -135,11 +135,11 @@ #define MENVCFG_CBIE 0x00000030 #define MENVCFG_CBCFE 0x00000040 #define MENVCFG_CBZE 0x00000080 -#define MENVCFG_HADE 0x2000000000000000 +#define MENVCFG_ADUE 0x2000000000000000 #define MENVCFG_PBMTE 0x4000000000000000 #define MENVCFG_STCE 0x8000000000000000 -#define MENVCFGH_HADE 0x20000000 +#define MENVCFGH_ADUE 0x20000000 #define MENVCFGH_PBMTE 0x40000000 #define MENVCFGH_STCE 0x80000000 diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h index fd44eb166..511be17eb 100644 --- a/riscv-test-suite/env/test_macros.h +++ b/riscv-test-suite/env/test_macros.h @@ -984,7 +984,27 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg) sub x1,x1,tempreg ;\ RVTEST_SIGUPD(swreg,x1,offset) -#define TEST_SVADU(swreg, PTE_ADDR, VA, offset, menvcfgaddr, hade_bit) \ +#define SETUP_PMP_SVADU_TEST(swreg, offset, TR0, TR1, TR2) \ + li TR0, -1 ;\ + csrw pmpaddr0, TR0 ;\ + j PMP_exist ;\ + li TR0, 0 ;\ + li TR1, 0 ;\ + j Mend_PMP ;\ +PMP_exist: ;\ + li TR1, PMP_TOR | PMP_X | PMP_W | PMP_R ;\ + csrw pmpcfg0, TR1 ;\ + csrr TR2, pmpcfg0 ;\ + beq TR1, TR2, Mend_PMP ;\ +no_TOR_try_NAPOT: ;\ + li TR1, PMP_NAPOT | PMP_X | PMP_W | PMP_R ;\ + csrw pmpcfg0, TR1 ;\ + csrr TR2, pmpcfg0 ;\ +Mend_PMP: ;\ + RVTEST_SIGUPD(x1,TR0,offset) ;\ + RVTEST_SIGUPD(x1,TR1,offset) ;\ + +#define TEST_SVADU(swreg, PTE_ADDR, VA, offset, menvcfgaddr, adue_bit) \ sfence.vma ;\ la t0, VA ;\ li t2, PTE_X | PTE_W | PTE_R ;\ @@ -1057,7 +1077,7 @@ RVTEST_SIGUPD_F(swreg,destreg,flagreg) SREG t0, (PTE_ADDR) ;\ sfence.vma ;\ ;\ - li t0, hade_bit ;\ + li t0, adue_bit ;\ csrs menvcfgaddr, t0 ;\ ;\ la t0, VA ;\ diff --git a/riscv-test-suite/rv32i_m/Svadu/src/svadu_sv32.S b/riscv-test-suite/rv32i_m/Svadu/src/svadu_sv32.S index 823df8bdf..9c228fd86 100644 --- a/riscv-test-suite/rv32i_m/Svadu/src/svadu_sv32.S +++ b/riscv-test-suite/rv32i_m/Svadu/src/svadu_sv32.S @@ -19,17 +19,14 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv32) + RVTEST_CASE(1,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv32) RVTEST_SIGBASE(x1, signature_x1_0) - # enable pmp to cover 4 GiB address space - li t0, -1 - csrw pmpaddr0, t0 - li t0, PMP_TOR | PMP_X | PMP_W | PMP_R - csrw pmpcfg0, t0 + # Setup PMP to cover 4G of address space + SETUP_PMP_SVADU_TEST(x1, offset, t0, t1, t2) - # ID map the page_4k + # Identity map the page_4k la t1, page_4k mv t2, t1 PTE_SETUP_SV32(t1, PTE_V, t0, s2, t2, 1) @@ -38,12 +35,11 @@ RVTEST_CODE_BEGIN SATP_SETUP(t0, t1, SATP32_MODE) # test svadu - TEST_SVADU(x1, s2, page_4k, offset, 0x31a, MENVCFGH_HADE) - - RVMODEL_HALT + TEST_SVADU(x1, s2, page_4k, offset, 0x31a, MENVCFGH_ADUE) #endif RVTEST_CODE_END +RVMODEL_HALT RVTEST_DATA_BEGIN .align 12 @@ -64,8 +60,10 @@ CANARY; signature_x1_0: .fill 128*(XLEN/32),4,0xdeadbeef +#ifdef rvtest_mtrap_routine mtrap_sigptr: .fill 128*4, 4, 0xdeadbeef +#endif #ifdef rvtest_gpr_save gpr_save: diff --git a/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv39.S b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv39.S index e1f53e8bf..750cdb72d 100644 --- a/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv39.S +++ b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv39.S @@ -19,30 +19,26 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv39) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv39) RVTEST_SIGBASE(x1, signature_x1_0) - # enable pmp to cover 4 GiB address space - li t0, -1 - csrw pmpaddr0, t0 - li t0, PMP_TOR | PMP_X | PMP_W | PMP_R - csrw pmpcfg0, t0 + # Setup PMP to cover 4G of address space + SETUP_PMP_SVADU_TEST(x1, offset, t0, t1, t2) - # ID map the page_4k + # Idenity map the page_4k la t1, page_4k mv t2, t1 PTE_SETUP_SV39(t1, PTE_V, t0, s2, t2, 2) - # enable virtual memory in Sv32 mode + # enable virtual memory in Sv39 mode SATP_SETUP(t0, t1, ((SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39)) # test svadu - TEST_SVADU(x1, s2, page_4k, offset, 0x30a, MENVCFG_HADE) - - RVMODEL_HALT + TEST_SVADU(x1, s2, page_4k, offset, 0x30a, MENVCFG_ADUE) #endif RVTEST_CODE_END +RVMODEL_HALT RVTEST_DATA_BEGIN .align 12 @@ -63,8 +59,10 @@ CANARY; signature_x1_0: .fill 64*(XLEN/32),4,0xdeadbeef +#ifdef rvtest_mtrap_routine mtrap_sigptr: .fill 128*4, 4, 0xdeadbeef +#endif #ifdef rvtest_gpr_save gpr_save: diff --git a/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv48.S b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv48.S index 1cd356e16..0297707a9 100644 --- a/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv48.S +++ b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv48.S @@ -19,30 +19,26 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv48) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv48) RVTEST_SIGBASE(x1, signature_x1_0) - # enable pmp to cover 4 GiB address space - li t0, -1 - csrw pmpaddr0, t0 - li t0, PMP_TOR | PMP_X | PMP_W | PMP_R - csrw pmpcfg0, t0 + # Setup PMP to cover 4G of address space + SETUP_PMP_SVADU_TEST(x1, offset, t0, t1, t2) - # ID map the page_4k + # Identity map the page_4k la t1, page_4k mv t2, t1 PTE_SETUP_SV48(t1, PTE_V, t0, s2, t2, 3) - # enable virtual memory in Sv32 mode + # enable virtual memory in Sv48 mode SATP_SETUP(t0, t1, ((SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV48)) # test svadu - TEST_SVADU(x1, s2, page_4k, offset, 0x30a, MENVCFG_HADE) - - RVMODEL_HALT + TEST_SVADU(x1, s2, page_4k, offset, 0x30a, MENVCFG_ADUE) #endif RVTEST_CODE_END +RVMODEL_HALT RVTEST_DATA_BEGIN .align 12 @@ -63,8 +59,10 @@ CANARY; signature_x1_0: .fill 64*(XLEN/32),4,0xdeadbeef +#ifdef rvtest_mtrap_routine mtrap_sigptr: .fill 128*4, 4, 0xdeadbeef +#endif #ifdef rvtest_gpr_save gpr_save: diff --git a/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv57.S b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv57.S index 38ff9f9ec..06f9d2405 100644 --- a/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv57.S +++ b/riscv-test-suite/rv64i_m/Svadu/src/svadu_sv57.S @@ -19,30 +19,26 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 - RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv57) + RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);check ISA:=regex(.*Svadu.*);def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",svadu_sv57) RVTEST_SIGBASE(x1, signature_x1_0) - # enable pmp to cover 4 GiB address space - li t0, -1 - csrw pmpaddr0, t0 - li t0, PMP_TOR | PMP_X | PMP_W | PMP_R - csrw pmpcfg0, t0 + # Setup PMP to cover 4G of address space + SETUP_PMP_SVADU_TEST(x1, offset, t0, t1, t2) - # ID map the page_4k + # Identity map the page_4k la t1, page_4k mv t2, t1 PTE_SETUP_SV57(t1, PTE_V, t0, s2, t2, 4) - # enable virtual memory in Sv32 mode + # enable virtual memory in Sv57 mode SATP_SETUP(t0, t1, ((SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV57)) # test svadu - TEST_SVADU(x1, s2, page_4k, offset, 0x30a, MENVCFG_HADE) - - RVMODEL_HALT + TEST_SVADU(x1, s2, page_4k, offset, 0x30a, MENVCFG_ADUE) #endif RVTEST_CODE_END +RVMODEL_HALT RVTEST_DATA_BEGIN .align 12 @@ -63,8 +59,10 @@ CANARY; signature_x1_0: .fill 64*(XLEN/32),4,0xdeadbeef +#ifdef rvtest_mtrap_routine mtrap_sigptr: .fill 128*4, 4, 0xdeadbeef +#endif #ifdef rvtest_gpr_save gpr_save: From 3e768a31b5a483fb0ec5ee9b71d3ee503bf2adce Mon Sep 17 00:00:00 2001 From: Umer Shahid Date: Tue, 7 May 2024 17:03:42 +0500 Subject: [PATCH 5/6] Update test_macros.h Forced changes to resolve the conflicts Signed-off-by: Umer Shahid --- riscv-test-suite/env/test_macros.h | 176 +++++++++++++++++++++++++++++ 1 file changed, 176 insertions(+) diff --git a/riscv-test-suite/env/test_macros.h b/riscv-test-suite/env/test_macros.h index d34373ca5..b74d34859 100644 --- a/riscv-test-suite/env/test_macros.h +++ b/riscv-test-suite/env/test_macros.h @@ -30,6 +30,127 @@ #define SIG sig_bgn_off #define VMEM vmem_bgn_off + +#define SATP_SETUP(_TR0, _TR1, MODE);\ + LA(_TR0, rvtest_Sroot_pg_tbl) ;\ + LI(_TR1, MODE) ;\ + srli _TR0, _TR0, 12 ;\ + or _TR0, _TR0, _TR1 ;\ + csrw satp, _TR0 ;\ + +#define SETUP_PMP_SVADU_TEST(swreg, offset, TR0, TR1, TR2) \ + li TR0, -1 ;\ + csrw pmpaddr0, TR0 ;\ + j PMP_exist ;\ + li TR0, 0 ;\ + li TR1, 0 ;\ + j Mend_PMP ;\ +PMP_exist: ;\ + li TR1, PMP_TOR | PMP_X | PMP_W | PMP_R ;\ + csrw pmpcfg0, TR1 ;\ + csrr TR2, pmpcfg0 ;\ + beq TR1, TR2, Mend_PMP ;\ +no_TOR_try_NAPOT: ;\ + li TR1, PMP_NAPOT | PMP_X | PMP_W | PMP_R ;\ + csrw pmpcfg0, TR1 ;\ + csrr TR2, pmpcfg0 ;\ +Mend_PMP: ;\ + RVTEST_SIGUPD(x1,TR0,offset) ;\ + RVTEST_SIGUPD(x1,TR1,offset) ;\ + +#define TEST_SVADU(swreg, PTE_ADDR, VA, offset, menvcfgaddr, adue_bit) \ + sfence.vma ;\ + la t0, VA ;\ + li t2, PTE_X | PTE_W | PTE_R ;\ +1: ;\ + LREG t1, (PTE_ADDR) ;\ + andi t1, t1, ~(PTE_X | PTE_W | PTE_R | PTE_V) ;\ + or t1, t1, t2 ;\ + SREG t1, (PTE_ADDR) ;\ + sfence.vma ;\ + ;\ + li t1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\ + csrs mstatus, t1 ;\ + ;\ + .align 2 ;\ + SREG x0, (t0) ;\ + unimp ;\ + ;\ + li t1, MSTATUS_MPRV ;\ + csrc mstatus, t1 ;\ + ;\ + beqz t2, 2f ;\ + addi t2, t2, -1 ;\ + li t1, PTE_W | PTE_R | PTE_V ;\ + bne t2, t1, 1b ;\ + addi t2, t2, -1 ;\ + j 1b ;\ +2: ;\ + li t0, MSTATUS_MPRV ;\ + csrc mstatus, t0 ;\ + LREG t0, (PTE_ADDR) ;\ + and t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\ + RVTEST_SIGUPD(x1,t0,offset) ;\ + ;\ + LREG t0, (PTE_ADDR) ;\ + andi t0, t0, ~(PTE_X | PTE_W | PTE_R | PTE_V | PTE_A | PTE_D | PTE_V) ;\ + ori t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A ;\ + SREG t0, (PTE_ADDR) ;\ + sfence.vma ;\ + ;\ + la t0, VA ;\ + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\ + csrs mstatus, a1 ;\ + ;\ + .align 2 ;\ + SREG x0, (t0) ;\ + unimp ;\ + ;\ + li t0, MSTATUS_MPRV ;\ + csrc mstatus, t0 ;\ + ;\ + LREG t0, (PTE_ADDR) ;\ + and t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\ + RVTEST_SIGUPD(x1,t0,offset) ;\ + ;\ + LREG t0, (PTE_ADDR) ;\ + andi t0, t0, ~(PTE_X | PTE_W | PTE_R | PTE_V | PTE_A | PTE_D | PTE_V) ;\ + ori t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\ + SREG t0, (PTE_ADDR) ;\ + sfence.vma ;\ + la t0, VA ;\ + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\ + csrs mstatus, a1 ;\ + ;\ + SREG x0, (t0) ;\ + j 3f ;\ + unimp ;\ +3: ;\ + LREG t0, (PTE_ADDR) ;\ + andi t0, t0, ~(PTE_D) ;\ + SREG t0, (PTE_ADDR) ;\ + sfence.vma ;\ + ;\ + li t0, adue_bit ;\ + csrs menvcfgaddr, t0 ;\ + ;\ + la t0, VA ;\ + li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM | MSTATUS_MPRV ;\ + csrs mstatus, a1 ;\ + ;\ + .align 2 ;\ + SREG x0, (t0) ;\ + j 4f ;\ + unimp ;\ +4: ;\ + li t0, MSTATUS_MPRV ;\ + csrc mstatus, t0 ;\ + ;\ + LREG t0, (PTE_ADDR) ;\ + and t0, t0, PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A | PTE_D ;\ + RVTEST_SIGUPD(x1,t0,offset) + + #define ALL_MEM_PMP ;\ li t2, -1 ;\ csrw pmpaddr0, t2 ;\ @@ -68,6 +189,61 @@ or _PAR, _PAR, _PR ;\ SREG _PAR, 0(_TR1); +#define PTE_SETUP_SV32(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + .endif ;\ + PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) + +#define PTE_SETUP_SV39(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + .if (level==2) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + .endif ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_slvl2_pg_tbl) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + .endif ;\ + PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) + +#define PTE_SETUP_SV48(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + .if (level==3) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + .endif ;\ + .if (level==2) ;\ + LA(_TR1, rvtest_slvl3_pg_tbl) ;\ + .endif ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_slvl2_pg_tbl) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + .endif ;\ + PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) + +#define PTE_SETUP_SV57(_PAR, _PR, _TR0, _TR1, _VAR, level) ;\ + .if (level==4) ;\ + LA(_TR1, rvtest_Sroot_pg_tbl) ;\ + .endif ;\ + .if (level==3) ;\ + LA(_TR1, rvtest_slvl4_pg_tbl) ;\ + .endif ;\ + .if (level==2) ;\ + LA(_TR1, rvtest_slvl3_pg_tbl) ;\ + .endif ;\ + .if (level==1) ;\ + LA(_TR1, rvtest_slvl2_pg_tbl) ;\ + .endif ;\ + .if (level==0) ;\ + LA(_TR1, rvtest_slvl1_pg_tbl) ;\ + .endif ;\ + PTE_SETUP_COMMON(_PAR, _PR, _TR0, _TR1, _VAR, level) + + #define PTE_SETUP_RV64(_PAR, _PR, _TR0, _TR1, VA, level, mode) ;\ srli _PAR, _PAR, 12 ;\ slli _PAR, _PAR, 10 ;\ From 09771ee3d4b8a3d57f1b0f38c6bd6d10540be414 Mon Sep 17 00:00:00 2001 From: Umer Shahid Date: Tue, 7 May 2024 17:09:16 +0500 Subject: [PATCH 6/6] Update CHANGELOG.md Updated Changelog file to remove version conflicts Signed-off-by: Umer Shahid --- CHANGELOG.md | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index b8a07cbed..7be8c3d9e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,8 @@ # CHANGELOG -## [3.8.18] - 2023-07-28 +## [3.8.19] - 2024-05-08 +- Add support for unratified Svadu extension + +## [3.8.18] - 2024-05-08 - Add Zacas ISA extension support. ## [3.8.17] - 2024-05-03