diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b1-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b1-01.S new file mode 100644 index 000000000..713b9aa20 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b1-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x8000; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x8001; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x83fe; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x3ff; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x83ff; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x400; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x8400; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x401; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x8455; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x7bff; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0xfbff; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x7c00; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0xfc00; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x7e00; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0xfe00; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x7e01; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0xfe55; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x7c01; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0xfd55; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x3c00; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0xbc00; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(1,16,FLEN) +NAN_BOXED(32769,16,FLEN) +NAN_BOXED(2,16,FLEN) +NAN_BOXED(33790,16,FLEN) +NAN_BOXED(1023,16,FLEN) +NAN_BOXED(33791,16,FLEN) +NAN_BOXED(1024,16,FLEN) +NAN_BOXED(33792,16,FLEN) +NAN_BOXED(1025,16,FLEN) +NAN_BOXED(33877,16,FLEN) +NAN_BOXED(31743,16,FLEN) +NAN_BOXED(64511,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(32256,16,FLEN) +NAN_BOXED(65024,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b22-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b22-01.S new file mode 100644 index 000000000..5b5acfff5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x3249; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x35b7; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x3a4f; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x3cd3; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x4340; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x474b; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x07 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x9e9d; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x04 and fm1 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x1023; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(13751,16,FLEN) +NAN_BOXED(14927,16,FLEN) +NAN_BOXED(15571,16,FLEN) +NAN_BOXED(17216,16,FLEN) +NAN_BOXED(18251,16,FLEN) +NAN_BOXED(40605,16,FLEN) +NAN_BOXED(4131,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b23-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b23-01.S new file mode 100644 index 000000000..452d29d44 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b23-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x77fc; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x77fd; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x77fe; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x77ff; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x7800; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x7801; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x7802; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x7803; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x7804; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30723,16,FLEN) +NAN_BOXED(30724,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b24-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b24-01.S new file mode 100644 index 000000000..255b71662 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b24-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0xbc0a; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x3c00; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0xa11e; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0xbb33; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0xf0; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x2f0a; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x3c70; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0xbc66; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0xae66; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x3b1e; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x3beb; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x3b33; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0xbc00; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0xbc70; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x211e; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x2e66; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0xaf0a; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x3c66; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0xbbeb; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x3c0a; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0xbb1e; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(48138,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(47923,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(12042,16,FLEN) +NAN_BOXED(15472,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(44646,16,FLEN) +NAN_BOXED(15134,16,FLEN) +NAN_BOXED(15339,16,FLEN) +NAN_BOXED(15155,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(48240,16,FLEN) +NAN_BOXED(8478,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(15370,16,FLEN) +NAN_BOXED(47902,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b27-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b27-01.S new file mode 100644 index 000000000..46a91fefb --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x7c01; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0xfc01; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x7d55; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0xfd55; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x7e01; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0xfe01; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x7e55; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0xfe55; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64513,16,FLEN) +NAN_BOXED(32085,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65025,16,FLEN) +NAN_BOXED(32341,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b28-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b28-01.S new file mode 100644 index 000000000..a59b503d8 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x3892; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x3c00; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x3d00; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x3e00; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x3f00; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x4000; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x4080; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x4100; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x4180; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x72dc; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x77ff; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x7c00; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x7c01; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x7e01; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x8000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0xb6c0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0xbc00; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0xc180; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0xc100; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0xc080; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0xc000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0xbf00; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0xbe00; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0xbd00; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0xf659; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0xf800; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0xfc00; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(14482,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15616,16,FLEN) +NAN_BOXED(15872,16,FLEN) +NAN_BOXED(16128,16,FLEN) +NAN_BOXED(16384,16,FLEN) +NAN_BOXED(16512,16,FLEN) +NAN_BOXED(16640,16,FLEN) +NAN_BOXED(16768,16,FLEN) +NAN_BOXED(29404,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(46784,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49536,16,FLEN) +NAN_BOXED(49408,16,FLEN) +NAN_BOXED(49280,16,FLEN) +NAN_BOXED(49152,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48384,16,FLEN) +NAN_BOXED(63065,16,FLEN) +NAN_BOXED(63488,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b29-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b29-01.S new file mode 100644 index 000000000..ed6f6e448 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.d.h_b29-01.S @@ -0,0 +1,729 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 13 19:12:48 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.d.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.d.h instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.d.h_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.d.h_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f31; op1val:0x3248; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f29; dest:f30; op1val:0x3248; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f29; op1val:0x3248; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f27; dest:f28; op1val:0x3248; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f28; dest:f27; op1val:0x3248; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f25; dest:f26; op1val:0x3249; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f26; dest:f25; op1val:0x3249; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f23; dest:f24; op1val:0x3249; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f24; dest:f23; op1val:0x3249; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f21; dest:f22; op1val:0x3249; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f22; dest:f21; op1val:0x324a; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f19; dest:f20; op1val:0x324a; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f20; dest:f19; op1val:0x324a; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f17; dest:f18; op1val:0x324a; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f18; dest:f17; op1val:0x324a; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f15; dest:f16; op1val:0x324b; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f16; dest:f15; op1val:0x324b; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f13; dest:f14; op1val:0x324b; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f14; dest:f13; op1val:0x324b; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f11; dest:f12; op1val:0x324b; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f12; dest:f11; op1val:0x324c; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f9; dest:f10; op1val:0x324c; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f10; dest:f9; op1val:0x324c; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f7; dest:f8; op1val:0x324c; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f8; dest:f7; op1val:0x324c; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f5; dest:f6; op1val:0x324d; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f6; dest:f5; op1val:0x324d; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f3; dest:f4; op1val:0x324d; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f4; dest:f3; op1val:0x324d; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f1; dest:f2; op1val:0x324d; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f2; dest:f1; op1val:0x324e; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f0; dest:f31; op1val:0x324e; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f31; dest:f0; op1val:0x324e; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324e; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324e; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0x324f; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb248; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb249; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24a; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24b; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24c; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24d; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24e; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff +/* opcode: fcvt.d.h ; op1:f30; dest:f31; op1val:0xb24f; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.d.h, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(12879,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45640,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45641,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45642,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45643,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45644,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45645,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45646,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +NAN_BOXED(45647,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 160*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b1-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b1-01.S new file mode 100644 index 000000000..68dba6c97 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b1-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x80000000; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x1; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x80000002; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0xfffffffffffff; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x100fffffffffffff; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x800002; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x80800002; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x7fefffffffffffff; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0xffefffffffffffff; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x7ff800000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x7ff8000000000000; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0xfff8000000000000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x7ff8000000000001; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0xfff8000000000001; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x3ff800001; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x7ff800001; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x3fc000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 0; +.dword 2147483648; +.dword 1; +.dword 2147483649; +.dword 2; +.dword 2147483650; +.dword 4503599627370495; +.dword 1157425104234217471; +.dword 8388608; +.dword 2155872256; +.dword 8388610; +.dword 2155872258; +.dword 9218868437227405311; +.dword 18442240474082181119; +.dword 17171480576; +.dword 34351349760; +.dword 9221120237041090560; +.dword 18444492273895866368; +.dword 9221120237041090561; +.dword 18444492273895866369; +.dword 17171480577; +.dword 34351349761; +.dword 8581545984; +.dword 17112760320; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b22-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b22-01.S new file mode 100644 index 000000000..d93c18ef6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08577924770d3 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x3fc8577924770d3; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x3fd and fm1 == 0x93fdc7b89296c and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x3fd93fdc7b89296c; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 1 and fe1 == 0x3fe and fm1 == 0x766ba34c2da80 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x3ff766ba34c2da80; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xd2d6b7dc59a3a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x3ffd2d6b7dc59a3a; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x400 and fm1 == 0xcf84ba749f9c5 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x400cf84ba749f9c5; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x401 and fm1 == 0x854a908ceac39 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x401854a908ceac39; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x0ff and fm1 == 0x137a953e8eb43 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x3ff37a953e8eb43; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xbedc2f3ebcf12 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x7febedc2f3ebcf12; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 287251224846627027; +.dword 4600778710533613932; +.dword 4609265693572127360; +.dword 4610891533192108602; +.dword 4615336721960794565; +.dword 4618534502842412089; +.dword 288010101571775299; +.dword 9217722483915607826; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b23-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b23-01.S new file mode 100644 index 000000000..5fc00bbce --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b23-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x43dffffffffffffc; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x43dffffffffffffd; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x43dffffffffffffe; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x43dfffffffffffff; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x21f000000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x21f000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x21f000000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x21f000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x21f000000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x21f000001; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x21f000001; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x21f000001; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x21f000001; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x21f000001; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x21f000002; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x21f000002; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x21f000002; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 4890909195324358652; +.dword 4890909195324358652; +.dword 4890909195324358652; +.dword 4890909195324358652; +.dword 4890909195324358652; +.dword 4890909195324358653; +.dword 4890909195324358653; +.dword 4890909195324358653; +.dword 4890909195324358653; +.dword 4890909195324358653; +.dword 4890909195324358654; +.dword 4890909195324358654; +.dword 4890909195324358654; +.dword 4890909195324358654; +.dword 4890909195324358654; +.dword 4890909195324358655; +.dword 4890909195324358655; +.dword 4890909195324358655; +.dword 4890909195324358655; +.dword 4890909195324358655; +.dword 9110028288; +.dword 9110028288; +.dword 9110028288; +.dword 9110028288; +.dword 9110028288; +.dword 9110028289; +.dword 9110028289; +.dword 9110028289; +.dword 9110028289; +.dword 9110028289; +.dword 9110028290; +.dword 9110028290; +.dword 9110028290; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b24-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b24-01.S new file mode 100644 index 000000000..586d5b71a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b24-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x7fec7ae147ae147b; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x7fb999999999999a; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0xffe8f5c28f5c29; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x1fc47ae147ae147b; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 9217877645309383803; +.dword 9217877645309383803; +.dword 9217877645309383803; +.dword 9217877645309383803; +.dword 9217877645309383803; +.dword 9203556198494345626; +.dword 9203556198494345626; +.dword 9203556198494345626; +.dword 9203556198494345626; +.dword 9203556198494345626; +.dword 72032261290023977; +.dword 72032261290023977; +.dword 72032261290023977; +.dword 72032261290023977; +.dword 72032261290023977; +.dword 2289089618599875707; +.dword 2289089618599875707; +.dword 2289089618599875707; +.dword 2289089618599875707; +.dword 2289089618599875707; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 17171480576; +.dword 17171480576; +.dword 17171480576; +.dword 17171480576; +.dword 17171480576; +.dword 8581545984; +.dword 8581545984; +.dword 8581545984; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b27-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b27-01.S new file mode 100644 index 000000000..6fb9ee31c --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x3ff800001; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x7ff800001; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x3ffcaaaaaaaaaaaa; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x7ffcaaaaaaaaaaaa; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x7ff8000000000001; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0xfff8000000000001; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x7ffc000000000001; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0xfffc000000000001; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 17171480577; +.dword 34351349761; +.dword 4610747768505019050; +.dword 9222433786932406954; +.dword 9221120237041090561; +.dword 18444492273895866369; +.dword 9222246136947933185; +.dword 18445618173802708993; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b28-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b28-01.S new file mode 100644 index 000000000..b79caf4c1 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0xffa48ee18215dfa; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x1ff800000; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x1ffc000000000000; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x3ff8000000000000; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x3ffc000000000000; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x200000000; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x1002000000000000; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x2004000000000000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x2006000000000000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x43c and fm1 == 0xb72eb13dc494a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x43cb72eb13dc494a; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x21f000000; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x3ff800000; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x3ff800001; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x7ff8000000000001; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x80000000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x3fd and fm1 == 0xb008d57e19f88 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x7fdb008d57e19f88; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x3fc000000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x6006000000000000; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x6004000000000000; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x3002000000000000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x600000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x7ffc000000000000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x7ff8000000000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x3ffc000000000000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x43d and fm1 == 0x967a4ae26514c and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0xc3d967a4ae26514c; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x61f000000; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x7ff800000; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 0; +.dword 1151312842190839290; +.dword 8581545984; +.dword 2304717109306851328; +.dword 4609434218613702656; +.dword 4610560118520545280; +.dword 8589934592; +.dword 1153484454560268288; +.dword 2306968909120536576; +.dword 2307531859073957888; +.dword 4885124574789519690; +.dword 9110028288; +.dword 17171480576; +.dword 17171480577; +.dword 9221120237041090561; +.dword 2147483648; +.dword 9212958069781274504; +.dword 17112760320; +.dword 6919217877501345792; +.dword 6918654927547924480; +.dword 3459327463773962240; +.dword 25769803776; +.dword 9222246136947933184; +.dword 9221120237041090560; +.dword 4610560118520545280; +.dword 14112424864336204108; +.dword 26289897472; +.dword 34351349760; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +.dword 0; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b29-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b29-01.S new file mode 100644 index 000000000..9063584b5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.d_b29-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Thu Sep 19 19:19:34 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.d.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.d instruction of the RISC-V RV32FD_Zicsr_Zfh,RV64FD_Zicsr_Zfh extension for the fcvt.h.d_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFD_Zicsr_Zfh,RV64IFD_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.d_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f30; dest:f31; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 == rd, rs1==f29, rd==f29,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f29; dest:f29; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f29, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f30; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f30, f31, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f27; dest:f28; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f28; dest:f27; op1val:0x3fc8574923b8698; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f25; dest:f26; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f26; dest:f25; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f23; dest:f24; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f24; dest:f23; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f21; dest:f22; op1val:0x3fc8574923b8699; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f22; dest:f21; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f19; dest:f20; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f20; dest:f19; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f17; dest:f18; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f18; dest:f17; op1val:0x3fc8574923b869a; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f15; dest:f16; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f16; dest:f15; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f13; dest:f14; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f14; dest:f13; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f11; dest:f12; op1val:0x3fc8574923b869b; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f12; dest:f11; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f9; dest:f10; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f10; dest:f9; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f7; dest:f8; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f8; dest:f7; op1val:0x3fc8574923b869c; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f5; dest:f6; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f6; dest:f5; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f3; dest:f4; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f4; dest:f3; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f1; dest:f2; op1val:0x3fc8574923b869d; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f2; dest:f1; op1val:0x3fc8574923b869e; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f0; dest:f31; op1val:0x3fc8574923b869e; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.d ; op1:f31; dest:f0; op1val:0x3fc8574923b869e; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.d, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +.dword 287251211960944280; +.dword 287251211960944280; +.dword 287251211960944280; +.dword 287251211960944280; +.dword 287251211960944280; +.dword 287251211960944281; +.dword 287251211960944281; +.dword 287251211960944281; +.dword 287251211960944281; +.dword 287251211960944281; +.dword 287251211960944282; +.dword 287251211960944282; +.dword 287251211960944282; +.dword 287251211960944282; +.dword 287251211960944282; +.dword 287251211960944283; +.dword 287251211960944283; +.dword 287251211960944283; +.dword 287251211960944283; +.dword 287251211960944283; +.dword 287251211960944284; +.dword 287251211960944284; +.dword 287251211960944284; +.dword 287251211960944284; +.dword 287251211960944284; +.dword 287251211960944285; +.dword 287251211960944285; +.dword 287251211960944285; +.dword 287251211960944285; +.dword 287251211960944285; +.dword 287251211960944286; +.dword 287251211960944286; +.dword 287251211960944286; +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b1-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b1-01.S new file mode 100644 index 000000000..49363d961 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b1-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b1 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b1) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x80000000; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x807ffffe; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x7fffff; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x807fffff; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x800001; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x80855555; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x7f7fffff; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0xff7fffff; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x7f800000; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0xff800000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x7fc00000; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0xffc00000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0xffc55555; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x7f800001; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x3f800000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0xbf800000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(2147483649,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(2155872254,32,FLEN) +NAN_BOXED(8388607,32,FLEN) +NAN_BOXED(2155872255,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(2155872256,32,FLEN) +NAN_BOXED(8388609,32,FLEN) +NAN_BOXED(2156221781,32,FLEN) +NAN_BOXED(2139095039,32,FLEN) +NAN_BOXED(4286578687,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(2143289344,32,FLEN) +NAN_BOXED(4290772992,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b22-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b22-01.S new file mode 100644 index 000000000..6d37c239d --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x7d and fm1 == 0x36e5d6 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x3eb6e5d6; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x7e and fm1 == 0x49fee5 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x3f49fee5; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7f and fm1 == 0x1a616d and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x3f9a616d; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x80 and fm1 == 0x681ae9 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x40681ae9; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x81 and fm1 == 0x696b5c and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x40e96b5c; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x67 and fm1 == 0x53a4fc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x33d3a4fc; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0xc4 and fm1 == 0x046756 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x62046756; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1052173782,32,FLEN) +NAN_BOXED(1061813989,32,FLEN) +NAN_BOXED(1067082093,32,FLEN) +NAN_BOXED(1080564457,32,FLEN) +NAN_BOXED(1089039196,32,FLEN) +NAN_BOXED(869508348,32,FLEN) +NAN_BOXED(1644455766,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b23-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b23-01.S new file mode 100644 index 000000000..f68582b2a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b23-01.S @@ -0,0 +1,449 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x4efffffc; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x4efffffd; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x4efffffe; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x4effffff; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x4effffff; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0x4effffff; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x4effffff; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0x4effffff; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x4f000000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x4f000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x4f000000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x4f000000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x4f000000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x4f000001; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x4f000001; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x4f000001; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x4f000001; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x4f000001; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x4f000002; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x4f000002; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000002; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000003; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x4f000004; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400060,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400061,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400062,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400064,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400065,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400066,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400067,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +NAN_BOXED(1325400068,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 90*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b24-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b24-01.S new file mode 100644 index 000000000..e7da9dea1 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b24-01.S @@ -0,0 +1,929 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x7f0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x7f0; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x7f0; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x7f0; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x7f0; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0xbf7d70a3; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x3dcccccc; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0xbf8ccccc; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x3de147ae; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x3f8e147a; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8147ae; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf63d70a; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbdcccccc; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f800000; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf800000; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8ccccc; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f666666; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbc23d70a; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f8147ae; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f63d70a; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) + +inst_80: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:80*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 80*FLEN/8, x4, x1, x2) + +inst_81: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:81*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 81*FLEN/8, x4, x1, x2) + +inst_82: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:82*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 82*FLEN/8, x4, x1, x2) + +inst_83: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:83*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 83*FLEN/8, x4, x1, x2) + +inst_84: +// fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbde147ae; valaddr_reg:x3; +val_offset:84*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 84*FLEN/8, x4, x1, x2) + +inst_85: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:85*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 85*FLEN/8, x4, x1, x2) + +inst_86: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:86*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 86*FLEN/8, x4, x1, x2) + +inst_87: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:87*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 87*FLEN/8, x4, x1, x2) + +inst_88: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:88*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 88*FLEN/8, x4, x1, x2) + +inst_89: +// fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3c23d70a; valaddr_reg:x3; +val_offset:89*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 89*FLEN/8, x4, x1, x2) + +inst_90: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:90*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 90*FLEN/8, x4, x1, x2) + +inst_91: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:91*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 91*FLEN/8, x4, x1, x2) + +inst_92: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:92*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 92*FLEN/8, x4, x1, x2) + +inst_93: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:93*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 93*FLEN/8, x4, x1, x2) + +inst_94: +// fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf666666; valaddr_reg:x3; +val_offset:94*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 94*FLEN/8, x4, x1, x2) + +inst_95: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:95*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 95*FLEN/8, x4, x1, x2) + +inst_96: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:96*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 96*FLEN/8, x4, x1, x2) + +inst_97: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:97*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 97*FLEN/8, x4, x1, x2) + +inst_98: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:98*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 98*FLEN/8, x4, x1, x2) + +inst_99: +// fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbf8e147a; valaddr_reg:x3; +val_offset:99*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 99*FLEN/8, x4, x1, x2) + +inst_100: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:100*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 100*FLEN/8, x4, x1, x2) + +inst_101: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:101*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 101*FLEN/8, x4, x1, x2) + +inst_102: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:102*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 102*FLEN/8, x4, x1, x2) + +inst_103: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:103*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 103*FLEN/8, x4, x1, x2) + +inst_104: +// fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3f7d70a3; valaddr_reg:x3; +val_offset:104*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 104*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(2032,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(3212669091,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(1036831948,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(3213675724,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1038174126,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(1066275962,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3212920750,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3210991370,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(3184315596,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1066192076,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(1063675494,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(3156465418,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1065437102,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(1063507722,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(3185657774,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(1008981770,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3211159142,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(3213759610,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +NAN_BOXED(1065185443,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 210*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b27-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b27-01.S new file mode 100644 index 000000000..7f6174289 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x7f800001; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0xff800001; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x7faaaaaa; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0xffaaaaaa; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0xffc00001; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x7fc55555; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0xffc55555; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(4286578689,32,FLEN) +NAN_BOXED(2141891242,32,FLEN) +NAN_BOXED(4289374890,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(4290772993,32,FLEN) +NAN_BOXED(2143638869,32,FLEN) +NAN_BOXED(4291122517,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b28-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b28-01.S new file mode 100644 index 000000000..4c5592ee2 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x7e and fm1 == 0x124770 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x3f124770; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x3f800000; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7f and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x3fa00000; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x7f and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x3fc00000; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x7f and fm1 == 0x600000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x3fe00000; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x80 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x40000000; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x80 and fm1 == 0x100000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x40100000; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x80 and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x40200000; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x80 and fm1 == 0x300000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x40300000; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x9c and fm1 == 0x5b9758 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x4e5b9758; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x4effffff; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x7f800000; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x7f800001; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x7fc00001; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x80000000; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x7d and fm1 == 0x58046a and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0xbed8046a; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0xbf800000; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x80 and fm1 == 0x300000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0xc0300000; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x80 and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0xc0200000; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x80 and fm1 == 0x100000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0xc0100000; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x80 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0xc0000000; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x7f and fm1 == 0x600000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0xbfe00000; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0xbfc00000; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x7f and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0xbfa00000; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x9d and fm1 == 0x4b3d25 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0xcecb3d25; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0xcf000000; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0xff800000; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1058162544,32,FLEN) +NAN_BOXED(1065353216,32,FLEN) +NAN_BOXED(1067450368,32,FLEN) +NAN_BOXED(1069547520,32,FLEN) +NAN_BOXED(1071644672,32,FLEN) +NAN_BOXED(1073741824,32,FLEN) +NAN_BOXED(1074790400,32,FLEN) +NAN_BOXED(1075838976,32,FLEN) +NAN_BOXED(1076887552,32,FLEN) +NAN_BOXED(1314625368,32,FLEN) +NAN_BOXED(1325400063,32,FLEN) +NAN_BOXED(2139095040,32,FLEN) +NAN_BOXED(2139095041,32,FLEN) +NAN_BOXED(2143289345,32,FLEN) +NAN_BOXED(2147483648,32,FLEN) +NAN_BOXED(3201827946,32,FLEN) +NAN_BOXED(3212836864,32,FLEN) +NAN_BOXED(3224371200,32,FLEN) +NAN_BOXED(3223322624,32,FLEN) +NAN_BOXED(3222274048,32,FLEN) +NAN_BOXED(3221225472,32,FLEN) +NAN_BOXED(3219128320,32,FLEN) +NAN_BOXED(3217031168,32,FLEN) +NAN_BOXED(3214934016,32,FLEN) +NAN_BOXED(3469425957,32,FLEN) +NAN_BOXED(3472883712,32,FLEN) +NAN_BOXED(4286578688,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b29-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b29-01.S new file mode 100644 index 000000000..adfa2f8b2 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.s_b29-01.S @@ -0,0 +1,729 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Sat Sep 14 02:42:23 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.s.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.h.s instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.s_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.s_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f31; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:0*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f29; dest:f30; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:1*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f29; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:2*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f27; dest:f28; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:3*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f28; dest:f27; op1val:0x3e4923b8; valaddr_reg:x3; +val_offset:4*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f25; dest:f26; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:5*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f26; dest:f25; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:6*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f23; dest:f24; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:7*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f24; dest:f23; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:8*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f21; dest:f22; op1val:0x3e4923b9; valaddr_reg:x3; +val_offset:9*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f22; dest:f21; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:10*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f19; dest:f20; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:11*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f20; dest:f19; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:12*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f17; dest:f18; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:13*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f18; dest:f17; op1val:0x3e4923ba; valaddr_reg:x3; +val_offset:14*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f15; dest:f16; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:15*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f16; dest:f15; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:16*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f13; dest:f14; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:17*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f14; dest:f13; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:18*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f11; dest:f12; op1val:0x3e4923bb; valaddr_reg:x3; +val_offset:19*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f12; dest:f11; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:20*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f9; dest:f10; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:21*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f10; dest:f9; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:22*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f7; dest:f8; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:23*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f8; dest:f7; op1val:0x3e4923bc; valaddr_reg:x3; +val_offset:24*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f5; dest:f6; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:25*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f6; dest:f5; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:26*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f3; dest:f4; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:27*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f4; dest:f3; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:28*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f1; dest:f2; op1val:0x3e4923bd; valaddr_reg:x3; +val_offset:29*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f2; dest:f1; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:30*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f0; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:31*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f31; dest:f0; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:32*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) + +inst_33: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:33*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 33*FLEN/8, x4, x1, x2) + +inst_34: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923be; valaddr_reg:x3; +val_offset:34*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 34*FLEN/8, x4, x1, x2) + +inst_35: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:35*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 35*FLEN/8, x4, x1, x2) + +inst_36: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:36*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 36*FLEN/8, x4, x1, x2) + +inst_37: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:37*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 37*FLEN/8, x4, x1, x2) + +inst_38: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:38*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 38*FLEN/8, x4, x1, x2) + +inst_39: +// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0x3e4923bf; valaddr_reg:x3; +val_offset:39*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 39*FLEN/8, x4, x1, x2) + +inst_40: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:40*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 40*FLEN/8, x4, x1, x2) + +inst_41: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:41*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 41*FLEN/8, x4, x1, x2) + +inst_42: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:42*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 42*FLEN/8, x4, x1, x2) + +inst_43: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:43*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 43*FLEN/8, x4, x1, x2) + +inst_44: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b8; valaddr_reg:x3; +val_offset:44*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 44*FLEN/8, x4, x1, x2) + +inst_45: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:45*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 45*FLEN/8, x4, x1, x2) + +inst_46: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:46*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 46*FLEN/8, x4, x1, x2) + +inst_47: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:47*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 47*FLEN/8, x4, x1, x2) + +inst_48: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:48*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 48*FLEN/8, x4, x1, x2) + +inst_49: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923b9; valaddr_reg:x3; +val_offset:49*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 49*FLEN/8, x4, x1, x2) + +inst_50: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:50*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 50*FLEN/8, x4, x1, x2) + +inst_51: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:51*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 51*FLEN/8, x4, x1, x2) + +inst_52: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:52*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 52*FLEN/8, x4, x1, x2) + +inst_53: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:53*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 53*FLEN/8, x4, x1, x2) + +inst_54: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923ba; valaddr_reg:x3; +val_offset:54*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 54*FLEN/8, x4, x1, x2) + +inst_55: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:55*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 55*FLEN/8, x4, x1, x2) + +inst_56: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:56*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 56*FLEN/8, x4, x1, x2) + +inst_57: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:57*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 57*FLEN/8, x4, x1, x2) + +inst_58: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:58*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 58*FLEN/8, x4, x1, x2) + +inst_59: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bb; valaddr_reg:x3; +val_offset:59*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 59*FLEN/8, x4, x1, x2) + +inst_60: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:60*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2) + +inst_61: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:61*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 61*FLEN/8, x4, x1, x2) + +inst_62: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:62*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 62*FLEN/8, x4, x1, x2) + +inst_63: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:63*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 63*FLEN/8, x4, x1, x2) + +inst_64: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bc; valaddr_reg:x3; +val_offset:64*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 64*FLEN/8, x4, x1, x2) + +inst_65: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:65*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 65*FLEN/8, x4, x1, x2) + +inst_66: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:66*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 66*FLEN/8, x4, x1, x2) + +inst_67: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:67*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 67*FLEN/8, x4, x1, x2) + +inst_68: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:68*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 68*FLEN/8, x4, x1, x2) + +inst_69: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bd; valaddr_reg:x3; +val_offset:69*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 69*FLEN/8, x4, x1, x2) + +inst_70: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:70*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2) + +inst_71: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:71*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 71*FLEN/8, x4, x1, x2) + +inst_72: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:72*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 72*FLEN/8, x4, x1, x2) + +inst_73: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:73*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 73*FLEN/8, x4, x1, x2) + +inst_74: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923be; valaddr_reg:x3; +val_offset:74*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 74*FLEN/8, x4, x1, x2) + +inst_75: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x0 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:75*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 0, 0, x3, 75*FLEN/8, x4, x1, x2) + +inst_76: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x20 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:76*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 32, 0, x3, 76*FLEN/8, x4, x1, x2) + +inst_77: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x40 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:77*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 64, 0, x3, 77*FLEN/8, x4, x1, x2) + +inst_78: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x60 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:78*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 96, 0, x3, 78*FLEN/8, x4, x1, x2) + +inst_79: +// fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x80 and rm_val == 7 +/* opcode: fcvt.h.s ; op1:f30; dest:f31; op1val:0xbe4923bf; valaddr_reg:x3; +val_offset:79*FLEN/8; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.h.s, f31, f30, 128, 0, x3, 79*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980664,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980665,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980666,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980667,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980668,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980669,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980670,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(1044980671,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464312,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464313,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464314,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464315,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464316,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464317,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464318,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +NAN_BOXED(3192464319,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 160*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b22-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b22-01.S new file mode 100644 index 000000000..8dfc6a638 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b22-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b22 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b22) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x3249; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x35b7; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x3a4f; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x3cd3; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x4340; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0x474b; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x07 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x9e9d; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x04 and fm1 == 0x023 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0x1023; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(13751,16,FLEN) +NAN_BOXED(14927,16,FLEN) +NAN_BOXED(15571,16,FLEN) +NAN_BOXED(17216,16,FLEN) +NAN_BOXED(18251,16,FLEN) +NAN_BOXED(40605,16,FLEN) +NAN_BOXED(4131,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b23-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b23-01.S new file mode 100644 index 000000000..50b7de7b4 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b23-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b23 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b23) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x77fc; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x77fc; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x77fc; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x77fc; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x77fc; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0x77fd; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x77fd; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0x77fd; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x77fd; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x77fd; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x77fe; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x77fe; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x77fe; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x77fe; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x77fe; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x77ff; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0x77ff; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0x77ff; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0x77ff; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0x77ff; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0x7800; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0x7800; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0x7800; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0x7800; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0x7800; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0x7801; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0x7801; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0x7801; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x7801; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x7801; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x7802; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x7802; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x7802; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30716,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30717,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30718,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30720,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30721,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +NAN_BOXED(30722,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b24-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b24-01.S new file mode 100644 index 000000000..d11e5d2cf --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b24-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b24 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b24) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x2e66; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x2e66; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x2e66; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x2e66; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x2e66; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0xbc66; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0xbc66; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0xbc66; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0xbc66; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0xbc66; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x3c66; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x3c66; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x3c66; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x3c66; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x3c66; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0xbbeb; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0xbbeb; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0xbbeb; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0xbbeb; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0xbbeb; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0xaf0a; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0xaf0a; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0xaf0a; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0xaf0a; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0xaf0a; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0xf0; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0xf0; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0xf0; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0xf0; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0xf0; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0xa11e; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0xa11e; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0xa11e; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(11878,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(48230,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(15462,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(48107,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(44810,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(240,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +NAN_BOXED(41246,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b27-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b27-01.S new file mode 100644 index 000000000..55fd97f01 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b27-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b27 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b27) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x7c01; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0xfc01; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x7d55; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0xfd55; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x7e01; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0xfe01; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x7e55; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0xfe55; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23, +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x0; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22, +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x0; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21, +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20, +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x0; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19, +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18, +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17, +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x0; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16, +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x0; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15, +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0x0; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14, +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0x0; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13, +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0x0; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12, +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0x0; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11, +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10, +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0x0; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9, +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0x0; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8, +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7, +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6, +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5, +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4, +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(64513,16,FLEN) +NAN_BOXED(32085,16,FLEN) +NAN_BOXED(64853,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(65025,16,FLEN) +NAN_BOXED(32341,16,FLEN) +NAN_BOXED(65109,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b28-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b28-01.S new file mode 100644 index 000000000..a22413aaf --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b28-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b28 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b28) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x3892; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x3c00; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x3d00; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x3e00; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0x3f00; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x4000; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 0, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0x4080; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x4100; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 0, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x4180; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 0, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x72dc; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x77ff; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x7c00; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 0, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x7c01; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 0, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x7e01; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 0, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x8000; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0xb6c0; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 0, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0xbc00; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0xc180; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 0, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0xc100; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 0, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0xc080; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0xc000; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 0, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0xbf00; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 0, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0xbe00; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 0, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0xbd00; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0xf659; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0xf800; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 0, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0xfc00; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3, +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 0, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2, +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 0, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1, +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0, +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 0, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0, +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 0, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,16,FLEN) +NAN_BOXED(14482,16,FLEN) +NAN_BOXED(15360,16,FLEN) +NAN_BOXED(15616,16,FLEN) +NAN_BOXED(15872,16,FLEN) +NAN_BOXED(16128,16,FLEN) +NAN_BOXED(16384,16,FLEN) +NAN_BOXED(16512,16,FLEN) +NAN_BOXED(16640,16,FLEN) +NAN_BOXED(16768,16,FLEN) +NAN_BOXED(29404,16,FLEN) +NAN_BOXED(30719,16,FLEN) +NAN_BOXED(31744,16,FLEN) +NAN_BOXED(31745,16,FLEN) +NAN_BOXED(32257,16,FLEN) +NAN_BOXED(32768,16,FLEN) +NAN_BOXED(46784,16,FLEN) +NAN_BOXED(48128,16,FLEN) +NAN_BOXED(49536,16,FLEN) +NAN_BOXED(49408,16,FLEN) +NAN_BOXED(49280,16,FLEN) +NAN_BOXED(49152,16,FLEN) +NAN_BOXED(48896,16,FLEN) +NAN_BOXED(48640,16,FLEN) +NAN_BOXED(48384,16,FLEN) +NAN_BOXED(63065,16,FLEN) +NAN_BOXED(63488,16,FLEN) +NAN_BOXED(64512,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +NAN_BOXED(0,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b29-01.S b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b29-01.S new file mode 100644 index 000000000..18444165b --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zfh/src/fcvt.s.h_b29-01.S @@ -0,0 +1,353 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Fri Sep 20 02:26:03 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/dataset.cgf \ +// --cgf /home/pager/Desktop/work/riscv-ctg_now/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.s.h.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the fcvt.s.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.s.h_b29 covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.s.h_b29) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f31; op1val:0x3248; valaddr_reg:x3; +val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2) + +inst_1: +// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f29; dest:f30; op1val:0x3248; valaddr_reg:x3; +val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f30, f29, 32, 0, x3, 1*FLEN/8, x4, x1, x2) + +inst_2: +// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f30; dest:f29; op1val:0x3248; valaddr_reg:x3; +val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f29, f30, 64, 0, x3, 2*FLEN/8, x4, x1, x2) + +inst_3: +// rs1==f27, rd==f28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f27; dest:f28; op1val:0x3248; valaddr_reg:x3; +val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f28, f27, 96, 0, x3, 3*FLEN/8, x4, x1, x2) + +inst_4: +// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f28; dest:f27; op1val:0x3248; valaddr_reg:x3; +val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f27, f28, 128, 0, x3, 4*FLEN/8, x4, x1, x2) + +inst_5: +// rs1==f25, rd==f26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f25; dest:f26; op1val:0x3249; valaddr_reg:x3; +val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f26, f25, 0, 0, x3, 5*FLEN/8, x4, x1, x2) + +inst_6: +// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f26; dest:f25; op1val:0x3249; valaddr_reg:x3; +val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f25, f26, 32, 0, x3, 6*FLEN/8, x4, x1, x2) + +inst_7: +// rs1==f23, rd==f24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f23; dest:f24; op1val:0x3249; valaddr_reg:x3; +val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f24, f23, 64, 0, x3, 7*FLEN/8, x4, x1, x2) + +inst_8: +// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f24; dest:f23; op1val:0x3249; valaddr_reg:x3; +val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f23, f24, 96, 0, x3, 8*FLEN/8, x4, x1, x2) + +inst_9: +// rs1==f21, rd==f22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f21; dest:f22; op1val:0x3249; valaddr_reg:x3; +val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f22, f21, 128, 0, x3, 9*FLEN/8, x4, x1, x2) + +inst_10: +// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f22; dest:f21; op1val:0x324a; valaddr_reg:x3; +val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f21, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2) + +inst_11: +// rs1==f19, rd==f20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f19; dest:f20; op1val:0x324a; valaddr_reg:x3; +val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f20, f19, 32, 0, x3, 11*FLEN/8, x4, x1, x2) + +inst_12: +// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f20; dest:f19; op1val:0x324a; valaddr_reg:x3; +val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f19, f20, 64, 0, x3, 12*FLEN/8, x4, x1, x2) + +inst_13: +// rs1==f17, rd==f18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f17; dest:f18; op1val:0x324a; valaddr_reg:x3; +val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f18, f17, 96, 0, x3, 13*FLEN/8, x4, x1, x2) + +inst_14: +// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f18; dest:f17; op1val:0x324a; valaddr_reg:x3; +val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f17, f18, 128, 0, x3, 14*FLEN/8, x4, x1, x2) + +inst_15: +// rs1==f15, rd==f16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f15; dest:f16; op1val:0x324b; valaddr_reg:x3; +val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2) + +inst_16: +// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f16; dest:f15; op1val:0x324b; valaddr_reg:x3; +val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f15, f16, 32, 0, x3, 16*FLEN/8, x4, x1, x2) + +inst_17: +// rs1==f13, rd==f14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f13; dest:f14; op1val:0x324b; valaddr_reg:x3; +val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f14, f13, 64, 0, x3, 17*FLEN/8, x4, x1, x2) + +inst_18: +// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f14; dest:f13; op1val:0x324b; valaddr_reg:x3; +val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f13, f14, 96, 0, x3, 18*FLEN/8, x4, x1, x2) + +inst_19: +// rs1==f11, rd==f12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f11; dest:f12; op1val:0x324b; valaddr_reg:x3; +val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f12, f11, 128, 0, x3, 19*FLEN/8, x4, x1, x2) + +inst_20: +// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f12; dest:f11; op1val:0x324c; valaddr_reg:x3; +val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f11, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2) + +inst_21: +// rs1==f9, rd==f10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f9; dest:f10; op1val:0x324c; valaddr_reg:x3; +val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f10, f9, 32, 0, x3, 21*FLEN/8, x4, x1, x2) + +inst_22: +// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f10; dest:f9; op1val:0x324c; valaddr_reg:x3; +val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f9, f10, 64, 0, x3, 22*FLEN/8, x4, x1, x2) + +inst_23: +// rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f7; dest:f8; op1val:0x324c; valaddr_reg:x3; +val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f8, f7, 96, 0, x3, 23*FLEN/8, x4, x1, x2) + +inst_24: +// rs1==f8, rd==f7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f8; dest:f7; op1val:0x324c; valaddr_reg:x3; +val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f7, f8, 128, 0, x3, 24*FLEN/8, x4, x1, x2) + +inst_25: +// rs1==f5, rd==f6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f5; dest:f6; op1val:0x324d; valaddr_reg:x3; +val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f6, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2) + +inst_26: +// rs1==f6, rd==f5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f6; dest:f5; op1val:0x324d; valaddr_reg:x3; +val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f5, f6, 32, 0, x3, 26*FLEN/8, x4, x1, x2) + +inst_27: +// rs1==f3, rd==f4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f3; dest:f4; op1val:0x324d; valaddr_reg:x3; +val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f4, f3, 64, 0, x3, 27*FLEN/8, x4, x1, x2) + +inst_28: +// rs1==f4, rd==f3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f4; dest:f3; op1val:0x324d; valaddr_reg:x3; +val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 96 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f3, f4, 96, 0, x3, 28*FLEN/8, x4, x1, x2) + +inst_29: +// rs1==f1, rd==f2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f1; dest:f2; op1val:0x324d; valaddr_reg:x3; +val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 128 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f2, f1, 128, 0, x3, 29*FLEN/8, x4, x1, x2) + +inst_30: +// rs1==f2, rd==f1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f2; dest:f1; op1val:0x324e; valaddr_reg:x3; +val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 0 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f1, f2, 0, 0, x3, 30*FLEN/8, x4, x1, x2) + +inst_31: +// rs1==f0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f0; dest:f31; op1val:0x324e; valaddr_reg:x3; +val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 32 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f31, f0, 32, 0, x3, 31*FLEN/8, x4, x1, x2) + +inst_32: +// rd==f0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xfffff +/* opcode: fcvt.s.h ; op1:f31; dest:f0; op1val:0x324e; valaddr_reg:x3; +val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2; +fcsr_val: 64 */ +TEST_FPSR_OP_NRM(fcvt.s.h, f0, f31, 64, 0, x3, 32*FLEN/8, x4, x1, x2) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12872,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12873,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12874,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12875,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12876,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12877,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +NAN_BOXED(12878,16,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((SIGALIGN)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 66*((SIGALIGN)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END