diff --git a/CHANGELOG.md b/CHANGELOG.md
index e18a8cdc9..6f76e7864 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,4 +1,8 @@
 # CHANGELOG
+
+## [3.8.12] - 2024-03-26
+Corrected missing RV64 strings in RVTEST_CASE macros for Zfh fcvt.h.l and similar tests
+
 ## [3.8.11] - 2024-03-26
 - Added test suites for Zfh extensions.
 - Introduced half word and half width in Nan boxing functionality to accomdate Zfh extensions.
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.l_b25-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.l_b25-01.S
index feb4ac7d8..9826c8aec 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.l_b25-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.l_b25-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b25)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.l_b25)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S
index ebc61f6fc..d94174586 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b25)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.lu_b25)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b1-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b1-01.S
index 527ff18c6..023331a9e 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b1-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b1-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b1)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b1)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b22-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b22-01.S
index c007104b6..34d47e7d2 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b22-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b22-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b22)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b22)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b23-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b23-01.S
index 04b8e5123..d184dcd46 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b23-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b23-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b23)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b23)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b24-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b24-01.S
index c6270460f..93fe8c697 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b24-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b24-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b24)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b24)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b27-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b27-01.S
index 9054667d0..780651643 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b27-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b27-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b27)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b27)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b28-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b28-01.S
index 5ce9941e9..1fa0c12da 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b28-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b28-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b28)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b28)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b29-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b29-01.S
index cabf5e2fe..7fea5f317 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b29-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.l.h_b29-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b29)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*D.*Zfh.*);def TEST_CASE_1=True;",fcvt.l.h_b29)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b1-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b1-01.S
index cddd6880a..56b754bce 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b1-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b1-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b1)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b1)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b22-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b22-01.S
index 81cdaf3f0..3236fd2c7 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b22-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b22-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b22)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b22)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b23-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b23-01.S
index bd1b53f74..e5c0d6a27 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b23-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b23-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b23)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b23)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b24-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b24-01.S
index 26aa1e6e2..f79f4314f 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b24-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b24-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b24)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b24)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S
index b0828ac0a..c311a966f 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b27)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b27)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S
index ff8f8d6f9..2889a7a64 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b28)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b28)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)
diff --git a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S
index b5a649b46..bccadaa1b 100644
--- a/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S
+++ b/riscv-test-suite/rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S
@@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN
 
 #ifdef TEST_CASE_1
 
-RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b29)
+RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.lu.h_b29)
 
 RVTEST_FP_ENABLE()
 RVTEST_VALBASEUPD(x3,test_dataset_0)