From 37e34be51a5f0bdaeaf7dec76ea5a1fc7691798d Mon Sep 17 00:00:00 2001 From: anuani21 <114156183+anuani21@users.noreply.github.com> Date: Tue, 7 Jan 2025 17:47:18 +0530 Subject: [PATCH] [ACT] [CTG] [ISAC] Add support Zdinx extension (#499) * Updated RV32Zdinx and RV64Zdinx test case * Updated Zdinx instruction support with respect to riscv-ctg and riscv-isac --------- Signed-off-by: anuani21 <114156183+anuani21@users.noreply.github.com> --- coverage/cgfs_fext/RV32Zdinx/fadd.d.cgf | 188 + coverage/cgfs_fext/RV32Zdinx/fclass.d.cgf | 14 + coverage/cgfs_fext/RV32Zdinx/fcvt.d.l.cgf | 14 + coverage/cgfs_fext/RV32Zdinx/fcvt.d.lu.cgf | 17 + coverage/cgfs_fext/RV32Zdinx/fcvt.d.w.cgf | 28 + coverage/cgfs_fext/RV32Zdinx/fcvt.d.wu.cgf | 28 + coverage/cgfs_fext/RV32Zdinx/fcvt.s.d.cgf | 106 + coverage/cgfs_fext/RV32Zdinx/fcvt.w.d.cgf | 92 + coverage/cgfs_fext/RV32Zdinx/fcvt.wu.d.cgf | 92 + coverage/cgfs_fext/RV32Zdinx/fdiv.d.cgf | 188 + coverage/cgfs_fext/RV32Zdinx/feq.d.cgf | 35 + coverage/cgfs_fext/RV32Zdinx/fle.d.cgf | 35 + coverage/cgfs_fext/RV32Zdinx/flt.d.cgf | 35 + coverage/cgfs_fext/RV32Zdinx/fmax.d.cgf | 35 + coverage/cgfs_fext/RV32Zdinx/fmin.d.cgf | 35 + coverage/cgfs_fext/RV32Zdinx/fmul.d.cgf | 154 + coverage/cgfs_fext/RV32Zdinx/fsgnj.d.cgf | 19 + coverage/cgfs_fext/RV32Zdinx/fsgnjn.d.cgf | 17 + coverage/cgfs_fext/RV32Zdinx/fsgnjx.d.cgf | 19 + coverage/cgfs_fext/RV32Zdinx/fsqrt.d.cgf | 136 + coverage/cgfs_fext/RV32Zdinx/fsub.d.cgf | 188 + coverage/cgfs_fext/RV64Zdinx/fcvt.d.l.cgf | 14 + coverage/cgfs_fext/RV64Zdinx/fcvt.d.lu.cgf | 17 + coverage/cgfs_fext/RV64Zdinx/fcvt.l.d.cgf | 92 + coverage/cgfs_fext/RV64Zdinx/fcvt.lu.d.cgf | 92 + riscv-ctg/riscv_ctg/generator.py | 3 +- riscv-isac/riscv_isac/InstructionObject.py | 15 + .../riscv_isac/data/rvopcodesdecoder.py | 9 +- .../rv32i_m/Zdinx/src/fadd.d_b1-01.S | 4730 + .../rv32i_m/Zdinx/src/fadd.d_b10-01.S | 5034 + .../rv32i_m/Zdinx/src/fadd.d_b11-01.S | 86005 ++++++++++++++++ .../rv32i_m/Zdinx/src/fadd.d_b12-01.S | 512 + .../rv32i_m/Zdinx/src/fadd.d_b13-01.S | 1712 + .../rv32i_m/Zdinx/src/fadd.d_b2-01.S | 2317 + .../rv32i_m/Zdinx/src/fadd.d_b3-01.S | 9092 ++ .../rv32i_m/Zdinx/src/fadd.d_b4-01.S | 1232 + .../rv32i_m/Zdinx/src/fadd.d_b5-01.S | 1792 + .../rv32i_m/Zdinx/src/fadd.d_b7-01.S | 2805 + .../rv32i_m/Zdinx/src/fadd.d_b8-01.S | 11897 +++ .../rv32i_m/Zdinx/src/fclass.d_b1-01.S | 264 + .../rv32i_m/Zdinx/src/fcvt.s.d_b1-01.S | 264 + .../rv32i_m/Zdinx/src/fcvt.s.d_b22-01.S | 201 + .../rv32i_m/Zdinx/src/fcvt.s.d_b23-01.S | 411 + .../rv32i_m/Zdinx/src/fcvt.s.d_b24-01.S | 831 + .../rv32i_m/Zdinx/src/fcvt.s.d_b27-01.S | 201 + .../rv32i_m/Zdinx/src/fcvt.s.d_b28-01.S | 292 + .../rv32i_m/Zdinx/src/fcvt.s.d_b29-01.S | 656 + .../rv32i_m/Zdinx/src/fcvt.w.d_b1-01.S | 264 + .../rv32i_m/Zdinx/src/fcvt.w.d_b22-01.S | 376 + .../rv32i_m/Zdinx/src/fcvt.w.d_b23-01.S | 411 + .../rv32i_m/Zdinx/src/fcvt.w.d_b24-01.S | 831 + .../rv32i_m/Zdinx/src/fcvt.w.d_b27-01.S | 208 + .../rv32i_m/Zdinx/src/fcvt.w.d_b28-01.S | 292 + .../rv32i_m/Zdinx/src/fcvt.w.d_b29-01.S | 656 + .../rv32i_m/Zdinx/src/fcvt.wu.d_b1-01.S | 264 + .../rv32i_m/Zdinx/src/fcvt.wu.d_b22-01.S | 376 + .../rv32i_m/Zdinx/src/fcvt.wu.d_b23-01.S | 411 + .../rv32i_m/Zdinx/src/fcvt.wu.d_b24-01.S | 831 + .../rv32i_m/Zdinx/src/fcvt.wu.d_b27-01.S | 208 + .../rv32i_m/Zdinx/src/fcvt.wu.d_b28-01.S | 292 + .../rv32i_m/Zdinx/src/fcvt.wu.d_b29-01.S | 656 + .../rv32i_m/Zdinx/src/fdiv.d_b1-01.S | 4730 + .../rv32i_m/Zdinx/src/fdiv.d_b2-01.S | 2325 + .../rv32i_m/Zdinx/src/fdiv.d_b20-01.S | 2088 + .../rv32i_m/Zdinx/src/fdiv.d_b21-01.S | 5530 + .../rv32i_m/Zdinx/src/fdiv.d_b3-01.S | 9092 ++ .../rv32i_m/Zdinx/src/fdiv.d_b4-01.S | 1232 + .../rv32i_m/Zdinx/src/fdiv.d_b5-01.S | 1792 + .../rv32i_m/Zdinx/src/fdiv.d_b6-01.S | 1232 + .../rv32i_m/Zdinx/src/fdiv.d_b7-01.S | 2805 + .../rv32i_m/Zdinx/src/fdiv.d_b8-01.S | 11897 +++ .../rv32i_m/Zdinx/src/fdiv.d_b9-01.S | 18685 ++++ .../rv32i_m/Zdinx/src/feq.d_b1-01.S | 4722 + .../rv32i_m/Zdinx/src/feq.d_b19-01.S | 8900 ++ .../rv32i_m/Zdinx/src/fle.d_b1-01.S | 4722 + .../rv32i_m/Zdinx/src/fle.d_b19-01.S | 8900 ++ .../rv32i_m/Zdinx/src/flt.d_b1-01.S | 4722 + .../rv32i_m/Zdinx/src/flt.d_b19-01.S | 9316 ++ .../rv32i_m/Zdinx/src/fmax.d_b1-01.S | 4730 + .../rv32i_m/Zdinx/src/fmax.d_b19-01.S | 9036 ++ .../rv32i_m/Zdinx/src/fmin.d_b1-01.S | 4732 + .../rv32i_m/Zdinx/src/fmin.d_b19-01.S | 8902 ++ .../rv32i_m/Zdinx/src/fmul.d_b1-01.S | 4730 + .../rv32i_m/Zdinx/src/fmul.d_b2-01.S | 2325 + .../rv32i_m/Zdinx/src/fmul.d_b3-01.S | 9092 ++ .../rv32i_m/Zdinx/src/fmul.d_b4-01.S | 1232 + .../rv32i_m/Zdinx/src/fmul.d_b5-01.S | 1792 + .../rv32i_m/Zdinx/src/fmul.d_b6-01.S | 1232 + .../rv32i_m/Zdinx/src/fmul.d_b7-01.S | 2805 + .../rv32i_m/Zdinx/src/fmul.d_b8-01.S | 11897 +++ .../rv32i_m/Zdinx/src/fmul.d_b9-01.S | 18685 ++++ .../rv32i_m/Zdinx/src/fsgnj.d_b1-01.S | 4732 + .../rv32i_m/Zdinx/src/fsgnjn.d_b1-01.S | 4730 + .../rv32i_m/Zdinx/src/fsgnjx.d_b1-01.S | 4730 + .../rv32i_m/Zdinx/src/fsqrt.d_b1-01.S | 264 + .../rv32i_m/Zdinx/src/fsqrt.d_b2-01.S | 432 + .../rv32i_m/Zdinx/src/fsqrt.d_b20-01.S | 1055 + .../rv32i_m/Zdinx/src/fsqrt.d_b3-01.S | 201 + .../rv32i_m/Zdinx/src/fsqrt.d_b4-01.S | 201 + .../rv32i_m/Zdinx/src/fsqrt.d_b5-01.S | 201 + .../rv32i_m/Zdinx/src/fsqrt.d_b7-01.S | 201 + .../rv32i_m/Zdinx/src/fsqrt.d_b8-01.S | 201 + .../rv32i_m/Zdinx/src/fsqrt.d_b9-01.S | 2782 + .../rv32i_m/Zdinx/src/fsub.d_b1-01.S | 4730 + .../rv32i_m/Zdinx/src/fsub.d_b10-01.S | 5010 + .../rv32i_m/Zdinx/src/fsub.d_b11-01.S | 86005 ++++++++++++++++ .../rv32i_m/Zdinx/src/fsub.d_b12-01.S | 512 + .../rv32i_m/Zdinx/src/fsub.d_b13-01.S | 1712 + .../rv32i_m/Zdinx/src/fsub.d_b2-01.S | 2309 + .../rv32i_m/Zdinx/src/fsub.d_b3-01.S | 9092 ++ .../rv32i_m/Zdinx/src/fsub.d_b4-01.S | 1232 + .../rv32i_m/Zdinx/src/fsub.d_b5-01.S | 1792 + .../rv32i_m/Zdinx/src/fsub.d_b7-01.S | 2805 + .../rv32i_m/Zdinx/src/fsub.d_b8-01.S | 11897 +++ .../rv64i_m/Zdinx/src/fcvt.d.lu_b25-01.S | 201 + .../rv64i_m/Zdinx/src/fcvt.l.d_b1-01.S | 257 + .../rv64i_m/Zdinx/src/fcvt.l.d_b22-01.S | 593 + .../rv64i_m/Zdinx/src/fcvt.l.d_b23-01.S | 404 + .../rv64i_m/Zdinx/src/fcvt.l.d_b24-01.S | 824 + .../rv64i_m/Zdinx/src/fcvt.l.d_b27-01.S | 201 + .../rv64i_m/Zdinx/src/fcvt.l.d_b28-01.S | 285 + .../rv64i_m/Zdinx/src/fcvt.l.d_b29-01.S | 649 + .../rv64i_m/Zdinx/src/fcvt.lu.d_b1-01.S | 257 + .../rv64i_m/Zdinx/src/fcvt.lu.d_b22-01.S | 593 + .../rv64i_m/Zdinx/src/fcvt.lu.d_b23-01.S | 404 + .../rv64i_m/Zdinx/src/fcvt.lu.d_b24-01.S | 824 + .../rv64i_m/Zdinx/src/fcvt.lu.d_b27-01.S | 201 + .../rv64i_m/Zdinx/src/fcvt.lu.d_b28-01.S | 285 + .../rv64i_m/Zdinx/src/fcvt.lu.d_b29-01.S | 649 + 129 files changed, 475369 insertions(+), 5 deletions(-) create mode 100644 coverage/cgfs_fext/RV32Zdinx/fadd.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fclass.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fcvt.d.l.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fcvt.d.lu.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fcvt.d.w.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fcvt.d.wu.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fcvt.s.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fcvt.w.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fcvt.wu.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fdiv.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/feq.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fle.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/flt.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fmax.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fmin.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fmul.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fsgnj.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fsgnjn.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fsgnjx.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fsqrt.d.cgf create mode 100644 coverage/cgfs_fext/RV32Zdinx/fsub.d.cgf create mode 100644 coverage/cgfs_fext/RV64Zdinx/fcvt.d.l.cgf create mode 100644 coverage/cgfs_fext/RV64Zdinx/fcvt.d.lu.cgf create mode 100644 coverage/cgfs_fext/RV64Zdinx/fcvt.l.d.cgf create mode 100644 coverage/cgfs_fext/RV64Zdinx/fcvt.lu.d.cgf create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fadd.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fadd.d_b10-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fadd.d_b11-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fadd.d_b12-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fadd.d_b13-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fadd.d_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fadd.d_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fadd.d_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fadd.d_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fadd.d_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fadd.d_b8-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fclass.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.s.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.s.d_b22-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.s.d_b23-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.s.d_b24-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.s.d_b27-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.s.d_b28-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.s.d_b29-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.w.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.w.d_b22-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.w.d_b23-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.w.d_b24-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.w.d_b27-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.w.d_b28-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.w.d_b29-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.wu.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.wu.d_b22-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.wu.d_b23-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.wu.d_b24-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.wu.d_b27-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.wu.d_b28-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fcvt.wu.d_b29-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fdiv.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fdiv.d_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fdiv.d_b20-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fdiv.d_b21-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fdiv.d_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fdiv.d_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fdiv.d_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fdiv.d_b6-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fdiv.d_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fdiv.d_b8-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fdiv.d_b9-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/feq.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/feq.d_b19-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fle.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fle.d_b19-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/flt.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/flt.d_b19-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fmax.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fmax.d_b19-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fmin.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fmin.d_b19-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fmul.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fmul.d_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fmul.d_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fmul.d_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fmul.d_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fmul.d_b6-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fmul.d_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fmul.d_b8-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fmul.d_b9-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsgnj.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsgnjn.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsgnjx.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsqrt.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsqrt.d_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsqrt.d_b20-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsqrt.d_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsqrt.d_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsqrt.d_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsqrt.d_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsqrt.d_b8-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsqrt.d_b9-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsub.d_b1-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsub.d_b10-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsub.d_b11-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsub.d_b12-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsub.d_b13-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsub.d_b2-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsub.d_b3-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsub.d_b4-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsub.d_b5-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsub.d_b7-01.S create mode 100644 riscv-test-suite/rv32i_m/Zdinx/src/fsub.d_b8-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.d.lu_b25-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.l.d_b1-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.l.d_b22-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.l.d_b23-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.l.d_b24-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.l.d_b27-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.l.d_b28-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.l.d_b29-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.lu.d_b1-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.lu.d_b22-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.lu.d_b23-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.lu.d_b24-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.lu.d_b27-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.lu.d_b28-01.S create mode 100644 riscv-test-suite/rv64i_m/Zdinx/src/fcvt.lu.d_b29-01.S diff --git a/coverage/cgfs_fext/RV32Zdinx/fadd.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fadd.d.cgf new file mode 100644 index 000000000..09b2b73ef --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fadd.d.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fadd.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fadd.d", 2, True)': 0 + +fadd.d_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fadd.d", 2, True)': 0 + +fadd.d_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fadd.d", 2, True)': 0 + +fadd.d_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fadd.d", 2, True)': 0 + +fadd.d_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fadd.d", 2, True)': 0 + +fadd.d_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fadd.d", 2, True)': 0 + +fadd.d_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fadd.d", 2, True)': 0 + +fadd.d_b10: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,64, "fadd.d", 2, True)': 0 + +fadd.d_b11: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,64, "fadd.d", 2, True)': 0 + +fadd.d_b12: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,64, "fadd.d", 2, True)': 0 + +fadd.d_b13: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fadd.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,64, "fadd.d", 2, True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/fclass.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fclass.d.cgf new file mode 100644 index 000000000..622b9cb1d --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fclass.d.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fclass.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fclass.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fclass.d", 1, True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/fcvt.d.l.cgf b/coverage/cgfs_fext/RV32Zdinx/fcvt.d.l.cgf new file mode 100644 index 000000000..6a886af45 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fcvt.d.l.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.l_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.d.l: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.d.l", 1, True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/fcvt.d.lu.cgf b/coverage/cgfs_fext/RV32Zdinx/fcvt.d.lu.cgf new file mode 100644 index 000000000..111edc945 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fcvt.d.lu.cgf @@ -0,0 +1,17 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.lu_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.d.lu: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.d.lu", 1, True)': 0 + + + diff --git a/coverage/cgfs_fext/RV32Zdinx/fcvt.d.w.cgf b/coverage/cgfs_fext/RV32Zdinx/fcvt.d.w.cgf new file mode 100644 index 000000000..0e0c01f4b --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fcvt.d.w.cgf @@ -0,0 +1,28 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.w_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.d.w: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fcvt.d.w", 1, True)': 0 + +fcvt.d.w_b26: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.d.w: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b26(32, "fcvt.d.w", 1, True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zdinx/fcvt.d.wu.cgf b/coverage/cgfs_fext/RV32Zdinx/fcvt.d.wu.cgf new file mode 100644 index 000000000..0e0720e8e --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fcvt.d.wu.cgf @@ -0,0 +1,28 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.wu_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx) + mnemonics: + fcvt.d.wu: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,32, "fcvt.d.wu", 1, True)': 0 + +fcvt.d.wu_b26: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx) + mnemonics: + fcvt.d.wu: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b26(32, "fcvt.d.wu", 1, True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zdinx/fcvt.s.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fcvt.s.d.cgf new file mode 100644 index 000000000..baa780913 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fcvt.s.d.cgf @@ -0,0 +1,106 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.s.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fcvt.s.d", 1, True)': 0 + +fcvt.s.d_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fcvt.s.d", 1, True)': 0 + +fcvt.s.d_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fcvt.s.d", 1, True)': 0 + +fcvt.s.d_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fcvt.s.d", 1, True)': 0 + +fcvt.s.d_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fcvt.s.d", 1, True)': 0 + +fcvt.s.d_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fcvt.s.d", 1, True)': 0 + +fcvt.s.d_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.s.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fcvt.s.d", 1, True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/fcvt.w.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fcvt.w.d.cgf new file mode 100644 index 000000000..d6973f04b --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fcvt.w.d.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.w.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fcvt.w.d", 1,True)': 0 + +fcvt.w.d_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fcvt.w.d", 1,True)': 0 + +fcvt.w.d_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fcvt.w.d", 1,True)': 0 + +fcvt.w.d_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fcvt.w.d", 1,True)': 0 + +fcvt.w.d_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fcvt.w.d", 1, True)': 0 + +fcvt.w.d_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fcvt.w.d", 1, True)': 0 + +fcvt.w.d_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.w.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fcvt.w.d", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/fcvt.wu.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fcvt.wu.d.cgf new file mode 100644 index 000000000..7964d9523 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fcvt.wu.d.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.wu.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fcvt.wu.d", 1, True)': 0 + +fcvt.wu.d_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fcvt.wu.d", 1, True)': 0 + +fcvt.wu.d_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fcvt.wu.d", 1, True)': 0 + +fcvt.wu.d_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fcvt.wu.d", 1, True)': 0 + +fcvt.wu.d_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fcvt.wu.d", 1, True)': 0 + +fcvt.wu.d_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fcvt.wu.d", 1, True)': 0 + +fcvt.wu.d_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.wu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fcvt.wu.d", 1,True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/fdiv.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fdiv.d.cgf new file mode 100644 index 000000000..8cc211b1c --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fdiv.d.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fdiv.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fdiv.d", 2, True)': 0 + +fdiv.d_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fdiv.d", 2, True)': 0 + +fdiv.d_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fdiv.d", 2, True)': 0 + +fdiv.d_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fdiv.d", 2, True)': 0 + +fdiv.d_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fdiv.d", 2, True)': 0 + +fdiv.d_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,64, "fdiv.d", 2, True)': 0 + +fdiv.d_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fdiv.d", 2, True)': 0 + +fdiv.d_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fdiv.d", 2, True)': 0 + +fdiv.d_b9: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,64, "fdiv.d", 2, True)': 0 + +fdiv.d_b20: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,64, "fdiv.d", 2, True)': 0 + +fdiv.d_b21: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fdiv.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b21(flen,64, "fdiv.d", 2, True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/feq.d.cgf b/coverage/cgfs_fext/RV32Zdinx/feq.d.cgf new file mode 100644 index 000000000..13d6ad625 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/feq.d.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +feq.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + feq.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "feq.d", 2, True)': 0 + +feq.d_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + feq.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,64, "feq.d", 2, True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/fle.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fle.d.cgf new file mode 100644 index 000000000..d5a94823f --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fle.d.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fle.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fle.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fle.d", 2, True)': 0 + +fle.d_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fle.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,64, "fle.d", 2, True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/flt.d.cgf b/coverage/cgfs_fext/RV32Zdinx/flt.d.cgf new file mode 100644 index 000000000..dd851b739 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/flt.d.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +flt.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + flt.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "flt.d", 2, True)': 0 + +flt.d_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + flt.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *sfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen, 64, "flt.d", 2, True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/fmax.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fmax.d.cgf new file mode 100644 index 000000000..669bd37aa --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fmax.d.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmax.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fmax.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fmax.d", 2, True)': 0 + +fmax.d_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fmax.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,64, "fmax.d", 2, True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/fmin.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fmin.d.cgf new file mode 100644 index 000000000..0d6a2a45e --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fmin.d.cgf @@ -0,0 +1,35 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmin.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fmin.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fmin.d", 2, True)': 0 + +fmin.d_b19: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fmin.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b19(flen,64, "fmin.d", 2, True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/fmul.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fmul.d.cgf new file mode 100644 index 000000000..08cb0fa0e --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fmul.d.cgf @@ -0,0 +1,154 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fmul.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fmul.d", 2, True)': 0 + +fmul.d_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fmul.d", 2, True)': 0 + +fmul.d_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fmul.d", 2, True)': 0 + +fmul.d_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fmul.d", 2, True)': 0 + +fmul.d_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fmul.d", 2, True)': 0 + +fmul.d_b6: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b6(flen,64, "fmul.d", 2, True)': 0 + +fmul.d_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fmul.d", 2, True)': 0 + +fmul.d_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fmul.d", 2, True)': 0 + +fmul.d_b9: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fmul.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,64, "fmul.d", 2, True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/fsgnj.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fsgnj.d.cgf new file mode 100644 index 000000000..05f0e0cac --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fsgnj.d.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnj.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsgnj.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fsgnj.d", 2, True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zdinx/fsgnjn.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fsgnjn.d.cgf new file mode 100644 index 000000000..5c45a5392 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fsgnjn.d.cgf @@ -0,0 +1,17 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore +fsgnjn.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsgnjn.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fsgnjn.d", 2, True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/fsgnjx.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fsgnjx.d.cgf new file mode 100644 index 000000000..3a674c08a --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fsgnjx.d.cgf @@ -0,0 +1,19 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsgnjx.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsgnjx.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fsgnjx.d", 2, True)': 0 + diff --git a/coverage/cgfs_fext/RV32Zdinx/fsqrt.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fsqrt.d.cgf new file mode 100644 index 000000000..d44bb7fa1 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fsqrt.d.cgf @@ -0,0 +1,136 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsqrt.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fsqrt.d", 1, True)': 0 + +fsqrt.d_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fsqrt.d", 1, True)': 0 + +fsqrt.d_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fsqrt.d", 1, True)': 0 + +fsqrt.d_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fsqrt.d", 1, True)': 0 + +fsqrt.d_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fsqrt.d", 1, True)': 0 + +fsqrt.d_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fsqrt.d", 1, True)': 0 + +fsqrt.d_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fsqrt.d", 1, True)': 0 + +fsqrt.d_b9: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b9(flen,64, "fsqrt.d", 1, True)': 0 + +fsqrt.d_b20: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsqrt.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *ifmt_op_comb + val_comb: + abstract_comb: + 'ibm_b20(flen,64, "fsqrt.d", 1, True)': 0 diff --git a/coverage/cgfs_fext/RV32Zdinx/fsub.d.cgf b/coverage/cgfs_fext/RV32Zdinx/fsub.d.cgf new file mode 100644 index 000000000..8ac0fd404 --- /dev/null +++ b/coverage/cgfs_fext/RV32Zdinx/fsub.d.cgf @@ -0,0 +1,188 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fsub.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fsub.d", 2, True)': 0 + +fsub.d_b2: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b2(flen,64, "fsub.d", 2, True)': 0 + +fsub.d_b3: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b3(flen,64, "fsub.d", 2, True)': 0 + +fsub.d_b4: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b4(flen,64, "fsub.d", 2, True)': 0 + +fsub.d_b5: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b5(flen,64, "fsub.d", 2, True)': 0 + +fsub.d_b7: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b7(flen,64, "fsub.d", 2, True)': 0 + +fsub.d_b8: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b8(flen,64, "fsub.d", 2, True)': 0 + +fsub.d_b10: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b10(flen,64, "fsub.d", 2, True)': 0 + +fsub.d_b11: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b11(flen,64, "fsub.d", 2, True)': 0 + +fsub.d_b12: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b12(flen,64, "fsub.d", 2, True)': 0 + +fsub.d_b13: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fsub.d: 0 + rs1: + <<: *pair_regs + rs2: + <<: *pair_regs + rd: + <<: *pair_regs + op_comb: + <<: *rfmt_op_comb + val_comb: + abstract_comb: + 'ibm_b13(flen,64, "fsub.d", 2, True)': 0 diff --git a/coverage/cgfs_fext/RV64Zdinx/fcvt.d.l.cgf b/coverage/cgfs_fext/RV64Zdinx/fcvt.d.l.cgf new file mode 100644 index 000000000..6a886af45 --- /dev/null +++ b/coverage/cgfs_fext/RV64Zdinx/fcvt.d.l.cgf @@ -0,0 +1,14 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.l_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.d.l: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.d.l", 1, True)': 0 diff --git a/coverage/cgfs_fext/RV64Zdinx/fcvt.d.lu.cgf b/coverage/cgfs_fext/RV64Zdinx/fcvt.d.lu.cgf new file mode 100644 index 000000000..111edc945 --- /dev/null +++ b/coverage/cgfs_fext/RV64Zdinx/fcvt.d.lu.cgf @@ -0,0 +1,17 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.d.lu_b25: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.d.lu: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b25(flen,64, "fcvt.d.lu", 1, True)': 0 + + + diff --git a/coverage/cgfs_fext/RV64Zdinx/fcvt.l.d.cgf b/coverage/cgfs_fext/RV64Zdinx/fcvt.l.d.cgf new file mode 100644 index 000000000..03eae6a9b --- /dev/null +++ b/coverage/cgfs_fext/RV64Zdinx/fcvt.l.d.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.l.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fcvt.l.d", 1, True)': 0 + +fcvt.l.d_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fcvt.l.d", 1, True)': 0 + +fcvt.l.d_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fcvt.l.d", 1, True)': 0 + +fcvt.l.d_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fcvt.l.d", 1, True)': 0 + +fcvt.l.d_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fcvt.l.d", 1, True)': 0 + +fcvt.l.d_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fcvt.l.d", 1, True)': 0 + +fcvt.l.d_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.l.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fcvt.l.d", 1, True)': 0 diff --git a/coverage/cgfs_fext/RV64Zdinx/fcvt.lu.d.cgf b/coverage/cgfs_fext/RV64Zdinx/fcvt.lu.d.cgf new file mode 100644 index 000000000..0471bd2f6 --- /dev/null +++ b/coverage/cgfs_fext/RV64Zdinx/fcvt.lu.d.cgf @@ -0,0 +1,92 @@ +# For Licence details look at https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg/-/blob/master/LICENSE.incore + +fcvt.lu.d_b1: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b1(flen,64, "fcvt.lu.d", 1, True)': 0 + +fcvt.lu.d_b22: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b22(flen,64, "fcvt.lu.d", 1, True)': 0 + +fcvt.lu.d_b23: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b23(flen,64, "fcvt.lu.d", 1, True)': 0 + +fcvt.lu.d_b24: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b24(flen,64, "fcvt.lu.d", 1, True)': 0 + +fcvt.lu.d_b27: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b27(flen,64, "fcvt.lu.d", 1, True)': 0 + +fcvt.lu.d_b28: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b28(flen,64, "fcvt.lu.d", 1, True)': 0 + +fcvt.lu.d_b29: + config: + - check ISA:=regex(.*I.*Zfinx.*Zdinx.*) + mnemonics: + fcvt.lu.d: 0 + rs1: + <<: *pair_regs + rd: + <<: *pair_regs + val_comb: + abstract_comb: + 'ibm_b29(flen,64, "fcvt.lu.d", 1, True)': 0 diff --git a/riscv-ctg/riscv_ctg/generator.py b/riscv-ctg/riscv_ctg/generator.py index c150785e9..082e31126 100644 --- a/riscv-ctg/riscv_ctg/generator.py +++ b/riscv-ctg/riscv_ctg/generator.py @@ -260,8 +260,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx is_nan_box = False - - is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x or 'Zcf' in x or 'Zcd' in x or 'Zhinx' in x for x in opnode['isa']]) + is_fext = any(['F' in x or 'D' in x or 'Zfh' in x or 'Zfinx' in x or 'Zcf' in x or 'Zcd' in x or 'Zhinx' in x or 'Zdinx' in x for x in opnode['isa']]) is_sgn_extd = True if (inxFlag and iflen