diff --git a/riscv-isac/riscv_isac/InstructionObject.py b/riscv-isac/riscv_isac/InstructionObject.py
index ad8496983..3d90c2099 100644
--- a/riscv-isac/riscv_isac/InstructionObject.py
+++ b/riscv-isac/riscv_isac/InstructionObject.py
@@ -22,6 +22,7 @@
         'sm4ed','sm4ks','ror','rol','rori','rorw','rolw','roriw','clmul','clmulh','clmulr',\
         'andn','orn','xnor','pack','packh','packu','packuw','packw',\
         'xperm.n','xperm.b','grevi','aes64ks1i', 'shfli', 'unshfli', \
+        'cbo.clean', 'cbo.flush', 'cbo.inval', 'cbo.zero', 'prefetch.i','prefetch.r','prefetch.w', \
         'aes32esmi', 'aes32esi', 'aes32dsmi', 'aes32dsi','bclr','bext','binv',\
         'bset','zext.h','sext.h','sext.b','zext.b','zext.w','minu','maxu','orc.b','add.uw','sh1add.uw',\
         'sh2add.uw','sh3add.uw','slli.uw','clz','clzw','ctz','ctzw','cpop','cpopw','rev8',\
@@ -326,7 +327,7 @@ def update_arch_state(self, arch_state, csr_regfile, mem_vals):
         arch_state.pc = self.instr_addr
 
         commitvalue = self.reg_commit
-        if commitvalue is not None:
+        if commitvalue is not None and len(self.rd) >= 1:
             if self.rd[1] == 'x':
                 arch_state.x_rf[int(commitvalue[1])] =  str(commitvalue[2][2:])
             elif self.rd[1] == 'f':
diff --git a/riscv-isac/riscv_isac/plugins/internaldecoder.py b/riscv-isac/riscv_isac/plugins/internaldecoder.py
index 3bd6592c5..5d5a9415d 100644
--- a/riscv-isac/riscv_isac/plugins/internaldecoder.py
+++ b/riscv-isac/riscv_isac/plugins/internaldecoder.py
@@ -14,7 +14,7 @@ def __init__(self):
             0b0100011: self.store_ops,
             0b0010011: self.arithi_ops,
             0b0110011: self.arith_ops,
-            0b0001111: self.fence_ops,
+            0b0001111: self.mem_ops,
             0b1110011: self.priviledged_ops,
             0b0011011: self.rv64i_arithi_ops,
             0b0111011: self.rv64i_arith_ops,
@@ -566,6 +566,11 @@ def arithi_ops(self, instrObj):
         funct6 = (instr & self.FUNCT6_MASK) >> 26
         funct7 = (instr >> 25)
         rd = ((instr & self.RD_MASK) >> 7, 'x')
+
+        if funct3 == 0b110:
+            if rd[0] == 0:
+                return self.prefetch_ops(instrObj)
+
         rs1 = ((instr & self.RS1_MASK) >> 15, 'x')
         rs2 = ((instr & self.RS2_MASK) >> 20, 'x')
         rs3 = ((instr & self.RS3_MASK) >> 27, 'x')
@@ -1306,6 +1311,14 @@ def arith_ops(self, instrObj):
 
         return instrObj
 
+    def mem_ops(self, instrObj):
+        instr = instrObj.instr
+        func3 = (instr & self.FUNCT3_MASK) >> 12
+        if func3 == 0b000 or func3 == 0b001:
+            return self.fence_ops(instrObj)
+        elif func3 == 0b010 :
+            return self.cbo_ops(instrObj)
+
     def fence_ops(self, instrObj):
         instr = instrObj.instr
         funct3 = (instr & self.FUNCT3_MASK) >> 12
@@ -1322,6 +1335,37 @@ def fence_ops(self, instrObj):
 
         return instrObj
 
+    def cbo_ops(self, instrObj):
+        instr = instrObj.instr
+        func = (instr) >> 20
+        instrObj.rs1 = ((instr & self.RS1_MASK) >> 15, 'x')
+        instrObj.imm = 0
+        if func == 0b1:
+            instrObj.instr_name = "cbo.clean"
+        elif func == 0b10:
+            instrObj.instr_name = "cbo.flush"
+        elif func == 0b0:
+            instrObj.instr_name = "cbo.inval"
+        elif func == 0b100:
+            instrObj.instr_name = "cbo.zero"
+        return instrObj
+
+    def prefetch_ops(self, instrObj):
+        instr = instrObj.instr
+        func = (instr & self.RS2_MASK) >> 20
+        instrObj.rs1 = ((instr & self.RS1_MASK) >> 15, 'x')
+
+        imm_11_5 = (instr & 0xfe000000) >> 20
+        instrObj.imm = self.twos_comp(imm_11_5, 12)
+
+        if func == 0b0:
+            instrObj.instr_name = "prefetch.i"
+        elif func == 0b1:
+            instrObj.instr_name = "prefetch.r"
+        elif func == 0b11:
+            instrObj.instr_name = "prefetch.w"
+        return instrObj
+
     def priviledged_ops(self, instrObj):
         instr = instrObj.instr
         funct3 = (instr & self.FUNCT3_MASK) >> 12