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riscv-013.c
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Support for RISC-V, debug version 0.13, which is currently (2/4/17) the
* latest draft.
*/
#include <assert.h>
#include <stdint.h>
#include <stdlib.h>
#include <time.h>
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "target/target.h"
#include "target/algorithm.h"
#include "target/target_type.h"
#include <helper/align.h>
#include <helper/log.h>
#include "jtag/jtag.h"
#include "target/register.h"
#include "target/breakpoints.h"
#include "helper/time_support.h"
#include "helper/list.h"
#include "riscv.h"
#include "riscv-013.h"
#include "riscv_reg.h"
#include "riscv-013_reg.h"
#include "debug_defines.h"
#include "rtos/rtos.h"
#include "program.h"
#include "batch.h"
#include "debug_reg_printer.h"
#include "field_helpers.h"
static int riscv013_on_step_or_resume(struct target *target, bool step);
static int riscv013_step_or_resume_current_hart(struct target *target,
bool step);
static int riscv013_clear_abstract_error(struct target *target);
/* Implementations of the functions in struct riscv_info. */
static int dm013_select_hart(struct target *target, int hart_index);
static int riscv013_halt_prep(struct target *target);
static int riscv013_halt_go(struct target *target);
static int riscv013_resume_go(struct target *target);
static int riscv013_step_current_hart(struct target *target);
static int riscv013_on_step(struct target *target);
static int riscv013_resume_prep(struct target *target);
static enum riscv_halt_reason riscv013_halt_reason(struct target *target);
static int riscv013_write_progbuf(struct target *target, unsigned int index,
riscv_insn_t d);
static riscv_insn_t riscv013_read_progbuf(struct target *target, unsigned int
index);
static int riscv013_invalidate_cached_progbuf(struct target *target);
static int riscv013_execute_progbuf(struct target *target, uint32_t *cmderr);
static void riscv013_fill_dmi_write(const struct target *target, uint8_t *buf, uint32_t a, uint32_t d);
static void riscv013_fill_dmi_read(const struct target *target, uint8_t *buf, uint32_t a);
static unsigned int riscv013_get_dmi_address_bits(const struct target *target);
static void riscv013_fill_dm_nop(const struct target *target, uint8_t *buf);
static unsigned int register_size(struct target *target, enum gdb_regno number);
static int register_read_direct(struct target *target, riscv_reg_t *value,
enum gdb_regno number);
static int register_write_direct(struct target *target, enum gdb_regno number,
riscv_reg_t value);
static int riscv013_access_memory(struct target *target, const riscv_mem_access_args_t args);
static bool riscv013_get_impebreak(const struct target *target);
static unsigned int riscv013_get_progbufsize(const struct target *target);
typedef enum {
HALT_GROUP,
RESUME_GROUP
} grouptype_t;
static int set_group(struct target *target, bool *supported, unsigned int group,
grouptype_t grouptype);
/**
* Since almost everything can be accomplish by scanning the dbus register, all
* functions here assume dbus is already selected. The exception are functions
* called directly by OpenOCD, which can't assume anything about what's
* currently in IR. They should set IR to dbus explicitly.
*/
#define RISCV013_INFO(r) riscv013_info_t *r = get_info(target)
/*** JTAG registers. ***/
typedef enum {
DMI_OP_NOP = DTM_DMI_OP_NOP,
DMI_OP_READ = DTM_DMI_OP_READ,
DMI_OP_WRITE = DTM_DMI_OP_WRITE
} dmi_op_t;
typedef enum {
DMI_STATUS_SUCCESS = DTM_DMI_OP_SUCCESS,
DMI_STATUS_FAILED = DTM_DMI_OP_FAILED,
DMI_STATUS_BUSY = DTM_DMI_OP_BUSY
} dmi_status_t;
/*** Debug Bus registers. ***/
/* TODO: CMDERR_* defines can removed */
#define CMDERR_NONE DM_ABSTRACTCS_CMDERR_NONE
#define CMDERR_BUSY DM_ABSTRACTCS_CMDERR_BUSY
#define CMDERR_NOT_SUPPORTED DM_ABSTRACTCS_CMDERR_NOT_SUPPORTED
#define CMDERR_EXCEPTION DM_ABSTRACTCS_CMDERR_EXCEPTION
#define CMDERR_HALT_RESUME DM_ABSTRACTCS_CMDERR_HALT_RESUME
#define CMDERR_OTHER DM_ABSTRACTCS_CMDERR_OTHER
#define HART_INDEX_MULTIPLE -1
#define HART_INDEX_UNKNOWN -2
typedef struct {
struct list_head list;
unsigned int abs_chain_position;
/* The base address to access this DM on DMI */
uint32_t base;
/* The number of harts connected to this DM. */
int hart_count;
/* Indicates we already examined this DM, so don't need to do it again. */
bool was_examined;
/* Indicates we already reset this DM, so don't need to do it again. */
bool was_reset;
/* Targets that are connected to this DM. */
struct list_head target_list;
/* Contains the ID of the hart that is currently selected by this DM.
* If multiple harts are selected this is HART_INDEX_MULTIPLE. */
int current_hartid;
bool hasel_supported;
/* The program buffer stores executable code. 0 is an illegal instruction,
* so we use 0 to mean the cached value is invalid. */
uint32_t progbuf_cache[16];
/* Some operations are illegal when an abstract command is running.
* The field is used to track whether the last command timed out, and
* abstractcs.busy may have remained set. In that case we may need to
* re-check the busy state before executing these operations. */
bool abstract_cmd_maybe_busy;
} dm013_info_t;
typedef struct {
struct list_head list;
struct target *target;
} target_list_t;
typedef struct {
/* The indexed used to address this hart in its DM. */
unsigned int index;
/* Number of address bits in the dbus register. */
unsigned int abits;
/* Number of abstract command data registers. */
unsigned int datacount;
/* Number of words in the Program Buffer. */
unsigned int progbufsize;
/* Hart contains an implicit ebreak at the end of the program buffer. */
bool impebreak;
/* We cache the read-only bits of sbcs here. */
uint32_t sbcs;
yes_no_maybe_t progbuf_writable;
/* We only need the address so that we know the alignment of the buffer. */
riscv_addr_t progbuf_address;
/* Number of run-test/idle cycles the target requests we do after each dbus
* access. */
unsigned int dtmcs_idle;
/* This structure is used to determine how many run-test/idle to use after
* an access of corresponding "riscv_scan_delay_class".
* Values are incremented every time an access results in a busy
* response.
*/
struct riscv_scan_delays learned_delays;
bool abstract_read_csr_supported;
bool abstract_write_csr_supported;
bool abstract_read_fpr_supported;
bool abstract_write_fpr_supported;
yes_no_maybe_t has_aampostincrement;
/* Some fields from hartinfo. */
uint8_t datasize;
uint8_t dataaccess;
int16_t dataaddr;
/* The width of the hartsel field. */
unsigned int hartsellen;
/* DM that provides access to this target. */
dm013_info_t *dm;
/* This target was selected using hasel. */
bool selected;
/* When false, we need to set dcsr.ebreak*, halting the target if that's
* necessary. */
bool dcsr_ebreak_is_set;
/* This hart was placed into a halt group in examine(). */
bool haltgroup_supported;
} riscv013_info_t;
static OOCD_LIST_HEAD(dm_list);
static riscv013_info_t *get_info(const struct target *target)
{
struct riscv_info *info = target->arch_info;
assert(info);
assert(info->version_specific);
return info->version_specific;
}
/**
* Return the DM structure for this target. If there isn't one, find it in the
* global list of DMs. If it's not in there, then create one and initialize it
* to 0.
*/
static dm013_info_t *get_dm(struct target *target)
{
RISCV013_INFO(info);
if (info->dm)
return info->dm;
unsigned int abs_chain_position = target->tap->abs_chain_position;
dm013_info_t *entry;
dm013_info_t *dm = NULL;
list_for_each_entry(entry, &dm_list, list) {
if (entry->abs_chain_position == abs_chain_position
&& entry->base == target->dbgbase) {
dm = entry;
break;
}
}
if (!dm) {
LOG_TARGET_DEBUG(target, "Coreid [%d] Allocating new DM", target->coreid);
dm = calloc(1, sizeof(dm013_info_t));
if (!dm)
return NULL;
dm->abs_chain_position = abs_chain_position;
/* Safety check for dbgbase */
assert(target->dbgbase_set || target->dbgbase == 0);
dm->base = target->dbgbase;
dm->current_hartid = 0;
dm->hart_count = -1;
INIT_LIST_HEAD(&dm->target_list);
list_add(&dm->list, &dm_list);
}
info->dm = dm;
target_list_t *target_entry;
list_for_each_entry(target_entry, &dm->target_list, list) {
if (target_entry->target == target)
return dm;
}
target_entry = calloc(1, sizeof(*target_entry));
if (!target_entry) {
info->dm = NULL;
return NULL;
}
target_entry->target = target;
list_add(&target_entry->list, &dm->target_list);
return dm;
}
static void riscv013_dm_free(struct target *target)
{
RISCV013_INFO(info);
dm013_info_t *dm = info->dm;
if (!dm)
return;
target_list_t *target_entry;
list_for_each_entry(target_entry, &dm->target_list, list) {
if (target_entry->target == target) {
list_del(&target_entry->list);
free(target_entry);
break;
}
}
if (list_empty(&dm->target_list)) {
list_del(&dm->list);
free(dm);
}
info->dm = NULL;
}
static riscv_debug_reg_ctx_t get_riscv_debug_reg_ctx(const struct target *target)
{
if (!target_was_examined(target)) {
const riscv_debug_reg_ctx_t default_context = {0};
return default_context;
}
RISCV013_INFO(info);
const riscv_debug_reg_ctx_t context = {
.XLEN = { .value = riscv_xlen(target), .is_set = true },
.DXLEN = { .value = riscv_xlen(target), .is_set = true },
.abits = { .value = info->abits, .is_set = true },
};
return context;
}
static void log_debug_reg(struct target *target, enum riscv_debug_reg_ordinal reg,
riscv_reg_t value, const char *file, unsigned int line, const char *func)
{
if (debug_level < LOG_LVL_DEBUG)
return;
const riscv_debug_reg_ctx_t context = get_riscv_debug_reg_ctx(target);
char * const buf = malloc(riscv_debug_reg_to_s(NULL, reg, context, value, RISCV_DEBUG_REG_HIDE_UNNAMED_0) + 1);
if (!buf) {
LOG_ERROR("Unable to allocate memory.");
return;
}
riscv_debug_reg_to_s(buf, reg, context, value, RISCV_DEBUG_REG_HIDE_UNNAMED_0);
log_printf_lf(LOG_LVL_DEBUG, file, line, func, "[%s] %s", target_name(target), buf);
free(buf);
}
#define LOG_DEBUG_REG(t, r, v) log_debug_reg(t, r##_ORDINAL, v, __FILE__, __LINE__, __func__)
static uint32_t set_dmcontrol_hartsel(uint32_t initial, int hart_index)
{
assert(hart_index != HART_INDEX_UNKNOWN);
if (hart_index >= 0) {
initial = set_field(initial, DM_DMCONTROL_HASEL, DM_DMCONTROL_HASEL_SINGLE);
uint32_t index_lo = hart_index & ((1 << DM_DMCONTROL_HARTSELLO_LENGTH) - 1);
initial = set_field(initial, DM_DMCONTROL_HARTSELLO, index_lo);
uint32_t index_hi = hart_index >> DM_DMCONTROL_HARTSELLO_LENGTH;
assert(index_hi < (1 << DM_DMCONTROL_HARTSELHI_LENGTH));
initial = set_field(initial, DM_DMCONTROL_HARTSELHI, index_hi);
} else if (hart_index == HART_INDEX_MULTIPLE) {
initial = set_field(initial, DM_DMCONTROL_HASEL, DM_DMCONTROL_HASEL_MULTIPLE);
/* TODO: https://github.com/riscv/riscv-openocd/issues/748 */
initial = set_field(initial, DM_DMCONTROL_HARTSELLO, 0);
initial = set_field(initial, DM_DMCONTROL_HARTSELHI, 0);
}
return initial;
}
/*** Utility functions. ***/
static void select_dmi(struct jtag_tap *tap)
{
if (bscan_tunnel_ir_width != 0) {
select_dmi_via_bscan(tap);
return;
}
if (!tap->enabled)
LOG_ERROR("BUG: Target's TAP '%s' is disabled!", jtag_tap_name(tap));
bool need_ir_scan = false;
/* FIXME: make "tap" a const pointer. */
for (struct jtag_tap *other_tap = jtag_tap_next_enabled(NULL);
other_tap; other_tap = jtag_tap_next_enabled(other_tap)) {
if (other_tap != tap) {
/* Different TAP than ours - check if it is in bypass */
if (!other_tap->bypass) {
need_ir_scan = true;
break;
}
} else {
/* Our TAP - check if the correct instruction is already loaded */
if (!buf_eq(tap->cur_instr, select_dbus.out_value, tap->ir_length)) {
need_ir_scan = true;
break;
}
}
}
if (need_ir_scan)
jtag_add_ir_scan(tap, &select_dbus, TAP_IDLE);
}
static int increase_dmi_busy_delay(struct target *target)
{
RISCV013_INFO(info);
int res = dtmcs_scan(target->tap, DTM_DTMCS_DMIRESET,
NULL /* discard result */);
if (res != ERROR_OK)
return res;
res = riscv_scan_increase_delay(&info->learned_delays,
RISCV_DELAY_BASE);
return res;
}
static void reset_learned_delays(struct target *target)
{
RISCV013_INFO(info);
assert(info);
memset(&info->learned_delays, 0, sizeof(info->learned_delays));
}
static void decrement_reset_delays_counter(struct target *target, size_t finished_scans)
{
RISCV_INFO(r);
if (r->reset_delays_wait < 0) {
assert(r->reset_delays_wait == -1);
return;
}
if ((size_t)r->reset_delays_wait >= finished_scans) {
r->reset_delays_wait -= finished_scans;
return;
}
r->reset_delays_wait = -1;
LOG_TARGET_DEBUG(target,
"resetting learned delays (reset_delays_wait counter expired)");
reset_learned_delays(target);
}
static uint32_t riscv013_get_dmi_address(const struct target *target, uint32_t address)
{
assert(target);
uint32_t base = 0;
RISCV013_INFO(info);
if (info && info->dm)
base = info->dm->base;
return address + base;
}
static int batch_run_timeout(struct target *target, struct riscv_batch *batch);
static int dmi_read(struct target *target, uint32_t *value, uint32_t address)
{
struct riscv_batch *batch = riscv_batch_alloc(target, 1);
riscv_batch_add_dmi_read(batch, address, RISCV_DELAY_BASE);
int res = batch_run_timeout(target, batch);
if (res == ERROR_OK && value)
*value = riscv_batch_get_dmi_read_data(batch, 0);
riscv_batch_free(batch);
return res;
}
static int dm_read(struct target *target, uint32_t *value, uint32_t address)
{
return dmi_read(target, value, riscv013_get_dmi_address(target, address));
}
static int dm_read_exec(struct target *target, uint32_t *value, uint32_t address)
{
dm013_info_t *dm = get_dm(target);
if (!dm)
return ERROR_FAIL;
struct riscv_batch *batch = riscv_batch_alloc(target, 1);
riscv_batch_add_dm_read(batch, address, RISCV_DELAY_ABSTRACT_COMMAND);
dm->abstract_cmd_maybe_busy = true;
int res = batch_run_timeout(target, batch);
if (res == ERROR_OK && value)
*value = riscv_batch_get_dmi_read_data(batch, 0);
riscv_batch_free(batch);
return res;
}
static int dmi_write(struct target *target, uint32_t address, uint32_t value)
{
struct riscv_batch *batch = riscv_batch_alloc(target, 1);
riscv_batch_add_dmi_write(batch, address, value, /*read_back*/ true,
RISCV_DELAY_BASE);
int res = batch_run_timeout(target, batch);
riscv_batch_free(batch);
return res;
}
static int dm_write(struct target *target, uint32_t address, uint32_t value)
{
return dmi_write(target, riscv013_get_dmi_address(target, address), value);
}
static bool check_dbgbase_exists(struct target *target)
{
uint32_t next_dm = 0;
unsigned int count = 1;
LOG_TARGET_DEBUG(target, "Searching for DM with DMI base address (dbgbase) = 0x%x", target->dbgbase);
while (1) {
uint32_t current_dm = next_dm;
if (current_dm == target->dbgbase)
return true;
if (dmi_read(target, &next_dm, DM_NEXTDM + current_dm) != ERROR_OK)
break;
LOG_TARGET_DEBUG(target, "dm @ 0x%x --> nextdm=0x%x", current_dm, next_dm);
/* Check if it's last one in the chain. */
if (next_dm == 0) {
LOG_TARGET_ERROR(target, "Reached the end of DM chain (detected %u DMs in total).", count);
break;
}
/* Safety: Avoid looping forever in case of buggy nextdm values in the hardware. */
if (count++ > RISCV_MAX_DMS) {
LOG_TARGET_ERROR(target, "Supporting no more than %d DMs on a DMI bus. Aborting", RISCV_MAX_DMS);
break;
}
}
return false;
}
static int dmstatus_read(struct target *target, uint32_t *dmstatus,
bool authenticated)
{
int result = dm_read(target, dmstatus, DM_DMSTATUS);
if (result != ERROR_OK)
return result;
int dmstatus_version = get_field(*dmstatus, DM_DMSTATUS_VERSION);
if (dmstatus_version != 2 && dmstatus_version != 3) {
LOG_ERROR("OpenOCD only supports Debug Module version 2 (0.13) and 3 (1.0), not "
"%" PRId32 " (dmstatus=0x%" PRIx32 "). This error might be caused by a JTAG "
"signal issue. Try reducing the JTAG clock speed.",
get_field32(*dmstatus, DM_DMSTATUS_VERSION), *dmstatus);
} else if (authenticated && !get_field(*dmstatus, DM_DMSTATUS_AUTHENTICATED)) {
LOG_ERROR("Debugger is not authenticated to target Debug Module. "
"(dmstatus=0x%x). Use `riscv authdata_read` and "
"`riscv authdata_write` commands to authenticate.", *dmstatus);
return ERROR_FAIL;
}
return ERROR_OK;
}
static int increase_ac_busy_delay(struct target *target)
{
riscv013_info_t *info = get_info(target);
return riscv_scan_increase_delay(&info->learned_delays,
RISCV_DELAY_ABSTRACT_COMMAND);
}
static uint32_t __attribute__((unused)) abstract_register_size(unsigned int width)
{
switch (width) {
case 32:
return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 2);
case 64:
return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 3);
case 128:
return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 4);
default:
LOG_ERROR("Unsupported register width: %d", width);
return 0;
}
}
static int wait_for_idle(struct target *target, uint32_t *abstractcs)
{
assert(target);
assert(abstractcs);
dm013_info_t *dm = get_dm(target);
if (!dm) {
LOG_ERROR("BUG: Target %s is not assigned to any RISC-V debug module",
target_name(target));
*abstractcs = 0;
return ERROR_FAIL;
}
time_t start = time(NULL);
do {
if (dm_read(target, abstractcs, DM_ABSTRACTCS) != ERROR_OK) {
/* We couldn't read abstractcs. For safety, overwrite the output value to
* prevent the caller working with a stale value of abstractcs. */
*abstractcs = 0;
LOG_TARGET_ERROR(target,
"potentially unrecoverable error detected - could not read abstractcs");
return ERROR_FAIL;
}
if (get_field(*abstractcs, DM_ABSTRACTCS_BUSY) == 0) {
dm->abstract_cmd_maybe_busy = false;
return ERROR_OK;
}
} while ((time(NULL) - start) < riscv_get_command_timeout_sec());
LOG_TARGET_ERROR(target,
"Timed out after %ds waiting for busy to go low (abstractcs=0x%" PRIx32 "). "
"Increase the timeout with riscv set_command_timeout_sec.",
riscv_get_command_timeout_sec(),
*abstractcs);
if (!dm->abstract_cmd_maybe_busy)
LOG_TARGET_ERROR(target,
"BUG: dm->abstract_cmd_maybe_busy had not been set when starting an abstract command.");
dm->abstract_cmd_maybe_busy = true;
return ERROR_TIMEOUT_REACHED;
}
static int dm013_select_target(struct target *target)
{
riscv013_info_t *info = get_info(target);
return dm013_select_hart(target, info->index);
}
#define ABSTRACT_COMMAND_BATCH_SIZE 2
static size_t abstract_cmd_fill_batch(struct riscv_batch *batch,
uint32_t command)
{
assert(riscv_batch_available_scans(batch)
>= ABSTRACT_COMMAND_BATCH_SIZE);
riscv_batch_add_dm_write(batch, DM_COMMAND, command, /* read_back */ true,
RISCV_DELAY_ABSTRACT_COMMAND);
return riscv_batch_add_dm_read(batch, DM_ABSTRACTCS, RISCV_DELAY_BASE);
}
static int abstract_cmd_batch_check_and_clear_cmderr(struct target *target,
const struct riscv_batch *batch, size_t abstractcs_read_key,
uint32_t *cmderr)
{
uint32_t abstractcs = riscv_batch_get_dmi_read_data(batch,
abstractcs_read_key);
int res;
LOG_DEBUG_REG(target, DM_ABSTRACTCS, abstractcs);
if (get_field32(abstractcs, DM_ABSTRACTCS_BUSY) != 0) {
res = wait_for_idle(target, &abstractcs);
if (res != ERROR_OK)
goto clear_cmderr;
res = increase_ac_busy_delay(target);
if (res != ERROR_OK)
goto clear_cmderr;
}
dm013_info_t * const dm = get_dm(target);
if (!dm) {
LOG_ERROR("BUG: Target %s is not assigned to any RISC-V debug module",
target_name(target));
return ERROR_FAIL;
}
dm->abstract_cmd_maybe_busy = false;
*cmderr = get_field32(abstractcs, DM_ABSTRACTCS_CMDERR);
if (*cmderr == CMDERR_NONE)
return ERROR_OK;
res = ERROR_FAIL;
LOG_TARGET_DEBUG(target,
"Abstract Command execution failed (abstractcs.cmderr = %" PRIx32 ").",
*cmderr);
clear_cmderr:
/* Attempt to clear the error. */
/* TODO: can we add a more substantial recovery if the clear operation fails? */
if (dm_write(target, DM_ABSTRACTCS, DM_ABSTRACTCS_CMDERR) != ERROR_OK)
LOG_TARGET_ERROR(target, "could not clear abstractcs error");
return res;
}
int riscv013_execute_abstract_command(struct target *target, uint32_t command,
uint32_t *cmderr)
{
assert(cmderr);
*cmderr = CMDERR_NONE;
if (debug_level >= LOG_LVL_DEBUG) {
switch (get_field(command, DM_COMMAND_CMDTYPE)) {
case 0:
LOG_DEBUG_REG(target, AC_ACCESS_REGISTER, command);
break;
default:
LOG_TARGET_DEBUG(target, "command=0x%x", command);
break;
}
}
dm013_info_t *dm = get_dm(target);
if (!dm)
return ERROR_FAIL;
struct riscv_batch *batch = riscv_batch_alloc(target,
ABSTRACT_COMMAND_BATCH_SIZE);
const size_t abstractcs_read_key = abstract_cmd_fill_batch(batch, command);
/* Abstract commands are executed while running the batch. */
dm->abstract_cmd_maybe_busy = true;
int res = batch_run_timeout(target, batch);
if (res != ERROR_OK)
goto cleanup;
res = abstract_cmd_batch_check_and_clear_cmderr(target, batch,
abstractcs_read_key, cmderr);
cleanup:
riscv_batch_free(batch);
return res;
}
/**
* Queue scans into a batch that read the value from abstract data registers:
* data[index] (and data[index+1] in case of 64-bit value).
*
* No extra DTM delay is added after the write to data[N]. It is assumed that
* this is a one-shot abstract command, that means no auto-execution is set up
* (abstractauto.autoexecdata bits are zero).
*/
static void abstract_data_read_fill_batch(struct riscv_batch *batch, unsigned int index,
unsigned int size_bits)
{
assert(size_bits >= 32);
assert(size_bits % 32 == 0);
const unsigned int size_in_words = size_bits / 32;
const unsigned int offset = index * size_in_words;
for (unsigned int i = 0; i < size_in_words; ++i) {
const unsigned int reg_address = DM_DATA0 + offset + i;
riscv_batch_add_dm_read(batch, reg_address, RISCV_DELAY_BASE);
}
}
static riscv_reg_t abstract_data_get_from_batch(struct riscv_batch *batch,
unsigned int index, unsigned int size_bits)
{
assert(size_bits >= 32);
assert(size_bits % 32 == 0);
const unsigned int size_in_words = size_bits / 32;
assert(size_in_words * sizeof(uint32_t) <= sizeof(riscv_reg_t));
riscv_reg_t value = 0;
for (unsigned int i = 0; i < size_in_words; ++i) {
const uint32_t v = riscv_batch_get_dmi_read_data(batch, i);
value |= ((riscv_reg_t)v) << (i * 32);
}
return value;
}
static int read_abstract_arg(struct target *target, riscv_reg_t *value,
unsigned int index, unsigned int size_bits)
{
assert(value);
assert(size_bits >= 32);
assert(size_bits % 32 == 0);
const unsigned char size_in_words = size_bits / 32;
struct riscv_batch * const batch = riscv_batch_alloc(target, size_in_words);
abstract_data_read_fill_batch(batch, index, size_bits);
int result = batch_run_timeout(target, batch);
if (result == ERROR_OK)
*value = abstract_data_get_from_batch(batch, index, size_bits);
riscv_batch_free(batch);
return result;
}
/**
* Queue scans into a batch that write the value to abstract data registers:
* data[index] (and data[index+1] in case of 64-bit value).
*
* No extra DTM delay is added after the write to data[N]. It is assumed that
* this is a one-shot abstract command, that means no auto-execution is set up
* (abstractauto.autoexecdata bits are zero).
*/
static void abstract_data_write_fill_batch(struct riscv_batch *batch,
riscv_reg_t value, unsigned int index, unsigned int size_bits)
{
assert(size_bits % 32 == 0);
const unsigned int size_in_words = size_bits / 32;
assert(value <= UINT32_MAX || size_in_words > 1);
const unsigned int offset = index * size_in_words;
for (unsigned int i = 0; i < size_in_words; ++i) {
const unsigned int reg_address = DM_DATA0 + offset + i;
riscv_batch_add_dm_write(batch, reg_address, (uint32_t)value,
/* read_back */ true, RISCV_DELAY_BASE);
value >>= 32;
}
}
/* TODO: reuse "abstract_data_write_fill_batch()" here*/
static int write_abstract_arg(struct target *target, unsigned int index,
riscv_reg_t value, unsigned int size_bits)
{
unsigned int offset = index * size_bits / 32;
switch (size_bits) {
default:
LOG_TARGET_ERROR(target, "Unsupported size: %d bits", size_bits);
return ERROR_FAIL;
case 64:
dm_write(target, DM_DATA0 + offset + 1, (uint32_t)(value >> 32));
/* falls through */
case 32:
dm_write(target, DM_DATA0 + offset, (uint32_t)value);
}
return ERROR_OK;
}
/**
* @par size in bits
*/
uint32_t riscv013_access_register_command(struct target *target, uint32_t number,
unsigned int size, uint32_t flags)
{
uint32_t command = set_field(0, DM_COMMAND_CMDTYPE, 0);
switch (size) {
case 32:
command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 2);
break;
case 64:
command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 3);
break;
default:
LOG_TARGET_ERROR(target, "%d-bit register %s not supported.",
size, riscv_reg_gdb_regno_name(target, number));
assert(0);
}
if (number <= GDB_REGNO_XPR31) {
command = set_field(command, AC_ACCESS_REGISTER_REGNO,
0x1000 + number - GDB_REGNO_ZERO);
} else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
command = set_field(command, AC_ACCESS_REGISTER_REGNO,
0x1020 + number - GDB_REGNO_FPR0);
} else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
command = set_field(command, AC_ACCESS_REGISTER_REGNO,
number - GDB_REGNO_CSR0);
} else if (number >= GDB_REGNO_COUNT) {
/* Custom register. */
assert(target->reg_cache->reg_list[number].arch_info);
riscv_reg_info_t *reg_info = target->reg_cache->reg_list[number].arch_info;
assert(reg_info);
command = set_field(command, AC_ACCESS_REGISTER_REGNO,
0xc000 + reg_info->custom_number);
} else {
assert(0);
}
command |= flags;
return command;
}
static int register_read_abstract_with_size(struct target *target,
riscv_reg_t *value, enum gdb_regno number, unsigned int size)
{
RISCV013_INFO(info);
if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31 &&
!info->abstract_read_fpr_supported)
return ERROR_FAIL;
if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095 &&
!info->abstract_read_csr_supported)
return ERROR_FAIL;
/* The spec doesn't define abstract register numbers for vector registers. */
if (number >= GDB_REGNO_V0 && number <= GDB_REGNO_V31)
return ERROR_FAIL;
uint32_t command = riscv013_access_register_command(target, number, size,
AC_ACCESS_REGISTER_TRANSFER);
uint32_t cmderr;
int result = riscv013_execute_abstract_command(target, command, &cmderr);
if (result != ERROR_OK) {
if (cmderr == CMDERR_NOT_SUPPORTED) {
if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
info->abstract_read_fpr_supported = false;
LOG_TARGET_INFO(target, "Disabling abstract command reads from FPRs.");
} else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
info->abstract_read_csr_supported = false;
LOG_TARGET_INFO(target, "Disabling abstract command reads from CSRs.");
}
}
return result;
}
if (value)
return read_abstract_arg(target, value, 0, size);
return ERROR_OK;
}
static int register_read_abstract(struct target *target, riscv_reg_t *value,
enum gdb_regno number)
{
const unsigned int size = register_size(target, number);
return register_read_abstract_with_size(target, value, number, size);
}
static int register_write_abstract(struct target *target, enum gdb_regno number,
riscv_reg_t value)
{
RISCV013_INFO(info);
dm013_info_t *dm = get_dm(target);
if (!dm)
return ERROR_FAIL;
if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31 &&
!info->abstract_write_fpr_supported)
return ERROR_FAIL;
if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095 &&
!info->abstract_write_csr_supported)
return ERROR_FAIL;
const unsigned int size_bits = register_size(target, number);
const uint32_t command = riscv013_access_register_command(target, number, size_bits,
AC_ACCESS_REGISTER_TRANSFER |
AC_ACCESS_REGISTER_WRITE);
LOG_DEBUG_REG(target, AC_ACCESS_REGISTER, command);
assert(size_bits % 32 == 0);
const unsigned int size_in_words = size_bits / 32;
const unsigned int batch_size = size_in_words
+ ABSTRACT_COMMAND_BATCH_SIZE;
struct riscv_batch * const batch = riscv_batch_alloc(target, batch_size);
abstract_data_write_fill_batch(batch, value, /*index*/ 0, size_bits);
const size_t abstractcs_read_key = abstract_cmd_fill_batch(batch, command);
/* Abstract commands are executed while running the batch. */
dm->abstract_cmd_maybe_busy = true;
int res = batch_run_timeout(target, batch);
if (res != ERROR_OK)
goto cleanup;
uint32_t cmderr;
res = abstract_cmd_batch_check_and_clear_cmderr(target, batch,
abstractcs_read_key, &cmderr);
if (res != ERROR_OK) {
if (cmderr == CMDERR_NOT_SUPPORTED) {
if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
info->abstract_write_fpr_supported = false;
LOG_TARGET_INFO(target, "Disabling abstract command writes to FPRs.");
} else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
info->abstract_write_csr_supported = false;
LOG_TARGET_INFO(target, "Disabling abstract command writes to CSRs.");
}
}
}
cleanup:
riscv_batch_free(batch);
return res;
}
/*
* Sets the AAMSIZE field of a memory access abstract command based on
* the width (bits).
*/
static uint32_t abstract_memory_size(unsigned int width)
{
switch (width) {
case 8:
return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 0);
case 16:
return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 1);
case 32:
return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 2);
case 64:
return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 3);
case 128:
return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 4);
default:
LOG_ERROR("Unsupported memory width: %d", width);
return 0;
}
}
/*
* Creates a memory access abstract command.
*/
static uint32_t access_memory_command(struct target *target, bool virtual,
unsigned int width, bool postincrement, bool is_write)
{
uint32_t command = set_field(0, AC_ACCESS_MEMORY_CMDTYPE, 2);
command = set_field(command, AC_ACCESS_MEMORY_AAMVIRTUAL, virtual);
command |= abstract_memory_size(width);
command = set_field(command, AC_ACCESS_MEMORY_AAMPOSTINCREMENT,
postincrement);
command = set_field(command, AC_ACCESS_MEMORY_WRITE, is_write);
return command;
}
static int examine_progbuf(struct target *target)
{
riscv013_info_t *info = get_info(target);
if (info->progbuf_writable != YNM_MAYBE)
return ERROR_OK;
/* Figure out if progbuf is writable. */
if (info->progbufsize < 1) {
info->progbuf_writable = YNM_NO;
LOG_TARGET_INFO(target, "No program buffer present.");
return ERROR_OK;
}
if (riscv013_reg_save(target, GDB_REGNO_S0) != ERROR_OK)
return ERROR_FAIL;
struct riscv_program program;
riscv_program_init(&program, target);
riscv_program_insert(&program, auipc(S0));
if (riscv_program_exec(&program, target) != ERROR_OK)
return ERROR_FAIL;
if (register_read_direct(target, &info->progbuf_address, GDB_REGNO_S0) != ERROR_OK)
return ERROR_FAIL;